1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCRegisterInfo.h" 18 #include "llvm/Constants.h" 19 #include "llvm/Type.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineLocation.h" 25 #include "llvm/Target/TargetFrameInfo.h" 26 #include "llvm/Target/TargetMachine.h" 27 #include "llvm/Target/TargetOptions.h" 28 #include "llvm/Support/CommandLine.h" 29 #include "llvm/Support/Debug.h" 30 #include "llvm/Support/MathExtras.h" 31 #include "llvm/ADT/STLExtras.h" 32 #include <cstdlib> 33 #include <iostream> 34 using namespace llvm; 35 36 PPCRegisterInfo::PPCRegisterInfo() 37 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) { 38 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 39 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 40 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 41 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 42 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 43 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 44 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 45 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 46 } 47 48 void 49 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 50 MachineBasicBlock::iterator MI, 51 unsigned SrcReg, int FrameIdx, 52 const TargetRegisterClass *RC) const { 53 if (SrcReg == PPC::LR) { 54 // FIXME: this spills LR immediately to memory in one step. To do this, we 55 // use R11, which we know cannot be used in the prolog/epilog. This is a 56 // hack. 57 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); 58 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 59 } else if (RC == PPC::CRRCRegisterClass) { 60 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11); 61 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 62 } else if (RC == PPC::GPRCRegisterClass) { 63 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); 64 } else if (RC == PPC::G8RCRegisterClass) { 65 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx); 66 } else if (RC == PPC::F8RCRegisterClass) { 67 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx); 68 } else if (RC == PPC::F4RCRegisterClass) { 69 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx); 70 } else if (RC == PPC::VRRCRegisterClass) { 71 // We don't have indexed addressing for vector loads. Emit: 72 // R11 = ADDI FI# 73 // Dest = LVX R0, R11 74 // 75 // FIXME: We use R0 here, because it isn't available for RA. 76 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 77 BuildMI(MBB, MI, PPC::STVX, 3) 78 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); 79 } else { 80 assert(0 && "Unknown regclass!"); 81 abort(); 82 } 83 } 84 85 void 86 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 87 MachineBasicBlock::iterator MI, 88 unsigned DestReg, int FrameIdx, 89 const TargetRegisterClass *RC) const { 90 if (DestReg == PPC::LR) { 91 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 92 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); 93 } else if (RC == PPC::CRRCRegisterClass) { 94 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 95 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11); 96 } else if (RC == PPC::GPRCRegisterClass) { 97 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); 98 } else if (RC == PPC::G8RCRegisterClass) { 99 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx); 100 } else if (RC == PPC::F8RCRegisterClass) { 101 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx); 102 } else if (RC == PPC::F4RCRegisterClass) { 103 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx); 104 } else if (RC == PPC::VRRCRegisterClass) { 105 // We don't have indexed addressing for vector loads. Emit: 106 // R11 = ADDI FI# 107 // Dest = LVX R0, R11 108 // 109 // FIXME: We use R0 here, because it isn't available for RA. 110 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 111 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0); 112 } else { 113 assert(0 && "Unknown regclass!"); 114 abort(); 115 } 116 } 117 118 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 119 MachineBasicBlock::iterator MI, 120 unsigned DestReg, unsigned SrcReg, 121 const TargetRegisterClass *RC) const { 122 if (RC == PPC::GPRCRegisterClass) { 123 BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 124 } else if (RC == PPC::G8RCRegisterClass) { 125 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 126 } else if (RC == PPC::F4RCRegisterClass) { 127 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg); 128 } else if (RC == PPC::F8RCRegisterClass) { 129 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg); 130 } else if (RC == PPC::CRRCRegisterClass) { 131 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg); 132 } else if (RC == PPC::VRRCRegisterClass) { 133 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 134 } else { 135 std::cerr << "Attempt to copy register that is not GPR or FPR"; 136 abort(); 137 } 138 } 139 140 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 141 /// copy instructions, turning them into load/store instructions. 142 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 143 unsigned OpNum, 144 int FrameIndex) const { 145 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 146 // it takes more than one instruction to store it. 147 unsigned Opc = MI->getOpcode(); 148 149 if ((Opc == PPC::OR4 && 150 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 151 if (OpNum == 0) { // move -> store 152 unsigned InReg = MI->getOperand(1).getReg(); 153 return addFrameReference(BuildMI(PPC::STW, 154 3).addReg(InReg), FrameIndex); 155 } else { // move -> load 156 unsigned OutReg = MI->getOperand(0).getReg(); 157 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex); 158 } 159 } else if ((Opc == PPC::OR8 && 160 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 161 if (OpNum == 0) { // move -> store 162 unsigned InReg = MI->getOperand(1).getReg(); 163 return addFrameReference(BuildMI(PPC::STD, 164 3).addReg(InReg), FrameIndex); 165 } else { // move -> load 166 unsigned OutReg = MI->getOperand(0).getReg(); 167 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex); 168 } 169 } else if (Opc == PPC::FMRD) { 170 if (OpNum == 0) { // move -> store 171 unsigned InReg = MI->getOperand(1).getReg(); 172 return addFrameReference(BuildMI(PPC::STFD, 173 3).addReg(InReg), FrameIndex); 174 } else { // move -> load 175 unsigned OutReg = MI->getOperand(0).getReg(); 176 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex); 177 } 178 } else if (Opc == PPC::FMRS) { 179 if (OpNum == 0) { // move -> store 180 unsigned InReg = MI->getOperand(1).getReg(); 181 return addFrameReference(BuildMI(PPC::STFS, 182 3).addReg(InReg), FrameIndex); 183 } else { // move -> load 184 unsigned OutReg = MI->getOperand(0).getReg(); 185 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex); 186 } 187 } 188 return 0; 189 } 190 191 //===----------------------------------------------------------------------===// 192 // Stack Frame Processing methods 193 //===----------------------------------------------------------------------===// 194 195 // hasFP - Return true if the specified function should have a dedicated frame 196 // pointer register. This is true if the function has variable sized allocas or 197 // if frame pointer elimination is disabled. 198 // 199 static bool hasFP(const MachineFunction &MF) { 200 const MachineFrameInfo *MFI = MF.getFrameInfo(); 201 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 202 203 // If frame pointers are forced, if there are variable sized stack objects, 204 // or if there is an object on the stack that requires more alignment than is 205 // normally provided, use a frame pointer. 206 // 207 return NoFramePointerElim || MFI->hasVarSizedObjects() || 208 MFI->getMaxAlignment() > TargetAlign; 209 } 210 211 void PPCRegisterInfo:: 212 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 213 MachineBasicBlock::iterator I) const { 214 if (hasFP(MF)) { 215 // If we have a frame pointer, convert as follows: 216 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount 217 // ADJCALLSTACKUP -> addi, r1, r1, amount 218 MachineInstr *Old = I; 219 unsigned Amount = Old->getOperand(0).getImmedValue(); 220 if (Amount != 0) { 221 // We need to keep the stack aligned properly. To do this, we round the 222 // amount of space needed for the outgoing arguments up to the next 223 // alignment boundary. 224 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 225 Amount = (Amount+Align-1)/Align*Align; 226 227 // Replace the pseudo instruction with a new instruction... 228 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { 229 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount); 230 } else { 231 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); 232 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount); 233 } 234 } 235 } 236 MBB.erase(I); 237 } 238 239 void 240 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 241 unsigned i = 0; 242 MachineInstr &MI = *II; 243 MachineBasicBlock &MBB = *MI.getParent(); 244 MachineFunction &MF = *MBB.getParent(); 245 246 while (!MI.getOperand(i).isFrameIndex()) { 247 ++i; 248 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 249 } 250 251 int FrameIndex = MI.getOperand(i).getFrameIndex(); 252 253 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 254 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1); 255 256 // Take into account whether it's an add or mem instruction 257 unsigned OffIdx = (i == 2) ? 1 : 2; 258 259 // Now add the frame object offset to the offset from r1. 260 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 261 MI.getOperand(OffIdx).getImmedValue(); 262 263 // If we're not using a Frame Pointer that has been set to the value of the 264 // SP before having the stack size subtracted from it, then add the stack size 265 // to Offset to get the correct offset. 266 Offset += MF.getFrameInfo()->getStackSize(); 267 268 if (Offset > 32767 || Offset < -32768) { 269 // Insert a set of r0 with the full offset value before the ld, st, or add 270 MachineBasicBlock *MBB = MI.getParent(); 271 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16); 272 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset); 273 274 // convert into indexed form of the instruction 275 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 276 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 277 assert(ImmToIdxMap.count(MI.getOpcode()) && 278 "No indexed form of load or store available!"); 279 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; 280 MI.setOpcode(NewOpcode); 281 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); 282 MI.SetMachineOperandReg(2, PPC::R0); 283 } else { 284 switch (MI.getOpcode()) { 285 case PPC::LWA: 286 case PPC::LD: 287 case PPC::STD: 288 case PPC::STD_32: 289 assert((Offset & 3) == 0 && "Invalid frame offset!"); 290 Offset >>= 2; // The actual encoded value has the low two bits zero. 291 break; 292 } 293 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed, 294 Offset); 295 } 296 } 297 298 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 299 // instruction selector. Based on the vector registers that have been used, 300 // transform this into the appropriate ORI instruction. 301 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) { 302 unsigned UsedRegMask = 0; 303 #define HANDLEREG(N) if (UsedRegs[PPC::V##N]) UsedRegMask |= 1 << (31-N) 304 HANDLEREG( 0); HANDLEREG( 1); HANDLEREG( 2); HANDLEREG( 3); 305 HANDLEREG( 4); HANDLEREG( 5); HANDLEREG( 6); HANDLEREG( 7); 306 HANDLEREG( 8); HANDLEREG( 9); HANDLEREG(10); HANDLEREG(11); 307 HANDLEREG(12); HANDLEREG(13); HANDLEREG(14); HANDLEREG(15); 308 HANDLEREG(16); HANDLEREG(17); HANDLEREG(18); HANDLEREG(19); 309 HANDLEREG(20); HANDLEREG(21); HANDLEREG(22); HANDLEREG(23); 310 HANDLEREG(24); HANDLEREG(25); HANDLEREG(26); HANDLEREG(27); 311 HANDLEREG(28); HANDLEREG(29); HANDLEREG(30); HANDLEREG(31); 312 #undef HANDLEREG 313 unsigned SrcReg = MI->getOperand(1).getReg(); 314 unsigned DstReg = MI->getOperand(0).getReg(); 315 // If no registers are used, turn this into a copy. 316 if (UsedRegMask == 0) { 317 if (SrcReg != DstReg) 318 BuildMI(*MI->getParent(), MI, PPC::OR4, 2, DstReg) 319 .addReg(SrcReg).addReg(SrcReg); 320 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 321 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 322 .addReg(SrcReg).addImm(UsedRegMask); 323 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 324 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 325 .addReg(SrcReg).addImm(UsedRegMask >> 16); 326 } else { 327 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 328 .addReg(SrcReg).addImm(UsedRegMask >> 16); 329 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 330 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 331 } 332 333 // Remove the old UPDATE_VRSAVE instruction. 334 MI->getParent()->erase(MI); 335 } 336 337 338 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 339 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 340 MachineBasicBlock::iterator MBBI = MBB.begin(); 341 MachineFrameInfo *MFI = MF.getFrameInfo(); 342 343 // Do we have a frame pointer for this function? 344 bool HasFP = hasFP(MF); 345 346 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 347 // process it. 348 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 349 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 350 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs()); 351 break; 352 } 353 } 354 355 // Move MBBI back to the beginning of the function. 356 MBBI = MBB.begin(); 357 358 // Get the number of bytes to allocate from the FrameInfo 359 unsigned NumBytes = MFI->getStackSize(); 360 361 // Get the alignments provided by the target, and the maximum alignment 362 // (if any) of the fixed frame objects. 363 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 364 unsigned MaxAlign = MFI->getMaxAlignment(); 365 366 // If we have calls, we cannot use the red zone to store callee save registers 367 // and we must set up a stack frame, so calculate the necessary size here. 368 if (MFI->hasCalls()) { 369 // We reserve argument space for call sites in the function immediately on 370 // entry to the current function. This eliminates the need for add/sub 371 // brackets around call sites. 372 NumBytes += MFI->getMaxCallFrameSize(); 373 } 374 375 // If we are a leaf function, and use up to 224 bytes of stack space, 376 // and don't have a frame pointer, then we do not need to adjust the stack 377 // pointer (we fit in the Red Zone). 378 if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() && 379 MaxAlign <= TargetAlign)) { 380 MFI->setStackSize(0); 381 return; 382 } 383 384 // Add the size of R1 to NumBytes size for the store of R1 to the bottom 385 // of the stack and round the size to a multiple of the alignment. 386 unsigned Align = std::max(TargetAlign, MaxAlign); 387 unsigned GPRSize = 4; 388 unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize; 389 NumBytes = (NumBytes+Size+Align-1)/Align*Align; 390 391 // Update frame info to pretend that this is part of the stack... 392 MFI->setStackSize(NumBytes); 393 394 // Adjust stack pointer: r1 -= numbytes. 395 if (NumBytes <= 32768) { 396 BuildMI(MBB, MBBI, PPC::STWU, 3) 397 .addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1); 398 } else { 399 int NegNumbytes = -NumBytes; 400 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16); 401 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0) 402 .addReg(PPC::R0).addImm(NegNumbytes & 0xFFFF); 403 BuildMI(MBB, MBBI, PPC::STWUX, 3) 404 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 405 } 406 407 // If there is a preferred stack alignment, align R1 now 408 // FIXME: If this ever matters, this could be made more efficient by folding 409 // this into the code above, so that we don't issue two store+update 410 // instructions. 411 if (MaxAlign > TargetAlign) { 412 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!"); 413 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) 414 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 415 BuildMI(MBB, MBBI, PPC::SUBFIC, 2,PPC::R0).addReg(PPC::R0).addImm(MaxAlign); 416 BuildMI(MBB, MBBI, PPC::STWUX, 3) 417 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 418 } 419 420 // If there is a frame pointer, copy R1 (SP) into R31 (FP) 421 if (HasFP) { 422 BuildMI(MBB, MBBI, PPC::STW, 3) 423 .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1); 424 BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); 425 } 426 } 427 428 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 429 MachineBasicBlock &MBB) const { 430 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 431 assert(MBBI->getOpcode() == PPC::BLR && 432 "Can only insert epilog into returning blocks"); 433 434 // Get the number of bytes allocated from the FrameInfo. 435 unsigned NumBytes = MF.getFrameInfo()->getStackSize(); 436 unsigned GPRSize = 4; 437 438 if (NumBytes != 0) { 439 // If this function has a frame pointer, load the saved stack pointer from 440 // its stack slot. 441 if (hasFP(MF)) { 442 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31) 443 .addSImm(GPRSize).addReg(PPC::R31); 444 } 445 446 // The loaded (or persistent) stack pointer value is offseted by the 'stwu' 447 // on entry to the function. Add this offset back now. 448 if (NumBytes < 32768) { 449 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1) 450 .addReg(PPC::R1).addSImm(NumBytes); 451 } else { 452 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NumBytes >> 16); 453 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0) 454 .addReg(PPC::R0).addImm(NumBytes & 0xFFFF); 455 BuildMI(MBB, MBBI, PPC::ADD4, 2, PPC::R1) 456 .addReg(PPC::R0).addReg(PPC::R1); 457 } 458 } 459 } 460 461 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 462 return getDwarfRegNum(hasFP(MF) ? PPC::R31 : PPC::R1); 463 } 464 465 #include "PPCGenRegisterInfo.inc" 466 467