1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCRegisterInfo.h" 19 #include "PPCFrameInfo.h" 20 #include "PPCSubtarget.h" 21 #include "llvm/Constants.h" 22 #include "llvm/Type.h" 23 #include "llvm/CodeGen/ValueTypes.h" 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 25 #include "llvm/CodeGen/MachineModuleInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineLocation.h" 29 #include "llvm/CodeGen/SelectionDAGNodes.h" 30 #include "llvm/Target/TargetFrameInfo.h" 31 #include "llvm/Target/TargetInstrInfo.h" 32 #include "llvm/Target/TargetMachine.h" 33 #include "llvm/Target/TargetOptions.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/ADT/BitVector.h" 38 #include "llvm/ADT/STLExtras.h" 39 #include <cstdlib> 40 using namespace llvm; 41 42 /// getRegisterNumbering - Given the enum value for some register, e.g. 43 /// PPC::F14, return the number that it corresponds to (e.g. 14). 44 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 45 using namespace PPC; 46 switch (RegEnum) { 47 case R0 : case X0 : case F0 : case V0 : case CR0: return 0; 48 case R1 : case X1 : case F1 : case V1 : case CR1: return 1; 49 case R2 : case X2 : case F2 : case V2 : case CR2: return 2; 50 case R3 : case X3 : case F3 : case V3 : case CR3: return 3; 51 case R4 : case X4 : case F4 : case V4 : case CR4: return 4; 52 case R5 : case X5 : case F5 : case V5 : case CR5: return 5; 53 case R6 : case X6 : case F6 : case V6 : case CR6: return 6; 54 case R7 : case X7 : case F7 : case V7 : case CR7: return 7; 55 case R8 : case X8 : case F8 : case V8 : return 8; 56 case R9 : case X9 : case F9 : case V9 : return 9; 57 case R10: case X10: case F10: case V10: return 10; 58 case R11: case X11: case F11: case V11: return 11; 59 case R12: case X12: case F12: case V12: return 12; 60 case R13: case X13: case F13: case V13: return 13; 61 case R14: case X14: case F14: case V14: return 14; 62 case R15: case X15: case F15: case V15: return 15; 63 case R16: case X16: case F16: case V16: return 16; 64 case R17: case X17: case F17: case V17: return 17; 65 case R18: case X18: case F18: case V18: return 18; 66 case R19: case X19: case F19: case V19: return 19; 67 case R20: case X20: case F20: case V20: return 20; 68 case R21: case X21: case F21: case V21: return 21; 69 case R22: case X22: case F22: case V22: return 22; 70 case R23: case X23: case F23: case V23: return 23; 71 case R24: case X24: case F24: case V24: return 24; 72 case R25: case X25: case F25: case V25: return 25; 73 case R26: case X26: case F26: case V26: return 26; 74 case R27: case X27: case F27: case V27: return 27; 75 case R28: case X28: case F28: case V28: return 28; 76 case R29: case X29: case F29: case V29: return 29; 77 case R30: case X30: case F30: case V30: return 30; 78 case R31: case X31: case F31: case V31: return 31; 79 default: 80 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; 81 abort(); 82 } 83 } 84 85 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 86 const TargetInstrInfo &tii) 87 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 88 Subtarget(ST), TII(tii) { 89 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 90 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 91 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 92 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 93 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 94 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 95 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 96 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 97 98 // 64-bit 99 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 100 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 101 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 102 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 103 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 104 } 105 106 void 107 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 108 MachineBasicBlock::iterator MI, 109 unsigned SrcReg, int FrameIdx, 110 const TargetRegisterClass *RC) const { 111 if (RC == PPC::GPRCRegisterClass) { 112 if (SrcReg != PPC::LR) { 113 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) 114 .addReg(SrcReg, false, false, true), FrameIdx); 115 } else { 116 // FIXME: this spills LR immediately to memory in one step. To do this, 117 // we use R11, which we know cannot be used in the prolog/epilog. This is 118 // a hack. 119 BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11); 120 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) 121 .addReg(PPC::R11, false, false, true), FrameIdx); 122 } 123 } else if (RC == PPC::G8RCRegisterClass) { 124 if (SrcReg != PPC::LR8) { 125 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)) 126 .addReg(SrcReg, false, false, true), FrameIdx); 127 } else { 128 // FIXME: this spills LR immediately to memory in one step. To do this, 129 // we use R11, which we know cannot be used in the prolog/epilog. This is 130 // a hack. 131 BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11); 132 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)) 133 .addReg(PPC::X11, false, false, true), FrameIdx); 134 } 135 } else if (RC == PPC::F8RCRegisterClass) { 136 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)) 137 .addReg(SrcReg, false, false, true), FrameIdx); 138 } else if (RC == PPC::F4RCRegisterClass) { 139 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)) 140 .addReg(SrcReg, false, false, true), FrameIdx); 141 } else if (RC == PPC::CRRCRegisterClass) { 142 // FIXME: We use R0 here, because it isn't available for RA. 143 // We need to store the CR in the low 4-bits of the saved value. First, 144 // issue a MFCR to save all of the CRBits. 145 BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0); 146 147 // If the saved register wasn't CR0, shift the bits left so that they are in 148 // CR0's slot. 149 if (SrcReg != PPC::CR0) { 150 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 151 // rlwinm r0, r0, ShiftBits, 0, 31. 152 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) 153 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31); 154 } 155 156 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) 157 .addReg(PPC::R0, false, false, true), FrameIdx); 158 } else if (RC == PPC::VRRCRegisterClass) { 159 // We don't have indexed addressing for vector loads. Emit: 160 // R0 = ADDI FI# 161 // STVX VAL, 0, R0 162 // 163 // FIXME: We use R0 here, because it isn't available for RA. 164 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), 165 FrameIdx, 0, 0); 166 BuildMI(MBB, MI, TII.get(PPC::STVX)) 167 .addReg(SrcReg, false, false, true).addReg(PPC::R0).addReg(PPC::R0); 168 } else { 169 assert(0 && "Unknown regclass!"); 170 abort(); 171 } 172 } 173 174 void 175 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 176 MachineBasicBlock::iterator MI, 177 unsigned DestReg, int FrameIdx, 178 const TargetRegisterClass *RC) const { 179 if (RC == PPC::GPRCRegisterClass) { 180 if (DestReg != PPC::LR) { 181 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), DestReg), FrameIdx); 182 } else { 183 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R11),FrameIdx); 184 BuildMI(MBB, MI, TII.get(PPC::MTLR)).addReg(PPC::R11); 185 } 186 } else if (RC == PPC::G8RCRegisterClass) { 187 if (DestReg != PPC::LR8) { 188 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), DestReg), FrameIdx); 189 } else { 190 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), PPC::R11), FrameIdx); 191 BuildMI(MBB, MI, TII.get(PPC::MTLR8)).addReg(PPC::R11); 192 } 193 } else if (RC == PPC::F8RCRegisterClass) { 194 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFD), DestReg), FrameIdx); 195 } else if (RC == PPC::F4RCRegisterClass) { 196 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFS), DestReg), FrameIdx); 197 } else if (RC == PPC::CRRCRegisterClass) { 198 // FIXME: We use R0 here, because it isn't available for RA. 199 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R0), FrameIdx); 200 201 // If the reloaded register isn't CR0, shift the bits right so that they are 202 // in the right CR's slot. 203 if (DestReg != PPC::CR0) { 204 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 205 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 206 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) 207 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31); 208 } 209 210 BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0); 211 } else if (RC == PPC::VRRCRegisterClass) { 212 // We don't have indexed addressing for vector loads. Emit: 213 // R0 = ADDI FI# 214 // Dest = LVX 0, R0 215 // 216 // FIXME: We use R0 here, because it isn't available for RA. 217 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), 218 FrameIdx, 0, 0); 219 BuildMI(MBB, MI, TII.get(PPC::LVX),DestReg).addReg(PPC::R0).addReg(PPC::R0); 220 } else { 221 assert(0 && "Unknown regclass!"); 222 abort(); 223 } 224 } 225 226 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 227 MachineBasicBlock::iterator MI, 228 unsigned DestReg, unsigned SrcReg, 229 const TargetRegisterClass *RC) const { 230 if (RC == PPC::GPRCRegisterClass) { 231 BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); 232 } else if (RC == PPC::G8RCRegisterClass) { 233 BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); 234 } else if (RC == PPC::F4RCRegisterClass) { 235 BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg); 236 } else if (RC == PPC::F8RCRegisterClass) { 237 BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg); 238 } else if (RC == PPC::CRRCRegisterClass) { 239 BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg); 240 } else if (RC == PPC::VRRCRegisterClass) { 241 BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); 242 } else { 243 cerr << "Attempt to copy register that is not GPR or FPR"; 244 abort(); 245 } 246 } 247 248 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB, 249 MachineBasicBlock::iterator I, 250 unsigned DestReg, 251 const MachineInstr *Orig) const { 252 MachineInstr *MI = Orig->clone(); 253 MI->getOperand(0).setReg(DestReg); 254 MBB.insert(I, MI); 255 } 256 257 const unsigned* 258 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 259 // 32-bit Darwin calling convention. 260 static const unsigned Macho32_CalleeSavedRegs[] = { 261 PPC::R13, PPC::R14, PPC::R15, 262 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 263 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 264 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 265 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 266 267 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 268 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 269 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 270 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 271 PPC::F30, PPC::F31, 272 273 PPC::CR2, PPC::CR3, PPC::CR4, 274 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 275 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 276 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 277 278 PPC::LR, 0 279 }; 280 281 static const unsigned ELF32_CalleeSavedRegs[] = { 282 PPC::R13, PPC::R14, PPC::R15, 283 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 284 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 285 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 286 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 287 288 PPC::F9, 289 PPC::F10, PPC::F11, PPC::F12, PPC::F13, 290 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 291 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 292 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 293 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 294 PPC::F30, PPC::F31, 295 296 PPC::CR2, PPC::CR3, PPC::CR4, 297 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 298 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 299 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 300 301 PPC::LR, 0 302 }; 303 // 64-bit Darwin calling convention. 304 static const unsigned Macho64_CalleeSavedRegs[] = { 305 PPC::X14, PPC::X15, 306 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 307 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 308 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 309 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 310 311 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 312 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 313 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 314 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 315 PPC::F30, PPC::F31, 316 317 PPC::CR2, PPC::CR3, PPC::CR4, 318 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 319 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 320 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 321 322 PPC::LR8, 0 323 }; 324 325 if (Subtarget.isMachoABI()) 326 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs : 327 Macho32_CalleeSavedRegs; 328 329 // ELF 32. 330 return ELF32_CalleeSavedRegs; 331 } 332 333 const TargetRegisterClass* const* 334 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 335 // 32-bit Macho calling convention. 336 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = { 337 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 338 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 339 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 340 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 341 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 342 343 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 344 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 345 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 346 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 347 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 348 349 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 350 351 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 352 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 353 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 354 355 &PPC::GPRCRegClass, 0 356 }; 357 358 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = { 359 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 360 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 361 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 362 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 363 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 364 365 &PPC::F8RCRegClass, 366 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 367 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 368 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 369 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 370 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 371 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 372 373 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 374 375 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 376 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 377 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 378 379 &PPC::GPRCRegClass, 0 380 }; 381 382 // 64-bit Macho calling convention. 383 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = { 384 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 385 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 386 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 387 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 388 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 389 390 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 391 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 392 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 393 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 394 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 395 396 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 397 398 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 399 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 400 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 401 402 &PPC::G8RCRegClass, 0 403 }; 404 405 if (Subtarget.isMachoABI()) 406 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses : 407 Macho32_CalleeSavedRegClasses; 408 409 // ELF 32. 410 return ELF32_CalleeSavedRegClasses; 411 } 412 413 // needsFP - Return true if the specified function should have a dedicated frame 414 // pointer register. This is true if the function has variable sized allocas or 415 // if frame pointer elimination is disabled. 416 // 417 static bool needsFP(const MachineFunction &MF) { 418 const MachineFrameInfo *MFI = MF.getFrameInfo(); 419 return NoFramePointerElim || MFI->hasVarSizedObjects(); 420 } 421 422 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 423 BitVector Reserved(getNumRegs()); 424 Reserved.set(PPC::R0); 425 Reserved.set(PPC::R1); 426 Reserved.set(PPC::LR); 427 // In Linux, r2 is reserved for the OS. 428 if (!Subtarget.isDarwin()) 429 Reserved.set(PPC::R2); 430 // On PPC64, r13 is the thread pointer. Never allocate this register. 431 // Note that this is overconservative, as it also prevents allocation of 432 // R31 when the FP is not needed. 433 if (Subtarget.isPPC64()) { 434 Reserved.set(PPC::R13); 435 Reserved.set(PPC::R31); 436 } 437 if (needsFP(MF)) 438 Reserved.set(PPC::R31); 439 return Reserved; 440 } 441 442 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 443 /// copy instructions, turning them into load/store instructions. 444 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 445 unsigned OpNum, 446 int FrameIndex) const { 447 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 448 // it takes more than one instruction to store it. 449 unsigned Opc = MI->getOpcode(); 450 451 MachineInstr *NewMI = NULL; 452 if ((Opc == PPC::OR && 453 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 454 if (OpNum == 0) { // move -> store 455 unsigned InReg = MI->getOperand(1).getReg(); 456 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg), 457 FrameIndex); 458 } else { // move -> load 459 unsigned OutReg = MI->getOperand(0).getReg(); 460 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg), 461 FrameIndex); 462 } 463 } else if ((Opc == PPC::OR8 && 464 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 465 if (OpNum == 0) { // move -> store 466 unsigned InReg = MI->getOperand(1).getReg(); 467 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg), 468 FrameIndex); 469 } else { // move -> load 470 unsigned OutReg = MI->getOperand(0).getReg(); 471 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex); 472 } 473 } else if (Opc == PPC::FMRD) { 474 if (OpNum == 0) { // move -> store 475 unsigned InReg = MI->getOperand(1).getReg(); 476 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg), 477 FrameIndex); 478 } else { // move -> load 479 unsigned OutReg = MI->getOperand(0).getReg(); 480 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex); 481 } 482 } else if (Opc == PPC::FMRS) { 483 if (OpNum == 0) { // move -> store 484 unsigned InReg = MI->getOperand(1).getReg(); 485 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg), 486 FrameIndex); 487 } else { // move -> load 488 unsigned OutReg = MI->getOperand(0).getReg(); 489 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex); 490 } 491 } 492 493 if (NewMI) 494 NewMI->copyKillDeadInfo(MI); 495 return NewMI; 496 } 497 498 //===----------------------------------------------------------------------===// 499 // Stack Frame Processing methods 500 //===----------------------------------------------------------------------===// 501 502 // hasFP - Return true if the specified function actually has a dedicated frame 503 // pointer register. This is true if the function needs a frame pointer and has 504 // a non-zero stack size. 505 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 506 const MachineFrameInfo *MFI = MF.getFrameInfo(); 507 return MFI->getStackSize() && needsFP(MF); 508 } 509 510 /// usesLR - Returns if the link registers (LR) has been used in the function. 511 /// 512 bool PPCRegisterInfo::usesLR(MachineFunction &MF) const { 513 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 514 return FI->usesLR(); 515 } 516 517 void PPCRegisterInfo:: 518 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 519 MachineBasicBlock::iterator I) const { 520 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 521 MBB.erase(I); 522 } 523 524 /// LowerDynamicAlloc - Generate the code for allocating an object in the 525 /// current frame. The sequence of code with be in the general form 526 /// 527 /// addi R0, SP, #frameSize ; get the address of the previous frame 528 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 529 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation 530 /// 531 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 532 // Get the instruction. 533 MachineInstr &MI = *II; 534 // Get the instruction's basic block. 535 MachineBasicBlock &MBB = *MI.getParent(); 536 // Get the basic block's function. 537 MachineFunction &MF = *MBB.getParent(); 538 // Get the frame info. 539 MachineFrameInfo *MFI = MF.getFrameInfo(); 540 // Determine whether 64-bit pointers are used. 541 bool LP64 = Subtarget.isPPC64(); 542 543 // Get the maximum call stack size. 544 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 545 // Get the total frame size. 546 unsigned FrameSize = MFI->getStackSize(); 547 548 // Get stack alignments. 549 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 550 unsigned MaxAlign = MFI->getMaxAlignment(); 551 assert(MaxAlign <= TargetAlign && 552 "Dynamic alloca with large aligns not supported"); 553 554 // Determine the previous frame's address. If FrameSize can't be 555 // represented as 16 bits or we need special alignment, then we load the 556 // previous frame's address from 0(SP). Why not do an addis of the hi? 557 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 558 // Constructing the constant and adding would take 3 instructions. 559 // Fortunately, a frame greater than 32K is rare. 560 if (MaxAlign < TargetAlign && isInt16(FrameSize)) { 561 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0) 562 .addReg(PPC::R31) 563 .addImm(FrameSize); 564 } else if (LP64) { 565 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) 566 .addImm(0) 567 .addReg(PPC::X1); 568 } else { 569 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0) 570 .addImm(0) 571 .addReg(PPC::R1); 572 } 573 574 // Grow the stack and update the stack pointer link, then 575 // determine the address of new allocated space. 576 if (LP64) { 577 BuildMI(MBB, II, TII.get(PPC::STDUX)) 578 .addReg(PPC::X0) 579 .addReg(PPC::X1) 580 .addReg(MI.getOperand(1).getReg()); 581 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 582 .addReg(PPC::X1) 583 .addImm(maxCallFrameSize); 584 } else { 585 BuildMI(MBB, II, TII.get(PPC::STWUX)) 586 .addReg(PPC::R0) 587 .addReg(PPC::R1) 588 .addReg(MI.getOperand(1).getReg()); 589 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 590 .addReg(PPC::R1) 591 .addImm(maxCallFrameSize); 592 } 593 594 // Discard the DYNALLOC instruction. 595 MBB.erase(II); 596 } 597 598 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 599 int SPAdj, RegScavenger *RS) const { 600 assert(SPAdj == 0 && "Unexpected"); 601 602 // Get the instruction. 603 MachineInstr &MI = *II; 604 // Get the instruction's basic block. 605 MachineBasicBlock &MBB = *MI.getParent(); 606 // Get the basic block's function. 607 MachineFunction &MF = *MBB.getParent(); 608 // Get the frame info. 609 MachineFrameInfo *MFI = MF.getFrameInfo(); 610 611 // Find out which operand is the frame index. 612 unsigned i = 0; 613 while (!MI.getOperand(i).isFrameIndex()) { 614 ++i; 615 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 616 } 617 // Take into account whether it's an add or mem instruction 618 unsigned OffIdx = (i == 2) ? 1 : 2; 619 if (MI.getOpcode() == TargetInstrInfo::INLINEASM) 620 OffIdx = i-1; 621 622 // Get the frame index. 623 int FrameIndex = MI.getOperand(i).getFrameIndex(); 624 625 // Get the frame pointer save index. Users of this index are primarily 626 // DYNALLOC instructions. 627 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 628 int FPSI = FI->getFramePointerSaveIndex(); 629 // Get the instruction opcode. 630 unsigned OpC = MI.getOpcode(); 631 632 // Special case for dynamic alloca. 633 if (FPSI && FrameIndex == FPSI && 634 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 635 lowerDynamicAlloc(II); 636 return; 637 } 638 639 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 640 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false); 641 642 // Figure out if the offset in the instruction is shifted right two bits. This 643 // is true for instructions like "STD", which the machine implicitly adds two 644 // low zeros to. 645 bool isIXAddr = false; 646 switch (OpC) { 647 case PPC::LWA: 648 case PPC::LD: 649 case PPC::STD: 650 case PPC::STD_32: 651 isIXAddr = true; 652 break; 653 } 654 655 // Now add the frame object offset to the offset from r1. 656 int Offset = MFI->getObjectOffset(FrameIndex); 657 658 if (!isIXAddr) 659 Offset += MI.getOperand(OffIdx).getImmedValue(); 660 else 661 Offset += MI.getOperand(OffIdx).getImmedValue() << 2; 662 663 // If we're not using a Frame Pointer that has been set to the value of the 664 // SP before having the stack size subtracted from it, then add the stack size 665 // to Offset to get the correct offset. 666 Offset += MFI->getStackSize(); 667 668 if (!isInt16(Offset)) { 669 // Insert a set of r0 with the full offset value before the ld, st, or add 670 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16); 671 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset); 672 673 // convert into indexed form of the instruction 674 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 675 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 676 assert(ImmToIdxMap.count(OpC) && 677 "No indexed form of load or store available!"); 678 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 679 MI.setInstrDescriptor(TII.get(NewOpcode)); 680 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false); 681 MI.getOperand(2).ChangeToRegister(PPC::R0, false); 682 } else { 683 if (isIXAddr) { 684 assert((Offset & 3) == 0 && "Invalid frame offset!"); 685 Offset >>= 2; // The actual encoded value has the low two bits zero. 686 } 687 MI.getOperand(OffIdx).ChangeToImmediate(Offset); 688 } 689 } 690 691 /// VRRegNo - Map from a numbered VR register to its enum value. 692 /// 693 static const unsigned short VRRegNo[] = { 694 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 695 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 696 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 697 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 698 }; 699 700 /// RemoveVRSaveCode - We have found that this function does not need any code 701 /// to manipulate the VRSAVE register, even though it uses vector registers. 702 /// This can happen when the only registers used are known to be live in or out 703 /// of the function. Remove all of the VRSAVE related code from the function. 704 static void RemoveVRSaveCode(MachineInstr *MI) { 705 MachineBasicBlock *Entry = MI->getParent(); 706 MachineFunction *MF = Entry->getParent(); 707 708 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 709 MachineBasicBlock::iterator MBBI = MI; 710 ++MBBI; 711 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 712 MBBI->eraseFromParent(); 713 714 bool RemovedAllMTVRSAVEs = true; 715 // See if we can find and remove the MTVRSAVE instruction from all of the 716 // epilog blocks. 717 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 718 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 719 // If last instruction is a return instruction, add an epilogue 720 if (!I->empty() && TII.isReturn(I->back().getOpcode())) { 721 bool FoundIt = false; 722 for (MBBI = I->end(); MBBI != I->begin(); ) { 723 --MBBI; 724 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 725 MBBI->eraseFromParent(); // remove it. 726 FoundIt = true; 727 break; 728 } 729 } 730 RemovedAllMTVRSAVEs &= FoundIt; 731 } 732 } 733 734 // If we found and removed all MTVRSAVE instructions, remove the read of 735 // VRSAVE as well. 736 if (RemovedAllMTVRSAVEs) { 737 MBBI = MI; 738 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 739 --MBBI; 740 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 741 MBBI->eraseFromParent(); 742 } 743 744 // Finally, nuke the UPDATE_VRSAVE. 745 MI->eraseFromParent(); 746 } 747 748 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 749 // instruction selector. Based on the vector registers that have been used, 750 // transform this into the appropriate ORI instruction. 751 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 752 MachineFunction *MF = MI->getParent()->getParent(); 753 754 unsigned UsedRegMask = 0; 755 for (unsigned i = 0; i != 32; ++i) 756 if (MF->isPhysRegUsed(VRRegNo[i])) 757 UsedRegMask |= 1 << (31-i); 758 759 // Live in and live out values already must be in the mask, so don't bother 760 // marking them. 761 for (MachineFunction::livein_iterator I = 762 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) { 763 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 764 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 765 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 766 } 767 for (MachineFunction::liveout_iterator I = 768 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) { 769 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 770 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 771 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 772 } 773 774 unsigned SrcReg = MI->getOperand(1).getReg(); 775 unsigned DstReg = MI->getOperand(0).getReg(); 776 // If no registers are used, turn this into a copy. 777 if (UsedRegMask == 0) { 778 // Remove all VRSAVE code. 779 RemoveVRSaveCode(MI); 780 return; 781 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 782 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 783 .addReg(SrcReg).addImm(UsedRegMask); 784 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 785 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 786 .addReg(SrcReg).addImm(UsedRegMask >> 16); 787 } else { 788 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 789 .addReg(SrcReg).addImm(UsedRegMask >> 16); 790 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 791 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 792 } 793 794 // Remove the old UPDATE_VRSAVE instruction. 795 MI->eraseFromParent(); 796 } 797 798 /// determineFrameLayout - Determine the size of the frame and maximum call 799 /// frame size. 800 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 801 MachineFrameInfo *MFI = MF.getFrameInfo(); 802 803 // Get the number of bytes to allocate from the FrameInfo 804 unsigned FrameSize = MFI->getStackSize(); 805 806 // Get the alignments provided by the target, and the maximum alignment 807 // (if any) of the fixed frame objects. 808 unsigned MaxAlign = MFI->getMaxAlignment(); 809 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 810 unsigned AlignMask = TargetAlign - 1; // 811 812 // If we are a leaf function, and use up to 224 bytes of stack space, 813 // don't have a frame pointer, calls, or dynamic alloca then we do not need 814 // to adjust the stack pointer (we fit in the Red Zone). 815 if (FrameSize <= 224 && // Fits in red zone. 816 !MFI->hasVarSizedObjects() && // No dynamic alloca. 817 !MFI->hasCalls() && // No calls. 818 MaxAlign <= TargetAlign) { // No special alignment. 819 // No need for frame 820 MFI->setStackSize(0); 821 return; 822 } 823 824 // Get the maximum call frame size of all the calls. 825 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 826 827 // Maximum call frame needs to be at least big enough for linkage and 8 args. 828 unsigned minCallFrameSize = 829 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), 830 Subtarget.isMachoABI()); 831 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 832 833 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 834 // that allocations will be aligned. 835 if (MFI->hasVarSizedObjects()) 836 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 837 838 // Update maximum call frame size. 839 MFI->setMaxCallFrameSize(maxCallFrameSize); 840 841 // Include call frame size in total. 842 FrameSize += maxCallFrameSize; 843 844 // Make sure the frame is aligned. 845 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 846 847 // Update frame info. 848 MFI->setStackSize(FrameSize); 849 } 850 851 void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 852 RegScavenger *RS) 853 const { 854 // Save and clear the LR state. 855 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 856 unsigned LR = getRARegister(); 857 FI->setUsesLR(MF.isPhysRegUsed(LR)); 858 MF.setPhysRegUnused(LR); 859 860 // Save R31 if necessary 861 int FPSI = FI->getFramePointerSaveIndex(); 862 bool IsPPC64 = Subtarget.isPPC64(); 863 bool IsELF32_ABI = Subtarget.isELF32_ABI(); 864 bool IsMachoABI = Subtarget.isMachoABI(); 865 const MachineFrameInfo *MFI = MF.getFrameInfo(); 866 867 // If the frame pointer save index hasn't been defined yet. 868 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) 869 && IsELF32_ABI) { 870 // Find out what the fix offset of the frame pointer save area. 871 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, 872 IsMachoABI); 873 // Allocate the frame index for frame pointer save area. 874 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 875 // Save the result. 876 FI->setFramePointerSaveIndex(FPSI); 877 } 878 879 } 880 881 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 882 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 883 MachineBasicBlock::iterator MBBI = MBB.begin(); 884 MachineFrameInfo *MFI = MF.getFrameInfo(); 885 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 886 887 // Prepare for frame info. 888 unsigned FrameLabelId = 0; 889 890 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 891 // process it. 892 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 893 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 894 HandleVRSaveUpdate(MBBI, TII); 895 break; 896 } 897 } 898 899 // Move MBBI back to the beginning of the function. 900 MBBI = MBB.begin(); 901 902 // Work out frame sizes. 903 determineFrameLayout(MF); 904 unsigned FrameSize = MFI->getStackSize(); 905 906 int NegFrameSize = -FrameSize; 907 908 // Get processor type. 909 bool IsPPC64 = Subtarget.isPPC64(); 910 // Get operating system 911 bool IsMachoABI = Subtarget.isMachoABI(); 912 // Check if the link register (LR) has been used. 913 bool UsesLR = MFI->hasCalls() || usesLR(MF); 914 // Do we have a frame pointer for this function? 915 bool HasFP = hasFP(MF) && FrameSize; 916 917 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 918 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 919 920 if (IsPPC64) { 921 if (UsesLR) 922 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); 923 924 if (HasFP) 925 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 926 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1); 927 928 if (UsesLR) 929 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 930 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1); 931 } else { 932 if (UsesLR) 933 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); 934 935 if (HasFP) 936 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 937 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1); 938 939 if (UsesLR) 940 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 941 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1); 942 } 943 944 // Skip if a leaf routine. 945 if (!FrameSize) return; 946 947 // Get stack alignments. 948 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 949 unsigned MaxAlign = MFI->getMaxAlignment(); 950 951 if (MMI && MMI->needsFrameInfo()) { 952 // Mark effective beginning of when frame pointer becomes valid. 953 FrameLabelId = MMI->NextLabelID(); 954 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId); 955 } 956 957 // Adjust stack pointer: r1 += NegFrameSize. 958 // If there is a preferred stack alignment, align R1 now 959 if (!IsPPC64) { 960 // PPC32. 961 if (MaxAlign > TargetAlign) { 962 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 963 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 964 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) 965 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 966 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0) 967 .addImm(NegFrameSize); 968 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 969 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 970 } else if (isInt16(NegFrameSize)) { 971 BuildMI(MBB, MBBI, TII.get(PPC::STWU), 972 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1); 973 } else { 974 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16); 975 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0) 976 .addImm(NegFrameSize & 0xFFFF); 977 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1) 978 .addReg(PPC::R0); 979 } 980 } else { // PPC64. 981 if (MaxAlign > TargetAlign) { 982 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 983 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 984 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) 985 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign)); 986 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0) 987 .addImm(NegFrameSize); 988 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 989 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0); 990 } else if (isInt16(NegFrameSize)) { 991 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) 992 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1); 993 } else { 994 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16); 995 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0) 996 .addImm(NegFrameSize & 0xFFFF); 997 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1) 998 .addReg(PPC::X0); 999 } 1000 } 1001 1002 if (MMI && MMI->needsFrameInfo()) { 1003 std::vector<MachineMove> &Moves = MMI->getFrameMoves(); 1004 1005 if (NegFrameSize) { 1006 // Show update of SP. 1007 MachineLocation SPDst(MachineLocation::VirtualFP); 1008 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 1009 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); 1010 } else { 1011 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31); 1012 Moves.push_back(MachineMove(FrameLabelId, SP, SP)); 1013 } 1014 1015 if (HasFP) { 1016 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 1017 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31); 1018 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); 1019 } 1020 1021 // Add callee saved registers to move list. 1022 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1023 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1024 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1025 unsigned Reg = CSI[I].getReg(); 1026 if (Reg == PPC::LR || Reg == PPC::LR8) continue; 1027 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 1028 MachineLocation CSSrc(Reg); 1029 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); 1030 } 1031 1032 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 1033 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR); 1034 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc)); 1035 1036 // Mark effective beginning of when frame pointer is ready. 1037 unsigned ReadyLabelId = MMI->NextLabelID(); 1038 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId); 1039 1040 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : 1041 (IsPPC64 ? PPC::X1 : PPC::R1)); 1042 MachineLocation FPSrc(MachineLocation::VirtualFP); 1043 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); 1044 } 1045 1046 // If there is a frame pointer, copy R1 into R31 1047 if (HasFP) { 1048 if (!IsPPC64) { 1049 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1) 1050 .addReg(PPC::R1); 1051 } else { 1052 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1) 1053 .addReg(PPC::X1); 1054 } 1055 } 1056 } 1057 1058 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 1059 MachineBasicBlock &MBB) const { 1060 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1061 assert(MBBI->getOpcode() == PPC::BLR && 1062 "Can only insert epilog into returning blocks"); 1063 1064 // Get alignment info so we know how to restore r1 1065 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1066 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1067 unsigned MaxAlign = MFI->getMaxAlignment(); 1068 1069 // Get the number of bytes allocated from the FrameInfo. 1070 unsigned FrameSize = MFI->getStackSize(); 1071 1072 // Get processor type. 1073 bool IsPPC64 = Subtarget.isPPC64(); 1074 // Get operating system 1075 bool IsMachoABI = Subtarget.isMachoABI(); 1076 // Check if the link register (LR) has been used. 1077 bool UsesLR = MFI->hasCalls() || usesLR(MF); 1078 // Do we have a frame pointer for this function? 1079 bool HasFP = hasFP(MF) && FrameSize; 1080 1081 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 1082 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 1083 1084 if (FrameSize) { 1085 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 1086 // on entry to the function. Add this offset back now. 1087 if (!Subtarget.isPPC64()) { 1088 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1089 !MFI->hasVarSizedObjects()) { 1090 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) 1091 .addReg(PPC::R1).addImm(FrameSize); 1092 } else { 1093 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); 1094 } 1095 } else { 1096 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1097 !MFI->hasVarSizedObjects()) { 1098 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) 1099 .addReg(PPC::X1).addImm(FrameSize); 1100 } else { 1101 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); 1102 } 1103 } 1104 } 1105 1106 if (IsPPC64) { 1107 if (UsesLR) 1108 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) 1109 .addImm(LROffset/4).addReg(PPC::X1); 1110 1111 if (HasFP) 1112 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) 1113 .addImm(FPOffset/4).addReg(PPC::X1); 1114 1115 if (UsesLR) 1116 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); 1117 } else { 1118 if (UsesLR) 1119 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) 1120 .addImm(LROffset).addReg(PPC::R1); 1121 1122 if (HasFP) 1123 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) 1124 .addImm(FPOffset).addReg(PPC::R1); 1125 1126 if (UsesLR) 1127 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); 1128 } 1129 } 1130 1131 unsigned PPCRegisterInfo::getRARegister() const { 1132 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1133 } 1134 1135 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1136 if (!Subtarget.isPPC64()) 1137 return hasFP(MF) ? PPC::R31 : PPC::R1; 1138 else 1139 return hasFP(MF) ? PPC::X31 : PPC::X1; 1140 } 1141 1142 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1143 const { 1144 // Initial state of the frame pointer is R1. 1145 MachineLocation Dst(MachineLocation::VirtualFP); 1146 MachineLocation Src(PPC::R1, 0); 1147 Moves.push_back(MachineMove(0, Dst, Src)); 1148 } 1149 1150 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 1151 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 1152 } 1153 1154 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 1155 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 1156 } 1157 1158 #include "PPCGenRegisterInfo.inc" 1159 1160