1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "PPCRegisterInfo.h" 16 #include "PPC.h" 17 #include "PPCFrameLowering.h" 18 #include "PPCInstrBuilder.h" 19 #include "PPCMachineFunctionInfo.h" 20 #include "PPCSubtarget.h" 21 #include "llvm/ADT/BitVector.h" 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineModuleInfo.h" 27 #include "llvm/CodeGen/MachineRegisterInfo.h" 28 #include "llvm/CodeGen/RegisterScavenging.h" 29 #include "llvm/IR/CallingConv.h" 30 #include "llvm/IR/Constants.h" 31 #include "llvm/IR/Function.h" 32 #include "llvm/IR/Type.h" 33 #include "llvm/Support/CommandLine.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/Support/raw_ostream.h" 38 #include "llvm/Target/TargetFrameLowering.h" 39 #include "llvm/Target/TargetInstrInfo.h" 40 #include "llvm/Target/TargetMachine.h" 41 #include "llvm/Target/TargetOptions.h" 42 #include <cstdlib> 43 44 using namespace llvm; 45 46 #define DEBUG_TYPE "reginfo" 47 48 #define GET_REGINFO_TARGET_DESC 49 #include "PPCGenRegisterInfo.inc" 50 51 static cl::opt<bool> 52 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), 53 cl::desc("Enable use of a base pointer for complex stack frames")); 54 55 static cl::opt<bool> 56 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), 57 cl::desc("Force the use of a base pointer in every function")); 58 59 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST) 60 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 61 ST.isPPC64() ? 0 : 1, 62 ST.isPPC64() ? 0 : 1), 63 Subtarget(ST) { 64 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 65 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 66 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 67 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 68 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 69 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 70 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 71 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 72 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; 73 74 // 64-bit 75 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 76 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 77 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 78 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 79 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 80 } 81 82 /// getPointerRegClass - Return the register class to use to hold pointers. 83 /// This is used for addressing modes. 84 const TargetRegisterClass * 85 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 86 const { 87 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value 88 // when it checks for ZERO folding. 89 if (Kind == 1) { 90 if (Subtarget.isPPC64()) 91 return &PPC::G8RC_NOX0RegClass; 92 return &PPC::GPRC_NOR0RegClass; 93 } 94 95 if (Subtarget.isPPC64()) 96 return &PPC::G8RCRegClass; 97 return &PPC::GPRCRegClass; 98 } 99 100 const MCPhysReg* 101 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 102 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) { 103 if (Subtarget.hasVSX()) 104 return CSR_64_AllRegs_VSX_SaveList; 105 if (Subtarget.hasAltivec()) 106 return CSR_64_AllRegs_Altivec_SaveList; 107 return CSR_64_AllRegs_SaveList; 108 } 109 110 if (Subtarget.isDarwinABI()) 111 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 112 CSR_Darwin64_Altivec_SaveList : 113 CSR_Darwin64_SaveList) : 114 (Subtarget.hasAltivec() ? 115 CSR_Darwin32_Altivec_SaveList : 116 CSR_Darwin32_SaveList); 117 118 // On PPC64, we might need to save r2 (but only if it is not reserved). 119 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); 120 121 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 122 (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : 123 CSR_SVR464_Altivec_SaveList) : 124 (SaveR2 ? CSR_SVR464_R2_SaveList : 125 CSR_SVR464_SaveList)) : 126 (Subtarget.hasAltivec() ? 127 CSR_SVR432_Altivec_SaveList : 128 CSR_SVR432_SaveList); 129 } 130 131 const uint32_t* 132 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 133 if (CC == CallingConv::AnyReg) { 134 if (Subtarget.hasVSX()) 135 return CSR_64_AllRegs_VSX_RegMask; 136 if (Subtarget.hasAltivec()) 137 return CSR_64_AllRegs_Altivec_RegMask; 138 return CSR_64_AllRegs_RegMask; 139 } 140 141 if (Subtarget.isDarwinABI()) 142 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 143 CSR_Darwin64_Altivec_RegMask : 144 CSR_Darwin64_RegMask) : 145 (Subtarget.hasAltivec() ? 146 CSR_Darwin32_Altivec_RegMask : 147 CSR_Darwin32_RegMask); 148 149 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 150 CSR_SVR464_Altivec_RegMask : 151 CSR_SVR464_RegMask) : 152 (Subtarget.hasAltivec() ? 153 CSR_SVR432_Altivec_RegMask : 154 CSR_SVR432_RegMask); 155 } 156 157 const uint32_t* 158 PPCRegisterInfo::getNoPreservedMask() const { 159 return CSR_NoRegs_RegMask; 160 } 161 162 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const { 163 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM}) 164 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32)); 165 } 166 167 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 168 BitVector Reserved(getNumRegs()); 169 const PPCFrameLowering *PPCFI = 170 static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering()); 171 172 // The ZERO register is not really a register, but the representation of r0 173 // when used in instructions that treat r0 as the constant 0. 174 Reserved.set(PPC::ZERO); 175 Reserved.set(PPC::ZERO8); 176 177 // The FP register is also not really a register, but is the representation 178 // of the frame pointer register used by ISD::FRAMEADDR. 179 Reserved.set(PPC::FP); 180 Reserved.set(PPC::FP8); 181 182 // The BP register is also not really a register, but is the representation 183 // of the base pointer register used by setjmp. 184 Reserved.set(PPC::BP); 185 Reserved.set(PPC::BP8); 186 187 // The counter registers must be reserved so that counter-based loops can 188 // be correctly formed (and the mtctr instructions are not DCE'd). 189 Reserved.set(PPC::CTR); 190 Reserved.set(PPC::CTR8); 191 192 Reserved.set(PPC::R1); 193 Reserved.set(PPC::LR); 194 Reserved.set(PPC::LR8); 195 Reserved.set(PPC::RM); 196 197 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec()) 198 Reserved.set(PPC::VRSAVE); 199 200 // The SVR4 ABI reserves r2 and r13 201 if (Subtarget.isSVR4ABI()) { 202 Reserved.set(PPC::R2); // System-reserved register 203 Reserved.set(PPC::R13); // Small Data Area pointer register 204 } 205 206 // On PPC64, r13 is the thread pointer. Never allocate this register. 207 if (Subtarget.isPPC64()) { 208 Reserved.set(PPC::R13); 209 210 Reserved.set(PPC::X1); 211 Reserved.set(PPC::X13); 212 213 if (PPCFI->needsFP(MF)) 214 Reserved.set(PPC::X31); 215 216 if (hasBasePointer(MF)) 217 Reserved.set(PPC::X30); 218 219 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 220 if (Subtarget.isSVR4ABI()) { 221 // We only reserve r2 if we need to use the TOC pointer. If we have no 222 // explicit uses of the TOC pointer (meaning we're a leaf function with 223 // no constant-pool loads, etc.) and we have no potential uses inside an 224 // inline asm block, then we can treat r2 has an ordinary callee-saved 225 // register. 226 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 227 if (FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm()) 228 Reserved.set(PPC::X2); 229 else 230 Reserved.reset(PPC::R2); 231 } 232 } 233 234 if (PPCFI->needsFP(MF)) 235 Reserved.set(PPC::R31); 236 237 if (hasBasePointer(MF)) { 238 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() && 239 MF.getTarget().getRelocationModel() == Reloc::PIC_) 240 Reserved.set(PPC::R29); 241 else 242 Reserved.set(PPC::R30); 243 } 244 245 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() && 246 MF.getTarget().getRelocationModel() == Reloc::PIC_) 247 Reserved.set(PPC::R30); 248 249 // Reserve Altivec registers when Altivec is unavailable. 250 if (!Subtarget.hasAltivec()) 251 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(), 252 IE = PPC::VRRCRegClass.end(); I != IE; ++I) 253 Reserved.set(*I); 254 255 return Reserved; 256 } 257 258 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 259 MachineFunction &MF) const { 260 const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); 261 const unsigned DefaultSafety = 1; 262 263 switch (RC->getID()) { 264 default: 265 return 0; 266 case PPC::G8RC_NOX0RegClassID: 267 case PPC::GPRC_NOR0RegClassID: 268 case PPC::G8RCRegClassID: 269 case PPC::GPRCRegClassID: { 270 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 271 return 32 - FP - DefaultSafety; 272 } 273 case PPC::F8RCRegClassID: 274 case PPC::F4RCRegClassID: 275 case PPC::QFRCRegClassID: 276 case PPC::QSRCRegClassID: 277 case PPC::QBRCRegClassID: 278 case PPC::VRRCRegClassID: 279 case PPC::VFRCRegClassID: 280 case PPC::VSLRCRegClassID: 281 case PPC::VSHRCRegClassID: 282 return 32 - DefaultSafety; 283 case PPC::VSRCRegClassID: 284 case PPC::VSFRCRegClassID: 285 return 64 - DefaultSafety; 286 case PPC::CRRCRegClassID: 287 return 8 - DefaultSafety; 288 } 289 } 290 291 const TargetRegisterClass * 292 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, 293 const MachineFunction &MF) const { 294 if (Subtarget.hasVSX()) { 295 // With VSX, we can inflate various sub-register classes to the full VSX 296 // register set. 297 298 if (RC == &PPC::F8RCRegClass) 299 return &PPC::VSFRCRegClass; 300 else if (RC == &PPC::VRRCRegClass) 301 return &PPC::VSRCRegClass; 302 } 303 304 return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF); 305 } 306 307 //===----------------------------------------------------------------------===// 308 // Stack Frame Processing methods 309 //===----------------------------------------------------------------------===// 310 311 /// lowerDynamicAlloc - Generate the code for allocating an object in the 312 /// current frame. The sequence of code with be in the general form 313 /// 314 /// addi R0, SP, \#frameSize ; get the address of the previous frame 315 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 316 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 317 /// 318 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 319 // Get the instruction. 320 MachineInstr &MI = *II; 321 // Get the instruction's basic block. 322 MachineBasicBlock &MBB = *MI.getParent(); 323 // Get the basic block's function. 324 MachineFunction &MF = *MBB.getParent(); 325 // Get the frame info. 326 MachineFrameInfo *MFI = MF.getFrameInfo(); 327 // Get the instruction info. 328 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 329 // Determine whether 64-bit pointers are used. 330 bool LP64 = Subtarget.isPPC64(); 331 DebugLoc dl = MI.getDebugLoc(); 332 333 // Get the maximum call stack size. 334 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 335 // Get the total frame size. 336 unsigned FrameSize = MFI->getStackSize(); 337 338 // Get stack alignments. 339 unsigned TargetAlign = Subtarget.getFrameLowering()->getStackAlignment(); 340 unsigned MaxAlign = MFI->getMaxAlignment(); 341 assert((maxCallFrameSize & (MaxAlign-1)) == 0 && 342 "Maximum call-frame size not sufficiently aligned"); 343 344 // Determine the previous frame's address. If FrameSize can't be 345 // represented as 16 bits or we need special alignment, then we load the 346 // previous frame's address from 0(SP). Why not do an addis of the hi? 347 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 348 // Constructing the constant and adding would take 3 instructions. 349 // Fortunately, a frame greater than 32K is rare. 350 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 351 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 352 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 353 354 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 355 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 356 .addReg(PPC::R31) 357 .addImm(FrameSize); 358 } else if (LP64) { 359 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 360 .addImm(0) 361 .addReg(PPC::X1); 362 } else { 363 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 364 .addImm(0) 365 .addReg(PPC::R1); 366 } 367 368 bool KillNegSizeReg = MI.getOperand(1).isKill(); 369 unsigned NegSizeReg = MI.getOperand(1).getReg(); 370 371 // Grow the stack and update the stack pointer link, then determine the 372 // address of new allocated space. 373 if (LP64) { 374 if (MaxAlign > TargetAlign) { 375 unsigned UnalNegSizeReg = NegSizeReg; 376 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 377 378 // Unfortunately, there is no andi, only andi., and we can't insert that 379 // here because we might clobber cr0 while it is live. 380 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) 381 .addImm(~(MaxAlign-1)); 382 383 unsigned NegSizeReg1 = NegSizeReg; 384 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 385 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) 386 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 387 .addReg(NegSizeReg1, RegState::Kill); 388 KillNegSizeReg = true; 389 } 390 391 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 392 .addReg(Reg, RegState::Kill) 393 .addReg(PPC::X1) 394 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 395 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 396 .addReg(PPC::X1) 397 .addImm(maxCallFrameSize); 398 } else { 399 if (MaxAlign > TargetAlign) { 400 unsigned UnalNegSizeReg = NegSizeReg; 401 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 402 403 // Unfortunately, there is no andi, only andi., and we can't insert that 404 // here because we might clobber cr0 while it is live. 405 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) 406 .addImm(~(MaxAlign-1)); 407 408 unsigned NegSizeReg1 = NegSizeReg; 409 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 410 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) 411 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 412 .addReg(NegSizeReg1, RegState::Kill); 413 KillNegSizeReg = true; 414 } 415 416 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 417 .addReg(Reg, RegState::Kill) 418 .addReg(PPC::R1) 419 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 420 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 421 .addReg(PPC::R1) 422 .addImm(maxCallFrameSize); 423 } 424 425 // Discard the DYNALLOC instruction. 426 MBB.erase(II); 427 } 428 429 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 430 /// reserving a whole register (R0), we scrounge for one here. This generates 431 /// code like this: 432 /// 433 /// mfcr rA ; Move the conditional register into GPR rA. 434 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 435 /// stw rA, FI ; Store rA to the frame. 436 /// 437 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 438 unsigned FrameIndex) const { 439 // Get the instruction. 440 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 441 // Get the instruction's basic block. 442 MachineBasicBlock &MBB = *MI.getParent(); 443 MachineFunction &MF = *MBB.getParent(); 444 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 445 DebugLoc dl = MI.getDebugLoc(); 446 447 bool LP64 = Subtarget.isPPC64(); 448 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 449 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 450 451 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 452 unsigned SrcReg = MI.getOperand(0).getReg(); 453 454 // We need to store the CR in the low 4-bits of the saved value. First, issue 455 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg. 456 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 457 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 458 459 // If the saved register wasn't CR0, shift the bits left so that they are in 460 // CR0's slot. 461 if (SrcReg != PPC::CR0) { 462 unsigned Reg1 = Reg; 463 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 464 465 // rlwinm rA, rA, ShiftBits, 0, 31. 466 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 467 .addReg(Reg1, RegState::Kill) 468 .addImm(getEncodingValue(SrcReg) * 4) 469 .addImm(0) 470 .addImm(31); 471 } 472 473 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 474 .addReg(Reg, RegState::Kill), 475 FrameIndex); 476 477 // Discard the pseudo instruction. 478 MBB.erase(II); 479 } 480 481 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 482 unsigned FrameIndex) const { 483 // Get the instruction. 484 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 485 // Get the instruction's basic block. 486 MachineBasicBlock &MBB = *MI.getParent(); 487 MachineFunction &MF = *MBB.getParent(); 488 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 489 DebugLoc dl = MI.getDebugLoc(); 490 491 bool LP64 = Subtarget.isPPC64(); 492 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 493 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 494 495 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 496 unsigned DestReg = MI.getOperand(0).getReg(); 497 assert(MI.definesRegister(DestReg) && 498 "RESTORE_CR does not define its destination"); 499 500 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 501 Reg), FrameIndex); 502 503 // If the reloaded register isn't CR0, shift the bits right so that they are 504 // in the right CR's slot. 505 if (DestReg != PPC::CR0) { 506 unsigned Reg1 = Reg; 507 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 508 509 unsigned ShiftBits = getEncodingValue(DestReg)*4; 510 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 511 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 512 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 513 .addImm(31); 514 } 515 516 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) 517 .addReg(Reg, RegState::Kill); 518 519 // Discard the pseudo instruction. 520 MBB.erase(II); 521 } 522 523 static unsigned getCRFromCRBit(unsigned SrcReg) { 524 unsigned Reg = 0; 525 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 526 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 527 Reg = PPC::CR0; 528 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 529 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 530 Reg = PPC::CR1; 531 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 532 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 533 Reg = PPC::CR2; 534 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 535 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 536 Reg = PPC::CR3; 537 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 538 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 539 Reg = PPC::CR4; 540 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 541 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 542 Reg = PPC::CR5; 543 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 544 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 545 Reg = PPC::CR6; 546 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 547 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 548 Reg = PPC::CR7; 549 550 assert(Reg != 0 && "Invalid CR bit register"); 551 return Reg; 552 } 553 554 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, 555 unsigned FrameIndex) const { 556 // Get the instruction. 557 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset> 558 // Get the instruction's basic block. 559 MachineBasicBlock &MBB = *MI.getParent(); 560 MachineFunction &MF = *MBB.getParent(); 561 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 562 DebugLoc dl = MI.getDebugLoc(); 563 564 bool LP64 = Subtarget.isPPC64(); 565 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 566 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 567 568 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 569 unsigned SrcReg = MI.getOperand(0).getReg(); 570 571 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL), 572 getCRFromCRBit(SrcReg)) 573 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 574 575 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 576 .addReg(getCRFromCRBit(SrcReg)); 577 578 // If the saved register wasn't CR0LT, shift the bits left so that the bit to 579 // store is the first one. Mask all but that bit. 580 unsigned Reg1 = Reg; 581 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 582 583 // rlwinm rA, rA, ShiftBits, 0, 0. 584 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 585 .addReg(Reg1, RegState::Kill) 586 .addImm(getEncodingValue(SrcReg)) 587 .addImm(0).addImm(0); 588 589 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 590 .addReg(Reg, RegState::Kill), 591 FrameIndex); 592 593 // Discard the pseudo instruction. 594 MBB.erase(II); 595 } 596 597 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, 598 unsigned FrameIndex) const { 599 // Get the instruction. 600 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset> 601 // Get the instruction's basic block. 602 MachineBasicBlock &MBB = *MI.getParent(); 603 MachineFunction &MF = *MBB.getParent(); 604 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 605 DebugLoc dl = MI.getDebugLoc(); 606 607 bool LP64 = Subtarget.isPPC64(); 608 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 609 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 610 611 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 612 unsigned DestReg = MI.getOperand(0).getReg(); 613 assert(MI.definesRegister(DestReg) && 614 "RESTORE_CRBIT does not define its destination"); 615 616 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 617 Reg), FrameIndex); 618 619 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg); 620 621 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 622 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) 623 .addReg(getCRFromCRBit(DestReg)); 624 625 unsigned ShiftBits = getEncodingValue(DestReg); 626 // rlwimi r11, r10, 32-ShiftBits, ..., ... 627 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) 628 .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill) 629 .addImm(ShiftBits ? 32-ShiftBits : 0) 630 .addImm(ShiftBits).addImm(ShiftBits); 631 632 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), 633 getCRFromCRBit(DestReg)) 634 .addReg(RegO, RegState::Kill) 635 // Make sure we have a use dependency all the way through this 636 // sequence of instructions. We can't have the other bits in the CR 637 // modified in between the mfocrf and the mtocrf. 638 .addReg(getCRFromCRBit(DestReg), RegState::Implicit); 639 640 // Discard the pseudo instruction. 641 MBB.erase(II); 642 } 643 644 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, 645 unsigned FrameIndex) const { 646 // Get the instruction. 647 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> 648 // Get the instruction's basic block. 649 MachineBasicBlock &MBB = *MI.getParent(); 650 MachineFunction &MF = *MBB.getParent(); 651 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 652 DebugLoc dl = MI.getDebugLoc(); 653 654 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 655 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 656 unsigned SrcReg = MI.getOperand(0).getReg(); 657 658 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) 659 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 660 661 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 662 .addReg(Reg, RegState::Kill), 663 FrameIndex); 664 665 // Discard the pseudo instruction. 666 MBB.erase(II); 667 } 668 669 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, 670 unsigned FrameIndex) const { 671 // Get the instruction. 672 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> 673 // Get the instruction's basic block. 674 MachineBasicBlock &MBB = *MI.getParent(); 675 MachineFunction &MF = *MBB.getParent(); 676 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 677 DebugLoc dl = MI.getDebugLoc(); 678 679 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 680 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 681 unsigned DestReg = MI.getOperand(0).getReg(); 682 assert(MI.definesRegister(DestReg) && 683 "RESTORE_VRSAVE does not define its destination"); 684 685 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), 686 Reg), FrameIndex); 687 688 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) 689 .addReg(Reg, RegState::Kill); 690 691 // Discard the pseudo instruction. 692 MBB.erase(II); 693 } 694 695 bool 696 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 697 unsigned Reg, int &FrameIdx) const { 698 699 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 700 // ABI, return true to prevent allocating an additional frame slot. 701 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 702 // is arbitrary and will be subsequently ignored. For 32-bit, we have 703 // previously created the stack slot if needed, so return its FrameIdx. 704 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 705 if (Subtarget.isPPC64()) 706 FrameIdx = 0; 707 else { 708 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 709 FrameIdx = FI->getCRSpillFrameIndex(); 710 } 711 return true; 712 } 713 return false; 714 } 715 716 // Figure out if the offset in the instruction must be a multiple of 4. 717 // This is true for instructions like "STD". 718 static bool usesIXAddr(const MachineInstr &MI) { 719 unsigned OpC = MI.getOpcode(); 720 721 switch (OpC) { 722 default: 723 return false; 724 case PPC::LWA: 725 case PPC::LWA_32: 726 case PPC::LD: 727 case PPC::STD: 728 return true; 729 } 730 } 731 732 // Return the OffsetOperandNo given the FIOperandNum (and the instruction). 733 static unsigned getOffsetONFromFION(const MachineInstr &MI, 734 unsigned FIOperandNum) { 735 // Take into account whether it's an add or mem instruction 736 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 737 if (MI.isInlineAsm()) 738 OffsetOperandNo = FIOperandNum - 1; 739 else if (MI.getOpcode() == TargetOpcode::STACKMAP || 740 MI.getOpcode() == TargetOpcode::PATCHPOINT) 741 OffsetOperandNo = FIOperandNum + 1; 742 743 return OffsetOperandNo; 744 } 745 746 void 747 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 748 int SPAdj, unsigned FIOperandNum, 749 RegScavenger *RS) const { 750 assert(SPAdj == 0 && "Unexpected"); 751 752 // Get the instruction. 753 MachineInstr &MI = *II; 754 // Get the instruction's basic block. 755 MachineBasicBlock &MBB = *MI.getParent(); 756 // Get the basic block's function. 757 MachineFunction &MF = *MBB.getParent(); 758 // Get the instruction info. 759 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 760 // Get the frame info. 761 MachineFrameInfo *MFI = MF.getFrameInfo(); 762 DebugLoc dl = MI.getDebugLoc(); 763 764 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 765 766 // Get the frame index. 767 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 768 769 // Get the frame pointer save index. Users of this index are primarily 770 // DYNALLOC instructions. 771 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 772 int FPSI = FI->getFramePointerSaveIndex(); 773 // Get the instruction opcode. 774 unsigned OpC = MI.getOpcode(); 775 776 // Special case for dynamic alloca. 777 if (FPSI && FrameIndex == FPSI && 778 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 779 lowerDynamicAlloc(II); 780 return; 781 } 782 783 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 784 if (OpC == PPC::SPILL_CR) { 785 lowerCRSpilling(II, FrameIndex); 786 return; 787 } else if (OpC == PPC::RESTORE_CR) { 788 lowerCRRestore(II, FrameIndex); 789 return; 790 } else if (OpC == PPC::SPILL_CRBIT) { 791 lowerCRBitSpilling(II, FrameIndex); 792 return; 793 } else if (OpC == PPC::RESTORE_CRBIT) { 794 lowerCRBitRestore(II, FrameIndex); 795 return; 796 } else if (OpC == PPC::SPILL_VRSAVE) { 797 lowerVRSAVESpilling(II, FrameIndex); 798 return; 799 } else if (OpC == PPC::RESTORE_VRSAVE) { 800 lowerVRSAVERestore(II, FrameIndex); 801 return; 802 } 803 804 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 805 MI.getOperand(FIOperandNum).ChangeToRegister( 806 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false); 807 808 // Figure out if the offset in the instruction is shifted right two bits. 809 bool isIXAddr = usesIXAddr(MI); 810 811 // If the instruction is not present in ImmToIdxMap, then it has no immediate 812 // form (and must be r+r). 813 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP && 814 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC); 815 816 // Now add the frame object offset to the offset from r1. 817 int Offset = MFI->getObjectOffset(FrameIndex); 818 Offset += MI.getOperand(OffsetOperandNo).getImm(); 819 820 // If we're not using a Frame Pointer that has been set to the value of the 821 // SP before having the stack size subtracted from it, then add the stack size 822 // to Offset to get the correct offset. 823 // Naked functions have stack size 0, although getStackSize may not reflect that 824 // because we didn't call all the pieces that compute it for naked functions. 825 if (!MF.getFunction()->hasFnAttribute(Attribute::Naked)) { 826 if (!(hasBasePointer(MF) && FrameIndex < 0)) 827 Offset += MFI->getStackSize(); 828 } 829 830 // If we can, encode the offset directly into the instruction. If this is a 831 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 832 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 833 // clear can be encoded. This is extremely uncommon, because normally you 834 // only "std" to a stack slot that is at least 4-byte aligned, but it can 835 // happen in invalid code. 836 assert(OpC != PPC::DBG_VALUE && 837 "This should be handled in a target-independent way"); 838 if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) || 839 OpC == TargetOpcode::STACKMAP || 840 OpC == TargetOpcode::PATCHPOINT)) { 841 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 842 return; 843 } 844 845 // The offset doesn't fit into a single register, scavenge one to build the 846 // offset in. 847 848 bool is64Bit = Subtarget.isPPC64(); 849 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 850 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 851 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; 852 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), 853 SReg = MF.getRegInfo().createVirtualRegister(RC); 854 855 // Insert a set of rA with the full offset value before the ld, st, or add 856 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) 857 .addImm(Offset >> 16); 858 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 859 .addReg(SRegHi, RegState::Kill) 860 .addImm(Offset); 861 862 // Convert into indexed form of the instruction: 863 // 864 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 865 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 866 unsigned OperandBase; 867 868 if (noImmForm) 869 OperandBase = 1; 870 else if (OpC != TargetOpcode::INLINEASM) { 871 assert(ImmToIdxMap.count(OpC) && 872 "No indexed form of load or store available!"); 873 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 874 MI.setDesc(TII.get(NewOpcode)); 875 OperandBase = 1; 876 } else { 877 OperandBase = OffsetOperandNo; 878 } 879 880 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 881 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 882 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 883 } 884 885 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 886 const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); 887 888 if (!Subtarget.isPPC64()) 889 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 890 else 891 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 892 } 893 894 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const { 895 if (!hasBasePointer(MF)) 896 return getFrameRegister(MF); 897 898 if (Subtarget.isPPC64()) 899 return PPC::X30; 900 901 if (Subtarget.isSVR4ABI() && 902 MF.getTarget().getRelocationModel() == Reloc::PIC_) 903 return PPC::R29; 904 905 return PPC::R30; 906 } 907 908 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 909 if (!EnableBasePointer) 910 return false; 911 if (AlwaysBasePointer) 912 return true; 913 914 // If we need to realign the stack, then the stack pointer can no longer 915 // serve as an offset into the caller's stack space. As a result, we need a 916 // base pointer. 917 return needsStackRealignment(MF); 918 } 919 920 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const { 921 if (MF.getFunction()->hasFnAttribute("no-realign-stack")) 922 return false; 923 924 return true; 925 } 926 927 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const { 928 const MachineFrameInfo *MFI = MF.getFrameInfo(); 929 const Function *F = MF.getFunction(); 930 unsigned StackAlign = Subtarget.getFrameLowering()->getStackAlignment(); 931 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || 932 F->hasFnAttribute(Attribute::StackAlignment)); 933 934 return requiresRealignment && canRealignStack(MF); 935 } 936 937 /// Returns true if the instruction's frame index 938 /// reference would be better served by a base register other than FP 939 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 940 /// references it should create new base registers for. 941 bool PPCRegisterInfo:: 942 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 943 assert(Offset < 0 && "Local offset must be negative"); 944 945 // It's the load/store FI references that cause issues, as it can be difficult 946 // to materialize the offset if it won't fit in the literal field. Estimate 947 // based on the size of the local frame and some conservative assumptions 948 // about the rest of the stack frame (note, this is pre-regalloc, so 949 // we don't know everything for certain yet) whether this offset is likely 950 // to be out of range of the immediate. Return true if so. 951 952 // We only generate virtual base registers for loads and stores that have 953 // an r+i form. Return false for everything else. 954 unsigned OpC = MI->getOpcode(); 955 if (!ImmToIdxMap.count(OpC)) 956 return false; 957 958 // Don't generate a new virtual base register just to add zero to it. 959 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && 960 MI->getOperand(2).getImm() == 0) 961 return false; 962 963 MachineBasicBlock &MBB = *MI->getParent(); 964 MachineFunction &MF = *MBB.getParent(); 965 966 const PPCFrameLowering *PPCFI = 967 static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering()); 968 unsigned StackEst = 969 PPCFI->determineFrameLayout(MF, false, true); 970 971 // If we likely don't need a stack frame, then we probably don't need a 972 // virtual base register either. 973 if (!StackEst) 974 return false; 975 976 // Estimate an offset from the stack pointer. 977 // The incoming offset is relating to the SP at the start of the function, 978 // but when we access the local it'll be relative to the SP after local 979 // allocation, so adjust our SP-relative offset by that allocation size. 980 Offset += StackEst; 981 982 // The frame pointer will point to the end of the stack, so estimate the 983 // offset as the difference between the object offset and the FP location. 984 return !isFrameOffsetLegal(MI, Offset); 985 } 986 987 /// Insert defining instruction(s) for BaseReg to 988 /// be a pointer to FrameIdx at the beginning of the basic block. 989 void PPCRegisterInfo:: 990 materializeFrameBaseRegister(MachineBasicBlock *MBB, 991 unsigned BaseReg, int FrameIdx, 992 int64_t Offset) const { 993 unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI; 994 995 MachineBasicBlock::iterator Ins = MBB->begin(); 996 DebugLoc DL; // Defaults to "unknown" 997 if (Ins != MBB->end()) 998 DL = Ins->getDebugLoc(); 999 1000 const MachineFunction &MF = *MBB->getParent(); 1001 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1002 const MCInstrDesc &MCID = TII.get(ADDriOpc); 1003 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 1004 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 1005 1006 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 1007 .addFrameIndex(FrameIdx).addImm(Offset); 1008 } 1009 1010 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 1011 int64_t Offset) const { 1012 unsigned FIOperandNum = 0; 1013 while (!MI.getOperand(FIOperandNum).isFI()) { 1014 ++FIOperandNum; 1015 assert(FIOperandNum < MI.getNumOperands() && 1016 "Instr doesn't have FrameIndex operand!"); 1017 } 1018 1019 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); 1020 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 1021 Offset += MI.getOperand(OffsetOperandNo).getImm(); 1022 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 1023 1024 MachineBasicBlock &MBB = *MI.getParent(); 1025 MachineFunction &MF = *MBB.getParent(); 1026 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1027 const MCInstrDesc &MCID = MI.getDesc(); 1028 MachineRegisterInfo &MRI = MF.getRegInfo(); 1029 MRI.constrainRegClass(BaseReg, 1030 TII.getRegClass(MCID, FIOperandNum, this, MF)); 1031 } 1032 1033 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 1034 int64_t Offset) const { 1035 unsigned FIOperandNum = 0; 1036 while (!MI->getOperand(FIOperandNum).isFI()) { 1037 ++FIOperandNum; 1038 assert(FIOperandNum < MI->getNumOperands() && 1039 "Instr doesn't have FrameIndex operand!"); 1040 } 1041 1042 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); 1043 Offset += MI->getOperand(OffsetOperandNo).getImm(); 1044 1045 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 1046 MI->getOpcode() == TargetOpcode::STACKMAP || 1047 MI->getOpcode() == TargetOpcode::PATCHPOINT || 1048 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0)); 1049 } 1050 1051