1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPCRegisterInfo.h" 17 #include "PPC.h" 18 #include "PPCInstrBuilder.h" 19 #include "PPCMachineFunctionInfo.h" 20 #include "PPCFrameLowering.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/CallingConv.h" 23 #include "llvm/Constants.h" 24 #include "llvm/Function.h" 25 #include "llvm/Type.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineModuleInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineFrameInfo.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/RegisterScavenging.h" 33 #include "llvm/Target/TargetFrameLowering.h" 34 #include "llvm/Target/TargetInstrInfo.h" 35 #include "llvm/Target/TargetMachine.h" 36 #include "llvm/Target/TargetOptions.h" 37 #include "llvm/Support/CommandLine.h" 38 #include "llvm/Support/Debug.h" 39 #include "llvm/Support/ErrorHandling.h" 40 #include "llvm/Support/MathExtras.h" 41 #include "llvm/Support/raw_ostream.h" 42 #include "llvm/ADT/BitVector.h" 43 #include "llvm/ADT/STLExtras.h" 44 #include <cstdlib> 45 46 #define GET_REGINFO_TARGET_DESC 47 #include "PPCGenRegisterInfo.inc" 48 49 namespace llvm { 50 cl::opt<bool> DisablePPC32RS("disable-ppc32-regscavenger", 51 cl::init(false), 52 cl::desc("Disable PPC32 register scavenger"), 53 cl::Hidden); 54 cl::opt<bool> DisablePPC64RS("disable-ppc64-regscavenger", 55 cl::init(false), 56 cl::desc("Disable PPC64 register scavenger"), 57 cl::Hidden); 58 } 59 60 using namespace llvm; 61 62 // FIXME (64-bit): Should be inlined. 63 bool 64 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 65 return ((!DisablePPC32RS && !Subtarget.isPPC64()) || 66 (!DisablePPC64RS && Subtarget.isPPC64())); 67 } 68 69 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 70 const TargetInstrInfo &tii) 71 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 72 ST.isPPC64() ? 0 : 1, 73 ST.isPPC64() ? 0 : 1), 74 Subtarget(ST), TII(tii) { 75 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 76 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 77 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 78 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 79 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 80 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 81 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 82 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 83 84 // 64-bit 85 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 86 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 87 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 88 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 89 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 90 } 91 92 bool 93 PPCRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 94 return requiresRegisterScavenging(MF); 95 } 96 97 98 /// getPointerRegClass - Return the register class to use to hold pointers. 99 /// This is used for addressing modes. 100 const TargetRegisterClass * 101 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 102 const { 103 if (Subtarget.isPPC64()) 104 return &PPC::G8RCRegClass; 105 return &PPC::GPRCRegClass; 106 } 107 108 const uint16_t* 109 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 110 if (Subtarget.isDarwinABI()) 111 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList : 112 CSR_Darwin32_SaveList; 113 114 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList; 115 } 116 117 const unsigned* 118 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 119 if (Subtarget.isDarwinABI()) 120 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask : 121 CSR_Darwin32_RegMask; 122 123 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask; 124 } 125 126 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 127 BitVector Reserved(getNumRegs()); 128 const PPCFrameLowering *PPCFI = 129 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 130 131 Reserved.set(PPC::R0); 132 Reserved.set(PPC::R1); 133 Reserved.set(PPC::LR); 134 Reserved.set(PPC::LR8); 135 Reserved.set(PPC::RM); 136 137 // The SVR4 ABI reserves r2 and r13 138 if (Subtarget.isSVR4ABI()) { 139 Reserved.set(PPC::R2); // System-reserved register 140 Reserved.set(PPC::R13); // Small Data Area pointer register 141 } 142 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 143 // when the stack frame is too big to address directly; we need two regs. 144 // This is a hack. 145 if (Subtarget.isDarwinABI()) { 146 Reserved.set(PPC::R2); 147 } 148 149 // On PPC64, r13 is the thread pointer. Never allocate this register. 150 // Note that this is over conservative, as it also prevents allocation of R31 151 // when the FP is not needed. 152 if (Subtarget.isPPC64()) { 153 Reserved.set(PPC::R13); 154 Reserved.set(PPC::R31); 155 156 Reserved.set(PPC::X0); 157 Reserved.set(PPC::X1); 158 Reserved.set(PPC::X13); 159 Reserved.set(PPC::X31); 160 161 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 162 if (Subtarget.isSVR4ABI()) { 163 Reserved.set(PPC::X2); 164 } 165 // Reserve X2 on Darwin to hack around the problem of save/restore of CR 166 // when the stack frame is too big to address directly; we need two regs. 167 // This is a hack. 168 if (Subtarget.isDarwinABI()) { 169 Reserved.set(PPC::X2); 170 } 171 } 172 173 if (PPCFI->needsFP(MF)) 174 Reserved.set(PPC::R31); 175 176 return Reserved; 177 } 178 179 unsigned 180 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 181 MachineFunction &MF) const { 182 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 183 const unsigned DefaultSafety = 1; 184 185 switch (RC->getID()) { 186 default: 187 return 0; 188 case PPC::G8RCRegClassID: 189 case PPC::GPRCRegClassID: { 190 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 191 return 32 - FP - DefaultSafety; 192 } 193 case PPC::F8RCRegClassID: 194 case PPC::F4RCRegClassID: 195 case PPC::VRRCRegClassID: 196 return 32 - DefaultSafety; 197 case PPC::CRRCRegClassID: 198 return 8 - DefaultSafety; 199 } 200 } 201 202 //===----------------------------------------------------------------------===// 203 // Stack Frame Processing methods 204 //===----------------------------------------------------------------------===// 205 206 void PPCRegisterInfo:: 207 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 208 MachineBasicBlock::iterator I) const { 209 if (MF.getTarget().Options.GuaranteedTailCallOpt && 210 I->getOpcode() == PPC::ADJCALLSTACKUP) { 211 // Add (actually subtract) back the amount the callee popped on return. 212 if (int CalleeAmt = I->getOperand(1).getImm()) { 213 bool is64Bit = Subtarget.isPPC64(); 214 CalleeAmt *= -1; 215 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 216 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 217 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 218 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 219 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 220 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 221 MachineInstr *MI = I; 222 DebugLoc dl = MI->getDebugLoc(); 223 224 if (isInt<16>(CalleeAmt)) { 225 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 226 .addReg(StackReg, RegState::Kill) 227 .addImm(CalleeAmt); 228 } else { 229 MachineBasicBlock::iterator MBBI = I; 230 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 231 .addImm(CalleeAmt >> 16); 232 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 233 .addReg(TmpReg, RegState::Kill) 234 .addImm(CalleeAmt & 0xFFFF); 235 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 236 .addReg(StackReg, RegState::Kill) 237 .addReg(TmpReg); 238 } 239 } 240 } 241 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 242 MBB.erase(I); 243 } 244 245 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 246 /// register first and then a spilled callee-saved register if that fails. 247 static 248 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 249 const TargetRegisterClass *RC, int SPAdj) { 250 assert(RS && "Register scavenging must be on"); 251 unsigned Reg = RS->FindUnusedReg(RC); 252 // FIXME: move ARM callee-saved reg scan to target independent code, then 253 // search for already spilled CS register here. 254 if (Reg == 0) 255 Reg = RS->scavengeRegister(RC, II, SPAdj); 256 return Reg; 257 } 258 259 /// lowerDynamicAlloc - Generate the code for allocating an object in the 260 /// current frame. The sequence of code with be in the general form 261 /// 262 /// addi R0, SP, \#frameSize ; get the address of the previous frame 263 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 264 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 265 /// 266 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 267 int SPAdj, RegScavenger *RS) const { 268 // Get the instruction. 269 MachineInstr &MI = *II; 270 // Get the instruction's basic block. 271 MachineBasicBlock &MBB = *MI.getParent(); 272 // Get the basic block's function. 273 MachineFunction &MF = *MBB.getParent(); 274 // Get the frame info. 275 MachineFrameInfo *MFI = MF.getFrameInfo(); 276 // Determine whether 64-bit pointers are used. 277 bool LP64 = Subtarget.isPPC64(); 278 DebugLoc dl = MI.getDebugLoc(); 279 280 // Get the maximum call stack size. 281 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 282 // Get the total frame size. 283 unsigned FrameSize = MFI->getStackSize(); 284 285 // Get stack alignments. 286 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 287 unsigned MaxAlign = MFI->getMaxAlignment(); 288 if (MaxAlign > TargetAlign) 289 report_fatal_error("Dynamic alloca with large aligns not supported"); 290 291 // Determine the previous frame's address. If FrameSize can't be 292 // represented as 16 bits or we need special alignment, then we load the 293 // previous frame's address from 0(SP). Why not do an addis of the hi? 294 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 295 // Constructing the constant and adding would take 3 instructions. 296 // Fortunately, a frame greater than 32K is rare. 297 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 298 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 299 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 300 301 // FIXME (64-bit): Use "findScratchRegister" 302 unsigned Reg; 303 if (requiresRegisterScavenging(MF)) 304 Reg = findScratchRegister(II, RS, RC, SPAdj); 305 else 306 Reg = PPC::R0; 307 308 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 309 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 310 .addReg(PPC::R31) 311 .addImm(FrameSize); 312 } else if (LP64) { 313 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 314 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 315 .addImm(0) 316 .addReg(PPC::X1); 317 else 318 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 319 .addImm(0) 320 .addReg(PPC::X1); 321 } else { 322 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 323 .addImm(0) 324 .addReg(PPC::R1); 325 } 326 327 // Grow the stack and update the stack pointer link, then determine the 328 // address of new allocated space. 329 if (LP64) { 330 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 331 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 332 .addReg(Reg, RegState::Kill) 333 .addReg(PPC::X1, RegState::Define) 334 .addReg(MI.getOperand(1).getReg()); 335 else 336 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 337 .addReg(PPC::X0, RegState::Kill) 338 .addReg(PPC::X1, RegState::Define) 339 .addReg(MI.getOperand(1).getReg()); 340 341 if (!MI.getOperand(1).isKill()) 342 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 343 .addReg(PPC::X1) 344 .addImm(maxCallFrameSize); 345 else 346 // Implicitly kill the register. 347 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 348 .addReg(PPC::X1) 349 .addImm(maxCallFrameSize) 350 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 351 } else { 352 BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) 353 .addReg(Reg, RegState::Kill) 354 .addReg(PPC::R1, RegState::Define) 355 .addReg(MI.getOperand(1).getReg()); 356 357 if (!MI.getOperand(1).isKill()) 358 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 359 .addReg(PPC::R1) 360 .addImm(maxCallFrameSize); 361 else 362 // Implicitly kill the register. 363 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 364 .addReg(PPC::R1) 365 .addImm(maxCallFrameSize) 366 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 367 } 368 369 // Discard the DYNALLOC instruction. 370 MBB.erase(II); 371 } 372 373 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 374 /// reserving a whole register (R0), we scrounge for one here. This generates 375 /// code like this: 376 /// 377 /// mfcr rA ; Move the conditional register into GPR rA. 378 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 379 /// stw rA, FI ; Store rA to the frame. 380 /// 381 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 382 unsigned FrameIndex, int SPAdj, 383 RegScavenger *RS) const { 384 // Get the instruction. 385 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 386 // Get the instruction's basic block. 387 MachineBasicBlock &MBB = *MI.getParent(); 388 DebugLoc dl = MI.getDebugLoc(); 389 390 // FIXME: Once LLVM supports creating virtual registers here, or the register 391 // scavenger can return multiple registers, stop using reserved registers 392 // here. 393 (void) SPAdj; 394 (void) RS; 395 396 bool LP64 = Subtarget.isPPC64(); 397 unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : 398 (LP64 ? PPC::X0 : PPC::R0); 399 unsigned SrcReg = MI.getOperand(0).getReg(); 400 401 // We need to store the CR in the low 4-bits of the saved value. First, issue 402 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 403 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg) 404 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 405 406 // If the saved register wasn't CR0, shift the bits left so that they are in 407 // CR0's slot. 408 if (SrcReg != PPC::CR0) 409 // rlwinm rA, rA, ShiftBits, 0, 31. 410 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 411 .addReg(Reg, RegState::Kill) 412 .addImm(getPPCRegisterNumbering(SrcReg) * 4) 413 .addImm(0) 414 .addImm(31); 415 416 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 417 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 418 FrameIndex); 419 420 // Discard the pseudo instruction. 421 MBB.erase(II); 422 } 423 424 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 425 unsigned FrameIndex, int SPAdj, 426 RegScavenger *RS) const { 427 // Get the instruction. 428 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 429 // Get the instruction's basic block. 430 MachineBasicBlock &MBB = *MI.getParent(); 431 DebugLoc dl = MI.getDebugLoc(); 432 433 // FIXME: Once LLVM supports creating virtual registers here, or the register 434 // scavenger can return multiple registers, stop using reserved registers 435 // here. 436 (void) SPAdj; 437 (void) RS; 438 439 bool LP64 = Subtarget.isPPC64(); 440 unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : 441 (LP64 ? PPC::X0 : PPC::R0); 442 unsigned DestReg = MI.getOperand(0).getReg(); 443 assert(MI.definesRegister(DestReg) && 444 "RESTORE_CR does not define its destination"); 445 446 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 447 Reg), FrameIndex); 448 449 // If the reloaded register isn't CR0, shift the bits right so that they are 450 // in the right CR's slot. 451 if (DestReg != PPC::CR0) { 452 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 453 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 454 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 455 .addReg(Reg).addImm(32-ShiftBits).addImm(0) 456 .addImm(31); 457 } 458 459 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg) 460 .addReg(Reg); 461 462 // Discard the pseudo instruction. 463 MBB.erase(II); 464 } 465 466 void 467 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 468 int SPAdj, RegScavenger *RS) const { 469 assert(SPAdj == 0 && "Unexpected"); 470 471 // Get the instruction. 472 MachineInstr &MI = *II; 473 // Get the instruction's basic block. 474 MachineBasicBlock &MBB = *MI.getParent(); 475 // Get the basic block's function. 476 MachineFunction &MF = *MBB.getParent(); 477 // Get the frame info. 478 MachineFrameInfo *MFI = MF.getFrameInfo(); 479 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 480 DebugLoc dl = MI.getDebugLoc(); 481 482 // Find out which operand is the frame index. 483 unsigned FIOperandNo = 0; 484 while (!MI.getOperand(FIOperandNo).isFI()) { 485 ++FIOperandNo; 486 assert(FIOperandNo != MI.getNumOperands() && 487 "Instr doesn't have FrameIndex operand!"); 488 } 489 // Take into account whether it's an add or mem instruction 490 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 491 if (MI.isInlineAsm()) 492 OffsetOperandNo = FIOperandNo-1; 493 494 // Get the frame index. 495 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 496 497 // Get the frame pointer save index. Users of this index are primarily 498 // DYNALLOC instructions. 499 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 500 int FPSI = FI->getFramePointerSaveIndex(); 501 // Get the instruction opcode. 502 unsigned OpC = MI.getOpcode(); 503 504 // Special case for dynamic alloca. 505 if (FPSI && FrameIndex == FPSI && 506 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 507 lowerDynamicAlloc(II, SPAdj, RS); 508 return; 509 } 510 511 // Special case for pseudo-ops SPILL_CR and RESTORE_CR. 512 if (requiresRegisterScavenging(MF)) { 513 if (OpC == PPC::SPILL_CR) { 514 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 515 return; 516 } else if (OpC == PPC::RESTORE_CR) { 517 lowerCRRestore(II, FrameIndex, SPAdj, RS); 518 return; 519 } 520 } 521 522 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 523 524 bool is64Bit = Subtarget.isPPC64(); 525 MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ? 526 (is64Bit ? PPC::X31 : PPC::R31) : 527 (is64Bit ? PPC::X1 : PPC::R1), 528 false); 529 530 // Figure out if the offset in the instruction is shifted right two bits. This 531 // is true for instructions like "STD", which the machine implicitly adds two 532 // low zeros to. 533 bool isIXAddr = false; 534 switch (OpC) { 535 case PPC::LWA: 536 case PPC::LD: 537 case PPC::STD: 538 case PPC::STD_32: 539 isIXAddr = true; 540 break; 541 } 542 543 // Now add the frame object offset to the offset from r1. 544 int Offset = MFI->getObjectOffset(FrameIndex); 545 if (!isIXAddr) 546 Offset += MI.getOperand(OffsetOperandNo).getImm(); 547 else 548 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 549 550 // If we're not using a Frame Pointer that has been set to the value of the 551 // SP before having the stack size subtracted from it, then add the stack size 552 // to Offset to get the correct offset. 553 // Naked functions have stack size 0, although getStackSize may not reflect that 554 // because we didn't call all the pieces that compute it for naked functions. 555 if (!MF.getFunction()->hasFnAttr(Attribute::Naked)) 556 Offset += MFI->getStackSize(); 557 558 // If we can, encode the offset directly into the instruction. If this is a 559 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 560 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 561 // clear can be encoded. This is extremely uncommon, because normally you 562 // only "std" to a stack slot that is at least 4-byte aligned, but it can 563 // happen in invalid code. 564 if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 565 (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) { 566 if (isIXAddr) 567 Offset >>= 2; // The actual encoded value has the low two bits zero. 568 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 569 return; 570 } 571 572 // The offset doesn't fit into a single register, scavenge one to build the 573 // offset in. 574 575 unsigned SReg; 576 if (requiresRegisterScavenging(MF)) { 577 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 578 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 579 SReg = findScratchRegister(II, RS, is64Bit ? G8RC : GPRC, SPAdj); 580 } else 581 SReg = is64Bit ? PPC::X0 : PPC::R0; 582 583 // Insert a set of rA with the full offset value before the ld, st, or add 584 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg) 585 .addImm(Offset >> 16); 586 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 587 .addReg(SReg, RegState::Kill) 588 .addImm(Offset); 589 590 // Convert into indexed form of the instruction: 591 // 592 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 593 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 594 unsigned OperandBase; 595 596 if (OpC != TargetOpcode::INLINEASM) { 597 assert(ImmToIdxMap.count(OpC) && 598 "No indexed form of load or store available!"); 599 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 600 MI.setDesc(TII.get(NewOpcode)); 601 OperandBase = 1; 602 } else { 603 OperandBase = OffsetOperandNo; 604 } 605 606 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 607 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 608 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 609 } 610 611 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 612 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 613 614 if (!Subtarget.isPPC64()) 615 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 616 else 617 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 618 } 619 620 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 621 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 622 } 623 624 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 625 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 626 } 627