1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPC.h" 17 #include "PPCInstrBuilder.h" 18 #include "PPCMachineFunctionInfo.h" 19 #include "PPCRegisterInfo.h" 20 #include "PPCFrameInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/CallingConv.h" 23 #include "llvm/Constants.h" 24 #include "llvm/Function.h" 25 #include "llvm/Type.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineModuleInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineFrameInfo.h" 31 #include "llvm/CodeGen/MachineLocation.h" 32 #include "llvm/CodeGen/MachineRegisterInfo.h" 33 #include "llvm/CodeGen/RegisterScavenging.h" 34 #include "llvm/Target/TargetFrameInfo.h" 35 #include "llvm/Target/TargetInstrInfo.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetOptions.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/ErrorHandling.h" 41 #include "llvm/Support/MathExtras.h" 42 #include "llvm/Support/raw_ostream.h" 43 #include "llvm/ADT/BitVector.h" 44 #include "llvm/ADT/STLExtras.h" 45 #include <cstdlib> 46 using namespace llvm; 47 48 // FIXME This disables some code that aligns the stack to a boundary 49 // bigger than the default (16 bytes on Darwin) when there is a stack local 50 // of greater alignment. This does not currently work, because the delta 51 // between old and new stack pointers is added to offsets that reference 52 // incoming parameters after the prolog is generated, and the code that 53 // does that doesn't handle a variable delta. You don't want to do that 54 // anyway; a better approach is to reserve another register that retains 55 // to the incoming stack pointer, and reference parameters relative to that. 56 #define ALIGN_STACK 0 57 58 // FIXME (64-bit): Eventually enable by default. 59 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", 60 cl::init(false), 61 cl::desc("Enable PPC32 register scavenger"), 62 cl::Hidden); 63 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", 64 cl::init(false), 65 cl::desc("Enable PPC64 register scavenger"), 66 cl::Hidden); 67 #define EnableRegisterScavenging \ 68 ((EnablePPC32RS && !Subtarget.isPPC64()) || \ 69 (EnablePPC64RS && Subtarget.isPPC64())) 70 71 // FIXME (64-bit): Should be inlined. 72 bool 73 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 74 return EnableRegisterScavenging; 75 } 76 77 /// getRegisterNumbering - Given the enum value for some register, e.g. 78 /// PPC::F14, return the number that it corresponds to (e.g. 14). 79 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 80 using namespace PPC; 81 switch (RegEnum) { 82 case 0: return 0; 83 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; 84 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; 85 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; 86 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; 87 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; 88 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; 89 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; 90 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; 91 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; 92 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; 93 case R10: case X10: case F10: case V10: case CR2EQ: return 10; 94 case R11: case X11: case F11: case V11: case CR2UN: return 11; 95 case R12: case X12: case F12: case V12: case CR3LT: return 12; 96 case R13: case X13: case F13: case V13: case CR3GT: return 13; 97 case R14: case X14: case F14: case V14: case CR3EQ: return 14; 98 case R15: case X15: case F15: case V15: case CR3UN: return 15; 99 case R16: case X16: case F16: case V16: case CR4LT: return 16; 100 case R17: case X17: case F17: case V17: case CR4GT: return 17; 101 case R18: case X18: case F18: case V18: case CR4EQ: return 18; 102 case R19: case X19: case F19: case V19: case CR4UN: return 19; 103 case R20: case X20: case F20: case V20: case CR5LT: return 20; 104 case R21: case X21: case F21: case V21: case CR5GT: return 21; 105 case R22: case X22: case F22: case V22: case CR5EQ: return 22; 106 case R23: case X23: case F23: case V23: case CR5UN: return 23; 107 case R24: case X24: case F24: case V24: case CR6LT: return 24; 108 case R25: case X25: case F25: case V25: case CR6GT: return 25; 109 case R26: case X26: case F26: case V26: case CR6EQ: return 26; 110 case R27: case X27: case F27: case V27: case CR6UN: return 27; 111 case R28: case X28: case F28: case V28: case CR7LT: return 28; 112 case R29: case X29: case F29: case V29: case CR7GT: return 29; 113 case R30: case X30: case F30: case V30: case CR7EQ: return 30; 114 case R31: case X31: case F31: case V31: case CR7UN: return 31; 115 default: 116 llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); 117 } 118 } 119 120 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 121 const TargetInstrInfo &tii) 122 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 123 Subtarget(ST), TII(tii) { 124 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 125 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 126 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 127 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 128 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 129 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 130 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 131 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 132 133 // 64-bit 134 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 135 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 136 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 137 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 138 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 139 } 140 141 /// getPointerRegClass - Return the register class to use to hold pointers. 142 /// This is used for addressing modes. 143 const TargetRegisterClass * 144 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const { 145 if (Subtarget.isPPC64()) 146 return &PPC::G8RCRegClass; 147 return &PPC::GPRCRegClass; 148 } 149 150 const unsigned* 151 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 152 // 32-bit Darwin calling convention. 153 static const unsigned Darwin32_CalleeSavedRegs[] = { 154 PPC::R13, PPC::R14, PPC::R15, 155 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 156 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 157 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 158 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 159 160 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 161 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 162 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 163 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 164 PPC::F30, PPC::F31, 165 166 PPC::CR2, PPC::CR3, PPC::CR4, 167 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 168 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 169 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 170 171 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 172 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 173 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 174 175 PPC::LR, 0 176 }; 177 178 // 32-bit SVR4 calling convention. 179 static const unsigned SVR4_CalleeSavedRegs[] = { 180 PPC::R14, PPC::R15, 181 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 182 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 183 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 184 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 185 186 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 187 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 188 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 189 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 190 PPC::F30, PPC::F31, 191 192 PPC::CR2, PPC::CR3, PPC::CR4, 193 194 PPC::VRSAVE, 195 196 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 197 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 198 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 199 200 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 201 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 202 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 203 204 0 205 }; 206 // 64-bit Darwin calling convention. 207 static const unsigned Darwin64_CalleeSavedRegs[] = { 208 PPC::X14, PPC::X15, 209 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 210 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 211 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 212 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 213 214 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 215 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 216 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 217 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 218 PPC::F30, PPC::F31, 219 220 PPC::CR2, PPC::CR3, PPC::CR4, 221 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 222 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 223 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 224 225 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 226 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 227 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 228 229 PPC::LR8, 0 230 }; 231 232 // 64-bit SVR4 calling convention. 233 static const unsigned SVR4_64_CalleeSavedRegs[] = { 234 PPC::X14, PPC::X15, 235 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 236 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 237 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 238 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 239 240 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 241 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 242 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 243 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 244 PPC::F30, PPC::F31, 245 246 PPC::CR2, PPC::CR3, PPC::CR4, 247 248 PPC::VRSAVE, 249 250 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 251 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 252 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 253 254 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 255 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 256 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 257 258 0 259 }; 260 261 if (Subtarget.isDarwinABI()) 262 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : 263 Darwin32_CalleeSavedRegs; 264 265 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs; 266 } 267 268 const TargetRegisterClass* const* 269 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 270 // 32-bit Darwin calling convention. 271 static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = { 272 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 273 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 274 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 275 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 276 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 277 278 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 279 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 280 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 281 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 282 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 283 284 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 285 286 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 287 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 288 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 289 290 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 291 &PPC::CRBITRCRegClass, 292 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 293 &PPC::CRBITRCRegClass, 294 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 295 &PPC::CRBITRCRegClass, 296 297 &PPC::GPRCRegClass, 0 298 }; 299 300 // 32-bit SVR4 calling convention. 301 static const TargetRegisterClass * const SVR4_CalleeSavedRegClasses[] = { 302 &PPC::GPRCRegClass,&PPC::GPRCRegClass, 303 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 304 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 305 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 306 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 307 308 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 309 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 310 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 311 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 312 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 313 314 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 315 316 &PPC::VRSAVERCRegClass, 317 318 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 319 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 320 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 321 322 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 323 &PPC::CRBITRCRegClass, 324 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 325 &PPC::CRBITRCRegClass, 326 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 327 &PPC::CRBITRCRegClass, 328 329 0 330 }; 331 332 // 64-bit Darwin calling convention. 333 static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = { 334 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 335 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 336 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 337 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 338 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 339 340 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 341 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 342 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 343 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 344 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 345 346 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 347 348 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 349 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 350 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 351 352 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 353 &PPC::CRBITRCRegClass, 354 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 355 &PPC::CRBITRCRegClass, 356 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 357 &PPC::CRBITRCRegClass, 358 359 &PPC::G8RCRegClass, 0 360 }; 361 362 // 64-bit SVR4 calling convention. 363 static const TargetRegisterClass * const SVR4_64_CalleeSavedRegClasses[] = { 364 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 365 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 366 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 367 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 368 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 369 370 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 371 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 372 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 373 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 374 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 375 376 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 377 378 &PPC::VRSAVERCRegClass, 379 380 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 381 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 382 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 383 384 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 385 &PPC::CRBITRCRegClass, 386 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 387 &PPC::CRBITRCRegClass, 388 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 389 &PPC::CRBITRCRegClass, 390 391 0 392 }; 393 394 if (Subtarget.isDarwinABI()) 395 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses : 396 Darwin32_CalleeSavedRegClasses; 397 398 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegClasses 399 : SVR4_CalleeSavedRegClasses; 400 } 401 402 // needsFP - Return true if the specified function should have a dedicated frame 403 // pointer register. This is true if the function has variable sized allocas or 404 // if frame pointer elimination is disabled. 405 // 406 static bool needsFP(const MachineFunction &MF) { 407 const MachineFrameInfo *MFI = MF.getFrameInfo(); 408 return NoFramePointerElim || MFI->hasVarSizedObjects() || 409 (PerformTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 410 } 411 412 static bool spillsCR(const MachineFunction &MF) { 413 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 414 return FuncInfo->isCRSpilled(); 415 } 416 417 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 418 BitVector Reserved(getNumRegs()); 419 Reserved.set(PPC::R0); 420 Reserved.set(PPC::R1); 421 Reserved.set(PPC::LR); 422 Reserved.set(PPC::LR8); 423 Reserved.set(PPC::RM); 424 425 // The SVR4 ABI reserves r2 and r13 426 if (Subtarget.isSVR4ABI()) { 427 Reserved.set(PPC::R2); // System-reserved register 428 Reserved.set(PPC::R13); // Small Data Area pointer register 429 } 430 431 // On PPC64, r13 is the thread pointer. Never allocate this register. 432 // Note that this is over conservative, as it also prevents allocation of R31 433 // when the FP is not needed. 434 if (Subtarget.isPPC64()) { 435 Reserved.set(PPC::R13); 436 Reserved.set(PPC::R31); 437 438 if (!EnableRegisterScavenging) 439 Reserved.set(PPC::R0); // FIXME (64-bit): Remove 440 441 Reserved.set(PPC::X0); 442 Reserved.set(PPC::X1); 443 Reserved.set(PPC::X13); 444 Reserved.set(PPC::X31); 445 446 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 447 if (Subtarget.isSVR4ABI()) { 448 Reserved.set(PPC::X2); 449 } 450 } 451 452 if (needsFP(MF)) 453 Reserved.set(PPC::R31); 454 455 return Reserved; 456 } 457 458 //===----------------------------------------------------------------------===// 459 // Stack Frame Processing methods 460 //===----------------------------------------------------------------------===// 461 462 // hasFP - Return true if the specified function actually has a dedicated frame 463 // pointer register. This is true if the function needs a frame pointer and has 464 // a non-zero stack size. 465 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 466 const MachineFrameInfo *MFI = MF.getFrameInfo(); 467 return MFI->getStackSize() && needsFP(MF); 468 } 469 470 /// MustSaveLR - Return true if this function requires that we save the LR 471 /// register onto the stack in the prolog and restore it in the epilog of the 472 /// function. 473 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 474 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 475 476 // We need a save/restore of LR if there is any def of LR (which is 477 // defined by calls, including the PIC setup sequence), or if there is 478 // some use of the LR stack slot (e.g. for builtin_return_address). 479 // (LR comes in 32 and 64 bit versions.) 480 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 481 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 482 } 483 484 485 486 void PPCRegisterInfo:: 487 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 488 MachineBasicBlock::iterator I) const { 489 if (PerformTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) { 490 // Add (actually subtract) back the amount the callee popped on return. 491 if (int CalleeAmt = I->getOperand(1).getImm()) { 492 bool is64Bit = Subtarget.isPPC64(); 493 CalleeAmt *= -1; 494 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 495 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 496 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 497 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 498 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 499 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 500 MachineInstr *MI = I; 501 DebugLoc dl = MI->getDebugLoc(); 502 503 if (isInt16(CalleeAmt)) { 504 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg). 505 addImm(CalleeAmt); 506 } else { 507 MachineBasicBlock::iterator MBBI = I; 508 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 509 .addImm(CalleeAmt >> 16); 510 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 511 .addReg(TmpReg, RegState::Kill) 512 .addImm(CalleeAmt & 0xFFFF); 513 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 514 .addReg(StackReg) 515 .addReg(StackReg) 516 .addReg(TmpReg); 517 } 518 } 519 } 520 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 521 MBB.erase(I); 522 } 523 524 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 525 /// register first and then a spilled callee-saved register if that fails. 526 static 527 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 528 const TargetRegisterClass *RC, int SPAdj) { 529 assert(RS && "Register scavenging must be on"); 530 unsigned Reg = RS->FindUnusedReg(RC); 531 // FIXME: move ARM callee-saved reg scan to target independent code, then 532 // search for already spilled CS register here. 533 if (Reg == 0) 534 Reg = RS->scavengeRegister(RC, II, SPAdj); 535 return Reg; 536 } 537 538 /// lowerDynamicAlloc - Generate the code for allocating an object in the 539 /// current frame. The sequence of code with be in the general form 540 /// 541 /// addi R0, SP, \#frameSize ; get the address of the previous frame 542 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 543 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 544 /// 545 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 546 int SPAdj, RegScavenger *RS) const { 547 // Get the instruction. 548 MachineInstr &MI = *II; 549 // Get the instruction's basic block. 550 MachineBasicBlock &MBB = *MI.getParent(); 551 // Get the basic block's function. 552 MachineFunction &MF = *MBB.getParent(); 553 // Get the frame info. 554 MachineFrameInfo *MFI = MF.getFrameInfo(); 555 // Determine whether 64-bit pointers are used. 556 bool LP64 = Subtarget.isPPC64(); 557 DebugLoc dl = MI.getDebugLoc(); 558 559 // Get the maximum call stack size. 560 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 561 // Get the total frame size. 562 unsigned FrameSize = MFI->getStackSize(); 563 564 // Get stack alignments. 565 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 566 unsigned MaxAlign = MFI->getMaxAlignment(); 567 assert(MaxAlign <= TargetAlign && 568 "Dynamic alloca with large aligns not supported"); 569 570 // Determine the previous frame's address. If FrameSize can't be 571 // represented as 16 bits or we need special alignment, then we load the 572 // previous frame's address from 0(SP). Why not do an addis of the hi? 573 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 574 // Constructing the constant and adding would take 3 instructions. 575 // Fortunately, a frame greater than 32K is rare. 576 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 577 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 578 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 579 580 // FIXME (64-bit): Use "findScratchRegister" 581 unsigned Reg; 582 if (EnableRegisterScavenging) 583 Reg = findScratchRegister(II, RS, RC, SPAdj); 584 else 585 Reg = PPC::R0; 586 587 if (MaxAlign < TargetAlign && isInt16(FrameSize)) { 588 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 589 .addReg(PPC::R31) 590 .addImm(FrameSize); 591 } else if (LP64) { 592 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 593 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 594 .addImm(0) 595 .addReg(PPC::X1); 596 else 597 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 598 .addImm(0) 599 .addReg(PPC::X1); 600 } else { 601 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 602 .addImm(0) 603 .addReg(PPC::R1); 604 } 605 606 // Grow the stack and update the stack pointer link, then determine the 607 // address of new allocated space. 608 if (LP64) { 609 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 610 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 611 .addReg(Reg, RegState::Kill) 612 .addReg(PPC::X1) 613 .addReg(MI.getOperand(1).getReg()); 614 else 615 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 616 .addReg(PPC::X0, RegState::Kill) 617 .addReg(PPC::X1) 618 .addReg(MI.getOperand(1).getReg()); 619 620 if (!MI.getOperand(1).isKill()) 621 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 622 .addReg(PPC::X1) 623 .addImm(maxCallFrameSize); 624 else 625 // Implicitly kill the register. 626 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 627 .addReg(PPC::X1) 628 .addImm(maxCallFrameSize) 629 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 630 } else { 631 BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) 632 .addReg(Reg, RegState::Kill) 633 .addReg(PPC::R1) 634 .addReg(MI.getOperand(1).getReg()); 635 636 if (!MI.getOperand(1).isKill()) 637 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 638 .addReg(PPC::R1) 639 .addImm(maxCallFrameSize); 640 else 641 // Implicitly kill the register. 642 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 643 .addReg(PPC::R1) 644 .addImm(maxCallFrameSize) 645 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 646 } 647 648 // Discard the DYNALLOC instruction. 649 MBB.erase(II); 650 } 651 652 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 653 /// reserving a whole register (R0), we scrounge for one here. This generates 654 /// code like this: 655 /// 656 /// mfcr rA ; Move the conditional register into GPR rA. 657 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 658 /// stw rA, FI ; Store rA to the frame. 659 /// 660 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 661 unsigned FrameIndex, int SPAdj, 662 RegScavenger *RS) const { 663 // Get the instruction. 664 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> 665 // Get the instruction's basic block. 666 MachineBasicBlock &MBB = *MI.getParent(); 667 DebugLoc dl = MI.getDebugLoc(); 668 669 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 670 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 671 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 672 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 673 674 // We need to store the CR in the low 4-bits of the saved value. First, issue 675 // an MFCR to save all of the CRBits. Add an implicit kill of the CR. 676 if (!MI.getOperand(0).isKill()) 677 BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg); 678 else 679 // Implicitly kill the CR register. 680 BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg) 681 .addReg(MI.getOperand(0).getReg(), RegState::ImplicitKill); 682 683 // If the saved register wasn't CR0, shift the bits left so that they are in 684 // CR0's slot. 685 unsigned SrcReg = MI.getOperand(0).getReg(); 686 if (SrcReg != PPC::CR0) 687 // rlwinm rA, rA, ShiftBits, 0, 31. 688 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) 689 .addReg(Reg, RegState::Kill) 690 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) 691 .addImm(0) 692 .addImm(31); 693 694 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 695 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 696 FrameIndex); 697 698 // Discard the pseudo instruction. 699 MBB.erase(II); 700 } 701 702 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 703 int SPAdj, RegScavenger *RS) const { 704 assert(SPAdj == 0 && "Unexpected"); 705 706 // Get the instruction. 707 MachineInstr &MI = *II; 708 // Get the instruction's basic block. 709 MachineBasicBlock &MBB = *MI.getParent(); 710 // Get the basic block's function. 711 MachineFunction &MF = *MBB.getParent(); 712 // Get the frame info. 713 MachineFrameInfo *MFI = MF.getFrameInfo(); 714 DebugLoc dl = MI.getDebugLoc(); 715 716 // Find out which operand is the frame index. 717 unsigned FIOperandNo = 0; 718 while (!MI.getOperand(FIOperandNo).isFI()) { 719 ++FIOperandNo; 720 assert(FIOperandNo != MI.getNumOperands() && 721 "Instr doesn't have FrameIndex operand!"); 722 } 723 // Take into account whether it's an add or mem instruction 724 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 725 if (MI.getOpcode() == TargetInstrInfo::INLINEASM) 726 OffsetOperandNo = FIOperandNo-1; 727 728 // Get the frame index. 729 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 730 731 // Get the frame pointer save index. Users of this index are primarily 732 // DYNALLOC instructions. 733 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 734 int FPSI = FI->getFramePointerSaveIndex(); 735 // Get the instruction opcode. 736 unsigned OpC = MI.getOpcode(); 737 738 // Special case for dynamic alloca. 739 if (FPSI && FrameIndex == FPSI && 740 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 741 lowerDynamicAlloc(II, SPAdj, RS); 742 return; 743 } 744 745 // Special case for pseudo-op SPILL_CR. 746 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default. 747 if (OpC == PPC::SPILL_CR) { 748 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 749 return; 750 } 751 752 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 753 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, 754 false); 755 756 // Figure out if the offset in the instruction is shifted right two bits. This 757 // is true for instructions like "STD", which the machine implicitly adds two 758 // low zeros to. 759 bool isIXAddr = false; 760 switch (OpC) { 761 case PPC::LWA: 762 case PPC::LD: 763 case PPC::STD: 764 case PPC::STD_32: 765 isIXAddr = true; 766 break; 767 } 768 769 // Now add the frame object offset to the offset from r1. 770 int Offset = MFI->getObjectOffset(FrameIndex); 771 if (!isIXAddr) 772 Offset += MI.getOperand(OffsetOperandNo).getImm(); 773 else 774 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 775 776 // If we're not using a Frame Pointer that has been set to the value of the 777 // SP before having the stack size subtracted from it, then add the stack size 778 // to Offset to get the correct offset. 779 Offset += MFI->getStackSize(); 780 781 // If we can, encode the offset directly into the instruction. If this is a 782 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 783 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 784 // clear can be encoded. This is extremely uncommon, because normally you 785 // only "std" to a stack slot that is at least 4-byte aligned, but it can 786 // happen in invalid code. 787 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 788 if (isIXAddr) 789 Offset >>= 2; // The actual encoded value has the low two bits zero. 790 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 791 return; 792 } 793 794 // The offset doesn't fit into a single register, scavenge one to build the 795 // offset in. 796 // FIXME: figure out what SPAdj is doing here. 797 798 // FIXME (64-bit): Use "findScratchRegister". 799 unsigned SReg; 800 if (EnableRegisterScavenging) 801 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); 802 else 803 SReg = PPC::R0; 804 805 // Insert a set of rA with the full offset value before the ld, st, or add 806 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) 807 .addImm(Offset >> 16); 808 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) 809 .addReg(SReg, RegState::Kill) 810 .addImm(Offset); 811 812 // Convert into indexed form of the instruction: 813 // 814 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 815 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 816 unsigned OperandBase; 817 818 if (OpC != TargetInstrInfo::INLINEASM) { 819 assert(ImmToIdxMap.count(OpC) && 820 "No indexed form of load or store available!"); 821 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 822 MI.setDesc(TII.get(NewOpcode)); 823 OperandBase = 1; 824 } else { 825 OperandBase = OffsetOperandNo; 826 } 827 828 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 829 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 830 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); 831 } 832 833 /// VRRegNo - Map from a numbered VR register to its enum value. 834 /// 835 static const unsigned short VRRegNo[] = { 836 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 837 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 838 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 839 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 840 }; 841 842 /// RemoveVRSaveCode - We have found that this function does not need any code 843 /// to manipulate the VRSAVE register, even though it uses vector registers. 844 /// This can happen when the only registers used are known to be live in or out 845 /// of the function. Remove all of the VRSAVE related code from the function. 846 static void RemoveVRSaveCode(MachineInstr *MI) { 847 MachineBasicBlock *Entry = MI->getParent(); 848 MachineFunction *MF = Entry->getParent(); 849 850 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 851 MachineBasicBlock::iterator MBBI = MI; 852 ++MBBI; 853 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 854 MBBI->eraseFromParent(); 855 856 bool RemovedAllMTVRSAVEs = true; 857 // See if we can find and remove the MTVRSAVE instruction from all of the 858 // epilog blocks. 859 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 860 // If last instruction is a return instruction, add an epilogue 861 if (!I->empty() && I->back().getDesc().isReturn()) { 862 bool FoundIt = false; 863 for (MBBI = I->end(); MBBI != I->begin(); ) { 864 --MBBI; 865 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 866 MBBI->eraseFromParent(); // remove it. 867 FoundIt = true; 868 break; 869 } 870 } 871 RemovedAllMTVRSAVEs &= FoundIt; 872 } 873 } 874 875 // If we found and removed all MTVRSAVE instructions, remove the read of 876 // VRSAVE as well. 877 if (RemovedAllMTVRSAVEs) { 878 MBBI = MI; 879 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 880 --MBBI; 881 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 882 MBBI->eraseFromParent(); 883 } 884 885 // Finally, nuke the UPDATE_VRSAVE. 886 MI->eraseFromParent(); 887 } 888 889 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 890 // instruction selector. Based on the vector registers that have been used, 891 // transform this into the appropriate ORI instruction. 892 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 893 MachineFunction *MF = MI->getParent()->getParent(); 894 DebugLoc dl = MI->getDebugLoc(); 895 896 unsigned UsedRegMask = 0; 897 for (unsigned i = 0; i != 32; ++i) 898 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 899 UsedRegMask |= 1 << (31-i); 900 901 // Live in and live out values already must be in the mask, so don't bother 902 // marking them. 903 for (MachineRegisterInfo::livein_iterator 904 I = MF->getRegInfo().livein_begin(), 905 E = MF->getRegInfo().livein_end(); I != E; ++I) { 906 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 907 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 908 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 909 } 910 for (MachineRegisterInfo::liveout_iterator 911 I = MF->getRegInfo().liveout_begin(), 912 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 913 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 914 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 915 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 916 } 917 918 // If no registers are used, turn this into a copy. 919 if (UsedRegMask == 0) { 920 // Remove all VRSAVE code. 921 RemoveVRSaveCode(MI); 922 return; 923 } 924 925 unsigned SrcReg = MI->getOperand(1).getReg(); 926 unsigned DstReg = MI->getOperand(0).getReg(); 927 928 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 929 if (DstReg != SrcReg) 930 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 931 .addReg(SrcReg) 932 .addImm(UsedRegMask); 933 else 934 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 935 .addReg(SrcReg, RegState::Kill) 936 .addImm(UsedRegMask); 937 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 938 if (DstReg != SrcReg) 939 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 940 .addReg(SrcReg) 941 .addImm(UsedRegMask >> 16); 942 else 943 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 944 .addReg(SrcReg, RegState::Kill) 945 .addImm(UsedRegMask >> 16); 946 } else { 947 if (DstReg != SrcReg) 948 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 949 .addReg(SrcReg) 950 .addImm(UsedRegMask >> 16); 951 else 952 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 953 .addReg(SrcReg, RegState::Kill) 954 .addImm(UsedRegMask >> 16); 955 956 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 957 .addReg(DstReg, RegState::Kill) 958 .addImm(UsedRegMask & 0xFFFF); 959 } 960 961 // Remove the old UPDATE_VRSAVE instruction. 962 MI->eraseFromParent(); 963 } 964 965 /// determineFrameLayout - Determine the size of the frame and maximum call 966 /// frame size. 967 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 968 MachineFrameInfo *MFI = MF.getFrameInfo(); 969 970 // Get the number of bytes to allocate from the FrameInfo 971 unsigned FrameSize = MFI->getStackSize(); 972 973 // Get the alignments provided by the target, and the maximum alignment 974 // (if any) of the fixed frame objects. 975 unsigned MaxAlign = MFI->getMaxAlignment(); 976 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 977 unsigned AlignMask = TargetAlign - 1; // 978 979 // If we are a leaf function, and use up to 224 bytes of stack space, 980 // don't have a frame pointer, calls, or dynamic alloca then we do not need 981 // to adjust the stack pointer (we fit in the Red Zone). 982 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone); 983 // FIXME SVR4 The 32-bit SVR4 ABI has no red zone. 984 if (!DisableRedZone && 985 FrameSize <= 224 && // Fits in red zone. 986 !MFI->hasVarSizedObjects() && // No dynamic alloca. 987 !MFI->hasCalls() && // No calls. 988 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 989 // No need for frame 990 MFI->setStackSize(0); 991 return; 992 } 993 994 // Get the maximum call frame size of all the calls. 995 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 996 997 // Maximum call frame needs to be at least big enough for linkage and 8 args. 998 unsigned minCallFrameSize = 999 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), 1000 Subtarget.isDarwinABI()); 1001 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 1002 1003 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 1004 // that allocations will be aligned. 1005 if (MFI->hasVarSizedObjects()) 1006 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 1007 1008 // Update maximum call frame size. 1009 MFI->setMaxCallFrameSize(maxCallFrameSize); 1010 1011 // Include call frame size in total. 1012 FrameSize += maxCallFrameSize; 1013 1014 // Make sure the frame is aligned. 1015 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 1016 1017 // Update frame info. 1018 MFI->setStackSize(FrameSize); 1019 } 1020 1021 void 1022 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 1023 RegScavenger *RS) const { 1024 // Save and clear the LR state. 1025 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1026 unsigned LR = getRARegister(); 1027 FI->setMustSaveLR(MustSaveLR(MF, LR)); 1028 MF.getRegInfo().setPhysRegUnused(LR); 1029 1030 // Save R31 if necessary 1031 int FPSI = FI->getFramePointerSaveIndex(); 1032 bool IsPPC64 = Subtarget.isPPC64(); 1033 bool IsSVR4ABI = Subtarget.isSVR4ABI(); 1034 bool isDarwinABI = Subtarget.isDarwinABI(); 1035 MachineFrameInfo *MFI = MF.getFrameInfo(); 1036 1037 // If the frame pointer save index hasn't been defined yet. 1038 if (!FPSI && needsFP(MF) && IsSVR4ABI) { 1039 // Find out what the fix offset of the frame pointer save area. 1040 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, 1041 isDarwinABI); 1042 // Allocate the frame index for frame pointer save area. 1043 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 1044 // Save the result. 1045 FI->setFramePointerSaveIndex(FPSI); 1046 } 1047 1048 // Reserve stack space to move the linkage area to in case of a tail call. 1049 int TCSPDelta = 0; 1050 if (PerformTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 1051 MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta); 1052 } 1053 1054 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1055 // a large stack, which will require scavenging a register to materialize a 1056 // large offset. 1057 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 1058 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 1059 // r0 for now. 1060 1061 if (EnableRegisterScavenging) // FIXME (64-bit): Enable. 1062 if (needsFP(MF) || spillsCR(MF)) { 1063 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1064 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1065 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC; 1066 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1067 RC->getAlignment())); 1068 } 1069 } 1070 1071 void 1072 PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) 1073 const { 1074 // Early exit if not using the SVR4 ABI. 1075 if (!Subtarget.isSVR4ABI()) { 1076 return; 1077 } 1078 1079 // Get callee saved register information. 1080 MachineFrameInfo *FFI = MF.getFrameInfo(); 1081 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 1082 1083 // Early exit if no callee saved registers are modified! 1084 if (CSI.empty() && !needsFP(MF)) { 1085 return; 1086 } 1087 1088 unsigned MinGPR = PPC::R31; 1089 unsigned MinG8R = PPC::X31; 1090 unsigned MinFPR = PPC::F31; 1091 unsigned MinVR = PPC::V31; 1092 1093 bool HasGPSaveArea = false; 1094 bool HasG8SaveArea = false; 1095 bool HasFPSaveArea = false; 1096 bool HasCRSaveArea = false; 1097 bool HasVRSAVESaveArea = false; 1098 bool HasVRSaveArea = false; 1099 1100 SmallVector<CalleeSavedInfo, 18> GPRegs; 1101 SmallVector<CalleeSavedInfo, 18> G8Regs; 1102 SmallVector<CalleeSavedInfo, 18> FPRegs; 1103 SmallVector<CalleeSavedInfo, 18> VRegs; 1104 1105 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1106 unsigned Reg = CSI[i].getReg(); 1107 const TargetRegisterClass *RC = CSI[i].getRegClass(); 1108 1109 if (RC == PPC::GPRCRegisterClass) { 1110 HasGPSaveArea = true; 1111 1112 GPRegs.push_back(CSI[i]); 1113 1114 if (Reg < MinGPR) { 1115 MinGPR = Reg; 1116 } 1117 } else if (RC == PPC::G8RCRegisterClass) { 1118 HasG8SaveArea = true; 1119 1120 G8Regs.push_back(CSI[i]); 1121 1122 if (Reg < MinG8R) { 1123 MinG8R = Reg; 1124 } 1125 } else if (RC == PPC::F8RCRegisterClass) { 1126 HasFPSaveArea = true; 1127 1128 FPRegs.push_back(CSI[i]); 1129 1130 if (Reg < MinFPR) { 1131 MinFPR = Reg; 1132 } 1133 // FIXME SVR4: Disable CR save area for now. 1134 } else if ( RC == PPC::CRBITRCRegisterClass 1135 || RC == PPC::CRRCRegisterClass) { 1136 // HasCRSaveArea = true; 1137 } else if (RC == PPC::VRSAVERCRegisterClass) { 1138 HasVRSAVESaveArea = true; 1139 } else if (RC == PPC::VRRCRegisterClass) { 1140 HasVRSaveArea = true; 1141 1142 VRegs.push_back(CSI[i]); 1143 1144 if (Reg < MinVR) { 1145 MinVR = Reg; 1146 } 1147 } else { 1148 llvm_unreachable("Unknown RegisterClass!"); 1149 } 1150 } 1151 1152 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 1153 1154 int64_t LowerBound = 0; 1155 1156 // Take into account stack space reserved for tail calls. 1157 int TCSPDelta = 0; 1158 if (PerformTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 1159 LowerBound = TCSPDelta; 1160 } 1161 1162 // The Floating-point register save area is right below the back chain word 1163 // of the previous stack frame. 1164 if (HasFPSaveArea) { 1165 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 1166 int FI = FPRegs[i].getFrameIdx(); 1167 1168 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1169 } 1170 1171 LowerBound -= (31 - getRegisterNumbering(MinFPR) + 1) * 8; 1172 } 1173 1174 // Check whether the frame pointer register is allocated. If so, make sure it 1175 // is spilled to the correct offset. 1176 if (needsFP(MF)) { 1177 HasGPSaveArea = true; 1178 1179 int FI = PFI->getFramePointerSaveIndex(); 1180 assert(FI && "No Frame Pointer Save Slot!"); 1181 1182 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1183 } 1184 1185 // General register save area starts right below the Floating-point 1186 // register save area. 1187 if (HasGPSaveArea || HasG8SaveArea) { 1188 // Move general register save area spill slots down, taking into account 1189 // the size of the Floating-point register save area. 1190 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 1191 int FI = GPRegs[i].getFrameIdx(); 1192 1193 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1194 } 1195 1196 // Move general register save area spill slots down, taking into account 1197 // the size of the Floating-point register save area. 1198 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1199 int FI = G8Regs[i].getFrameIdx(); 1200 1201 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1202 } 1203 1204 unsigned MinReg = std::min<unsigned>(getRegisterNumbering(MinGPR), 1205 getRegisterNumbering(MinG8R)); 1206 1207 if (Subtarget.isPPC64()) { 1208 LowerBound -= (31 - MinReg + 1) * 8; 1209 } else { 1210 LowerBound -= (31 - MinReg + 1) * 4; 1211 } 1212 } 1213 1214 // The CR save area is below the general register save area. 1215 if (HasCRSaveArea) { 1216 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1217 // which have the CR/CRBIT register class? 1218 // Adjust the frame index of the CR spill slot. 1219 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1220 const TargetRegisterClass *RC = CSI[i].getRegClass(); 1221 1222 if (RC == PPC::CRBITRCRegisterClass || RC == PPC::CRRCRegisterClass) { 1223 int FI = CSI[i].getFrameIdx(); 1224 1225 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1226 } 1227 } 1228 1229 LowerBound -= 4; // The CR save area is always 4 bytes long. 1230 } 1231 1232 if (HasVRSAVESaveArea) { 1233 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1234 // which have the VRSAVE register class? 1235 // Adjust the frame index of the VRSAVE spill slot. 1236 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1237 const TargetRegisterClass *RC = CSI[i].getRegClass(); 1238 1239 if (RC == PPC::VRSAVERCRegisterClass) { 1240 int FI = CSI[i].getFrameIdx(); 1241 1242 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1243 } 1244 } 1245 1246 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1247 } 1248 1249 if (HasVRSaveArea) { 1250 // Insert alignment padding, we need 16-byte alignment. 1251 LowerBound = (LowerBound - 15) & ~(15); 1252 1253 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1254 int FI = VRegs[i].getFrameIdx(); 1255 1256 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1257 } 1258 } 1259 } 1260 1261 void 1262 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 1263 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 1264 MachineBasicBlock::iterator MBBI = MBB.begin(); 1265 MachineFrameInfo *MFI = MF.getFrameInfo(); 1266 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 1267 DebugLoc dl = DebugLoc::getUnknownLoc(); 1268 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) || 1269 !MF.getFunction()->doesNotThrow() || 1270 UnwindTablesMandatory; 1271 1272 // Prepare for frame info. 1273 unsigned FrameLabelId = 0; 1274 1275 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 1276 // process it. 1277 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 1278 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 1279 HandleVRSaveUpdate(MBBI, TII); 1280 break; 1281 } 1282 } 1283 1284 // Move MBBI back to the beginning of the function. 1285 MBBI = MBB.begin(); 1286 1287 // Work out frame sizes. 1288 determineFrameLayout(MF); 1289 unsigned FrameSize = MFI->getStackSize(); 1290 1291 int NegFrameSize = -FrameSize; 1292 1293 // Get processor type. 1294 bool IsPPC64 = Subtarget.isPPC64(); 1295 // Get operating system 1296 bool isDarwinABI = Subtarget.isDarwinABI(); 1297 // Check if the link register (LR) must be saved. 1298 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1299 bool MustSaveLR = FI->mustSaveLR(); 1300 // Do we have a frame pointer for this function? 1301 bool HasFP = hasFP(MF) && FrameSize; 1302 1303 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI); 1304 1305 int FPOffset = 0; 1306 if (HasFP) { 1307 if (Subtarget.isSVR4ABI()) { 1308 MachineFrameInfo *FFI = MF.getFrameInfo(); 1309 int FPIndex = FI->getFramePointerSaveIndex(); 1310 assert(FPIndex && "No Frame Pointer Save Slot!"); 1311 FPOffset = FFI->getObjectOffset(FPIndex); 1312 } else { 1313 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isDarwinABI); 1314 } 1315 } 1316 1317 if (IsPPC64) { 1318 if (MustSaveLR) 1319 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 1320 1321 if (HasFP) 1322 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 1323 .addReg(PPC::X31) 1324 .addImm(FPOffset/4) 1325 .addReg(PPC::X1); 1326 1327 if (MustSaveLR) 1328 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 1329 .addReg(PPC::X0) 1330 .addImm(LROffset / 4) 1331 .addReg(PPC::X1); 1332 } else { 1333 if (MustSaveLR) 1334 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 1335 1336 if (HasFP) 1337 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 1338 .addReg(PPC::R31) 1339 .addImm(FPOffset) 1340 .addReg(PPC::R1); 1341 1342 if (MustSaveLR) 1343 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 1344 .addReg(PPC::R0) 1345 .addImm(LROffset) 1346 .addReg(PPC::R1); 1347 } 1348 1349 // Skip if a leaf routine. 1350 if (!FrameSize) return; 1351 1352 // Get stack alignments. 1353 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1354 unsigned MaxAlign = MFI->getMaxAlignment(); 1355 1356 if (needsFrameMoves) { 1357 // Mark effective beginning of when frame pointer becomes valid. 1358 FrameLabelId = MMI->NextLabelID(); 1359 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId); 1360 } 1361 1362 // Adjust stack pointer: r1 += NegFrameSize. 1363 // If there is a preferred stack alignment, align R1 now 1364 if (!IsPPC64) { 1365 // PPC32. 1366 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1367 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 1368 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 1369 1370 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 1371 .addReg(PPC::R1) 1372 .addImm(0) 1373 .addImm(32 - Log2_32(MaxAlign)) 1374 .addImm(31); 1375 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 1376 .addReg(PPC::R0, RegState::Kill) 1377 .addImm(NegFrameSize); 1378 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) 1379 .addReg(PPC::R1) 1380 .addReg(PPC::R1) 1381 .addReg(PPC::R0); 1382 } else if (isInt16(NegFrameSize)) { 1383 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 1384 .addReg(PPC::R1) 1385 .addImm(NegFrameSize) 1386 .addReg(PPC::R1); 1387 } else { 1388 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 1389 .addImm(NegFrameSize >> 16); 1390 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 1391 .addReg(PPC::R0, RegState::Kill) 1392 .addImm(NegFrameSize & 0xFFFF); 1393 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) 1394 .addReg(PPC::R1) 1395 .addReg(PPC::R1) 1396 .addReg(PPC::R0); 1397 } 1398 } else { // PPC64. 1399 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1400 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 1401 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 1402 1403 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 1404 .addReg(PPC::X1) 1405 .addImm(0) 1406 .addImm(64 - Log2_32(MaxAlign)); 1407 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 1408 .addReg(PPC::X0) 1409 .addImm(NegFrameSize); 1410 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) 1411 .addReg(PPC::X1) 1412 .addReg(PPC::X1) 1413 .addReg(PPC::X0); 1414 } else if (isInt16(NegFrameSize)) { 1415 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 1416 .addReg(PPC::X1) 1417 .addImm(NegFrameSize / 4) 1418 .addReg(PPC::X1); 1419 } else { 1420 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 1421 .addImm(NegFrameSize >> 16); 1422 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 1423 .addReg(PPC::X0, RegState::Kill) 1424 .addImm(NegFrameSize & 0xFFFF); 1425 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) 1426 .addReg(PPC::X1) 1427 .addReg(PPC::X1) 1428 .addReg(PPC::X0); 1429 } 1430 } 1431 1432 if (needsFrameMoves) { 1433 std::vector<MachineMove> &Moves = MMI->getFrameMoves(); 1434 1435 if (NegFrameSize) { 1436 // Show update of SP. 1437 MachineLocation SPDst(MachineLocation::VirtualFP); 1438 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 1439 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); 1440 } else { 1441 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31); 1442 Moves.push_back(MachineMove(FrameLabelId, SP, SP)); 1443 } 1444 1445 if (HasFP) { 1446 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 1447 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31); 1448 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); 1449 } 1450 1451 // Add callee saved registers to move list. 1452 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1453 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1454 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1455 unsigned Reg = CSI[I].getReg(); 1456 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 1457 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 1458 MachineLocation CSSrc(Reg); 1459 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); 1460 } 1461 1462 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 1463 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR); 1464 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc)); 1465 1466 // Mark effective beginning of when frame pointer is ready. 1467 unsigned ReadyLabelId = MMI->NextLabelID(); 1468 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId); 1469 1470 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : 1471 (IsPPC64 ? PPC::X1 : PPC::R1)); 1472 MachineLocation FPSrc(MachineLocation::VirtualFP); 1473 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); 1474 } 1475 1476 // If there is a frame pointer, copy R1 into R31 1477 if (HasFP) { 1478 if (!IsPPC64) { 1479 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 1480 .addReg(PPC::R1) 1481 .addReg(PPC::R1); 1482 } else { 1483 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 1484 .addReg(PPC::X1) 1485 .addReg(PPC::X1); 1486 } 1487 } 1488 } 1489 1490 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 1491 MachineBasicBlock &MBB) const { 1492 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1493 unsigned RetOpcode = MBBI->getOpcode(); 1494 DebugLoc dl = DebugLoc::getUnknownLoc(); 1495 1496 assert( (RetOpcode == PPC::BLR || 1497 RetOpcode == PPC::TCRETURNri || 1498 RetOpcode == PPC::TCRETURNdi || 1499 RetOpcode == PPC::TCRETURNai || 1500 RetOpcode == PPC::TCRETURNri8 || 1501 RetOpcode == PPC::TCRETURNdi8 || 1502 RetOpcode == PPC::TCRETURNai8) && 1503 "Can only insert epilog into returning blocks"); 1504 1505 // Get alignment info so we know how to restore r1 1506 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1507 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1508 unsigned MaxAlign = MFI->getMaxAlignment(); 1509 1510 // Get the number of bytes allocated from the FrameInfo. 1511 int FrameSize = MFI->getStackSize(); 1512 1513 // Get processor type. 1514 bool IsPPC64 = Subtarget.isPPC64(); 1515 // Get operating system 1516 bool isDarwinABI = Subtarget.isDarwinABI(); 1517 // Check if the link register (LR) has been saved. 1518 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1519 bool MustSaveLR = FI->mustSaveLR(); 1520 // Do we have a frame pointer for this function? 1521 bool HasFP = hasFP(MF) && FrameSize; 1522 1523 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI); 1524 1525 int FPOffset = 0; 1526 if (HasFP) { 1527 if (Subtarget.isSVR4ABI()) { 1528 MachineFrameInfo *FFI = MF.getFrameInfo(); 1529 int FPIndex = FI->getFramePointerSaveIndex(); 1530 assert(FPIndex && "No Frame Pointer Save Slot!"); 1531 FPOffset = FFI->getObjectOffset(FPIndex); 1532 } else { 1533 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isDarwinABI); 1534 } 1535 } 1536 1537 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 1538 RetOpcode == PPC::TCRETURNdi || 1539 RetOpcode == PPC::TCRETURNai || 1540 RetOpcode == PPC::TCRETURNri8 || 1541 RetOpcode == PPC::TCRETURNdi8 || 1542 RetOpcode == PPC::TCRETURNai8; 1543 1544 if (UsesTCRet) { 1545 int MaxTCRetDelta = FI->getTailCallSPDelta(); 1546 MachineOperand &StackAdjust = MBBI->getOperand(1); 1547 assert(StackAdjust.isImm() && "Expecting immediate value."); 1548 // Adjust stack pointer. 1549 int StackAdj = StackAdjust.getImm(); 1550 int Delta = StackAdj - MaxTCRetDelta; 1551 assert((Delta >= 0) && "Delta must be positive"); 1552 if (MaxTCRetDelta>0) 1553 FrameSize += (StackAdj +Delta); 1554 else 1555 FrameSize += StackAdj; 1556 } 1557 1558 if (FrameSize) { 1559 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 1560 // on entry to the function. Add this offset back now. 1561 if (!IsPPC64) { 1562 // If this function contained a fastcc call and PerformTailCallOpt is 1563 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 1564 // call which invalidates the stack pointer value in SP(0). So we use the 1565 // value of R31 in this case. 1566 if (FI->hasFastCall() && isInt16(FrameSize)) { 1567 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 1568 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 1569 .addReg(PPC::R31).addImm(FrameSize); 1570 } else if(FI->hasFastCall()) { 1571 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 1572 .addImm(FrameSize >> 16); 1573 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 1574 .addReg(PPC::R0, RegState::Kill) 1575 .addImm(FrameSize & 0xFFFF); 1576 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 1577 .addReg(PPC::R1) 1578 .addReg(PPC::R31) 1579 .addReg(PPC::R0); 1580 } else if (isInt16(FrameSize) && 1581 (!ALIGN_STACK || TargetAlign >= MaxAlign) && 1582 !MFI->hasVarSizedObjects()) { 1583 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 1584 .addReg(PPC::R1).addImm(FrameSize); 1585 } else { 1586 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 1587 .addImm(0).addReg(PPC::R1); 1588 } 1589 } else { 1590 if (FI->hasFastCall() && isInt16(FrameSize)) { 1591 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 1592 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 1593 .addReg(PPC::X31).addImm(FrameSize); 1594 } else if(FI->hasFastCall()) { 1595 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 1596 .addImm(FrameSize >> 16); 1597 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 1598 .addReg(PPC::X0, RegState::Kill) 1599 .addImm(FrameSize & 0xFFFF); 1600 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 1601 .addReg(PPC::X1) 1602 .addReg(PPC::X31) 1603 .addReg(PPC::X0); 1604 } else if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1605 !MFI->hasVarSizedObjects()) { 1606 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 1607 .addReg(PPC::X1).addImm(FrameSize); 1608 } else { 1609 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 1610 .addImm(0).addReg(PPC::X1); 1611 } 1612 } 1613 } 1614 1615 if (IsPPC64) { 1616 if (MustSaveLR) 1617 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 1618 .addImm(LROffset/4).addReg(PPC::X1); 1619 1620 if (HasFP) 1621 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 1622 .addImm(FPOffset/4).addReg(PPC::X1); 1623 1624 if (MustSaveLR) 1625 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 1626 } else { 1627 if (MustSaveLR) 1628 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 1629 .addImm(LROffset).addReg(PPC::R1); 1630 1631 if (HasFP) 1632 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 1633 .addImm(FPOffset).addReg(PPC::R1); 1634 1635 if (MustSaveLR) 1636 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 1637 } 1638 1639 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 1640 // call optimization 1641 if (PerformTailCallOpt && RetOpcode == PPC::BLR && 1642 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 1643 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1644 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 1645 unsigned StackReg = IsPPC64 ? PPC::X1 : PPC::R1; 1646 unsigned FPReg = IsPPC64 ? PPC::X31 : PPC::R31; 1647 unsigned TmpReg = IsPPC64 ? PPC::X0 : PPC::R0; 1648 unsigned ADDIInstr = IsPPC64 ? PPC::ADDI8 : PPC::ADDI; 1649 unsigned ADDInstr = IsPPC64 ? PPC::ADD8 : PPC::ADD4; 1650 unsigned LISInstr = IsPPC64 ? PPC::LIS8 : PPC::LIS; 1651 unsigned ORIInstr = IsPPC64 ? PPC::ORI8 : PPC::ORI; 1652 1653 if (CallerAllocatedAmt && isInt16(CallerAllocatedAmt)) { 1654 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 1655 .addReg(StackReg).addImm(CallerAllocatedAmt); 1656 } else { 1657 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1658 .addImm(CallerAllocatedAmt >> 16); 1659 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1660 .addReg(TmpReg, RegState::Kill) 1661 .addImm(CallerAllocatedAmt & 0xFFFF); 1662 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 1663 .addReg(StackReg) 1664 .addReg(FPReg) 1665 .addReg(TmpReg); 1666 } 1667 } else if (RetOpcode == PPC::TCRETURNdi) { 1668 MBBI = prior(MBB.end()); 1669 MachineOperand &JumpTarget = MBBI->getOperand(0); 1670 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 1671 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1672 } else if (RetOpcode == PPC::TCRETURNri) { 1673 MBBI = prior(MBB.end()); 1674 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1675 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 1676 } else if (RetOpcode == PPC::TCRETURNai) { 1677 MBBI = prior(MBB.end()); 1678 MachineOperand &JumpTarget = MBBI->getOperand(0); 1679 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 1680 } else if (RetOpcode == PPC::TCRETURNdi8) { 1681 MBBI = prior(MBB.end()); 1682 MachineOperand &JumpTarget = MBBI->getOperand(0); 1683 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 1684 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1685 } else if (RetOpcode == PPC::TCRETURNri8) { 1686 MBBI = prior(MBB.end()); 1687 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1688 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 1689 } else if (RetOpcode == PPC::TCRETURNai8) { 1690 MBBI = prior(MBB.end()); 1691 MachineOperand &JumpTarget = MBBI->getOperand(0); 1692 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 1693 } 1694 } 1695 1696 unsigned PPCRegisterInfo::getRARegister() const { 1697 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1698 } 1699 1700 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1701 if (!Subtarget.isPPC64()) 1702 return hasFP(MF) ? PPC::R31 : PPC::R1; 1703 else 1704 return hasFP(MF) ? PPC::X31 : PPC::X1; 1705 } 1706 1707 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1708 const { 1709 // Initial state of the frame pointer is R1. 1710 MachineLocation Dst(MachineLocation::VirtualFP); 1711 MachineLocation Src(PPC::R1, 0); 1712 Moves.push_back(MachineMove(0, Dst, Src)); 1713 } 1714 1715 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 1716 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 1717 } 1718 1719 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 1720 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 1721 } 1722 1723 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1724 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 1725 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 1726 } 1727 1728 #include "PPCGenRegisterInfo.inc" 1729 1730