1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCRegisterInfo.h" 19 #include "PPCFrameInfo.h" 20 #include "PPCSubtarget.h" 21 #include "llvm/Constants.h" 22 #include "llvm/Type.h" 23 #include "llvm/CodeGen/ValueTypes.h" 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 25 #include "llvm/CodeGen/MachineModuleInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineLocation.h" 29 #include "llvm/CodeGen/SelectionDAGNodes.h" 30 #include "llvm/Target/TargetFrameInfo.h" 31 #include "llvm/Target/TargetInstrInfo.h" 32 #include "llvm/Target/TargetMachine.h" 33 #include "llvm/Target/TargetOptions.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/ADT/BitVector.h" 38 #include "llvm/ADT/STLExtras.h" 39 #include <cstdlib> 40 using namespace llvm; 41 42 /// getRegisterNumbering - Given the enum value for some register, e.g. 43 /// PPC::F14, return the number that it corresponds to (e.g. 14). 44 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 45 using namespace PPC; 46 switch (RegEnum) { 47 case R0 : case X0 : case F0 : case V0 : case CR0: return 0; 48 case R1 : case X1 : case F1 : case V1 : case CR1: return 1; 49 case R2 : case X2 : case F2 : case V2 : case CR2: return 2; 50 case R3 : case X3 : case F3 : case V3 : case CR3: return 3; 51 case R4 : case X4 : case F4 : case V4 : case CR4: return 4; 52 case R5 : case X5 : case F5 : case V5 : case CR5: return 5; 53 case R6 : case X6 : case F6 : case V6 : case CR6: return 6; 54 case R7 : case X7 : case F7 : case V7 : case CR7: return 7; 55 case R8 : case X8 : case F8 : case V8 : return 8; 56 case R9 : case X9 : case F9 : case V9 : return 9; 57 case R10: case X10: case F10: case V10: return 10; 58 case R11: case X11: case F11: case V11: return 11; 59 case R12: case X12: case F12: case V12: return 12; 60 case R13: case X13: case F13: case V13: return 13; 61 case R14: case X14: case F14: case V14: return 14; 62 case R15: case X15: case F15: case V15: return 15; 63 case R16: case X16: case F16: case V16: return 16; 64 case R17: case X17: case F17: case V17: return 17; 65 case R18: case X18: case F18: case V18: return 18; 66 case R19: case X19: case F19: case V19: return 19; 67 case R20: case X20: case F20: case V20: return 20; 68 case R21: case X21: case F21: case V21: return 21; 69 case R22: case X22: case F22: case V22: return 22; 70 case R23: case X23: case F23: case V23: return 23; 71 case R24: case X24: case F24: case V24: return 24; 72 case R25: case X25: case F25: case V25: return 25; 73 case R26: case X26: case F26: case V26: return 26; 74 case R27: case X27: case F27: case V27: return 27; 75 case R28: case X28: case F28: case V28: return 28; 76 case R29: case X29: case F29: case V29: return 29; 77 case R30: case X30: case F30: case V30: return 30; 78 case R31: case X31: case F31: case V31: return 31; 79 default: 80 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; 81 abort(); 82 } 83 } 84 85 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 86 const TargetInstrInfo &tii) 87 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 88 Subtarget(ST), TII(tii) { 89 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 90 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 91 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 92 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 93 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 94 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 95 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 96 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 97 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 98 } 99 100 void 101 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 102 MachineBasicBlock::iterator MI, 103 unsigned SrcReg, int FrameIdx, 104 const TargetRegisterClass *RC) const { 105 if (RC == PPC::GPRCRegisterClass) { 106 if (SrcReg != PPC::LR) { 107 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) 108 .addReg(SrcReg, false, false, true), FrameIdx); 109 } else { 110 // FIXME: this spills LR immediately to memory in one step. To do this, 111 // we use R11, which we know cannot be used in the prolog/epilog. This is 112 // a hack. 113 BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11); 114 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) 115 .addReg(PPC::R11, false, false, true), FrameIdx); 116 } 117 } else if (RC == PPC::G8RCRegisterClass) { 118 if (SrcReg != PPC::LR8) { 119 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)) 120 .addReg(SrcReg, false, false, true), FrameIdx); 121 } else { 122 // FIXME: this spills LR immediately to memory in one step. To do this, 123 // we use R11, which we know cannot be used in the prolog/epilog. This is 124 // a hack. 125 BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11); 126 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)) 127 .addReg(PPC::X11, false, false, true), FrameIdx); 128 } 129 } else if (RC == PPC::F8RCRegisterClass) { 130 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)) 131 .addReg(SrcReg, false, false, true), FrameIdx); 132 } else if (RC == PPC::F4RCRegisterClass) { 133 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)) 134 .addReg(SrcReg, false, false, true), FrameIdx); 135 } else if (RC == PPC::CRRCRegisterClass) { 136 // FIXME: We use R0 here, because it isn't available for RA. 137 // We need to store the CR in the low 4-bits of the saved value. First, 138 // issue a MFCR to save all of the CRBits. 139 BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0); 140 141 // If the saved register wasn't CR0, shift the bits left so that they are in 142 // CR0's slot. 143 if (SrcReg != PPC::CR0) { 144 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 145 // rlwinm r0, r0, ShiftBits, 0, 31. 146 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) 147 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31); 148 } 149 150 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) 151 .addReg(PPC::R0, false, false, true), FrameIdx); 152 } else if (RC == PPC::VRRCRegisterClass) { 153 // We don't have indexed addressing for vector loads. Emit: 154 // R11 = ADDI FI# 155 // Dest = LVX R0, R11 156 // 157 // FIXME: We use R0 here, because it isn't available for RA. 158 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), 159 FrameIdx, 0, 0); 160 BuildMI(MBB, MI, TII.get(PPC::STVX)) 161 .addReg(SrcReg, false, false, true).addReg(PPC::R0).addReg(PPC::R0); 162 } else { 163 assert(0 && "Unknown regclass!"); 164 abort(); 165 } 166 } 167 168 void 169 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 170 MachineBasicBlock::iterator MI, 171 unsigned DestReg, int FrameIdx, 172 const TargetRegisterClass *RC) const { 173 if (RC == PPC::GPRCRegisterClass) { 174 if (DestReg != PPC::LR) { 175 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), DestReg), FrameIdx); 176 } else { 177 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R11),FrameIdx); 178 BuildMI(MBB, MI, TII.get(PPC::MTLR)).addReg(PPC::R11); 179 } 180 } else if (RC == PPC::G8RCRegisterClass) { 181 if (DestReg != PPC::LR8) { 182 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), DestReg), FrameIdx); 183 } else { 184 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), PPC::R11), FrameIdx); 185 BuildMI(MBB, MI, TII.get(PPC::MTLR8)).addReg(PPC::R11); 186 } 187 } else if (RC == PPC::F8RCRegisterClass) { 188 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFD), DestReg), FrameIdx); 189 } else if (RC == PPC::F4RCRegisterClass) { 190 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFS), DestReg), FrameIdx); 191 } else if (RC == PPC::CRRCRegisterClass) { 192 // FIXME: We use R0 here, because it isn't available for RA. 193 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R0), FrameIdx); 194 195 // If the reloaded register isn't CR0, shift the bits right so that they are 196 // in the right CR's slot. 197 if (DestReg != PPC::CR0) { 198 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 199 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 200 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) 201 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31); 202 } 203 204 BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0); 205 } else if (RC == PPC::VRRCRegisterClass) { 206 // We don't have indexed addressing for vector loads. Emit: 207 // R11 = ADDI FI# 208 // Dest = LVX R0, R11 209 // 210 // FIXME: We use R0 here, because it isn't available for RA. 211 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), 212 FrameIdx, 0, 0); 213 BuildMI(MBB, MI, TII.get(PPC::LVX),DestReg).addReg(PPC::R0).addReg(PPC::R0); 214 } else { 215 assert(0 && "Unknown regclass!"); 216 abort(); 217 } 218 } 219 220 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 221 MachineBasicBlock::iterator MI, 222 unsigned DestReg, unsigned SrcReg, 223 const TargetRegisterClass *RC) const { 224 if (RC == PPC::GPRCRegisterClass) { 225 BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); 226 } else if (RC == PPC::G8RCRegisterClass) { 227 BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); 228 } else if (RC == PPC::F4RCRegisterClass) { 229 BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg); 230 } else if (RC == PPC::F8RCRegisterClass) { 231 BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg); 232 } else if (RC == PPC::CRRCRegisterClass) { 233 BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg); 234 } else if (RC == PPC::VRRCRegisterClass) { 235 BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); 236 } else { 237 cerr << "Attempt to copy register that is not GPR or FPR"; 238 abort(); 239 } 240 } 241 242 const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const { 243 // 32-bit Darwin calling convention. 244 static const unsigned Darwin32_CalleeSavedRegs[] = { 245 PPC::R13, PPC::R14, PPC::R15, 246 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 247 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 248 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 249 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 250 251 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 252 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 253 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 254 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 255 PPC::F30, PPC::F31, 256 257 PPC::CR2, PPC::CR3, PPC::CR4, 258 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 259 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 260 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 261 262 PPC::LR, 0 263 }; 264 // 64-bit Darwin calling convention. 265 static const unsigned Darwin64_CalleeSavedRegs[] = { 266 PPC::X14, PPC::X15, 267 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 268 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 269 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 270 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 271 272 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 273 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 274 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 275 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 276 PPC::F30, PPC::F31, 277 278 PPC::CR2, PPC::CR3, PPC::CR4, 279 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 280 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 281 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 282 283 PPC::LR8, 0 284 }; 285 286 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : 287 Darwin32_CalleeSavedRegs; 288 } 289 290 const TargetRegisterClass* const* 291 PPCRegisterInfo::getCalleeSavedRegClasses() const { 292 // 32-bit Darwin calling convention. 293 static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = { 294 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 295 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 296 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 297 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 298 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 299 300 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 301 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 302 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 303 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 304 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 305 306 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 307 308 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 309 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 310 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 311 312 &PPC::GPRCRegClass, 0 313 }; 314 315 // 64-bit Darwin calling convention. 316 static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = { 317 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 318 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 319 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 320 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 321 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 322 323 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 324 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 325 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 326 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 327 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 328 329 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 330 331 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 332 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 333 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 334 335 &PPC::G8RCRegClass, 0 336 }; 337 338 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses : 339 Darwin32_CalleeSavedRegClasses; 340 } 341 342 // needsFP - Return true if the specified function should have a dedicated frame 343 // pointer register. This is true if the function has variable sized allocas or 344 // if frame pointer elimination is disabled. 345 // 346 static bool needsFP(const MachineFunction &MF) { 347 const MachineFrameInfo *MFI = MF.getFrameInfo(); 348 return NoFramePointerElim || MFI->hasVarSizedObjects(); 349 } 350 351 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 352 BitVector Reserved(getNumRegs()); 353 Reserved.set(PPC::R0); 354 Reserved.set(PPC::R1); 355 Reserved.set(PPC::LR); 356 // In Linux, r2 is reserved for the OS. 357 if (!Subtarget.isDarwin()) 358 Reserved.set(PPC::R2); 359 // On PPC64, r13 is the thread pointer. Never allocate this register. 360 // Note that this is overconservative, as it also prevents allocation of 361 // R31 when the FP is not needed. 362 if (Subtarget.isPPC64()) { 363 Reserved.set(PPC::R13); 364 Reserved.set(PPC::R31); 365 } 366 if (needsFP(MF)) 367 Reserved.set(PPC::R31); 368 return Reserved; 369 } 370 371 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 372 /// copy instructions, turning them into load/store instructions. 373 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 374 unsigned OpNum, 375 int FrameIndex) const { 376 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 377 // it takes more than one instruction to store it. 378 unsigned Opc = MI->getOpcode(); 379 380 MachineInstr *NewMI = NULL; 381 if ((Opc == PPC::OR && 382 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 383 if (OpNum == 0) { // move -> store 384 unsigned InReg = MI->getOperand(1).getReg(); 385 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg), 386 FrameIndex); 387 } else { // move -> load 388 unsigned OutReg = MI->getOperand(0).getReg(); 389 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg), 390 FrameIndex); 391 } 392 } else if ((Opc == PPC::OR8 && 393 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 394 if (OpNum == 0) { // move -> store 395 unsigned InReg = MI->getOperand(1).getReg(); 396 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg), 397 FrameIndex); 398 } else { // move -> load 399 unsigned OutReg = MI->getOperand(0).getReg(); 400 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex); 401 } 402 } else if (Opc == PPC::FMRD) { 403 if (OpNum == 0) { // move -> store 404 unsigned InReg = MI->getOperand(1).getReg(); 405 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg), 406 FrameIndex); 407 } else { // move -> load 408 unsigned OutReg = MI->getOperand(0).getReg(); 409 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex); 410 } 411 } else if (Opc == PPC::FMRS) { 412 if (OpNum == 0) { // move -> store 413 unsigned InReg = MI->getOperand(1).getReg(); 414 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg), 415 FrameIndex); 416 } else { // move -> load 417 unsigned OutReg = MI->getOperand(0).getReg(); 418 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex); 419 } 420 } 421 422 if (NewMI) 423 NewMI->copyKillDeadInfo(MI); 424 return NewMI; 425 } 426 427 //===----------------------------------------------------------------------===// 428 // Stack Frame Processing methods 429 //===----------------------------------------------------------------------===// 430 431 // hasFP - Return true if the specified function actually has a dedicated frame 432 // pointer register. This is true if the function needs a frame pointer and has 433 // a non-zero stack size. 434 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 435 const MachineFrameInfo *MFI = MF.getFrameInfo(); 436 return MFI->getStackSize() && needsFP(MF); 437 } 438 439 /// usesLR - Returns if the link registers (LR) has been used in the function. 440 /// 441 bool PPCRegisterInfo::usesLR(MachineFunction &MF) const { 442 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 443 return FI->usesLR(); 444 } 445 446 void PPCRegisterInfo:: 447 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 448 MachineBasicBlock::iterator I) const { 449 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 450 MBB.erase(I); 451 } 452 453 /// LowerDynamicAlloc - Generate the code for allocating an object in the 454 /// current frame. The sequence of code with be in the general form 455 /// 456 /// addi R0, SP, #frameSize ; get the address of the previous frame 457 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 458 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation 459 /// 460 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 461 // Get the instruction. 462 MachineInstr &MI = *II; 463 // Get the instruction's basic block. 464 MachineBasicBlock &MBB = *MI.getParent(); 465 // Get the basic block's function. 466 MachineFunction &MF = *MBB.getParent(); 467 // Get the frame info. 468 MachineFrameInfo *MFI = MF.getFrameInfo(); 469 // Determine whether 64-bit pointers are used. 470 bool LP64 = Subtarget.isPPC64(); 471 472 // Get the maximum call stack size. 473 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 474 // Get the total frame size. 475 unsigned FrameSize = MFI->getStackSize(); 476 477 // Get stack alignments. 478 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 479 unsigned MaxAlign = MFI->getMaxAlignment(); 480 assert(MaxAlign <= TargetAlign && 481 "Dynamic alloca with large aligns not supported"); 482 483 // Determine the previous frame's address. If FrameSize can't be 484 // represented as 16 bits or we need special alignment, then we load the 485 // previous frame's address from 0(SP). Why not do an addis of the hi? 486 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 487 // Constructing the constant and adding would take 3 instructions. 488 // Fortunately, a frame greater than 32K is rare. 489 if (MaxAlign < TargetAlign && isInt16(FrameSize)) { 490 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0) 491 .addReg(PPC::R31) 492 .addImm(FrameSize); 493 } else if (LP64) { 494 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) 495 .addImm(0) 496 .addReg(PPC::X1); 497 } else { 498 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0) 499 .addImm(0) 500 .addReg(PPC::R1); 501 } 502 503 // Grow the stack and update the stack pointer link, then 504 // determine the address of new allocated space. 505 if (LP64) { 506 BuildMI(MBB, II, TII.get(PPC::STDUX)) 507 .addReg(PPC::X0) 508 .addReg(PPC::X1) 509 .addReg(MI.getOperand(1).getReg()); 510 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 511 .addReg(PPC::X1) 512 .addImm(maxCallFrameSize); 513 } else { 514 BuildMI(MBB, II, TII.get(PPC::STWUX)) 515 .addReg(PPC::R0) 516 .addReg(PPC::R1) 517 .addReg(MI.getOperand(1).getReg()); 518 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 519 .addReg(PPC::R1) 520 .addImm(maxCallFrameSize); 521 } 522 523 // Discard the DYNALLOC instruction. 524 MBB.erase(II); 525 } 526 527 void 528 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 529 // Get the instruction. 530 MachineInstr &MI = *II; 531 // Get the instruction's basic block. 532 MachineBasicBlock &MBB = *MI.getParent(); 533 // Get the basic block's function. 534 MachineFunction &MF = *MBB.getParent(); 535 // Get the frame info. 536 MachineFrameInfo *MFI = MF.getFrameInfo(); 537 538 // Find out which operand is the frame index. 539 unsigned i = 0; 540 while (!MI.getOperand(i).isFrameIndex()) { 541 ++i; 542 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 543 } 544 // Take into account whether it's an add or mem instruction 545 unsigned OffIdx = (i == 2) ? 1 : 2; 546 if (MI.getOpcode() == TargetInstrInfo::INLINEASM) 547 OffIdx = i-1; 548 549 // Get the frame index. 550 int FrameIndex = MI.getOperand(i).getFrameIndex(); 551 552 // Get the frame pointer save index. Users of this index are primarily 553 // DYNALLOC instructions. 554 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 555 int FPSI = FI->getFramePointerSaveIndex(); 556 // Get the instruction opcode. 557 unsigned OpC = MI.getOpcode(); 558 559 // Special case for dynamic alloca. 560 if (FPSI && FrameIndex == FPSI && 561 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 562 lowerDynamicAlloc(II); 563 return; 564 } 565 566 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 567 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false); 568 569 // Figure out if the offset in the instruction is shifted right two bits. This 570 // is true for instructions like "STD", which the machine implicitly adds two 571 // low zeros to. 572 bool isIXAddr = false; 573 switch (OpC) { 574 case PPC::LWA: 575 case PPC::LD: 576 case PPC::STD: 577 case PPC::STD_32: 578 isIXAddr = true; 579 break; 580 } 581 582 // Now add the frame object offset to the offset from r1. 583 int Offset = MFI->getObjectOffset(FrameIndex); 584 585 if (!isIXAddr) 586 Offset += MI.getOperand(OffIdx).getImmedValue(); 587 else 588 Offset += MI.getOperand(OffIdx).getImmedValue() << 2; 589 590 // If we're not using a Frame Pointer that has been set to the value of the 591 // SP before having the stack size subtracted from it, then add the stack size 592 // to Offset to get the correct offset. 593 Offset += MFI->getStackSize(); 594 595 if (!isInt16(Offset)) { 596 // Insert a set of r0 with the full offset value before the ld, st, or add 597 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16); 598 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset); 599 600 // convert into indexed form of the instruction 601 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 602 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 603 assert(ImmToIdxMap.count(OpC) && 604 "No indexed form of load or store available!"); 605 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 606 MI.setInstrDescriptor(TII.get(NewOpcode)); 607 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false); 608 MI.getOperand(2).ChangeToRegister(PPC::R0, false); 609 } else { 610 if (isIXAddr) { 611 assert((Offset & 3) == 0 && "Invalid frame offset!"); 612 Offset >>= 2; // The actual encoded value has the low two bits zero. 613 } 614 MI.getOperand(OffIdx).ChangeToImmediate(Offset); 615 } 616 } 617 618 /// VRRegNo - Map from a numbered VR register to its enum value. 619 /// 620 static const unsigned short VRRegNo[] = { 621 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 622 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 623 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 624 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 625 }; 626 627 /// RemoveVRSaveCode - We have found that this function does not need any code 628 /// to manipulate the VRSAVE register, even though it uses vector registers. 629 /// This can happen when the only registers used are known to be live in or out 630 /// of the function. Remove all of the VRSAVE related code from the function. 631 static void RemoveVRSaveCode(MachineInstr *MI) { 632 MachineBasicBlock *Entry = MI->getParent(); 633 MachineFunction *MF = Entry->getParent(); 634 635 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 636 MachineBasicBlock::iterator MBBI = MI; 637 ++MBBI; 638 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 639 MBBI->eraseFromParent(); 640 641 bool RemovedAllMTVRSAVEs = true; 642 // See if we can find and remove the MTVRSAVE instruction from all of the 643 // epilog blocks. 644 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 645 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 646 // If last instruction is a return instruction, add an epilogue 647 if (!I->empty() && TII.isReturn(I->back().getOpcode())) { 648 bool FoundIt = false; 649 for (MBBI = I->end(); MBBI != I->begin(); ) { 650 --MBBI; 651 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 652 MBBI->eraseFromParent(); // remove it. 653 FoundIt = true; 654 break; 655 } 656 } 657 RemovedAllMTVRSAVEs &= FoundIt; 658 } 659 } 660 661 // If we found and removed all MTVRSAVE instructions, remove the read of 662 // VRSAVE as well. 663 if (RemovedAllMTVRSAVEs) { 664 MBBI = MI; 665 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 666 --MBBI; 667 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 668 MBBI->eraseFromParent(); 669 } 670 671 // Finally, nuke the UPDATE_VRSAVE. 672 MI->eraseFromParent(); 673 } 674 675 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 676 // instruction selector. Based on the vector registers that have been used, 677 // transform this into the appropriate ORI instruction. 678 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs, 679 const TargetInstrInfo &TII) { 680 unsigned UsedRegMask = 0; 681 for (unsigned i = 0; i != 32; ++i) 682 if (UsedRegs[VRRegNo[i]]) 683 UsedRegMask |= 1 << (31-i); 684 685 // Live in and live out values already must be in the mask, so don't bother 686 // marking them. 687 MachineFunction *MF = MI->getParent()->getParent(); 688 for (MachineFunction::livein_iterator I = 689 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) { 690 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 691 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 692 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 693 } 694 for (MachineFunction::liveout_iterator I = 695 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) { 696 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 697 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 698 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 699 } 700 701 unsigned SrcReg = MI->getOperand(1).getReg(); 702 unsigned DstReg = MI->getOperand(0).getReg(); 703 // If no registers are used, turn this into a copy. 704 if (UsedRegMask == 0) { 705 // Remove all VRSAVE code. 706 RemoveVRSaveCode(MI); 707 return; 708 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 709 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 710 .addReg(SrcReg).addImm(UsedRegMask); 711 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 712 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 713 .addReg(SrcReg).addImm(UsedRegMask >> 16); 714 } else { 715 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 716 .addReg(SrcReg).addImm(UsedRegMask >> 16); 717 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 718 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 719 } 720 721 // Remove the old UPDATE_VRSAVE instruction. 722 MI->eraseFromParent(); 723 } 724 725 /// determineFrameLayout - Determine the size of the frame and maximum call 726 /// frame size. 727 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 728 MachineFrameInfo *MFI = MF.getFrameInfo(); 729 730 // Get the number of bytes to allocate from the FrameInfo 731 unsigned FrameSize = MFI->getStackSize(); 732 733 // Get the alignments provided by the target, and the maximum alignment 734 // (if any) of the fixed frame objects. 735 unsigned MaxAlign = MFI->getMaxAlignment(); 736 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 737 unsigned AlignMask = TargetAlign - 1; // 738 739 // If we are a leaf function, and use up to 224 bytes of stack space, 740 // don't have a frame pointer, calls, or dynamic alloca then we do not need 741 // to adjust the stack pointer (we fit in the Red Zone). 742 if (FrameSize <= 224 && // Fits in red zone. 743 !MFI->hasVarSizedObjects() && // No dynamic alloca. 744 !MFI->hasCalls() && // No calls. 745 MaxAlign <= TargetAlign) { // No special alignment. 746 // No need for frame 747 MFI->setStackSize(0); 748 return; 749 } 750 751 // Get the maximum call frame size of all the calls. 752 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 753 754 // Maximum call frame needs to be at least big enough for linkage and 8 args. 755 unsigned minCallFrameSize = 756 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64()); 757 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 758 759 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 760 // that allocations will be aligned. 761 if (MFI->hasVarSizedObjects()) 762 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 763 764 // Update maximum call frame size. 765 MFI->setMaxCallFrameSize(maxCallFrameSize); 766 767 // Include call frame size in total. 768 FrameSize += maxCallFrameSize; 769 770 // Make sure the frame is aligned. 771 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 772 773 // Update frame info. 774 MFI->setStackSize(FrameSize); 775 } 776 777 void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF) 778 const { 779 // Save and clear the LR state. 780 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 781 unsigned LR = getRARegister(); 782 FI->setUsesLR(MF.isPhysRegUsed(LR)); 783 MF.changePhyRegUsed(LR, false); 784 } 785 786 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 787 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 788 MachineBasicBlock::iterator MBBI = MBB.begin(); 789 MachineFrameInfo *MFI = MF.getFrameInfo(); 790 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 791 792 // Prepare for frame info. 793 unsigned FrameLabelId = 0; 794 795 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 796 // process it. 797 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 798 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 799 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs(), TII); 800 break; 801 } 802 } 803 804 // Move MBBI back to the beginning of the function. 805 MBBI = MBB.begin(); 806 807 // Work out frame sizes. 808 determineFrameLayout(MF); 809 unsigned FrameSize = MFI->getStackSize(); 810 811 // Skip if a leaf routine. 812 if (!FrameSize) return; 813 814 int NegFrameSize = -FrameSize; 815 816 // Get processor type. 817 bool IsPPC64 = Subtarget.isPPC64(); 818 // Check if the link register (LR) has been used. 819 bool UsesLR = MFI->hasCalls() || usesLR(MF); 820 // Do we have a frame pointer for this function? 821 bool HasFP = hasFP(MF); 822 823 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64); 824 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64); 825 826 if (IsPPC64) { 827 if (UsesLR) 828 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); 829 830 if (HasFP) 831 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 832 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1); 833 834 if (UsesLR) 835 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 836 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1); 837 } else { 838 if (UsesLR) 839 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); 840 841 if (HasFP) 842 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 843 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1); 844 845 if (UsesLR) 846 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 847 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1); 848 } 849 850 // Get stack alignments. 851 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 852 unsigned MaxAlign = MFI->getMaxAlignment(); 853 854 if (MMI && MMI->needsFrameInfo()) { 855 // Mark effective beginning of when frame pointer becomes valid. 856 FrameLabelId = MMI->NextLabelID(); 857 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId); 858 } 859 860 // Adjust stack pointer: r1 += NegFrameSize. 861 // If there is a preferred stack alignment, align R1 now 862 if (!IsPPC64) { 863 // PPC32. 864 if (MaxAlign > TargetAlign) { 865 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 866 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 867 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) 868 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 869 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0) 870 .addImm(NegFrameSize); 871 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 872 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 873 } else if (isInt16(NegFrameSize)) { 874 BuildMI(MBB, MBBI, TII.get(PPC::STWU), 875 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1); 876 } else { 877 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16); 878 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0) 879 .addImm(NegFrameSize & 0xFFFF); 880 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1) 881 .addReg(PPC::R0); 882 } 883 } else { // PPC64. 884 if (MaxAlign > TargetAlign) { 885 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 886 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 887 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) 888 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign)); 889 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0) 890 .addImm(NegFrameSize); 891 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 892 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0); 893 } else if (isInt16(NegFrameSize)) { 894 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) 895 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1); 896 } else { 897 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16); 898 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0) 899 .addImm(NegFrameSize & 0xFFFF); 900 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1) 901 .addReg(PPC::X0); 902 } 903 } 904 905 if (MMI && MMI->needsFrameInfo()) { 906 std::vector<MachineMove> &Moves = MMI->getFrameMoves(); 907 908 if (NegFrameSize) { 909 // Show update of SP. 910 MachineLocation SPDst(MachineLocation::VirtualFP); 911 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 912 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); 913 } else { 914 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31); 915 Moves.push_back(MachineMove(FrameLabelId, SP, SP)); 916 } 917 918 if (HasFP) { 919 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 920 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31); 921 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); 922 } 923 924 // Add callee saved registers to move list. 925 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 926 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 927 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 928 unsigned Reg = CSI[I].getReg(); 929 if (Reg == PPC::LR || Reg == PPC::LR8) continue; 930 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 931 MachineLocation CSSrc(Reg); 932 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); 933 } 934 935 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 936 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR); 937 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc)); 938 939 // Mark effective beginning of when frame pointer is ready. 940 unsigned ReadyLabelId = MMI->NextLabelID(); 941 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId); 942 943 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : 944 (IsPPC64 ? PPC::X1 : PPC::R1)); 945 MachineLocation FPSrc(MachineLocation::VirtualFP); 946 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); 947 } 948 949 // If there is a frame pointer, copy R1 into R31 950 if (HasFP) { 951 if (!IsPPC64) { 952 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1) 953 .addReg(PPC::R1); 954 } else { 955 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1) 956 .addReg(PPC::X1); 957 } 958 } 959 } 960 961 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 962 MachineBasicBlock &MBB) const { 963 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 964 assert(MBBI->getOpcode() == PPC::BLR && 965 "Can only insert epilog into returning blocks"); 966 967 // Get alignment info so we know how to restore r1 968 const MachineFrameInfo *MFI = MF.getFrameInfo(); 969 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 970 unsigned MaxAlign = MFI->getMaxAlignment(); 971 972 // Get the number of bytes allocated from the FrameInfo. 973 unsigned FrameSize = MFI->getStackSize(); 974 975 if (!FrameSize) return; 976 977 // Get processor type. 978 bool IsPPC64 = Subtarget.isPPC64(); 979 // Check if the link register (LR) has been used. 980 bool UsesLR = MFI->hasCalls() || usesLR(MF); 981 // Do we have a frame pointer for this function? 982 bool HasFP = hasFP(MF); 983 984 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 985 // on entry to the function. Add this offset back now. 986 if (!Subtarget.isPPC64()) { 987 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 988 !MFI->hasVarSizedObjects()) { 989 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) 990 .addReg(PPC::R1).addImm(FrameSize); 991 } else { 992 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); 993 } 994 } else { 995 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 996 !MFI->hasVarSizedObjects()) { 997 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) 998 .addReg(PPC::X1).addImm(FrameSize); 999 } else { 1000 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); 1001 } 1002 } 1003 1004 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64); 1005 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64); 1006 1007 if (IsPPC64) { 1008 if (UsesLR) 1009 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) 1010 .addImm(LROffset/4).addReg(PPC::X1); 1011 1012 if (HasFP) 1013 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) 1014 .addImm(FPOffset/4).addReg(PPC::X1); 1015 1016 if (UsesLR) 1017 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); 1018 } else { 1019 if (UsesLR) 1020 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) 1021 .addImm(LROffset).addReg(PPC::R1); 1022 1023 if (HasFP) 1024 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) 1025 .addImm(FPOffset).addReg(PPC::R1); 1026 1027 if (UsesLR) 1028 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); 1029 } 1030 } 1031 1032 unsigned PPCRegisterInfo::getRARegister() const { 1033 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1034 } 1035 1036 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1037 if (!Subtarget.isPPC64()) 1038 return hasFP(MF) ? PPC::R31 : PPC::R1; 1039 else 1040 return hasFP(MF) ? PPC::X31 : PPC::X1; 1041 } 1042 1043 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1044 const { 1045 // Initial state of the frame pointer is R1. 1046 MachineLocation Dst(MachineLocation::VirtualFP); 1047 MachineLocation Src(PPC::R1, 0); 1048 Moves.push_back(MachineMove(0, Dst, Src)); 1049 } 1050 1051 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 1052 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 1053 } 1054 1055 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 1056 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 1057 } 1058 1059 #include "PPCGenRegisterInfo.inc" 1060 1061