1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCRegisterInfo.h" 18 #include "llvm/Constants.h" 19 #include "llvm/Type.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineDebugInfo.h" 23 #include "llvm/CodeGen/MachineFunction.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineLocation.h" 26 #include "llvm/CodeGen/SelectionDAGNodes.h" 27 #include "llvm/Target/TargetFrameInfo.h" 28 #include "llvm/Target/TargetMachine.h" 29 #include "llvm/Target/TargetOptions.h" 30 #include "llvm/Support/CommandLine.h" 31 #include "llvm/Support/Debug.h" 32 #include "llvm/Support/MathExtras.h" 33 #include "llvm/ADT/STLExtras.h" 34 #include <cstdlib> 35 #include <iostream> 36 using namespace llvm; 37 38 PPCRegisterInfo::PPCRegisterInfo() 39 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) { 40 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 41 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 42 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 43 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 44 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 45 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 46 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 47 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 48 } 49 50 void 51 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 52 MachineBasicBlock::iterator MI, 53 unsigned SrcReg, int FrameIdx, 54 const TargetRegisterClass *RC) const { 55 if (SrcReg == PPC::LR) { 56 // FIXME: this spills LR immediately to memory in one step. To do this, we 57 // use R11, which we know cannot be used in the prolog/epilog. This is a 58 // hack. 59 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); 60 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 61 } else if (RC == PPC::CRRCRegisterClass) { 62 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11); 63 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 64 } else if (RC == PPC::GPRCRegisterClass) { 65 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); 66 } else if (RC == PPC::G8RCRegisterClass) { 67 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx); 68 } else if (RC == PPC::F8RCRegisterClass) { 69 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx); 70 } else if (RC == PPC::F4RCRegisterClass) { 71 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx); 72 } else if (RC == PPC::VRRCRegisterClass) { 73 // We don't have indexed addressing for vector loads. Emit: 74 // R11 = ADDI FI# 75 // Dest = LVX R0, R11 76 // 77 // FIXME: We use R0 here, because it isn't available for RA. 78 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 79 BuildMI(MBB, MI, PPC::STVX, 3) 80 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); 81 } else { 82 assert(0 && "Unknown regclass!"); 83 abort(); 84 } 85 } 86 87 void 88 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 89 MachineBasicBlock::iterator MI, 90 unsigned DestReg, int FrameIdx, 91 const TargetRegisterClass *RC) const { 92 if (DestReg == PPC::LR) { 93 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 94 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); 95 } else if (RC == PPC::CRRCRegisterClass) { 96 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 97 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11); 98 } else if (RC == PPC::GPRCRegisterClass) { 99 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); 100 } else if (RC == PPC::G8RCRegisterClass) { 101 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx); 102 } else if (RC == PPC::F8RCRegisterClass) { 103 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx); 104 } else if (RC == PPC::F4RCRegisterClass) { 105 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx); 106 } else if (RC == PPC::VRRCRegisterClass) { 107 // We don't have indexed addressing for vector loads. Emit: 108 // R11 = ADDI FI# 109 // Dest = LVX R0, R11 110 // 111 // FIXME: We use R0 here, because it isn't available for RA. 112 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 113 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0); 114 } else { 115 assert(0 && "Unknown regclass!"); 116 abort(); 117 } 118 } 119 120 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 121 MachineBasicBlock::iterator MI, 122 unsigned DestReg, unsigned SrcReg, 123 const TargetRegisterClass *RC) const { 124 if (RC == PPC::GPRCRegisterClass) { 125 BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 126 } else if (RC == PPC::G8RCRegisterClass) { 127 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 128 } else if (RC == PPC::F4RCRegisterClass) { 129 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg); 130 } else if (RC == PPC::F8RCRegisterClass) { 131 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg); 132 } else if (RC == PPC::CRRCRegisterClass) { 133 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg); 134 } else if (RC == PPC::VRRCRegisterClass) { 135 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 136 } else { 137 std::cerr << "Attempt to copy register that is not GPR or FPR"; 138 abort(); 139 } 140 } 141 142 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 143 /// copy instructions, turning them into load/store instructions. 144 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 145 unsigned OpNum, 146 int FrameIndex) const { 147 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 148 // it takes more than one instruction to store it. 149 unsigned Opc = MI->getOpcode(); 150 151 if ((Opc == PPC::OR4 && 152 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 153 if (OpNum == 0) { // move -> store 154 unsigned InReg = MI->getOperand(1).getReg(); 155 return addFrameReference(BuildMI(PPC::STW, 156 3).addReg(InReg), FrameIndex); 157 } else { // move -> load 158 unsigned OutReg = MI->getOperand(0).getReg(); 159 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex); 160 } 161 } else if ((Opc == PPC::OR8 && 162 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 163 if (OpNum == 0) { // move -> store 164 unsigned InReg = MI->getOperand(1).getReg(); 165 return addFrameReference(BuildMI(PPC::STD, 166 3).addReg(InReg), FrameIndex); 167 } else { // move -> load 168 unsigned OutReg = MI->getOperand(0).getReg(); 169 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex); 170 } 171 } else if (Opc == PPC::FMRD) { 172 if (OpNum == 0) { // move -> store 173 unsigned InReg = MI->getOperand(1).getReg(); 174 return addFrameReference(BuildMI(PPC::STFD, 175 3).addReg(InReg), FrameIndex); 176 } else { // move -> load 177 unsigned OutReg = MI->getOperand(0).getReg(); 178 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex); 179 } 180 } else if (Opc == PPC::FMRS) { 181 if (OpNum == 0) { // move -> store 182 unsigned InReg = MI->getOperand(1).getReg(); 183 return addFrameReference(BuildMI(PPC::STFS, 184 3).addReg(InReg), FrameIndex); 185 } else { // move -> load 186 unsigned OutReg = MI->getOperand(0).getReg(); 187 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex); 188 } 189 } 190 return 0; 191 } 192 193 //===----------------------------------------------------------------------===// 194 // Stack Frame Processing methods 195 //===----------------------------------------------------------------------===// 196 197 // hasFP - Return true if the specified function should have a dedicated frame 198 // pointer register. This is true if the function has variable sized allocas or 199 // if frame pointer elimination is disabled. 200 // 201 static bool hasFP(const MachineFunction &MF) { 202 const MachineFrameInfo *MFI = MF.getFrameInfo(); 203 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 204 205 // If frame pointers are forced, if there are variable sized stack objects, 206 // or if there is an object on the stack that requires more alignment than is 207 // normally provided, use a frame pointer. 208 // 209 return NoFramePointerElim || MFI->hasVarSizedObjects() || 210 MFI->getMaxAlignment() > TargetAlign; 211 } 212 213 void PPCRegisterInfo:: 214 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 215 MachineBasicBlock::iterator I) const { 216 if (hasFP(MF)) { 217 // If we have a frame pointer, convert as follows: 218 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount 219 // ADJCALLSTACKUP -> addi, r1, r1, amount 220 MachineInstr *Old = I; 221 unsigned Amount = Old->getOperand(0).getImmedValue(); 222 if (Amount != 0) { 223 // We need to keep the stack aligned properly. To do this, we round the 224 // amount of space needed for the outgoing arguments up to the next 225 // alignment boundary. 226 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 227 Amount = (Amount+Align-1)/Align*Align; 228 229 // Replace the pseudo instruction with a new instruction... 230 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { 231 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount); 232 } else { 233 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); 234 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount); 235 } 236 } 237 } 238 MBB.erase(I); 239 } 240 241 void 242 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 243 unsigned i = 0; 244 MachineInstr &MI = *II; 245 MachineBasicBlock &MBB = *MI.getParent(); 246 MachineFunction &MF = *MBB.getParent(); 247 248 while (!MI.getOperand(i).isFrameIndex()) { 249 ++i; 250 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 251 } 252 253 int FrameIndex = MI.getOperand(i).getFrameIndex(); 254 255 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 256 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1); 257 258 // Take into account whether it's an add or mem instruction 259 unsigned OffIdx = (i == 2) ? 1 : 2; 260 261 // Now add the frame object offset to the offset from r1. 262 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 263 MI.getOperand(OffIdx).getImmedValue(); 264 265 // If we're not using a Frame Pointer that has been set to the value of the 266 // SP before having the stack size subtracted from it, then add the stack size 267 // to Offset to get the correct offset. 268 Offset += MF.getFrameInfo()->getStackSize(); 269 270 if (Offset > 32767 || Offset < -32768) { 271 // Insert a set of r0 with the full offset value before the ld, st, or add 272 MachineBasicBlock *MBB = MI.getParent(); 273 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16); 274 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset); 275 276 // convert into indexed form of the instruction 277 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 278 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 279 assert(ImmToIdxMap.count(MI.getOpcode()) && 280 "No indexed form of load or store available!"); 281 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; 282 MI.setOpcode(NewOpcode); 283 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); 284 MI.SetMachineOperandReg(2, PPC::R0); 285 } else { 286 switch (MI.getOpcode()) { 287 case PPC::LWA: 288 case PPC::LD: 289 case PPC::STD: 290 case PPC::STD_32: 291 assert((Offset & 3) == 0 && "Invalid frame offset!"); 292 Offset >>= 2; // The actual encoded value has the low two bits zero. 293 break; 294 } 295 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed, 296 Offset); 297 } 298 } 299 300 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 301 // instruction selector. Based on the vector registers that have been used, 302 // transform this into the appropriate ORI instruction. 303 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) { 304 unsigned UsedRegMask = 0; 305 #define HANDLEREG(N) if (UsedRegs[PPC::V##N]) UsedRegMask |= 1 << (31-N) 306 HANDLEREG( 0); HANDLEREG( 1); HANDLEREG( 2); HANDLEREG( 3); 307 HANDLEREG( 4); HANDLEREG( 5); HANDLEREG( 6); HANDLEREG( 7); 308 HANDLEREG( 8); HANDLEREG( 9); HANDLEREG(10); HANDLEREG(11); 309 HANDLEREG(12); HANDLEREG(13); HANDLEREG(14); HANDLEREG(15); 310 HANDLEREG(16); HANDLEREG(17); HANDLEREG(18); HANDLEREG(19); 311 HANDLEREG(20); HANDLEREG(21); HANDLEREG(22); HANDLEREG(23); 312 HANDLEREG(24); HANDLEREG(25); HANDLEREG(26); HANDLEREG(27); 313 HANDLEREG(28); HANDLEREG(29); HANDLEREG(30); HANDLEREG(31); 314 #undef HANDLEREG 315 unsigned SrcReg = MI->getOperand(1).getReg(); 316 unsigned DstReg = MI->getOperand(0).getReg(); 317 // If no registers are used, turn this into a copy. 318 if (UsedRegMask == 0) { 319 if (SrcReg != DstReg) 320 BuildMI(*MI->getParent(), MI, PPC::OR4, 2, DstReg) 321 .addReg(SrcReg).addReg(SrcReg); 322 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 323 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 324 .addReg(SrcReg).addImm(UsedRegMask); 325 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 326 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 327 .addReg(SrcReg).addImm(UsedRegMask >> 16); 328 } else { 329 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 330 .addReg(SrcReg).addImm(UsedRegMask >> 16); 331 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 332 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 333 } 334 335 // Remove the old UPDATE_VRSAVE instruction. 336 MI->getParent()->erase(MI); 337 } 338 339 340 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 341 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 342 MachineBasicBlock::iterator MBBI = MBB.begin(); 343 MachineFrameInfo *MFI = MF.getFrameInfo(); 344 MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo(); 345 346 // Do we have a frame pointer for this function? 347 bool HasFP = hasFP(MF); 348 349 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 350 // process it. 351 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 352 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 353 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs()); 354 break; 355 } 356 } 357 358 // Move MBBI back to the beginning of the function. 359 MBBI = MBB.begin(); 360 361 // Get the number of bytes to allocate from the FrameInfo 362 unsigned NumBytes = MFI->getStackSize(); 363 364 // Get the alignments provided by the target, and the maximum alignment 365 // (if any) of the fixed frame objects. 366 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 367 unsigned MaxAlign = MFI->getMaxAlignment(); 368 369 // If we have calls, we cannot use the red zone to store callee save registers 370 // and we must set up a stack frame, so calculate the necessary size here. 371 if (MFI->hasCalls()) { 372 // We reserve argument space for call sites in the function immediately on 373 // entry to the current function. This eliminates the need for add/sub 374 // brackets around call sites. 375 NumBytes += MFI->getMaxCallFrameSize(); 376 } 377 378 // If we are a leaf function, and use up to 224 bytes of stack space, 379 // and don't have a frame pointer, then we do not need to adjust the stack 380 // pointer (we fit in the Red Zone). 381 if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() && 382 MaxAlign <= TargetAlign)) { 383 MFI->setStackSize(0); 384 return; 385 } 386 387 // Add the size of R1 to NumBytes size for the store of R1 to the bottom 388 // of the stack and round the size to a multiple of the alignment. 389 unsigned Align = std::max(TargetAlign, MaxAlign); 390 unsigned GPRSize = 4; 391 unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize; 392 NumBytes = (NumBytes+Size+Align-1)/Align*Align; 393 394 // Update frame info to pretend that this is part of the stack... 395 MFI->setStackSize(NumBytes); 396 int NegNumbytes = -NumBytes; 397 398 // Adjust stack pointer: r1 -= numbytes. 399 if (NumBytes <= 32768) { 400 BuildMI(MBB, MBBI, PPC::STWU, 3) 401 .addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1); 402 } else { 403 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16); 404 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0) 405 .addReg(PPC::R0).addImm(NegNumbytes & 0xFFFF); 406 BuildMI(MBB, MBBI, PPC::STWUX, 3) 407 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 408 } 409 410 if (DebugInfo) { 411 std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves(); 412 unsigned LabelID = DebugInfo->NextLabelID(); 413 414 // Show update of SP. 415 MachineLocation Dst(MachineLocation::VirtualFP); 416 MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes); 417 Moves.push_back(new MachineMove(LabelID, Dst, Src)); 418 419 BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID); 420 } 421 422 // If there is a preferred stack alignment, align R1 now 423 // FIXME: If this ever matters, this could be made more efficient by folding 424 // this into the code above, so that we don't issue two store+update 425 // instructions. 426 if (MaxAlign > TargetAlign) { 427 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!"); 428 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) 429 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 430 BuildMI(MBB, MBBI, PPC::SUBFIC, 2,PPC::R0).addReg(PPC::R0).addImm(MaxAlign); 431 BuildMI(MBB, MBBI, PPC::STWUX, 3) 432 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 433 } 434 435 // If there is a frame pointer, copy R1 (SP) into R31 (FP) 436 if (HasFP) { 437 BuildMI(MBB, MBBI, PPC::STW, 3) 438 .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1); 439 BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); 440 } 441 } 442 443 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 444 MachineBasicBlock &MBB) const { 445 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 446 assert(MBBI->getOpcode() == PPC::BLR && 447 "Can only insert epilog into returning blocks"); 448 449 // Get the number of bytes allocated from the FrameInfo. 450 unsigned NumBytes = MF.getFrameInfo()->getStackSize(); 451 unsigned GPRSize = 4; 452 453 if (NumBytes != 0) { 454 // If this function has a frame pointer, load the saved stack pointer from 455 // its stack slot. 456 if (hasFP(MF)) { 457 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31) 458 .addSImm(GPRSize).addReg(PPC::R31); 459 } 460 461 // The loaded (or persistent) stack pointer value is offseted by the 'stwu' 462 // on entry to the function. Add this offset back now. 463 if (NumBytes < 32768) { 464 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1) 465 .addReg(PPC::R1).addSImm(NumBytes); 466 } else { 467 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NumBytes >> 16); 468 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0) 469 .addReg(PPC::R0).addImm(NumBytes & 0xFFFF); 470 BuildMI(MBB, MBBI, PPC::ADD4, 2, PPC::R1) 471 .addReg(PPC::R0).addReg(PPC::R1); 472 } 473 } 474 } 475 476 unsigned PPCRegisterInfo::getRARegister() const { 477 return PPC::LR; 478 } 479 480 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 481 return hasFP(MF) ? PPC::R31 : PPC::R1; 482 } 483 484 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves) 485 const { 486 // Initial state is the frame pointer is R1. 487 MachineLocation Dst(MachineLocation::VirtualFP); 488 MachineLocation Src(PPC::R1, 0); 489 Moves.push_back(new MachineMove(0, Dst, Src)); 490 } 491 492 #include "PPCGenRegisterInfo.inc" 493 494