1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCRegisterInfo.h" 18 #include "llvm/Constants.h" 19 #include "llvm/Type.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/Target/TargetFrameInfo.h" 25 #include "llvm/Target/TargetMachine.h" 26 #include "llvm/Target/TargetOptions.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Support/Debug.h" 29 #include "llvm/Support/MathExtras.h" 30 #include "llvm/ADT/STLExtras.h" 31 #include <cstdlib> 32 #include <iostream> 33 using namespace llvm; 34 35 PPCRegisterInfo::PPCRegisterInfo() 36 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) { 37 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 38 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 39 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 40 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 41 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 42 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 43 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 44 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 45 } 46 47 void 48 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 49 MachineBasicBlock::iterator MI, 50 unsigned SrcReg, int FrameIdx, 51 const TargetRegisterClass *RC) const { 52 if (SrcReg == PPC::LR) { 53 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); 54 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 55 } else if (RC == PPC::CRRCRegisterClass) { 56 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11); 57 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 58 } else if (RC == PPC::GPRCRegisterClass) { 59 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); 60 } else if (RC == PPC::G8RCRegisterClass) { 61 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx); 62 } else if (RC == PPC::F8RCRegisterClass) { 63 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx); 64 } else if (RC == PPC::F4RCRegisterClass) { 65 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx); 66 } else { 67 assert(0 && "Unknown regclass!"); 68 abort(); 69 } 70 } 71 72 void 73 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 74 MachineBasicBlock::iterator MI, 75 unsigned DestReg, int FrameIdx, 76 const TargetRegisterClass *RC) const { 77 if (DestReg == PPC::LR) { 78 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 79 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); 80 } else if (RC == PPC::CRRCRegisterClass) { 81 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 82 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11); 83 } else if (RC == PPC::GPRCRegisterClass) { 84 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); 85 } else if (RC == PPC::G8RCRegisterClass) { 86 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx); 87 } else if (RC == PPC::F8RCRegisterClass) { 88 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx); 89 } else if (RC == PPC::F4RCRegisterClass) { 90 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx); 91 } else { 92 assert(0 && "Unknown regclass!"); 93 abort(); 94 } 95 } 96 97 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 98 MachineBasicBlock::iterator MI, 99 unsigned DestReg, unsigned SrcReg, 100 const TargetRegisterClass *RC) const { 101 MachineInstr *I; 102 103 if (RC == PPC::GPRCRegisterClass) { 104 BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 105 } else if (RC == PPC::G8RCRegisterClass) { 106 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 107 } else if (RC == PPC::F4RCRegisterClass) { 108 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg); 109 } else if (RC == PPC::F8RCRegisterClass) { 110 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg); 111 } else if (RC == PPC::CRRCRegisterClass) { 112 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg); 113 } else { 114 std::cerr << "Attempt to copy register that is not GPR or FPR"; 115 abort(); 116 } 117 } 118 119 unsigned PPCRegisterInfo::isLoadFromStackSlot(MachineInstr *MI, 120 int &FrameIndex) const { 121 switch (MI->getOpcode()) { 122 default: break; 123 case PPC::LD: 124 case PPC::LWZ: 125 case PPC::LFS: 126 case PPC::LFD: 127 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() && 128 MI->getOperand(2).isFrameIndex()) { 129 FrameIndex = MI->getOperand(2).getFrameIndex(); 130 return MI->getOperand(0).getReg(); 131 } 132 break; 133 } 134 return 0; 135 } 136 137 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 138 /// copy instructions, turning them into load/store instructions. 139 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 140 unsigned OpNum, 141 int FrameIndex) const { 142 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 143 // it takes more than one instruction to store it. 144 unsigned Opc = MI->getOpcode(); 145 146 if ((Opc == PPC::OR4 && 147 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 148 if (OpNum == 0) { // move -> store 149 unsigned InReg = MI->getOperand(1).getReg(); 150 return addFrameReference(BuildMI(PPC::STW, 151 3).addReg(InReg), FrameIndex); 152 } else { // move -> load 153 unsigned OutReg = MI->getOperand(0).getReg(); 154 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex); 155 } 156 } else if ((Opc == PPC::OR8 && 157 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 158 if (OpNum == 0) { // move -> store 159 unsigned InReg = MI->getOperand(1).getReg(); 160 return addFrameReference(BuildMI(PPC::STD, 161 3).addReg(InReg), FrameIndex); 162 } else { // move -> load 163 unsigned OutReg = MI->getOperand(0).getReg(); 164 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex); 165 } 166 } else if (Opc == PPC::FMRD) { 167 if (OpNum == 0) { // move -> store 168 unsigned InReg = MI->getOperand(1).getReg(); 169 return addFrameReference(BuildMI(PPC::STFD, 170 3).addReg(InReg), FrameIndex); 171 } else { // move -> load 172 unsigned OutReg = MI->getOperand(0).getReg(); 173 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex); 174 } 175 } else if (Opc == PPC::FMRS) { 176 if (OpNum == 0) { // move -> store 177 unsigned InReg = MI->getOperand(1).getReg(); 178 return addFrameReference(BuildMI(PPC::STFS, 179 3).addReg(InReg), FrameIndex); 180 } else { // move -> load 181 unsigned OutReg = MI->getOperand(0).getReg(); 182 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex); 183 } 184 } 185 return 0; 186 } 187 188 //===----------------------------------------------------------------------===// 189 // Stack Frame Processing methods 190 //===----------------------------------------------------------------------===// 191 192 // hasFP - Return true if the specified function should have a dedicated frame 193 // pointer register. This is true if the function has variable sized allocas or 194 // if frame pointer elimination is disabled. 195 // 196 static bool hasFP(MachineFunction &MF) { 197 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 198 } 199 200 void PPCRegisterInfo:: 201 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 202 MachineBasicBlock::iterator I) const { 203 if (hasFP(MF)) { 204 // If we have a frame pointer, convert as follows: 205 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount 206 // ADJCALLSTACKUP -> addi, r1, r1, amount 207 MachineInstr *Old = I; 208 unsigned Amount = Old->getOperand(0).getImmedValue(); 209 if (Amount != 0) { 210 // We need to keep the stack aligned properly. To do this, we round the 211 // amount of space needed for the outgoing arguments up to the next 212 // alignment boundary. 213 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 214 Amount = (Amount+Align-1)/Align*Align; 215 216 // Replace the pseudo instruction with a new instruction... 217 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { 218 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount); 219 } else { 220 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); 221 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount); 222 } 223 } 224 } 225 MBB.erase(I); 226 } 227 228 void 229 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 230 unsigned i = 0; 231 MachineInstr &MI = *II; 232 MachineBasicBlock &MBB = *MI.getParent(); 233 MachineFunction &MF = *MBB.getParent(); 234 235 while (!MI.getOperand(i).isFrameIndex()) { 236 ++i; 237 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 238 } 239 240 int FrameIndex = MI.getOperand(i).getFrameIndex(); 241 242 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 243 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1); 244 245 // Take into account whether it's an add or mem instruction 246 unsigned OffIdx = (i == 2) ? 1 : 2; 247 248 // Now add the frame object offset to the offset from r1. 249 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 250 MI.getOperand(OffIdx).getImmedValue(); 251 252 // If we're not using a Frame Pointer that has been set to the value of the 253 // SP before having the stack size subtracted from it, then add the stack size 254 // to Offset to get the correct offset. 255 Offset += MF.getFrameInfo()->getStackSize(); 256 257 if (Offset > 32767 || Offset < -32768) { 258 // Insert a set of r0 with the full offset value before the ld, st, or add 259 MachineBasicBlock *MBB = MI.getParent(); 260 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16); 261 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset); 262 263 // convert into indexed form of the instruction 264 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 265 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 266 assert(ImmToIdxMap.count(MI.getOpcode()) && 267 "No indexed form of load or store available!"); 268 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; 269 MI.setOpcode(NewOpcode); 270 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); 271 MI.SetMachineOperandReg(2, PPC::R0); 272 } else { 273 switch (MI.getOpcode()) { 274 case PPC::LWA: 275 case PPC::LD: 276 case PPC::STD: 277 case PPC::STDU: 278 assert((Offset & 3) == 0 && "Invalid frame offset!"); 279 Offset >>= 2; // The actual encoded value has the low two bits zero. 280 break; 281 } 282 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed, 283 Offset); 284 } 285 } 286 287 288 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 289 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 290 MachineBasicBlock::iterator MBBI = MBB.begin(); 291 MachineFrameInfo *MFI = MF.getFrameInfo(); 292 293 // Get the number of bytes to allocate from the FrameInfo 294 unsigned NumBytes = MFI->getStackSize(); 295 296 // Get the alignments provided by the target, and the maximum alignment 297 // (if any) of the fixed frame objects. 298 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 299 unsigned MaxAlign = MFI->getMaxAlignment(); 300 301 // If we have calls, we cannot use the red zone to store callee save registers 302 // and we must set up a stack frame, so calculate the necessary size here. 303 if (MFI->hasCalls()) { 304 // We reserve argument space for call sites in the function immediately on 305 // entry to the current function. This eliminates the need for add/sub 306 // brackets around call sites. 307 NumBytes += MFI->getMaxCallFrameSize(); 308 } 309 310 // If we are a leaf function, and use up to 224 bytes of stack space, 311 // and don't have a frame pointer, then we do not need to adjust the stack 312 // pointer (we fit in the Red Zone). 313 if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls() && 314 MaxAlign <= TargetAlign)) { 315 MFI->setStackSize(0); 316 return; 317 } 318 319 // Add the size of R1 to NumBytes size for the store of R1 to the bottom 320 // of the stack and round the size to a multiple of the alignment. 321 unsigned Align = std::max(TargetAlign, MaxAlign); 322 unsigned GPRSize = 4; 323 unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize; 324 NumBytes = (NumBytes+Size+Align-1)/Align*Align; 325 326 // Update frame info to pretend that this is part of the stack... 327 MFI->setStackSize(NumBytes); 328 329 // Adjust stack pointer: r1 -= numbytes. 330 if (NumBytes <= 32768) { 331 BuildMI(MBB, MBBI, PPC::STWU, 3) 332 .addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1); 333 } else { 334 int NegNumbytes = -NumBytes; 335 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16); 336 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0) 337 .addReg(PPC::R0).addImm(NegNumbytes & 0xFFFF); 338 BuildMI(MBB, MBBI, PPC::STWUX, 3) 339 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 340 } 341 342 // If there is a preferred stack alignment, align R1 now 343 // FIXME: If this ever matters, this could be made more efficient by folding 344 // this into the code above, so that we don't issue two store+update 345 // instructions. 346 if (MaxAlign > TargetAlign) { 347 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!"); 348 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) 349 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 350 BuildMI(MBB, MBBI, PPC::SUBFIC, 2,PPC::R0).addReg(PPC::R0).addImm(MaxAlign); 351 BuildMI(MBB, MBBI, PPC::STWUX, 3) 352 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 353 } 354 355 // If there is a frame pointer, copy R1 (SP) into R31 (FP) 356 if (hasFP(MF)) { 357 BuildMI(MBB, MBBI, PPC::STW, 3) 358 .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1); 359 BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); 360 } 361 } 362 363 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 364 MachineBasicBlock &MBB) const { 365 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 366 assert(MBBI->getOpcode() == PPC::BLR && 367 "Can only insert epilog into returning blocks"); 368 369 // Get the number of bytes allocated from the FrameInfo. 370 unsigned NumBytes = MF.getFrameInfo()->getStackSize(); 371 unsigned GPRSize = 4; 372 373 if (NumBytes != 0) { 374 // If this function has a frame pointer, load the saved stack pointer from 375 // its stack slot. 376 if (hasFP(MF)) { 377 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31) 378 .addSImm(GPRSize).addReg(PPC::R31); 379 } 380 381 // The loaded (or persistent) stack pointer value is offseted by the 'stwu' 382 // on entry to the function. Add this offset back now. 383 if (NumBytes < 32768) { 384 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1) 385 .addReg(PPC::R1).addSImm(NumBytes); 386 } else { 387 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NumBytes >> 16); 388 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0) 389 .addReg(PPC::R0).addImm(NumBytes & 0xFFFF); 390 BuildMI(MBB, MBBI, PPC::ADD4, 2, PPC::R1) 391 .addReg(PPC::R0).addReg(PPC::R1); 392 } 393 } 394 } 395 396 #include "PPCGenRegisterInfo.inc" 397 398