1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPCRegisterInfo.h" 17 #include "PPC.h" 18 #include "PPCFrameLowering.h" 19 #include "PPCInstrBuilder.h" 20 #include "PPCMachineFunctionInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineModuleInfo.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/RegisterScavenging.h" 30 #include "llvm/IR/CallingConv.h" 31 #include "llvm/IR/Constants.h" 32 #include "llvm/IR/Function.h" 33 #include "llvm/IR/Type.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/MathExtras.h" 38 #include "llvm/Support/raw_ostream.h" 39 #include "llvm/Target/TargetFrameLowering.h" 40 #include "llvm/Target/TargetInstrInfo.h" 41 #include "llvm/Target/TargetMachine.h" 42 #include "llvm/Target/TargetOptions.h" 43 #include <cstdlib> 44 45 #define GET_REGINFO_TARGET_DESC 46 #include "PPCGenRegisterInfo.inc" 47 48 using namespace llvm; 49 50 static cl::opt<bool> 51 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), 52 cl::desc("Enable use of a base pointer for complex stack frames")); 53 54 static cl::opt<bool> 55 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), 56 cl::desc("Force the use of a base pointer in every function")); 57 58 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST) 59 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 60 ST.isPPC64() ? 0 : 1, 61 ST.isPPC64() ? 0 : 1), 62 Subtarget(ST) { 63 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 64 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 65 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 66 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 67 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 68 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 69 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 70 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 71 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; 72 73 // 64-bit 74 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 75 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 76 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 77 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 78 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 79 } 80 81 /// getPointerRegClass - Return the register class to use to hold pointers. 82 /// This is used for addressing modes. 83 const TargetRegisterClass * 84 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 85 const { 86 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value 87 // when it checks for ZERO folding. 88 if (Kind == 1) { 89 if (Subtarget.isPPC64()) 90 return &PPC::G8RC_NOX0RegClass; 91 return &PPC::GPRC_NOR0RegClass; 92 } 93 94 if (Subtarget.isPPC64()) 95 return &PPC::G8RCRegClass; 96 return &PPC::GPRCRegClass; 97 } 98 99 const uint16_t* 100 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 101 if (Subtarget.isDarwinABI()) 102 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 103 CSR_Darwin64_Altivec_SaveList : 104 CSR_Darwin64_SaveList) : 105 (Subtarget.hasAltivec() ? 106 CSR_Darwin32_Altivec_SaveList : 107 CSR_Darwin32_SaveList); 108 109 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 110 CSR_SVR464_Altivec_SaveList : 111 CSR_SVR464_SaveList) : 112 (Subtarget.hasAltivec() ? 113 CSR_SVR432_Altivec_SaveList : 114 CSR_SVR432_SaveList); 115 } 116 117 const uint32_t* 118 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 119 if (Subtarget.isDarwinABI()) 120 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 121 CSR_Darwin64_Altivec_RegMask : 122 CSR_Darwin64_RegMask) : 123 (Subtarget.hasAltivec() ? 124 CSR_Darwin32_Altivec_RegMask : 125 CSR_Darwin32_RegMask); 126 127 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 128 CSR_SVR464_Altivec_RegMask : 129 CSR_SVR464_RegMask) : 130 (Subtarget.hasAltivec() ? 131 CSR_SVR432_Altivec_RegMask : 132 CSR_SVR432_RegMask); 133 } 134 135 const uint32_t* 136 PPCRegisterInfo::getNoPreservedMask() const { 137 return CSR_NoRegs_RegMask; 138 } 139 140 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 141 BitVector Reserved(getNumRegs()); 142 const PPCFrameLowering *PPCFI = 143 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 144 145 // The ZERO register is not really a register, but the representation of r0 146 // when used in instructions that treat r0 as the constant 0. 147 Reserved.set(PPC::ZERO); 148 Reserved.set(PPC::ZERO8); 149 150 // The FP register is also not really a register, but is the representation 151 // of the frame pointer register used by ISD::FRAMEADDR. 152 Reserved.set(PPC::FP); 153 Reserved.set(PPC::FP8); 154 155 // The BP register is also not really a register, but is the representation 156 // of the base pointer register used by setjmp. 157 Reserved.set(PPC::BP); 158 Reserved.set(PPC::BP8); 159 160 // The counter registers must be reserved so that counter-based loops can 161 // be correctly formed (and the mtctr instructions are not DCE'd). 162 Reserved.set(PPC::CTR); 163 Reserved.set(PPC::CTR8); 164 165 Reserved.set(PPC::R1); 166 Reserved.set(PPC::LR); 167 Reserved.set(PPC::LR8); 168 Reserved.set(PPC::RM); 169 170 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec()) 171 Reserved.set(PPC::VRSAVE); 172 173 // The SVR4 ABI reserves r2 and r13 174 if (Subtarget.isSVR4ABI()) { 175 Reserved.set(PPC::R2); // System-reserved register 176 Reserved.set(PPC::R13); // Small Data Area pointer register 177 } 178 179 // On PPC64, r13 is the thread pointer. Never allocate this register. 180 if (Subtarget.isPPC64()) { 181 Reserved.set(PPC::R13); 182 183 Reserved.set(PPC::X1); 184 Reserved.set(PPC::X13); 185 186 if (PPCFI->needsFP(MF)) 187 Reserved.set(PPC::X31); 188 189 if (hasBasePointer(MF)) 190 Reserved.set(PPC::X30); 191 192 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 193 if (Subtarget.isSVR4ABI()) { 194 Reserved.set(PPC::X2); 195 } 196 } 197 198 if (PPCFI->needsFP(MF)) 199 Reserved.set(PPC::R31); 200 201 if (hasBasePointer(MF)) 202 Reserved.set(PPC::R30); 203 204 // Reserve Altivec registers when Altivec is unavailable. 205 if (!Subtarget.hasAltivec()) 206 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(), 207 IE = PPC::VRRCRegClass.end(); I != IE; ++I) 208 Reserved.set(*I); 209 210 return Reserved; 211 } 212 213 unsigned 214 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 215 MachineFunction &MF) const { 216 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 217 const unsigned DefaultSafety = 1; 218 219 switch (RC->getID()) { 220 default: 221 return 0; 222 case PPC::G8RC_NOX0RegClassID: 223 case PPC::GPRC_NOR0RegClassID: 224 case PPC::G8RCRegClassID: 225 case PPC::GPRCRegClassID: { 226 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 227 return 32 - FP - DefaultSafety; 228 } 229 case PPC::F8RCRegClassID: 230 case PPC::F4RCRegClassID: 231 case PPC::VRRCRegClassID: 232 return 32 - DefaultSafety; 233 case PPC::CRRCRegClassID: 234 return 8 - DefaultSafety; 235 } 236 } 237 238 //===----------------------------------------------------------------------===// 239 // Stack Frame Processing methods 240 //===----------------------------------------------------------------------===// 241 242 /// lowerDynamicAlloc - Generate the code for allocating an object in the 243 /// current frame. The sequence of code with be in the general form 244 /// 245 /// addi R0, SP, \#frameSize ; get the address of the previous frame 246 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 247 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 248 /// 249 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 250 // Get the instruction. 251 MachineInstr &MI = *II; 252 // Get the instruction's basic block. 253 MachineBasicBlock &MBB = *MI.getParent(); 254 // Get the basic block's function. 255 MachineFunction &MF = *MBB.getParent(); 256 // Get the frame info. 257 MachineFrameInfo *MFI = MF.getFrameInfo(); 258 // Get the instruction info. 259 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 260 // Determine whether 64-bit pointers are used. 261 bool LP64 = Subtarget.isPPC64(); 262 DebugLoc dl = MI.getDebugLoc(); 263 264 // Get the maximum call stack size. 265 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 266 // Get the total frame size. 267 unsigned FrameSize = MFI->getStackSize(); 268 269 // Get stack alignments. 270 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 271 unsigned MaxAlign = MFI->getMaxAlignment(); 272 assert((maxCallFrameSize & (MaxAlign-1)) == 0 && 273 "Maximum call-frame size not sufficiently aligned"); 274 275 // Determine the previous frame's address. If FrameSize can't be 276 // represented as 16 bits or we need special alignment, then we load the 277 // previous frame's address from 0(SP). Why not do an addis of the hi? 278 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 279 // Constructing the constant and adding would take 3 instructions. 280 // Fortunately, a frame greater than 32K is rare. 281 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 282 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 283 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 284 285 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 286 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 287 .addReg(PPC::R31) 288 .addImm(FrameSize); 289 } else if (LP64) { 290 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 291 .addImm(0) 292 .addReg(PPC::X1); 293 } else { 294 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 295 .addImm(0) 296 .addReg(PPC::R1); 297 } 298 299 bool KillNegSizeReg = MI.getOperand(1).isKill(); 300 unsigned NegSizeReg = MI.getOperand(1).getReg(); 301 302 // Grow the stack and update the stack pointer link, then determine the 303 // address of new allocated space. 304 if (LP64) { 305 if (MaxAlign > TargetAlign) { 306 unsigned UnalNegSizeReg = NegSizeReg; 307 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 308 309 // Unfortunately, there is no andi, only andi., and we can't insert that 310 // here because we might clobber cr0 while it is live. 311 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) 312 .addImm(~(MaxAlign-1)); 313 314 unsigned NegSizeReg1 = NegSizeReg; 315 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 316 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) 317 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 318 .addReg(NegSizeReg1, RegState::Kill); 319 KillNegSizeReg = true; 320 } 321 322 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 323 .addReg(Reg, RegState::Kill) 324 .addReg(PPC::X1) 325 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 326 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 327 .addReg(PPC::X1) 328 .addImm(maxCallFrameSize); 329 } else { 330 if (MaxAlign > TargetAlign) { 331 unsigned UnalNegSizeReg = NegSizeReg; 332 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 333 334 // Unfortunately, there is no andi, only andi., and we can't insert that 335 // here because we might clobber cr0 while it is live. 336 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) 337 .addImm(~(MaxAlign-1)); 338 339 unsigned NegSizeReg1 = NegSizeReg; 340 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 341 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) 342 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 343 .addReg(NegSizeReg1, RegState::Kill); 344 KillNegSizeReg = true; 345 } 346 347 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 348 .addReg(Reg, RegState::Kill) 349 .addReg(PPC::R1) 350 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 351 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 352 .addReg(PPC::R1) 353 .addImm(maxCallFrameSize); 354 } 355 356 // Discard the DYNALLOC instruction. 357 MBB.erase(II); 358 } 359 360 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 361 /// reserving a whole register (R0), we scrounge for one here. This generates 362 /// code like this: 363 /// 364 /// mfcr rA ; Move the conditional register into GPR rA. 365 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 366 /// stw rA, FI ; Store rA to the frame. 367 /// 368 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 369 unsigned FrameIndex) const { 370 // Get the instruction. 371 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 372 // Get the instruction's basic block. 373 MachineBasicBlock &MBB = *MI.getParent(); 374 MachineFunction &MF = *MBB.getParent(); 375 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 376 DebugLoc dl = MI.getDebugLoc(); 377 378 bool LP64 = Subtarget.isPPC64(); 379 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 380 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 381 382 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 383 unsigned SrcReg = MI.getOperand(0).getReg(); 384 385 // We need to store the CR in the low 4-bits of the saved value. First, issue 386 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg. 387 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 388 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 389 390 // If the saved register wasn't CR0, shift the bits left so that they are in 391 // CR0's slot. 392 if (SrcReg != PPC::CR0) { 393 unsigned Reg1 = Reg; 394 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 395 396 // rlwinm rA, rA, ShiftBits, 0, 31. 397 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 398 .addReg(Reg1, RegState::Kill) 399 .addImm(getEncodingValue(SrcReg) * 4) 400 .addImm(0) 401 .addImm(31); 402 } 403 404 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 405 .addReg(Reg, RegState::Kill), 406 FrameIndex); 407 408 // Discard the pseudo instruction. 409 MBB.erase(II); 410 } 411 412 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 413 unsigned FrameIndex) const { 414 // Get the instruction. 415 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 416 // Get the instruction's basic block. 417 MachineBasicBlock &MBB = *MI.getParent(); 418 MachineFunction &MF = *MBB.getParent(); 419 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 420 DebugLoc dl = MI.getDebugLoc(); 421 422 bool LP64 = Subtarget.isPPC64(); 423 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 424 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 425 426 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 427 unsigned DestReg = MI.getOperand(0).getReg(); 428 assert(MI.definesRegister(DestReg) && 429 "RESTORE_CR does not define its destination"); 430 431 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 432 Reg), FrameIndex); 433 434 // If the reloaded register isn't CR0, shift the bits right so that they are 435 // in the right CR's slot. 436 if (DestReg != PPC::CR0) { 437 unsigned Reg1 = Reg; 438 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 439 440 unsigned ShiftBits = getEncodingValue(DestReg)*4; 441 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 442 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 443 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 444 .addImm(31); 445 } 446 447 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) 448 .addReg(Reg, RegState::Kill); 449 450 // Discard the pseudo instruction. 451 MBB.erase(II); 452 } 453 454 static unsigned getCRFromCRBit(unsigned SrcReg) { 455 unsigned Reg = 0; 456 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 457 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 458 Reg = PPC::CR0; 459 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 460 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 461 Reg = PPC::CR1; 462 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 463 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 464 Reg = PPC::CR2; 465 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 466 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 467 Reg = PPC::CR3; 468 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 469 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 470 Reg = PPC::CR4; 471 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 472 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 473 Reg = PPC::CR5; 474 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 475 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 476 Reg = PPC::CR6; 477 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 478 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 479 Reg = PPC::CR7; 480 481 assert(Reg != 0 && "Invalid CR bit register"); 482 return Reg; 483 } 484 485 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, 486 unsigned FrameIndex) const { 487 // Get the instruction. 488 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset> 489 // Get the instruction's basic block. 490 MachineBasicBlock &MBB = *MI.getParent(); 491 MachineFunction &MF = *MBB.getParent(); 492 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 493 DebugLoc dl = MI.getDebugLoc(); 494 495 bool LP64 = Subtarget.isPPC64(); 496 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 497 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 498 499 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 500 unsigned SrcReg = MI.getOperand(0).getReg(); 501 502 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL), 503 getCRFromCRBit(SrcReg)) 504 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 505 506 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 507 .addReg(getCRFromCRBit(SrcReg)); 508 509 // If the saved register wasn't CR0LT, shift the bits left so that the bit to 510 // store is the first one. Mask all but that bit. 511 unsigned Reg1 = Reg; 512 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 513 514 // rlwinm rA, rA, ShiftBits, 0, 0. 515 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 516 .addReg(Reg1, RegState::Kill) 517 .addImm(getEncodingValue(SrcReg)) 518 .addImm(0).addImm(0); 519 520 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 521 .addReg(Reg, RegState::Kill), 522 FrameIndex); 523 524 // Discard the pseudo instruction. 525 MBB.erase(II); 526 } 527 528 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, 529 unsigned FrameIndex) const { 530 // Get the instruction. 531 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset> 532 // Get the instruction's basic block. 533 MachineBasicBlock &MBB = *MI.getParent(); 534 MachineFunction &MF = *MBB.getParent(); 535 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 536 DebugLoc dl = MI.getDebugLoc(); 537 538 bool LP64 = Subtarget.isPPC64(); 539 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 540 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 541 542 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 543 unsigned DestReg = MI.getOperand(0).getReg(); 544 assert(MI.definesRegister(DestReg) && 545 "RESTORE_CRBIT does not define its destination"); 546 547 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 548 Reg), FrameIndex); 549 550 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg); 551 552 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 553 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) 554 .addReg(getCRFromCRBit(DestReg)); 555 556 unsigned ShiftBits = getEncodingValue(DestReg); 557 // rlwimi r11, r10, 32-ShiftBits, ..., ... 558 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) 559 .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill) 560 .addImm(ShiftBits ? 32-ShiftBits : 0) 561 .addImm(ShiftBits).addImm(ShiftBits); 562 563 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), 564 getCRFromCRBit(DestReg)) 565 .addReg(RegO, RegState::Kill) 566 // Make sure we have a use dependency all the way through this 567 // sequence of instructions. We can't have the other bits in the CR 568 // modified in between the mfocrf and the mtocrf. 569 .addReg(getCRFromCRBit(DestReg), RegState::Implicit); 570 571 // Discard the pseudo instruction. 572 MBB.erase(II); 573 } 574 575 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, 576 unsigned FrameIndex) const { 577 // Get the instruction. 578 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> 579 // Get the instruction's basic block. 580 MachineBasicBlock &MBB = *MI.getParent(); 581 MachineFunction &MF = *MBB.getParent(); 582 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 583 DebugLoc dl = MI.getDebugLoc(); 584 585 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 586 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 587 unsigned SrcReg = MI.getOperand(0).getReg(); 588 589 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) 590 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 591 592 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 593 .addReg(Reg, RegState::Kill), 594 FrameIndex); 595 596 // Discard the pseudo instruction. 597 MBB.erase(II); 598 } 599 600 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, 601 unsigned FrameIndex) const { 602 // Get the instruction. 603 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> 604 // Get the instruction's basic block. 605 MachineBasicBlock &MBB = *MI.getParent(); 606 MachineFunction &MF = *MBB.getParent(); 607 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 608 DebugLoc dl = MI.getDebugLoc(); 609 610 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 611 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 612 unsigned DestReg = MI.getOperand(0).getReg(); 613 assert(MI.definesRegister(DestReg) && 614 "RESTORE_VRSAVE does not define its destination"); 615 616 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), 617 Reg), FrameIndex); 618 619 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) 620 .addReg(Reg, RegState::Kill); 621 622 // Discard the pseudo instruction. 623 MBB.erase(II); 624 } 625 626 bool 627 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 628 unsigned Reg, int &FrameIdx) const { 629 630 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 631 // ABI, return true to prevent allocating an additional frame slot. 632 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 633 // is arbitrary and will be subsequently ignored. For 32-bit, we have 634 // previously created the stack slot if needed, so return its FrameIdx. 635 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 636 if (Subtarget.isPPC64()) 637 FrameIdx = 0; 638 else { 639 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 640 FrameIdx = FI->getCRSpillFrameIndex(); 641 } 642 return true; 643 } 644 return false; 645 } 646 647 // Figure out if the offset in the instruction must be a multiple of 4. 648 // This is true for instructions like "STD". 649 static bool usesIXAddr(const MachineInstr &MI) { 650 unsigned OpC = MI.getOpcode(); 651 652 switch (OpC) { 653 default: 654 return false; 655 case PPC::LWA: 656 case PPC::LWA_32: 657 case PPC::LD: 658 case PPC::STD: 659 return true; 660 } 661 } 662 663 // Return the OffsetOperandNo given the FIOperandNum (and the instruction). 664 static unsigned getOffsetONFromFION(const MachineInstr &MI, 665 unsigned FIOperandNum) { 666 // Take into account whether it's an add or mem instruction 667 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 668 if (MI.isInlineAsm()) 669 OffsetOperandNo = FIOperandNum-1; 670 671 return OffsetOperandNo; 672 } 673 674 void 675 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 676 int SPAdj, unsigned FIOperandNum, 677 RegScavenger *RS) const { 678 assert(SPAdj == 0 && "Unexpected"); 679 680 // Get the instruction. 681 MachineInstr &MI = *II; 682 // Get the instruction's basic block. 683 MachineBasicBlock &MBB = *MI.getParent(); 684 // Get the basic block's function. 685 MachineFunction &MF = *MBB.getParent(); 686 // Get the instruction info. 687 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 688 // Get the frame info. 689 MachineFrameInfo *MFI = MF.getFrameInfo(); 690 DebugLoc dl = MI.getDebugLoc(); 691 692 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 693 694 // Get the frame index. 695 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 696 697 // Get the frame pointer save index. Users of this index are primarily 698 // DYNALLOC instructions. 699 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 700 int FPSI = FI->getFramePointerSaveIndex(); 701 // Get the instruction opcode. 702 unsigned OpC = MI.getOpcode(); 703 704 // Special case for dynamic alloca. 705 if (FPSI && FrameIndex == FPSI && 706 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 707 lowerDynamicAlloc(II); 708 return; 709 } 710 711 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 712 if (OpC == PPC::SPILL_CR) { 713 lowerCRSpilling(II, FrameIndex); 714 return; 715 } else if (OpC == PPC::RESTORE_CR) { 716 lowerCRRestore(II, FrameIndex); 717 return; 718 } else if (OpC == PPC::SPILL_CRBIT) { 719 lowerCRBitSpilling(II, FrameIndex); 720 return; 721 } else if (OpC == PPC::RESTORE_CRBIT) { 722 lowerCRBitRestore(II, FrameIndex); 723 return; 724 } else if (OpC == PPC::SPILL_VRSAVE) { 725 lowerVRSAVESpilling(II, FrameIndex); 726 return; 727 } else if (OpC == PPC::RESTORE_VRSAVE) { 728 lowerVRSAVERestore(II, FrameIndex); 729 return; 730 } 731 732 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 733 MI.getOperand(FIOperandNum).ChangeToRegister( 734 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false); 735 736 // Figure out if the offset in the instruction is shifted right two bits. 737 bool isIXAddr = usesIXAddr(MI); 738 739 // If the instruction is not present in ImmToIdxMap, then it has no immediate 740 // form (and must be r+r). 741 bool noImmForm = !MI.isInlineAsm() && !ImmToIdxMap.count(OpC); 742 743 // Now add the frame object offset to the offset from r1. 744 int Offset = MFI->getObjectOffset(FrameIndex); 745 Offset += MI.getOperand(OffsetOperandNo).getImm(); 746 747 // If we're not using a Frame Pointer that has been set to the value of the 748 // SP before having the stack size subtracted from it, then add the stack size 749 // to Offset to get the correct offset. 750 // Naked functions have stack size 0, although getStackSize may not reflect that 751 // because we didn't call all the pieces that compute it for naked functions. 752 if (!MF.getFunction()->getAttributes(). 753 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked)) { 754 if (!(hasBasePointer(MF) && FrameIndex < 0)) 755 Offset += MFI->getStackSize(); 756 } 757 758 // If we can, encode the offset directly into the instruction. If this is a 759 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 760 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 761 // clear can be encoded. This is extremely uncommon, because normally you 762 // only "std" to a stack slot that is at least 4-byte aligned, but it can 763 // happen in invalid code. 764 assert(OpC != PPC::DBG_VALUE && 765 "This should be handle in a target independent way"); 766 if (!noImmForm && isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 767 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 768 return; 769 } 770 771 // The offset doesn't fit into a single register, scavenge one to build the 772 // offset in. 773 774 bool is64Bit = Subtarget.isPPC64(); 775 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 776 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 777 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; 778 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), 779 SReg = MF.getRegInfo().createVirtualRegister(RC); 780 781 // Insert a set of rA with the full offset value before the ld, st, or add 782 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) 783 .addImm(Offset >> 16); 784 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 785 .addReg(SRegHi, RegState::Kill) 786 .addImm(Offset); 787 788 // Convert into indexed form of the instruction: 789 // 790 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 791 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 792 unsigned OperandBase; 793 794 if (noImmForm) 795 OperandBase = 1; 796 else if (OpC != TargetOpcode::INLINEASM) { 797 assert(ImmToIdxMap.count(OpC) && 798 "No indexed form of load or store available!"); 799 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 800 MI.setDesc(TII.get(NewOpcode)); 801 OperandBase = 1; 802 } else { 803 OperandBase = OffsetOperandNo; 804 } 805 806 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 807 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 808 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 809 } 810 811 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 812 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 813 814 if (!Subtarget.isPPC64()) 815 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 816 else 817 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 818 } 819 820 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const { 821 if (!hasBasePointer(MF)) 822 return getFrameRegister(MF); 823 824 return Subtarget.isPPC64() ? PPC::X30 : PPC::R30; 825 } 826 827 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 828 if (!EnableBasePointer) 829 return false; 830 if (AlwaysBasePointer) 831 return true; 832 833 // If we need to realign the stack, then the stack pointer can no longer 834 // serve as an offset into the caller's stack space. As a result, we need a 835 // base pointer. 836 return needsStackRealignment(MF); 837 } 838 839 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const { 840 if (MF.getFunction()->hasFnAttribute("no-realign-stack")) 841 return false; 842 843 return true; 844 } 845 846 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const { 847 const MachineFrameInfo *MFI = MF.getFrameInfo(); 848 const Function *F = MF.getFunction(); 849 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 850 bool requiresRealignment = 851 ((MFI->getMaxAlignment() > StackAlign) || 852 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 853 Attribute::StackAlignment)); 854 855 return requiresRealignment && canRealignStack(MF); 856 } 857 858 /// Returns true if the instruction's frame index 859 /// reference would be better served by a base register other than FP 860 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 861 /// references it should create new base registers for. 862 bool PPCRegisterInfo:: 863 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 864 assert(Offset < 0 && "Local offset must be negative"); 865 866 unsigned FIOperandNum = 0; 867 while (!MI->getOperand(FIOperandNum).isFI()) { 868 ++FIOperandNum; 869 assert(FIOperandNum < MI->getNumOperands() && 870 "Instr doesn't have FrameIndex operand!"); 871 } 872 873 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); 874 Offset += MI->getOperand(OffsetOperandNo).getImm(); 875 876 // It's the load/store FI references that cause issues, as it can be difficult 877 // to materialize the offset if it won't fit in the literal field. Estimate 878 // based on the size of the local frame and some conservative assumptions 879 // about the rest of the stack frame (note, this is pre-regalloc, so 880 // we don't know everything for certain yet) whether this offset is likely 881 // to be out of range of the immediate. Return true if so. 882 883 // We only generate virtual base registers for loads and stores that have 884 // an r+i form. Return false for everything else. 885 unsigned OpC = MI->getOpcode(); 886 if (!ImmToIdxMap.count(OpC)) 887 return false; 888 889 // Don't generate a new virtual base register just to add zero to it. 890 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && 891 MI->getOperand(2).getImm() == 0) 892 return false; 893 894 MachineBasicBlock &MBB = *MI->getParent(); 895 MachineFunction &MF = *MBB.getParent(); 896 897 const PPCFrameLowering *PPCFI = 898 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 899 unsigned StackEst = 900 PPCFI->determineFrameLayout(MF, false, true); 901 902 // If we likely don't need a stack frame, then we probably don't need a 903 // virtual base register either. 904 if (!StackEst) 905 return false; 906 907 // Estimate an offset from the stack pointer. 908 // The incoming offset is relating to the SP at the start of the function, 909 // but when we access the local it'll be relative to the SP after local 910 // allocation, so adjust our SP-relative offset by that allocation size. 911 Offset += StackEst; 912 913 // The frame pointer will point to the end of the stack, so estimate the 914 // offset as the difference between the object offset and the FP location. 915 return !isFrameOffsetLegal(MI, Offset); 916 } 917 918 /// Insert defining instruction(s) for BaseReg to 919 /// be a pointer to FrameIdx at the beginning of the basic block. 920 void PPCRegisterInfo:: 921 materializeFrameBaseRegister(MachineBasicBlock *MBB, 922 unsigned BaseReg, int FrameIdx, 923 int64_t Offset) const { 924 unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI; 925 926 MachineBasicBlock::iterator Ins = MBB->begin(); 927 DebugLoc DL; // Defaults to "unknown" 928 if (Ins != MBB->end()) 929 DL = Ins->getDebugLoc(); 930 931 const MachineFunction &MF = *MBB->getParent(); 932 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 933 const MCInstrDesc &MCID = TII.get(ADDriOpc); 934 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 935 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 936 937 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 938 .addFrameIndex(FrameIdx).addImm(Offset); 939 } 940 941 void 942 PPCRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, 943 unsigned BaseReg, int64_t Offset) const { 944 MachineInstr &MI = *I; 945 946 unsigned FIOperandNum = 0; 947 while (!MI.getOperand(FIOperandNum).isFI()) { 948 ++FIOperandNum; 949 assert(FIOperandNum < MI.getNumOperands() && 950 "Instr doesn't have FrameIndex operand!"); 951 } 952 953 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); 954 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 955 Offset += MI.getOperand(OffsetOperandNo).getImm(); 956 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 957 } 958 959 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 960 int64_t Offset) const { 961 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 962 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0)); 963 } 964 965