1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPC.h" 17 #include "PPCInstrBuilder.h" 18 #include "PPCMachineFunctionInfo.h" 19 #include "PPCRegisterInfo.h" 20 #include "PPCFrameLowering.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/CallingConv.h" 23 #include "llvm/Constants.h" 24 #include "llvm/Function.h" 25 #include "llvm/Type.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineModuleInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineFrameInfo.h" 31 #include "llvm/CodeGen/MachineLocation.h" 32 #include "llvm/CodeGen/MachineRegisterInfo.h" 33 #include "llvm/CodeGen/RegisterScavenging.h" 34 #include "llvm/Target/TargetFrameLowering.h" 35 #include "llvm/Target/TargetInstrInfo.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetOptions.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/ErrorHandling.h" 41 #include "llvm/Support/MathExtras.h" 42 #include "llvm/Support/raw_ostream.h" 43 #include "llvm/ADT/BitVector.h" 44 #include "llvm/ADT/STLExtras.h" 45 #include <cstdlib> 46 47 #define GET_REGINFO_MC_DESC 48 #define GET_REGINFO_TARGET_DESC 49 #include "PPCGenRegisterInfo.inc" 50 51 // FIXME (64-bit): Eventually enable by default. 52 namespace llvm { 53 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", 54 cl::init(false), 55 cl::desc("Enable PPC32 register scavenger"), 56 cl::Hidden); 57 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", 58 cl::init(false), 59 cl::desc("Enable PPC64 register scavenger"), 60 cl::Hidden); 61 } 62 63 using namespace llvm; 64 65 // FIXME (64-bit): Should be inlined. 66 bool 67 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 68 return ((EnablePPC32RS && !Subtarget.isPPC64()) || 69 (EnablePPC64RS && Subtarget.isPPC64())); 70 } 71 72 /// getRegisterNumbering - Given the enum value for some register, e.g. 73 /// PPC::F14, return the number that it corresponds to (e.g. 14). 74 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 75 using namespace PPC; 76 switch (RegEnum) { 77 case 0: return 0; 78 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; 79 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; 80 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; 81 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; 82 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; 83 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; 84 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; 85 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; 86 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; 87 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; 88 case R10: case X10: case F10: case V10: case CR2EQ: return 10; 89 case R11: case X11: case F11: case V11: case CR2UN: return 11; 90 case R12: case X12: case F12: case V12: case CR3LT: return 12; 91 case R13: case X13: case F13: case V13: case CR3GT: return 13; 92 case R14: case X14: case F14: case V14: case CR3EQ: return 14; 93 case R15: case X15: case F15: case V15: case CR3UN: return 15; 94 case R16: case X16: case F16: case V16: case CR4LT: return 16; 95 case R17: case X17: case F17: case V17: case CR4GT: return 17; 96 case R18: case X18: case F18: case V18: case CR4EQ: return 18; 97 case R19: case X19: case F19: case V19: case CR4UN: return 19; 98 case R20: case X20: case F20: case V20: case CR5LT: return 20; 99 case R21: case X21: case F21: case V21: case CR5GT: return 21; 100 case R22: case X22: case F22: case V22: case CR5EQ: return 22; 101 case R23: case X23: case F23: case V23: case CR5UN: return 23; 102 case R24: case X24: case F24: case V24: case CR6LT: return 24; 103 case R25: case X25: case F25: case V25: case CR6GT: return 25; 104 case R26: case X26: case F26: case V26: case CR6EQ: return 26; 105 case R27: case X27: case F27: case V27: case CR6UN: return 27; 106 case R28: case X28: case F28: case V28: case CR7LT: return 28; 107 case R29: case X29: case F29: case V29: case CR7GT: return 29; 108 case R30: case X30: case F30: case V30: case CR7EQ: return 30; 109 case R31: case X31: case F31: case V31: case CR7UN: return 31; 110 default: 111 llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); 112 } 113 } 114 115 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 116 const TargetInstrInfo &tii) 117 : PPCGenRegisterInfo(), Subtarget(ST), TII(tii) { 118 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 119 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 120 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 121 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 122 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 123 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 124 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 125 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 126 127 // 64-bit 128 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 129 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 130 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 131 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 132 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 133 } 134 135 /// getPointerRegClass - Return the register class to use to hold pointers. 136 /// This is used for addressing modes. 137 const TargetRegisterClass * 138 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const { 139 if (Subtarget.isPPC64()) 140 return &PPC::G8RCRegClass; 141 return &PPC::GPRCRegClass; 142 } 143 144 const unsigned* 145 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 146 // 32-bit Darwin calling convention. 147 static const unsigned Darwin32_CalleeSavedRegs[] = { 148 PPC::R13, PPC::R14, PPC::R15, 149 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 150 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 151 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 152 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 153 154 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 155 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 156 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 157 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 158 PPC::F30, PPC::F31, 159 160 PPC::CR2, PPC::CR3, PPC::CR4, 161 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 162 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 163 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 164 165 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 166 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 167 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 168 169 PPC::LR, 0 170 }; 171 172 // 32-bit SVR4 calling convention. 173 static const unsigned SVR4_CalleeSavedRegs[] = { 174 PPC::R14, PPC::R15, 175 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 176 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 177 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 178 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 179 180 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 181 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 182 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 183 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 184 PPC::F30, PPC::F31, 185 186 PPC::CR2, PPC::CR3, PPC::CR4, 187 188 PPC::VRSAVE, 189 190 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 191 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 192 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 193 194 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 195 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 196 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 197 198 0 199 }; 200 // 64-bit Darwin calling convention. 201 static const unsigned Darwin64_CalleeSavedRegs[] = { 202 PPC::X14, PPC::X15, 203 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 204 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 205 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 206 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 207 208 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 209 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 210 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 211 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 212 PPC::F30, PPC::F31, 213 214 PPC::CR2, PPC::CR3, PPC::CR4, 215 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 216 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 217 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 218 219 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 220 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 221 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 222 223 PPC::LR8, 0 224 }; 225 226 // 64-bit SVR4 calling convention. 227 static const unsigned SVR4_64_CalleeSavedRegs[] = { 228 PPC::X14, PPC::X15, 229 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 230 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 231 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 232 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 233 234 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 235 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 236 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 237 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 238 PPC::F30, PPC::F31, 239 240 PPC::CR2, PPC::CR3, PPC::CR4, 241 242 PPC::VRSAVE, 243 244 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 245 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 246 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 247 248 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 249 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 250 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 251 252 0 253 }; 254 255 if (Subtarget.isDarwinABI()) 256 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : 257 Darwin32_CalleeSavedRegs; 258 259 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs; 260 } 261 262 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 263 BitVector Reserved(getNumRegs()); 264 const PPCFrameLowering *PPCFI = 265 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 266 267 Reserved.set(PPC::R0); 268 Reserved.set(PPC::R1); 269 Reserved.set(PPC::LR); 270 Reserved.set(PPC::LR8); 271 Reserved.set(PPC::RM); 272 273 // The SVR4 ABI reserves r2 and r13 274 if (Subtarget.isSVR4ABI()) { 275 Reserved.set(PPC::R2); // System-reserved register 276 Reserved.set(PPC::R13); // Small Data Area pointer register 277 } 278 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 279 // when the stack frame is too big to address directly; we need two regs. 280 // This is a hack. 281 if (Subtarget.isDarwinABI()) { 282 Reserved.set(PPC::R2); 283 } 284 285 // On PPC64, r13 is the thread pointer. Never allocate this register. 286 // Note that this is over conservative, as it also prevents allocation of R31 287 // when the FP is not needed. 288 if (Subtarget.isPPC64()) { 289 Reserved.set(PPC::R13); 290 Reserved.set(PPC::R31); 291 292 if (!requiresRegisterScavenging(MF)) 293 Reserved.set(PPC::R0); // FIXME (64-bit): Remove 294 295 Reserved.set(PPC::X0); 296 Reserved.set(PPC::X1); 297 Reserved.set(PPC::X13); 298 Reserved.set(PPC::X31); 299 300 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 301 if (Subtarget.isSVR4ABI()) { 302 Reserved.set(PPC::X2); 303 } 304 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 305 // when the stack frame is too big to address directly; we need two regs. 306 // This is a hack. 307 if (Subtarget.isDarwinABI()) { 308 Reserved.set(PPC::X2); 309 } 310 } 311 312 if (PPCFI->needsFP(MF)) 313 Reserved.set(PPC::R31); 314 315 return Reserved; 316 } 317 318 //===----------------------------------------------------------------------===// 319 // Stack Frame Processing methods 320 //===----------------------------------------------------------------------===// 321 322 void PPCRegisterInfo:: 323 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 324 MachineBasicBlock::iterator I) const { 325 if (GuaranteedTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) { 326 // Add (actually subtract) back the amount the callee popped on return. 327 if (int CalleeAmt = I->getOperand(1).getImm()) { 328 bool is64Bit = Subtarget.isPPC64(); 329 CalleeAmt *= -1; 330 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 331 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 332 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 333 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 334 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 335 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 336 MachineInstr *MI = I; 337 DebugLoc dl = MI->getDebugLoc(); 338 339 if (isInt<16>(CalleeAmt)) { 340 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg). 341 addImm(CalleeAmt); 342 } else { 343 MachineBasicBlock::iterator MBBI = I; 344 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 345 .addImm(CalleeAmt >> 16); 346 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 347 .addReg(TmpReg, RegState::Kill) 348 .addImm(CalleeAmt & 0xFFFF); 349 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 350 .addReg(StackReg) 351 .addReg(StackReg) 352 .addReg(TmpReg); 353 } 354 } 355 } 356 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 357 MBB.erase(I); 358 } 359 360 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 361 /// register first and then a spilled callee-saved register if that fails. 362 static 363 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 364 const TargetRegisterClass *RC, int SPAdj) { 365 assert(RS && "Register scavenging must be on"); 366 unsigned Reg = RS->FindUnusedReg(RC); 367 // FIXME: move ARM callee-saved reg scan to target independent code, then 368 // search for already spilled CS register here. 369 if (Reg == 0) 370 Reg = RS->scavengeRegister(RC, II, SPAdj); 371 return Reg; 372 } 373 374 /// lowerDynamicAlloc - Generate the code for allocating an object in the 375 /// current frame. The sequence of code with be in the general form 376 /// 377 /// addi R0, SP, \#frameSize ; get the address of the previous frame 378 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 379 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 380 /// 381 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 382 int SPAdj, RegScavenger *RS) const { 383 // Get the instruction. 384 MachineInstr &MI = *II; 385 // Get the instruction's basic block. 386 MachineBasicBlock &MBB = *MI.getParent(); 387 // Get the basic block's function. 388 MachineFunction &MF = *MBB.getParent(); 389 // Get the frame info. 390 MachineFrameInfo *MFI = MF.getFrameInfo(); 391 // Determine whether 64-bit pointers are used. 392 bool LP64 = Subtarget.isPPC64(); 393 DebugLoc dl = MI.getDebugLoc(); 394 395 // Get the maximum call stack size. 396 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 397 // Get the total frame size. 398 unsigned FrameSize = MFI->getStackSize(); 399 400 // Get stack alignments. 401 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 402 unsigned MaxAlign = MFI->getMaxAlignment(); 403 if (MaxAlign > TargetAlign) 404 report_fatal_error("Dynamic alloca with large aligns not supported"); 405 406 // Determine the previous frame's address. If FrameSize can't be 407 // represented as 16 bits or we need special alignment, then we load the 408 // previous frame's address from 0(SP). Why not do an addis of the hi? 409 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 410 // Constructing the constant and adding would take 3 instructions. 411 // Fortunately, a frame greater than 32K is rare. 412 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 413 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 414 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 415 416 // FIXME (64-bit): Use "findScratchRegister" 417 unsigned Reg; 418 if (requiresRegisterScavenging(MF)) 419 Reg = findScratchRegister(II, RS, RC, SPAdj); 420 else 421 Reg = PPC::R0; 422 423 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 424 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 425 .addReg(PPC::R31) 426 .addImm(FrameSize); 427 } else if (LP64) { 428 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 429 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 430 .addImm(0) 431 .addReg(PPC::X1); 432 else 433 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 434 .addImm(0) 435 .addReg(PPC::X1); 436 } else { 437 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 438 .addImm(0) 439 .addReg(PPC::R1); 440 } 441 442 // Grow the stack and update the stack pointer link, then determine the 443 // address of new allocated space. 444 if (LP64) { 445 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 446 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 447 .addReg(Reg, RegState::Kill) 448 .addReg(PPC::X1) 449 .addReg(MI.getOperand(1).getReg()); 450 else 451 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 452 .addReg(PPC::X0, RegState::Kill) 453 .addReg(PPC::X1) 454 .addReg(MI.getOperand(1).getReg()); 455 456 if (!MI.getOperand(1).isKill()) 457 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 458 .addReg(PPC::X1) 459 .addImm(maxCallFrameSize); 460 else 461 // Implicitly kill the register. 462 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 463 .addReg(PPC::X1) 464 .addImm(maxCallFrameSize) 465 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 466 } else { 467 BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) 468 .addReg(Reg, RegState::Kill) 469 .addReg(PPC::R1) 470 .addReg(MI.getOperand(1).getReg()); 471 472 if (!MI.getOperand(1).isKill()) 473 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 474 .addReg(PPC::R1) 475 .addImm(maxCallFrameSize); 476 else 477 // Implicitly kill the register. 478 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 479 .addReg(PPC::R1) 480 .addImm(maxCallFrameSize) 481 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 482 } 483 484 // Discard the DYNALLOC instruction. 485 MBB.erase(II); 486 } 487 488 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 489 /// reserving a whole register (R0), we scrounge for one here. This generates 490 /// code like this: 491 /// 492 /// mfcr rA ; Move the conditional register into GPR rA. 493 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 494 /// stw rA, FI ; Store rA to the frame. 495 /// 496 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 497 unsigned FrameIndex, int SPAdj, 498 RegScavenger *RS) const { 499 // Get the instruction. 500 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> 501 // Get the instruction's basic block. 502 MachineBasicBlock &MBB = *MI.getParent(); 503 DebugLoc dl = MI.getDebugLoc(); 504 505 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 506 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 507 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 508 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 509 unsigned SrcReg = MI.getOperand(0).getReg(); 510 bool LP64 = Subtarget.isPPC64(); 511 512 // We need to store the CR in the low 4-bits of the saved value. First, issue 513 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 514 BuildMI(MBB, II, dl, TII.get(PPC::MFCRpseud), Reg) 515 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 516 517 // If the saved register wasn't CR0, shift the bits left so that they are in 518 // CR0's slot. 519 if (SrcReg != PPC::CR0) 520 // rlwinm rA, rA, ShiftBits, 0, 31. 521 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) 522 .addReg(Reg, RegState::Kill) 523 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) 524 .addImm(0) 525 .addImm(31); 526 527 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 528 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 529 FrameIndex); 530 531 // Discard the pseudo instruction. 532 MBB.erase(II); 533 } 534 535 void 536 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 537 int SPAdj, RegScavenger *RS) const { 538 assert(SPAdj == 0 && "Unexpected"); 539 540 // Get the instruction. 541 MachineInstr &MI = *II; 542 // Get the instruction's basic block. 543 MachineBasicBlock &MBB = *MI.getParent(); 544 // Get the basic block's function. 545 MachineFunction &MF = *MBB.getParent(); 546 // Get the frame info. 547 MachineFrameInfo *MFI = MF.getFrameInfo(); 548 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 549 DebugLoc dl = MI.getDebugLoc(); 550 551 // Find out which operand is the frame index. 552 unsigned FIOperandNo = 0; 553 while (!MI.getOperand(FIOperandNo).isFI()) { 554 ++FIOperandNo; 555 assert(FIOperandNo != MI.getNumOperands() && 556 "Instr doesn't have FrameIndex operand!"); 557 } 558 // Take into account whether it's an add or mem instruction 559 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 560 if (MI.isInlineAsm()) 561 OffsetOperandNo = FIOperandNo-1; 562 563 // Get the frame index. 564 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 565 566 // Get the frame pointer save index. Users of this index are primarily 567 // DYNALLOC instructions. 568 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 569 int FPSI = FI->getFramePointerSaveIndex(); 570 // Get the instruction opcode. 571 unsigned OpC = MI.getOpcode(); 572 573 // Special case for dynamic alloca. 574 if (FPSI && FrameIndex == FPSI && 575 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 576 lowerDynamicAlloc(II, SPAdj, RS); 577 return; 578 } 579 580 // Special case for pseudo-op SPILL_CR. 581 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable by default. 582 if (OpC == PPC::SPILL_CR) { 583 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 584 return; 585 } 586 587 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 588 MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ? 589 PPC::R31 : PPC::R1, 590 false); 591 592 // Figure out if the offset in the instruction is shifted right two bits. This 593 // is true for instructions like "STD", which the machine implicitly adds two 594 // low zeros to. 595 bool isIXAddr = false; 596 switch (OpC) { 597 case PPC::LWA: 598 case PPC::LD: 599 case PPC::STD: 600 case PPC::STD_32: 601 isIXAddr = true; 602 break; 603 } 604 605 // Now add the frame object offset to the offset from r1. 606 int Offset = MFI->getObjectOffset(FrameIndex); 607 if (!isIXAddr) 608 Offset += MI.getOperand(OffsetOperandNo).getImm(); 609 else 610 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 611 612 // If we're not using a Frame Pointer that has been set to the value of the 613 // SP before having the stack size subtracted from it, then add the stack size 614 // to Offset to get the correct offset. 615 // Naked functions have stack size 0, although getStackSize may not reflect that 616 // because we didn't call all the pieces that compute it for naked functions. 617 if (!MF.getFunction()->hasFnAttr(Attribute::Naked)) 618 Offset += MFI->getStackSize(); 619 620 // If we can, encode the offset directly into the instruction. If this is a 621 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 622 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 623 // clear can be encoded. This is extremely uncommon, because normally you 624 // only "std" to a stack slot that is at least 4-byte aligned, but it can 625 // happen in invalid code. 626 if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 627 if (isIXAddr) 628 Offset >>= 2; // The actual encoded value has the low two bits zero. 629 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 630 return; 631 } 632 633 // The offset doesn't fit into a single register, scavenge one to build the 634 // offset in. 635 // FIXME: figure out what SPAdj is doing here. 636 637 // FIXME (64-bit): Use "findScratchRegister". 638 unsigned SReg; 639 if (requiresRegisterScavenging(MF)) 640 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); 641 else 642 SReg = PPC::R0; 643 644 // Insert a set of rA with the full offset value before the ld, st, or add 645 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) 646 .addImm(Offset >> 16); 647 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) 648 .addReg(SReg, RegState::Kill) 649 .addImm(Offset); 650 651 // Convert into indexed form of the instruction: 652 // 653 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 654 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 655 unsigned OperandBase; 656 657 if (OpC != TargetOpcode::INLINEASM) { 658 assert(ImmToIdxMap.count(OpC) && 659 "No indexed form of load or store available!"); 660 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 661 MI.setDesc(TII.get(NewOpcode)); 662 OperandBase = 1; 663 } else { 664 OperandBase = OffsetOperandNo; 665 } 666 667 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 668 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 669 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); 670 } 671 672 unsigned PPCRegisterInfo::getRARegister() const { 673 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 674 } 675 676 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 677 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 678 679 if (!Subtarget.isPPC64()) 680 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 681 else 682 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 683 } 684 685 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 686 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 687 } 688 689 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 690 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 691 } 692 693 /// DWARFFlavour - Flavour of dwarf regnumbers 694 /// 695 namespace DWARFFlavour { 696 enum { 697 PPC64 = 0, PPC32 = 1 698 }; 699 } 700 701 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 702 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 703 unsigned Flavour = Subtarget.isPPC64() ? 704 DWARFFlavour::PPC64 : DWARFFlavour::PPC32; 705 706 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, Flavour); 707 } 708 709 int PPCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { 710 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 711 unsigned Flavour = Subtarget.isPPC64() ? 712 DWARFFlavour::PPC64 : DWARFFlavour::PPC32; 713 714 return PPCGenRegisterInfo::getLLVMRegNumFull(RegNum, Flavour); 715 } 716