1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPC.h" 17 #include "PPCInstrBuilder.h" 18 #include "PPCMachineFunctionInfo.h" 19 #include "PPCRegisterInfo.h" 20 #include "PPCFrameInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/CallingConv.h" 23 #include "llvm/Constants.h" 24 #include "llvm/Function.h" 25 #include "llvm/Type.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineModuleInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineFrameInfo.h" 31 #include "llvm/CodeGen/MachineLocation.h" 32 #include "llvm/CodeGen/MachineRegisterInfo.h" 33 #include "llvm/CodeGen/RegisterScavenging.h" 34 #include "llvm/Target/TargetFrameInfo.h" 35 #include "llvm/Target/TargetInstrInfo.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetOptions.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/ErrorHandling.h" 41 #include "llvm/Support/MathExtras.h" 42 #include "llvm/Support/raw_ostream.h" 43 #include "llvm/ADT/BitVector.h" 44 #include "llvm/ADT/STLExtras.h" 45 #include <cstdlib> 46 47 // FIXME (64-bit): Eventually enable by default. 48 namespace llvm { 49 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", 50 cl::init(false), 51 cl::desc("Enable PPC32 register scavenger"), 52 cl::Hidden); 53 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", 54 cl::init(false), 55 cl::desc("Enable PPC64 register scavenger"), 56 cl::Hidden); 57 } 58 59 using namespace llvm; 60 61 #define EnableRegisterScavenging \ 62 ((EnablePPC32RS && !Subtarget.isPPC64()) || \ 63 (EnablePPC64RS && Subtarget.isPPC64())) 64 65 // FIXME (64-bit): Should be inlined. 66 bool 67 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 68 return EnableRegisterScavenging; 69 } 70 71 /// getRegisterNumbering - Given the enum value for some register, e.g. 72 /// PPC::F14, return the number that it corresponds to (e.g. 14). 73 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 74 using namespace PPC; 75 switch (RegEnum) { 76 case 0: return 0; 77 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; 78 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; 79 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; 80 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; 81 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; 82 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; 83 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; 84 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; 85 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; 86 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; 87 case R10: case X10: case F10: case V10: case CR2EQ: return 10; 88 case R11: case X11: case F11: case V11: case CR2UN: return 11; 89 case R12: case X12: case F12: case V12: case CR3LT: return 12; 90 case R13: case X13: case F13: case V13: case CR3GT: return 13; 91 case R14: case X14: case F14: case V14: case CR3EQ: return 14; 92 case R15: case X15: case F15: case V15: case CR3UN: return 15; 93 case R16: case X16: case F16: case V16: case CR4LT: return 16; 94 case R17: case X17: case F17: case V17: case CR4GT: return 17; 95 case R18: case X18: case F18: case V18: case CR4EQ: return 18; 96 case R19: case X19: case F19: case V19: case CR4UN: return 19; 97 case R20: case X20: case F20: case V20: case CR5LT: return 20; 98 case R21: case X21: case F21: case V21: case CR5GT: return 21; 99 case R22: case X22: case F22: case V22: case CR5EQ: return 22; 100 case R23: case X23: case F23: case V23: case CR5UN: return 23; 101 case R24: case X24: case F24: case V24: case CR6LT: return 24; 102 case R25: case X25: case F25: case V25: case CR6GT: return 25; 103 case R26: case X26: case F26: case V26: case CR6EQ: return 26; 104 case R27: case X27: case F27: case V27: case CR6UN: return 27; 105 case R28: case X28: case F28: case V28: case CR7LT: return 28; 106 case R29: case X29: case F29: case V29: case CR7GT: return 29; 107 case R30: case X30: case F30: case V30: case CR7EQ: return 30; 108 case R31: case X31: case F31: case V31: case CR7UN: return 31; 109 default: 110 llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); 111 } 112 } 113 114 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 115 const TargetInstrInfo &tii) 116 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 117 Subtarget(ST), TII(tii) { 118 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 119 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 120 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 121 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 122 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 123 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 124 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 125 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 126 127 // 64-bit 128 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 129 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 130 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 131 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 132 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 133 } 134 135 /// getPointerRegClass - Return the register class to use to hold pointers. 136 /// This is used for addressing modes. 137 const TargetRegisterClass * 138 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const { 139 if (Subtarget.isPPC64()) 140 return &PPC::G8RCRegClass; 141 return &PPC::GPRCRegClass; 142 } 143 144 const unsigned* 145 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 146 // 32-bit Darwin calling convention. 147 static const unsigned Darwin32_CalleeSavedRegs[] = { 148 PPC::R13, PPC::R14, PPC::R15, 149 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 150 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 151 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 152 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 153 154 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 155 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 156 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 157 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 158 PPC::F30, PPC::F31, 159 160 PPC::CR2, PPC::CR3, PPC::CR4, 161 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 162 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 163 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 164 165 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 166 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 167 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 168 169 PPC::LR, 0 170 }; 171 172 // 32-bit SVR4 calling convention. 173 static const unsigned SVR4_CalleeSavedRegs[] = { 174 PPC::R14, PPC::R15, 175 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 176 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 177 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 178 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 179 180 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 181 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 182 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 183 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 184 PPC::F30, PPC::F31, 185 186 PPC::CR2, PPC::CR3, PPC::CR4, 187 188 PPC::VRSAVE, 189 190 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 191 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 192 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 193 194 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 195 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 196 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 197 198 0 199 }; 200 // 64-bit Darwin calling convention. 201 static const unsigned Darwin64_CalleeSavedRegs[] = { 202 PPC::X14, PPC::X15, 203 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 204 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 205 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 206 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 207 208 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 209 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 210 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 211 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 212 PPC::F30, PPC::F31, 213 214 PPC::CR2, PPC::CR3, PPC::CR4, 215 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 216 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 217 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 218 219 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 220 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 221 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 222 223 PPC::LR8, 0 224 }; 225 226 // 64-bit SVR4 calling convention. 227 static const unsigned SVR4_64_CalleeSavedRegs[] = { 228 PPC::X14, PPC::X15, 229 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 230 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 231 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 232 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 233 234 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 235 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 236 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 237 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 238 PPC::F30, PPC::F31, 239 240 PPC::CR2, PPC::CR3, PPC::CR4, 241 242 PPC::VRSAVE, 243 244 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 245 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 246 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 247 248 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 249 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 250 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 251 252 0 253 }; 254 255 if (Subtarget.isDarwinABI()) 256 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : 257 Darwin32_CalleeSavedRegs; 258 259 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs; 260 } 261 262 static bool spillsCR(const MachineFunction &MF) { 263 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 264 return FuncInfo->isCRSpilled(); 265 } 266 267 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 268 BitVector Reserved(getNumRegs()); 269 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); 270 271 Reserved.set(PPC::R0); 272 Reserved.set(PPC::R1); 273 Reserved.set(PPC::LR); 274 Reserved.set(PPC::LR8); 275 Reserved.set(PPC::RM); 276 277 // The SVR4 ABI reserves r2 and r13 278 if (Subtarget.isSVR4ABI()) { 279 Reserved.set(PPC::R2); // System-reserved register 280 Reserved.set(PPC::R13); // Small Data Area pointer register 281 } 282 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 283 // when the stack frame is too big to address directly; we need two regs. 284 // This is a hack. 285 if (Subtarget.isDarwinABI()) { 286 Reserved.set(PPC::R2); 287 } 288 289 // On PPC64, r13 is the thread pointer. Never allocate this register. 290 // Note that this is over conservative, as it also prevents allocation of R31 291 // when the FP is not needed. 292 if (Subtarget.isPPC64()) { 293 Reserved.set(PPC::R13); 294 Reserved.set(PPC::R31); 295 296 if (!EnableRegisterScavenging) 297 Reserved.set(PPC::R0); // FIXME (64-bit): Remove 298 299 Reserved.set(PPC::X0); 300 Reserved.set(PPC::X1); 301 Reserved.set(PPC::X13); 302 Reserved.set(PPC::X31); 303 304 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 305 if (Subtarget.isSVR4ABI()) { 306 Reserved.set(PPC::X2); 307 } 308 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 309 // when the stack frame is too big to address directly; we need two regs. 310 // This is a hack. 311 if (Subtarget.isDarwinABI()) { 312 Reserved.set(PPC::X2); 313 } 314 } 315 316 if (TFI->hasFP(MF)) 317 Reserved.set(PPC::R31); 318 319 return Reserved; 320 } 321 322 //===----------------------------------------------------------------------===// 323 // Stack Frame Processing methods 324 //===----------------------------------------------------------------------===// 325 326 /// MustSaveLR - Return true if this function requires that we save the LR 327 /// register onto the stack in the prolog and restore it in the epilog of the 328 /// function. 329 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 330 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 331 332 // We need a save/restore of LR if there is any def of LR (which is 333 // defined by calls, including the PIC setup sequence), or if there is 334 // some use of the LR stack slot (e.g. for builtin_return_address). 335 // (LR comes in 32 and 64 bit versions.) 336 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 337 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 338 } 339 340 341 342 void PPCRegisterInfo:: 343 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 344 MachineBasicBlock::iterator I) const { 345 if (GuaranteedTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) { 346 // Add (actually subtract) back the amount the callee popped on return. 347 if (int CalleeAmt = I->getOperand(1).getImm()) { 348 bool is64Bit = Subtarget.isPPC64(); 349 CalleeAmt *= -1; 350 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 351 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 352 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 353 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 354 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 355 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 356 MachineInstr *MI = I; 357 DebugLoc dl = MI->getDebugLoc(); 358 359 if (isInt<16>(CalleeAmt)) { 360 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg). 361 addImm(CalleeAmt); 362 } else { 363 MachineBasicBlock::iterator MBBI = I; 364 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 365 .addImm(CalleeAmt >> 16); 366 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 367 .addReg(TmpReg, RegState::Kill) 368 .addImm(CalleeAmt & 0xFFFF); 369 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 370 .addReg(StackReg) 371 .addReg(StackReg) 372 .addReg(TmpReg); 373 } 374 } 375 } 376 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 377 MBB.erase(I); 378 } 379 380 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 381 /// register first and then a spilled callee-saved register if that fails. 382 static 383 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 384 const TargetRegisterClass *RC, int SPAdj) { 385 assert(RS && "Register scavenging must be on"); 386 unsigned Reg = RS->FindUnusedReg(RC); 387 // FIXME: move ARM callee-saved reg scan to target independent code, then 388 // search for already spilled CS register here. 389 if (Reg == 0) 390 Reg = RS->scavengeRegister(RC, II, SPAdj); 391 return Reg; 392 } 393 394 /// lowerDynamicAlloc - Generate the code for allocating an object in the 395 /// current frame. The sequence of code with be in the general form 396 /// 397 /// addi R0, SP, \#frameSize ; get the address of the previous frame 398 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 399 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 400 /// 401 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 402 int SPAdj, RegScavenger *RS) const { 403 // Get the instruction. 404 MachineInstr &MI = *II; 405 // Get the instruction's basic block. 406 MachineBasicBlock &MBB = *MI.getParent(); 407 // Get the basic block's function. 408 MachineFunction &MF = *MBB.getParent(); 409 // Get the frame info. 410 MachineFrameInfo *MFI = MF.getFrameInfo(); 411 // Determine whether 64-bit pointers are used. 412 bool LP64 = Subtarget.isPPC64(); 413 DebugLoc dl = MI.getDebugLoc(); 414 415 // Get the maximum call stack size. 416 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 417 // Get the total frame size. 418 unsigned FrameSize = MFI->getStackSize(); 419 420 // Get stack alignments. 421 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 422 unsigned MaxAlign = MFI->getMaxAlignment(); 423 if (MaxAlign > TargetAlign) 424 report_fatal_error("Dynamic alloca with large aligns not supported"); 425 426 // Determine the previous frame's address. If FrameSize can't be 427 // represented as 16 bits or we need special alignment, then we load the 428 // previous frame's address from 0(SP). Why not do an addis of the hi? 429 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 430 // Constructing the constant and adding would take 3 instructions. 431 // Fortunately, a frame greater than 32K is rare. 432 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 433 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 434 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 435 436 // FIXME (64-bit): Use "findScratchRegister" 437 unsigned Reg; 438 if (EnableRegisterScavenging) 439 Reg = findScratchRegister(II, RS, RC, SPAdj); 440 else 441 Reg = PPC::R0; 442 443 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 444 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 445 .addReg(PPC::R31) 446 .addImm(FrameSize); 447 } else if (LP64) { 448 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 449 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 450 .addImm(0) 451 .addReg(PPC::X1); 452 else 453 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 454 .addImm(0) 455 .addReg(PPC::X1); 456 } else { 457 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 458 .addImm(0) 459 .addReg(PPC::R1); 460 } 461 462 // Grow the stack and update the stack pointer link, then determine the 463 // address of new allocated space. 464 if (LP64) { 465 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 466 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 467 .addReg(Reg, RegState::Kill) 468 .addReg(PPC::X1) 469 .addReg(MI.getOperand(1).getReg()); 470 else 471 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 472 .addReg(PPC::X0, RegState::Kill) 473 .addReg(PPC::X1) 474 .addReg(MI.getOperand(1).getReg()); 475 476 if (!MI.getOperand(1).isKill()) 477 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 478 .addReg(PPC::X1) 479 .addImm(maxCallFrameSize); 480 else 481 // Implicitly kill the register. 482 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 483 .addReg(PPC::X1) 484 .addImm(maxCallFrameSize) 485 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 486 } else { 487 BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) 488 .addReg(Reg, RegState::Kill) 489 .addReg(PPC::R1) 490 .addReg(MI.getOperand(1).getReg()); 491 492 if (!MI.getOperand(1).isKill()) 493 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 494 .addReg(PPC::R1) 495 .addImm(maxCallFrameSize); 496 else 497 // Implicitly kill the register. 498 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 499 .addReg(PPC::R1) 500 .addImm(maxCallFrameSize) 501 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 502 } 503 504 // Discard the DYNALLOC instruction. 505 MBB.erase(II); 506 } 507 508 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 509 /// reserving a whole register (R0), we scrounge for one here. This generates 510 /// code like this: 511 /// 512 /// mfcr rA ; Move the conditional register into GPR rA. 513 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 514 /// stw rA, FI ; Store rA to the frame. 515 /// 516 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 517 unsigned FrameIndex, int SPAdj, 518 RegScavenger *RS) const { 519 // Get the instruction. 520 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> 521 // Get the instruction's basic block. 522 MachineBasicBlock &MBB = *MI.getParent(); 523 DebugLoc dl = MI.getDebugLoc(); 524 525 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 526 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 527 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 528 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 529 unsigned SrcReg = MI.getOperand(0).getReg(); 530 531 // We need to store the CR in the low 4-bits of the saved value. First, issue 532 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 533 BuildMI(MBB, II, dl, TII.get(PPC::MFCRpseud), Reg) 534 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 535 536 // If the saved register wasn't CR0, shift the bits left so that they are in 537 // CR0's slot. 538 if (SrcReg != PPC::CR0) 539 // rlwinm rA, rA, ShiftBits, 0, 31. 540 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) 541 .addReg(Reg, RegState::Kill) 542 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) 543 .addImm(0) 544 .addImm(31); 545 546 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 547 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 548 FrameIndex); 549 550 // Discard the pseudo instruction. 551 MBB.erase(II); 552 } 553 554 void 555 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 556 int SPAdj, RegScavenger *RS) const { 557 assert(SPAdj == 0 && "Unexpected"); 558 559 // Get the instruction. 560 MachineInstr &MI = *II; 561 // Get the instruction's basic block. 562 MachineBasicBlock &MBB = *MI.getParent(); 563 // Get the basic block's function. 564 MachineFunction &MF = *MBB.getParent(); 565 // Get the frame info. 566 MachineFrameInfo *MFI = MF.getFrameInfo(); 567 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); 568 DebugLoc dl = MI.getDebugLoc(); 569 570 // Find out which operand is the frame index. 571 unsigned FIOperandNo = 0; 572 while (!MI.getOperand(FIOperandNo).isFI()) { 573 ++FIOperandNo; 574 assert(FIOperandNo != MI.getNumOperands() && 575 "Instr doesn't have FrameIndex operand!"); 576 } 577 // Take into account whether it's an add or mem instruction 578 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 579 if (MI.isInlineAsm()) 580 OffsetOperandNo = FIOperandNo-1; 581 582 // Get the frame index. 583 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 584 585 // Get the frame pointer save index. Users of this index are primarily 586 // DYNALLOC instructions. 587 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 588 int FPSI = FI->getFramePointerSaveIndex(); 589 // Get the instruction opcode. 590 unsigned OpC = MI.getOpcode(); 591 592 // Special case for dynamic alloca. 593 if (FPSI && FrameIndex == FPSI && 594 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 595 lowerDynamicAlloc(II, SPAdj, RS); 596 return; 597 } 598 599 // Special case for pseudo-op SPILL_CR. 600 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default. 601 if (OpC == PPC::SPILL_CR) { 602 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 603 return; 604 } 605 606 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 607 MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ? 608 PPC::R31 : PPC::R1, 609 false); 610 611 // Figure out if the offset in the instruction is shifted right two bits. This 612 // is true for instructions like "STD", which the machine implicitly adds two 613 // low zeros to. 614 bool isIXAddr = false; 615 switch (OpC) { 616 case PPC::LWA: 617 case PPC::LD: 618 case PPC::STD: 619 case PPC::STD_32: 620 isIXAddr = true; 621 break; 622 } 623 624 // Now add the frame object offset to the offset from r1. 625 int Offset = MFI->getObjectOffset(FrameIndex); 626 if (!isIXAddr) 627 Offset += MI.getOperand(OffsetOperandNo).getImm(); 628 else 629 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 630 631 // If we're not using a Frame Pointer that has been set to the value of the 632 // SP before having the stack size subtracted from it, then add the stack size 633 // to Offset to get the correct offset. 634 // Naked functions have stack size 0, although getStackSize may not reflect that 635 // because we didn't call all the pieces that compute it for naked functions. 636 if (!MF.getFunction()->hasFnAttr(Attribute::Naked)) 637 Offset += MFI->getStackSize(); 638 639 // If we can, encode the offset directly into the instruction. If this is a 640 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 641 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 642 // clear can be encoded. This is extremely uncommon, because normally you 643 // only "std" to a stack slot that is at least 4-byte aligned, but it can 644 // happen in invalid code. 645 if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 646 if (isIXAddr) 647 Offset >>= 2; // The actual encoded value has the low two bits zero. 648 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 649 return; 650 } 651 652 // The offset doesn't fit into a single register, scavenge one to build the 653 // offset in. 654 // FIXME: figure out what SPAdj is doing here. 655 656 // FIXME (64-bit): Use "findScratchRegister". 657 unsigned SReg; 658 if (EnableRegisterScavenging) 659 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); 660 else 661 SReg = PPC::R0; 662 663 // Insert a set of rA with the full offset value before the ld, st, or add 664 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) 665 .addImm(Offset >> 16); 666 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) 667 .addReg(SReg, RegState::Kill) 668 .addImm(Offset); 669 670 // Convert into indexed form of the instruction: 671 // 672 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 673 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 674 unsigned OperandBase; 675 676 if (OpC != TargetOpcode::INLINEASM) { 677 assert(ImmToIdxMap.count(OpC) && 678 "No indexed form of load or store available!"); 679 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 680 MI.setDesc(TII.get(NewOpcode)); 681 OperandBase = 1; 682 } else { 683 OperandBase = OffsetOperandNo; 684 } 685 686 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 687 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 688 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); 689 } 690 691 void 692 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 693 RegScavenger *RS) const { 694 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); 695 696 // Save and clear the LR state. 697 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 698 unsigned LR = getRARegister(); 699 FI->setMustSaveLR(MustSaveLR(MF, LR)); 700 MF.getRegInfo().setPhysRegUnused(LR); 701 702 // Save R31 if necessary 703 int FPSI = FI->getFramePointerSaveIndex(); 704 bool isPPC64 = Subtarget.isPPC64(); 705 bool isDarwinABI = Subtarget.isDarwinABI(); 706 MachineFrameInfo *MFI = MF.getFrameInfo(); 707 708 // If the frame pointer save index hasn't been defined yet. 709 if (!FPSI && TFI->hasFP(MF)) { 710 // Find out what the fix offset of the frame pointer save area. 711 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, 712 isDarwinABI); 713 // Allocate the frame index for frame pointer save area. 714 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 715 // Save the result. 716 FI->setFramePointerSaveIndex(FPSI); 717 } 718 719 // Reserve stack space to move the linkage area to in case of a tail call. 720 int TCSPDelta = 0; 721 if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 722 MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 723 } 724 725 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 726 // a large stack, which will require scavenging a register to materialize a 727 // large offset. 728 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 729 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 730 // r0 for now. 731 732 if (EnableRegisterScavenging) // FIXME (64-bit): Enable. 733 if (TFI->hasFP(MF) || spillsCR(MF)) { 734 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 735 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 736 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; 737 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 738 RC->getAlignment(), 739 false)); 740 } 741 } 742 743 void 744 PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) 745 const { 746 // Early exit if not using the SVR4 ABI. 747 if (!Subtarget.isSVR4ABI()) { 748 return; 749 } 750 751 // Get callee saved register information. 752 MachineFrameInfo *FFI = MF.getFrameInfo(); 753 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 754 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); 755 756 // Early exit if no callee saved registers are modified! 757 if (CSI.empty() && !TFI->hasFP(MF)) { 758 return; 759 } 760 761 unsigned MinGPR = PPC::R31; 762 unsigned MinG8R = PPC::X31; 763 unsigned MinFPR = PPC::F31; 764 unsigned MinVR = PPC::V31; 765 766 bool HasGPSaveArea = false; 767 bool HasG8SaveArea = false; 768 bool HasFPSaveArea = false; 769 bool HasCRSaveArea = false; 770 bool HasVRSAVESaveArea = false; 771 bool HasVRSaveArea = false; 772 773 SmallVector<CalleeSavedInfo, 18> GPRegs; 774 SmallVector<CalleeSavedInfo, 18> G8Regs; 775 SmallVector<CalleeSavedInfo, 18> FPRegs; 776 SmallVector<CalleeSavedInfo, 18> VRegs; 777 778 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 779 unsigned Reg = CSI[i].getReg(); 780 if (PPC::GPRCRegisterClass->contains(Reg)) { 781 HasGPSaveArea = true; 782 783 GPRegs.push_back(CSI[i]); 784 785 if (Reg < MinGPR) { 786 MinGPR = Reg; 787 } 788 } else if (PPC::G8RCRegisterClass->contains(Reg)) { 789 HasG8SaveArea = true; 790 791 G8Regs.push_back(CSI[i]); 792 793 if (Reg < MinG8R) { 794 MinG8R = Reg; 795 } 796 } else if (PPC::F8RCRegisterClass->contains(Reg)) { 797 HasFPSaveArea = true; 798 799 FPRegs.push_back(CSI[i]); 800 801 if (Reg < MinFPR) { 802 MinFPR = Reg; 803 } 804 // FIXME SVR4: Disable CR save area for now. 805 } else if (PPC::CRBITRCRegisterClass->contains(Reg) 806 || PPC::CRRCRegisterClass->contains(Reg)) { 807 // HasCRSaveArea = true; 808 } else if (PPC::VRSAVERCRegisterClass->contains(Reg)) { 809 HasVRSAVESaveArea = true; 810 } else if (PPC::VRRCRegisterClass->contains(Reg)) { 811 HasVRSaveArea = true; 812 813 VRegs.push_back(CSI[i]); 814 815 if (Reg < MinVR) { 816 MinVR = Reg; 817 } 818 } else { 819 llvm_unreachable("Unknown RegisterClass!"); 820 } 821 } 822 823 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 824 825 int64_t LowerBound = 0; 826 827 // Take into account stack space reserved for tail calls. 828 int TCSPDelta = 0; 829 if (GuaranteedTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 830 LowerBound = TCSPDelta; 831 } 832 833 // The Floating-point register save area is right below the back chain word 834 // of the previous stack frame. 835 if (HasFPSaveArea) { 836 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 837 int FI = FPRegs[i].getFrameIdx(); 838 839 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 840 } 841 842 LowerBound -= (31 - getRegisterNumbering(MinFPR) + 1) * 8; 843 } 844 845 // Check whether the frame pointer register is allocated. If so, make sure it 846 // is spilled to the correct offset. 847 if (TFI->hasFP(MF)) { 848 HasGPSaveArea = true; 849 850 int FI = PFI->getFramePointerSaveIndex(); 851 assert(FI && "No Frame Pointer Save Slot!"); 852 853 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 854 } 855 856 // General register save area starts right below the Floating-point 857 // register save area. 858 if (HasGPSaveArea || HasG8SaveArea) { 859 // Move general register save area spill slots down, taking into account 860 // the size of the Floating-point register save area. 861 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 862 int FI = GPRegs[i].getFrameIdx(); 863 864 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 865 } 866 867 // Move general register save area spill slots down, taking into account 868 // the size of the Floating-point register save area. 869 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 870 int FI = G8Regs[i].getFrameIdx(); 871 872 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 873 } 874 875 unsigned MinReg = std::min<unsigned>(getRegisterNumbering(MinGPR), 876 getRegisterNumbering(MinG8R)); 877 878 if (Subtarget.isPPC64()) { 879 LowerBound -= (31 - MinReg + 1) * 8; 880 } else { 881 LowerBound -= (31 - MinReg + 1) * 4; 882 } 883 } 884 885 // The CR save area is below the general register save area. 886 if (HasCRSaveArea) { 887 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 888 // which have the CR/CRBIT register class? 889 // Adjust the frame index of the CR spill slot. 890 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 891 unsigned Reg = CSI[i].getReg(); 892 893 if (PPC::CRBITRCRegisterClass->contains(Reg) || 894 PPC::CRRCRegisterClass->contains(Reg)) { 895 int FI = CSI[i].getFrameIdx(); 896 897 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 898 } 899 } 900 901 LowerBound -= 4; // The CR save area is always 4 bytes long. 902 } 903 904 if (HasVRSAVESaveArea) { 905 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 906 // which have the VRSAVE register class? 907 // Adjust the frame index of the VRSAVE spill slot. 908 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 909 unsigned Reg = CSI[i].getReg(); 910 911 if (PPC::VRSAVERCRegisterClass->contains(Reg)) { 912 int FI = CSI[i].getFrameIdx(); 913 914 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 915 } 916 } 917 918 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 919 } 920 921 if (HasVRSaveArea) { 922 // Insert alignment padding, we need 16-byte alignment. 923 LowerBound = (LowerBound - 15) & ~(15); 924 925 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 926 int FI = VRegs[i].getFrameIdx(); 927 928 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 929 } 930 } 931 } 932 933 unsigned PPCRegisterInfo::getRARegister() const { 934 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 935 } 936 937 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 938 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); 939 940 if (!Subtarget.isPPC64()) 941 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 942 else 943 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 944 } 945 946 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 947 const { 948 // Initial state of the frame pointer is R1. 949 MachineLocation Dst(MachineLocation::VirtualFP); 950 MachineLocation Src(PPC::R1, 0); 951 Moves.push_back(MachineMove(0, Dst, Src)); 952 } 953 954 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 955 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 956 } 957 958 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 959 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 960 } 961 962 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 963 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 964 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 965 } 966 967 #include "PPCGenRegisterInfo.inc" 968