1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPC.h" 17 #include "PPCInstrBuilder.h" 18 #include "PPCMachineFunctionInfo.h" 19 #include "PPCRegisterInfo.h" 20 #include "PPCFrameInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/CallingConv.h" 23 #include "llvm/Constants.h" 24 #include "llvm/Function.h" 25 #include "llvm/Type.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineModuleInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineFrameInfo.h" 31 #include "llvm/CodeGen/MachineLocation.h" 32 #include "llvm/CodeGen/MachineRegisterInfo.h" 33 #include "llvm/CodeGen/RegisterScavenging.h" 34 #include "llvm/Target/TargetFrameInfo.h" 35 #include "llvm/Target/TargetInstrInfo.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetOptions.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/MathExtras.h" 41 #include "llvm/ADT/BitVector.h" 42 #include "llvm/ADT/STLExtras.h" 43 #include <cstdlib> 44 using namespace llvm; 45 46 // FIXME This disables some code that aligns the stack to a boundary 47 // bigger than the default (16 bytes on Darwin) when there is a stack local 48 // of greater alignment. This does not currently work, because the delta 49 // between old and new stack pointers is added to offsets that reference 50 // incoming parameters after the prolog is generated, and the code that 51 // does that doesn't handle a variable delta. You don't want to do that 52 // anyway; a better approach is to reserve another register that retains 53 // to the incoming stack pointer, and reference parameters relative to that. 54 #define ALIGN_STACK 0 55 56 // FIXME (64-bit): Eventually enable by default. 57 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", 58 cl::init(false), 59 cl::desc("Enable PPC32 register scavenger"), 60 cl::Hidden); 61 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", 62 cl::init(false), 63 cl::desc("Enable PPC64 register scavenger"), 64 cl::Hidden); 65 #define EnableRegisterScavenging \ 66 ((EnablePPC32RS && !Subtarget.isPPC64()) || \ 67 (EnablePPC64RS && Subtarget.isPPC64())) 68 69 // FIXME (64-bit): Should be inlined. 70 bool 71 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 72 return EnableRegisterScavenging; 73 } 74 75 /// getRegisterNumbering - Given the enum value for some register, e.g. 76 /// PPC::F14, return the number that it corresponds to (e.g. 14). 77 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 78 using namespace PPC; 79 switch (RegEnum) { 80 case 0: return 0; 81 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; 82 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; 83 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; 84 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; 85 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; 86 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; 87 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; 88 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; 89 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; 90 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; 91 case R10: case X10: case F10: case V10: case CR2EQ: return 10; 92 case R11: case X11: case F11: case V11: case CR2UN: return 11; 93 case R12: case X12: case F12: case V12: case CR3LT: return 12; 94 case R13: case X13: case F13: case V13: case CR3GT: return 13; 95 case R14: case X14: case F14: case V14: case CR3EQ: return 14; 96 case R15: case X15: case F15: case V15: case CR3UN: return 15; 97 case R16: case X16: case F16: case V16: case CR4LT: return 16; 98 case R17: case X17: case F17: case V17: case CR4GT: return 17; 99 case R18: case X18: case F18: case V18: case CR4EQ: return 18; 100 case R19: case X19: case F19: case V19: case CR4UN: return 19; 101 case R20: case X20: case F20: case V20: case CR5LT: return 20; 102 case R21: case X21: case F21: case V21: case CR5GT: return 21; 103 case R22: case X22: case F22: case V22: case CR5EQ: return 22; 104 case R23: case X23: case F23: case V23: case CR5UN: return 23; 105 case R24: case X24: case F24: case V24: case CR6LT: return 24; 106 case R25: case X25: case F25: case V25: case CR6GT: return 25; 107 case R26: case X26: case F26: case V26: case CR6EQ: return 26; 108 case R27: case X27: case F27: case V27: case CR6UN: return 27; 109 case R28: case X28: case F28: case V28: case CR7LT: return 28; 110 case R29: case X29: case F29: case V29: case CR7GT: return 29; 111 case R30: case X30: case F30: case V30: case CR7EQ: return 30; 112 case R31: case X31: case F31: case V31: case CR7UN: return 31; 113 default: 114 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; 115 abort(); 116 } 117 } 118 119 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 120 const TargetInstrInfo &tii) 121 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 122 Subtarget(ST), TII(tii) { 123 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 124 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 125 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 126 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 127 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 128 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 129 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 130 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 131 132 // 64-bit 133 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 134 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 135 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 136 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 137 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 138 } 139 140 /// getPointerRegClass - Return the register class to use to hold pointers. 141 /// This is used for addressing modes. 142 const TargetRegisterClass *PPCRegisterInfo::getPointerRegClass() const { 143 if (Subtarget.isPPC64()) 144 return &PPC::G8RCRegClass; 145 else 146 return &PPC::GPRCRegClass; 147 } 148 149 const unsigned* 150 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 151 // 32-bit Darwin calling convention. 152 static const unsigned Macho32_CalleeSavedRegs[] = { 153 PPC::R13, PPC::R14, PPC::R15, 154 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 155 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 156 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 157 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 158 159 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 160 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 161 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 162 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 163 PPC::F30, PPC::F31, 164 165 PPC::CR2, PPC::CR3, PPC::CR4, 166 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 167 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 168 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 169 170 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 171 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 172 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 173 174 PPC::LR, 0 175 }; 176 177 static const unsigned ELF32_CalleeSavedRegs[] = { 178 PPC::R13, PPC::R14, PPC::R15, 179 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 180 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 181 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 182 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 183 184 PPC::F9, 185 PPC::F10, PPC::F11, PPC::F12, PPC::F13, 186 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 187 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 188 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 189 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 190 PPC::F30, PPC::F31, 191 192 PPC::CR2, PPC::CR3, PPC::CR4, 193 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 194 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 195 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 196 197 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 198 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 199 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 200 201 PPC::LR, 0 202 }; 203 // 64-bit Darwin calling convention. 204 static const unsigned Macho64_CalleeSavedRegs[] = { 205 PPC::X14, PPC::X15, 206 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 207 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 208 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 209 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 210 211 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 212 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 213 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 214 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 215 PPC::F30, PPC::F31, 216 217 PPC::CR2, PPC::CR3, PPC::CR4, 218 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 219 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 220 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 221 222 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 223 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 224 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 225 226 PPC::LR8, 0 227 }; 228 229 if (Subtarget.isMachoABI()) 230 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs : 231 Macho32_CalleeSavedRegs; 232 233 // ELF 32. 234 return ELF32_CalleeSavedRegs; 235 } 236 237 const TargetRegisterClass* const* 238 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 239 // 32-bit Macho calling convention. 240 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = { 241 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 242 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 243 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 244 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 245 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 246 247 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 248 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 249 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 250 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 251 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 252 253 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 254 255 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 256 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 257 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 258 259 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 260 &PPC::CRBITRCRegClass, 261 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 262 &PPC::CRBITRCRegClass, 263 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 264 &PPC::CRBITRCRegClass, 265 266 &PPC::GPRCRegClass, 0 267 }; 268 269 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = { 270 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 271 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 272 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 273 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 274 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 275 276 &PPC::F8RCRegClass, 277 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 278 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 279 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 280 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 281 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 282 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 283 284 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 285 286 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 287 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 288 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 289 290 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 291 &PPC::CRBITRCRegClass, 292 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 293 &PPC::CRBITRCRegClass, 294 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 295 &PPC::CRBITRCRegClass, 296 297 &PPC::GPRCRegClass, 0 298 }; 299 300 // 64-bit Macho calling convention. 301 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = { 302 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 303 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 304 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 305 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 306 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 307 308 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 309 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 310 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 311 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 312 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 313 314 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 315 316 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 317 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 318 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 319 320 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 321 &PPC::CRBITRCRegClass, 322 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 323 &PPC::CRBITRCRegClass, 324 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 325 &PPC::CRBITRCRegClass, 326 327 &PPC::G8RCRegClass, 0 328 }; 329 330 if (Subtarget.isMachoABI()) 331 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses : 332 Macho32_CalleeSavedRegClasses; 333 334 // ELF 32. 335 return ELF32_CalleeSavedRegClasses; 336 } 337 338 // needsFP - Return true if the specified function should have a dedicated frame 339 // pointer register. This is true if the function has variable sized allocas or 340 // if frame pointer elimination is disabled. 341 // 342 static bool needsFP(const MachineFunction &MF) { 343 const MachineFrameInfo *MFI = MF.getFrameInfo(); 344 return NoFramePointerElim || MFI->hasVarSizedObjects() || 345 (PerformTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 346 } 347 348 static bool spillsCR(const MachineFunction &MF) { 349 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 350 return FuncInfo->isCRSpilled(); 351 } 352 353 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 354 BitVector Reserved(getNumRegs()); 355 Reserved.set(PPC::R0); 356 Reserved.set(PPC::R1); 357 Reserved.set(PPC::LR); 358 Reserved.set(PPC::LR8); 359 Reserved.set(PPC::RM); 360 361 // In Linux, r2 is reserved for the OS. 362 if (!Subtarget.isDarwin()) 363 Reserved.set(PPC::R2); 364 365 // On PPC64, r13 is the thread pointer. Never allocate this register. Note 366 // that this is over conservative, as it also prevents allocation of R31 when 367 // the FP is not needed. 368 if (Subtarget.isPPC64()) { 369 Reserved.set(PPC::R13); 370 Reserved.set(PPC::R31); 371 372 if (!EnableRegisterScavenging) 373 Reserved.set(PPC::R0); // FIXME (64-bit): Remove 374 375 Reserved.set(PPC::X0); 376 Reserved.set(PPC::X1); 377 Reserved.set(PPC::X13); 378 Reserved.set(PPC::X31); 379 } 380 381 if (needsFP(MF)) 382 Reserved.set(PPC::R31); 383 384 return Reserved; 385 } 386 387 //===----------------------------------------------------------------------===// 388 // Stack Frame Processing methods 389 //===----------------------------------------------------------------------===// 390 391 // hasFP - Return true if the specified function actually has a dedicated frame 392 // pointer register. This is true if the function needs a frame pointer and has 393 // a non-zero stack size. 394 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 395 const MachineFrameInfo *MFI = MF.getFrameInfo(); 396 return MFI->getStackSize() && needsFP(MF); 397 } 398 399 /// MustSaveLR - Return true if this function requires that we save the LR 400 /// register onto the stack in the prolog and restore it in the epilog of the 401 /// function. 402 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 403 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 404 405 // We need a save/restore of LR if there is any def of LR (which is 406 // defined by calls, including the PIC setup sequence), or if there is 407 // some use of the LR stack slot (e.g. for builtin_return_address). 408 // (LR comes in 32 and 64 bit versions.) 409 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 410 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 411 } 412 413 414 415 void PPCRegisterInfo:: 416 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 417 MachineBasicBlock::iterator I) const { 418 if (PerformTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) { 419 // Add (actually subtract) back the amount the callee popped on return. 420 if (int CalleeAmt = I->getOperand(1).getImm()) { 421 bool is64Bit = Subtarget.isPPC64(); 422 CalleeAmt *= -1; 423 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 424 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 425 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 426 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 427 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 428 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 429 430 if (isInt16(CalleeAmt)) { 431 BuildMI(MBB, I, TII.get(ADDIInstr), StackReg).addReg(StackReg). 432 addImm(CalleeAmt); 433 } else { 434 MachineBasicBlock::iterator MBBI = I; 435 BuildMI(MBB, MBBI, TII.get(LISInstr), TmpReg) 436 .addImm(CalleeAmt >> 16); 437 BuildMI(MBB, MBBI, TII.get(ORIInstr), TmpReg) 438 .addReg(TmpReg, false, false, true) 439 .addImm(CalleeAmt & 0xFFFF); 440 BuildMI(MBB, MBBI, TII.get(ADDInstr)) 441 .addReg(StackReg) 442 .addReg(StackReg) 443 .addReg(TmpReg); 444 } 445 } 446 } 447 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 448 MBB.erase(I); 449 } 450 451 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 452 /// register first and then a spilled callee-saved register if that fails. 453 static 454 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 455 const TargetRegisterClass *RC, int SPAdj) { 456 assert(RS && "Register scavenging must be on"); 457 unsigned Reg = RS->FindUnusedReg(RC, true); 458 // FIXME: move ARM callee-saved reg scan to target independent code, then 459 // search for already spilled CS register here. 460 if (Reg == 0) 461 Reg = RS->scavengeRegister(RC, II, SPAdj); 462 return Reg; 463 } 464 465 /// lowerDynamicAlloc - Generate the code for allocating an object in the 466 /// current frame. The sequence of code with be in the general form 467 /// 468 /// addi R0, SP, #frameSize ; get the address of the previous frame 469 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 470 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation 471 /// 472 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 473 int SPAdj, RegScavenger *RS) const { 474 // Get the instruction. 475 MachineInstr &MI = *II; 476 // Get the instruction's basic block. 477 MachineBasicBlock &MBB = *MI.getParent(); 478 // Get the basic block's function. 479 MachineFunction &MF = *MBB.getParent(); 480 // Get the frame info. 481 MachineFrameInfo *MFI = MF.getFrameInfo(); 482 // Determine whether 64-bit pointers are used. 483 bool LP64 = Subtarget.isPPC64(); 484 485 // Get the maximum call stack size. 486 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 487 // Get the total frame size. 488 unsigned FrameSize = MFI->getStackSize(); 489 490 // Get stack alignments. 491 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 492 unsigned MaxAlign = MFI->getMaxAlignment(); 493 assert(MaxAlign <= TargetAlign && 494 "Dynamic alloca with large aligns not supported"); 495 496 // Determine the previous frame's address. If FrameSize can't be 497 // represented as 16 bits or we need special alignment, then we load the 498 // previous frame's address from 0(SP). Why not do an addis of the hi? 499 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 500 // Constructing the constant and adding would take 3 instructions. 501 // Fortunately, a frame greater than 32K is rare. 502 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 503 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 504 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 505 506 // FIXME (64-bit): Use "findScratchRegister" 507 unsigned Reg; 508 if (EnableRegisterScavenging) 509 Reg = findScratchRegister(II, RS, RC, SPAdj); 510 else 511 Reg = PPC::R0; 512 513 if (MaxAlign < TargetAlign && isInt16(FrameSize)) { 514 BuildMI(MBB, II, TII.get(PPC::ADDI), Reg) 515 .addReg(PPC::R31) 516 .addImm(FrameSize); 517 } else if (LP64) { 518 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 519 BuildMI(MBB, II, TII.get(PPC::LD), Reg) 520 .addImm(0) 521 .addReg(PPC::X1); 522 else 523 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) 524 .addImm(0) 525 .addReg(PPC::X1); 526 } else { 527 BuildMI(MBB, II, TII.get(PPC::LWZ), Reg) 528 .addImm(0) 529 .addReg(PPC::R1); 530 } 531 532 // Grow the stack and update the stack pointer link, then determine the 533 // address of new allocated space. 534 if (LP64) { 535 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 536 BuildMI(MBB, II, TII.get(PPC::STDUX)) 537 .addReg(Reg, false, false, true) 538 .addReg(PPC::X1) 539 .addReg(MI.getOperand(1).getReg()); 540 else 541 BuildMI(MBB, II, TII.get(PPC::STDUX)) 542 .addReg(PPC::X0, false, false, true) 543 .addReg(PPC::X1) 544 .addReg(MI.getOperand(1).getReg()); 545 546 if (!MI.getOperand(1).isKill()) 547 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 548 .addReg(PPC::X1) 549 .addImm(maxCallFrameSize); 550 else 551 // Implicitly kill the register. 552 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 553 .addReg(PPC::X1) 554 .addImm(maxCallFrameSize) 555 .addReg(MI.getOperand(1).getReg(), false, true, true); 556 } else { 557 BuildMI(MBB, II, TII.get(PPC::STWUX)) 558 .addReg(Reg, false, false, true) 559 .addReg(PPC::R1) 560 .addReg(MI.getOperand(1).getReg()); 561 562 if (!MI.getOperand(1).isKill()) 563 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 564 .addReg(PPC::R1) 565 .addImm(maxCallFrameSize); 566 else 567 // Implicitly kill the register. 568 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 569 .addReg(PPC::R1) 570 .addImm(maxCallFrameSize) 571 .addReg(MI.getOperand(1).getReg(), false, true, true); 572 } 573 574 // Discard the DYNALLOC instruction. 575 MBB.erase(II); 576 } 577 578 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 579 /// reserving a whole register (R0), we scrounge for one here. This generates 580 /// code like this: 581 /// 582 /// mfcr rA ; Move the conditional register into GPR rA. 583 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 584 /// stw rA, FI ; Store rA to the frame. 585 /// 586 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 587 unsigned FrameIndex, int SPAdj, 588 RegScavenger *RS) const { 589 // Get the instruction. 590 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> 591 // Get the instruction's basic block. 592 MachineBasicBlock &MBB = *MI.getParent(); 593 594 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 595 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 596 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 597 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 598 599 // We need to store the CR in the low 4-bits of the saved value. First, issue 600 // an MFCR to save all of the CRBits. Add an implicit kill of the CR. 601 if (!MI.getOperand(0).isKill()) 602 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg); 603 else 604 // Implicitly kill the CR register. 605 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg) 606 .addReg(MI.getOperand(0).getReg(), false, true, true); 607 608 // If the saved register wasn't CR0, shift the bits left so that they are in 609 // CR0's slot. 610 unsigned SrcReg = MI.getOperand(0).getReg(); 611 if (SrcReg != PPC::CR0) 612 // rlwinm rA, rA, ShiftBits, 0, 31. 613 BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg) 614 .addReg(Reg, false, false, true) 615 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) 616 .addImm(0) 617 .addImm(31); 618 619 addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW)) 620 .addReg(Reg, false, false, MI.getOperand(1).getImm()), 621 FrameIndex); 622 623 // Discard the pseudo instruction. 624 MBB.erase(II); 625 } 626 627 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 628 int SPAdj, RegScavenger *RS) const { 629 assert(SPAdj == 0 && "Unexpected"); 630 631 // Get the instruction. 632 MachineInstr &MI = *II; 633 // Get the instruction's basic block. 634 MachineBasicBlock &MBB = *MI.getParent(); 635 // Get the basic block's function. 636 MachineFunction &MF = *MBB.getParent(); 637 // Get the frame info. 638 MachineFrameInfo *MFI = MF.getFrameInfo(); 639 640 // Find out which operand is the frame index. 641 unsigned FIOperandNo = 0; 642 while (!MI.getOperand(FIOperandNo).isFI()) { 643 ++FIOperandNo; 644 assert(FIOperandNo != MI.getNumOperands() && 645 "Instr doesn't have FrameIndex operand!"); 646 } 647 // Take into account whether it's an add or mem instruction 648 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 649 if (MI.getOpcode() == TargetInstrInfo::INLINEASM) 650 OffsetOperandNo = FIOperandNo-1; 651 652 // Get the frame index. 653 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 654 655 // Get the frame pointer save index. Users of this index are primarily 656 // DYNALLOC instructions. 657 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 658 int FPSI = FI->getFramePointerSaveIndex(); 659 // Get the instruction opcode. 660 unsigned OpC = MI.getOpcode(); 661 662 // Special case for dynamic alloca. 663 if (FPSI && FrameIndex == FPSI && 664 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 665 lowerDynamicAlloc(II, SPAdj, RS); 666 return; 667 } 668 669 // Special case for pseudo-op SPILL_CR. 670 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default. 671 if (OpC == PPC::SPILL_CR) { 672 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 673 return; 674 } 675 676 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 677 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, 678 false); 679 680 // Figure out if the offset in the instruction is shifted right two bits. This 681 // is true for instructions like "STD", which the machine implicitly adds two 682 // low zeros to. 683 bool isIXAddr = false; 684 switch (OpC) { 685 case PPC::LWA: 686 case PPC::LD: 687 case PPC::STD: 688 case PPC::STD_32: 689 isIXAddr = true; 690 break; 691 } 692 693 // Now add the frame object offset to the offset from r1. 694 int Offset = MFI->getObjectOffset(FrameIndex); 695 if (!isIXAddr) 696 Offset += MI.getOperand(OffsetOperandNo).getImm(); 697 else 698 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 699 700 // If we're not using a Frame Pointer that has been set to the value of the 701 // SP before having the stack size subtracted from it, then add the stack size 702 // to Offset to get the correct offset. 703 Offset += MFI->getStackSize(); 704 705 // If we can, encode the offset directly into the instruction. If this is a 706 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 707 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 708 // clear can be encoded. This is extremely uncommon, because normally you 709 // only "std" to a stack slot that is at least 4-byte aligned, but it can 710 // happen in invalid code. 711 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 712 if (isIXAddr) 713 Offset >>= 2; // The actual encoded value has the low two bits zero. 714 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 715 return; 716 } 717 718 // The offset doesn't fit into a single register, scavenge one to build the 719 // offset in. 720 // FIXME: figure out what SPAdj is doing here. 721 722 // FIXME (64-bit): Use "findScratchRegister". 723 unsigned SReg; 724 if (EnableRegisterScavenging) 725 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); 726 else 727 SReg = PPC::R0; 728 729 // Insert a set of rA with the full offset value before the ld, st, or add 730 BuildMI(MBB, II, TII.get(PPC::LIS), SReg) 731 .addImm(Offset >> 16); 732 BuildMI(MBB, II, TII.get(PPC::ORI), SReg) 733 .addReg(SReg, false, false, true) 734 .addImm(Offset); 735 736 // Convert into indexed form of the instruction: 737 // 738 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 739 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 740 unsigned OperandBase; 741 742 if (OpC != TargetInstrInfo::INLINEASM) { 743 assert(ImmToIdxMap.count(OpC) && 744 "No indexed form of load or store available!"); 745 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 746 MI.setDesc(TII.get(NewOpcode)); 747 OperandBase = 1; 748 } else { 749 OperandBase = OffsetOperandNo; 750 } 751 752 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 753 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 754 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); 755 } 756 757 /// VRRegNo - Map from a numbered VR register to its enum value. 758 /// 759 static const unsigned short VRRegNo[] = { 760 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 761 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 762 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 763 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 764 }; 765 766 /// RemoveVRSaveCode - We have found that this function does not need any code 767 /// to manipulate the VRSAVE register, even though it uses vector registers. 768 /// This can happen when the only registers used are known to be live in or out 769 /// of the function. Remove all of the VRSAVE related code from the function. 770 static void RemoveVRSaveCode(MachineInstr *MI) { 771 MachineBasicBlock *Entry = MI->getParent(); 772 MachineFunction *MF = Entry->getParent(); 773 774 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 775 MachineBasicBlock::iterator MBBI = MI; 776 ++MBBI; 777 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 778 MBBI->eraseFromParent(); 779 780 bool RemovedAllMTVRSAVEs = true; 781 // See if we can find and remove the MTVRSAVE instruction from all of the 782 // epilog blocks. 783 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 784 // If last instruction is a return instruction, add an epilogue 785 if (!I->empty() && I->back().getDesc().isReturn()) { 786 bool FoundIt = false; 787 for (MBBI = I->end(); MBBI != I->begin(); ) { 788 --MBBI; 789 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 790 MBBI->eraseFromParent(); // remove it. 791 FoundIt = true; 792 break; 793 } 794 } 795 RemovedAllMTVRSAVEs &= FoundIt; 796 } 797 } 798 799 // If we found and removed all MTVRSAVE instructions, remove the read of 800 // VRSAVE as well. 801 if (RemovedAllMTVRSAVEs) { 802 MBBI = MI; 803 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 804 --MBBI; 805 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 806 MBBI->eraseFromParent(); 807 } 808 809 // Finally, nuke the UPDATE_VRSAVE. 810 MI->eraseFromParent(); 811 } 812 813 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 814 // instruction selector. Based on the vector registers that have been used, 815 // transform this into the appropriate ORI instruction. 816 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 817 MachineFunction *MF = MI->getParent()->getParent(); 818 819 unsigned UsedRegMask = 0; 820 for (unsigned i = 0; i != 32; ++i) 821 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 822 UsedRegMask |= 1 << (31-i); 823 824 // Live in and live out values already must be in the mask, so don't bother 825 // marking them. 826 for (MachineRegisterInfo::livein_iterator 827 I = MF->getRegInfo().livein_begin(), 828 E = MF->getRegInfo().livein_end(); I != E; ++I) { 829 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 830 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 831 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 832 } 833 for (MachineRegisterInfo::liveout_iterator 834 I = MF->getRegInfo().liveout_begin(), 835 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 836 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 837 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 838 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 839 } 840 841 // If no registers are used, turn this into a copy. 842 if (UsedRegMask == 0) { 843 // Remove all VRSAVE code. 844 RemoveVRSaveCode(MI); 845 return; 846 } 847 848 unsigned SrcReg = MI->getOperand(1).getReg(); 849 unsigned DstReg = MI->getOperand(0).getReg(); 850 851 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 852 if (DstReg != SrcReg) 853 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 854 .addReg(SrcReg) 855 .addImm(UsedRegMask); 856 else 857 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 858 .addReg(SrcReg, false, false, true) 859 .addImm(UsedRegMask); 860 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 861 if (DstReg != SrcReg) 862 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 863 .addReg(SrcReg) 864 .addImm(UsedRegMask >> 16); 865 else 866 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 867 .addReg(SrcReg, false, false, true) 868 .addImm(UsedRegMask >> 16); 869 } else { 870 if (DstReg != SrcReg) 871 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 872 .addReg(SrcReg) 873 .addImm(UsedRegMask >> 16); 874 else 875 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 876 .addReg(SrcReg, false, false, true) 877 .addImm(UsedRegMask >> 16); 878 879 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 880 .addReg(DstReg, false, false, true) 881 .addImm(UsedRegMask & 0xFFFF); 882 } 883 884 // Remove the old UPDATE_VRSAVE instruction. 885 MI->eraseFromParent(); 886 } 887 888 /// determineFrameLayout - Determine the size of the frame and maximum call 889 /// frame size. 890 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 891 MachineFrameInfo *MFI = MF.getFrameInfo(); 892 893 // Get the number of bytes to allocate from the FrameInfo 894 unsigned FrameSize = MFI->getStackSize(); 895 896 // Get the alignments provided by the target, and the maximum alignment 897 // (if any) of the fixed frame objects. 898 unsigned MaxAlign = MFI->getMaxAlignment(); 899 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 900 unsigned AlignMask = TargetAlign - 1; // 901 902 // If we are a leaf function, and use up to 224 bytes of stack space, 903 // don't have a frame pointer, calls, or dynamic alloca then we do not need 904 // to adjust the stack pointer (we fit in the Red Zone). 905 if (!DisableRedZone && 906 FrameSize <= 224 && // Fits in red zone. 907 !MFI->hasVarSizedObjects() && // No dynamic alloca. 908 !MFI->hasCalls() && // No calls. 909 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 910 // No need for frame 911 MFI->setStackSize(0); 912 return; 913 } 914 915 // Get the maximum call frame size of all the calls. 916 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 917 918 // Maximum call frame needs to be at least big enough for linkage and 8 args. 919 unsigned minCallFrameSize = 920 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), 921 Subtarget.isMachoABI()); 922 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 923 924 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 925 // that allocations will be aligned. 926 if (MFI->hasVarSizedObjects()) 927 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 928 929 // Update maximum call frame size. 930 MFI->setMaxCallFrameSize(maxCallFrameSize); 931 932 // Include call frame size in total. 933 FrameSize += maxCallFrameSize; 934 935 // Make sure the frame is aligned. 936 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 937 938 // Update frame info. 939 MFI->setStackSize(FrameSize); 940 } 941 942 void 943 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 944 RegScavenger *RS) const { 945 // Save and clear the LR state. 946 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 947 unsigned LR = getRARegister(); 948 FI->setMustSaveLR(MustSaveLR(MF, LR)); 949 MF.getRegInfo().setPhysRegUnused(LR); 950 951 // Save R31 if necessary 952 int FPSI = FI->getFramePointerSaveIndex(); 953 bool IsPPC64 = Subtarget.isPPC64(); 954 bool IsELF32_ABI = Subtarget.isELF32_ABI(); 955 bool IsMachoABI = Subtarget.isMachoABI(); 956 MachineFrameInfo *MFI = MF.getFrameInfo(); 957 958 // If the frame pointer save index hasn't been defined yet. 959 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) && 960 IsELF32_ABI) { 961 // Find out what the fix offset of the frame pointer save area. 962 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, 963 IsMachoABI); 964 // Allocate the frame index for frame pointer save area. 965 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 966 // Save the result. 967 FI->setFramePointerSaveIndex(FPSI); 968 } 969 970 // Reserve stack space to move the linkage area to in case of a tail call. 971 int TCSPDelta = 0; 972 if (PerformTailCallOpt && (TCSPDelta=FI->getTailCallSPDelta()) < 0) { 973 int AddFPOffsetAmount = IsELF32_ABI ? -4 : 0; 974 MF.getFrameInfo()->CreateFixedObject( -1 * TCSPDelta, 975 AddFPOffsetAmount + TCSPDelta); 976 } 977 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 978 // a large stack, which will require scavenging a register to materialize a 979 // large offset. 980 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 981 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 982 // r0 for now. 983 984 if (EnableRegisterScavenging) // FIXME (64-bit): Enable. 985 if (needsFP(MF) || spillsCR(MF)) { 986 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 987 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 988 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC; 989 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 990 RC->getAlignment())); 991 } 992 } 993 994 void 995 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 996 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 997 MachineBasicBlock::iterator MBBI = MBB.begin(); 998 MachineFrameInfo *MFI = MF.getFrameInfo(); 999 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 1000 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) || 1001 !MF.getFunction()->doesNotThrow() || 1002 UnwindTablesMandatory; 1003 1004 // Prepare for frame info. 1005 unsigned FrameLabelId = 0; 1006 1007 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 1008 // process it. 1009 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 1010 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 1011 HandleVRSaveUpdate(MBBI, TII); 1012 break; 1013 } 1014 } 1015 1016 // Move MBBI back to the beginning of the function. 1017 MBBI = MBB.begin(); 1018 1019 // Work out frame sizes. 1020 determineFrameLayout(MF); 1021 unsigned FrameSize = MFI->getStackSize(); 1022 1023 int NegFrameSize = -FrameSize; 1024 1025 // Get processor type. 1026 bool IsPPC64 = Subtarget.isPPC64(); 1027 // Get operating system 1028 bool IsMachoABI = Subtarget.isMachoABI(); 1029 // Check if the link register (LR) must be saved. 1030 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1031 bool MustSaveLR = FI->mustSaveLR(); 1032 // Do we have a frame pointer for this function? 1033 bool HasFP = hasFP(MF) && FrameSize; 1034 1035 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 1036 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 1037 1038 if (IsPPC64) { 1039 if (MustSaveLR) 1040 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); 1041 1042 if (HasFP) 1043 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 1044 .addReg(PPC::X31) 1045 .addImm(FPOffset/4) 1046 .addReg(PPC::X1); 1047 1048 if (MustSaveLR) 1049 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 1050 .addReg(PPC::X0) 1051 .addImm(LROffset / 4) 1052 .addReg(PPC::X1); 1053 } else { 1054 if (MustSaveLR) 1055 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); 1056 1057 if (HasFP) 1058 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 1059 .addReg(PPC::R31) 1060 .addImm(FPOffset) 1061 .addReg(PPC::R1); 1062 1063 if (MustSaveLR) 1064 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 1065 .addReg(PPC::R0) 1066 .addImm(LROffset) 1067 .addReg(PPC::R1); 1068 } 1069 1070 // Skip if a leaf routine. 1071 if (!FrameSize) return; 1072 1073 // Get stack alignments. 1074 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1075 unsigned MaxAlign = MFI->getMaxAlignment(); 1076 1077 if (needsFrameMoves) { 1078 // Mark effective beginning of when frame pointer becomes valid. 1079 FrameLabelId = MMI->NextLabelID(); 1080 BuildMI(MBB, MBBI, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId); 1081 } 1082 1083 // Adjust stack pointer: r1 += NegFrameSize. 1084 // If there is a preferred stack alignment, align R1 now 1085 if (!IsPPC64) { 1086 // PPC32. 1087 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1088 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 1089 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 1090 1091 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) 1092 .addReg(PPC::R1) 1093 .addImm(0) 1094 .addImm(32 - Log2_32(MaxAlign)) 1095 .addImm(31); 1096 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0) 1097 .addReg(PPC::R0, false, false, true) 1098 .addImm(NegFrameSize); 1099 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 1100 .addReg(PPC::R1) 1101 .addReg(PPC::R1) 1102 .addReg(PPC::R0); 1103 } else if (isInt16(NegFrameSize)) { 1104 BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1) 1105 .addReg(PPC::R1) 1106 .addImm(NegFrameSize) 1107 .addReg(PPC::R1); 1108 } else { 1109 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0) 1110 .addImm(NegFrameSize >> 16); 1111 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0) 1112 .addReg(PPC::R0, false, false, true) 1113 .addImm(NegFrameSize & 0xFFFF); 1114 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 1115 .addReg(PPC::R1) 1116 .addReg(PPC::R1) 1117 .addReg(PPC::R0); 1118 } 1119 } else { // PPC64. 1120 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1121 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 1122 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 1123 1124 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) 1125 .addReg(PPC::X1) 1126 .addImm(0) 1127 .addImm(64 - Log2_32(MaxAlign)); 1128 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0) 1129 .addReg(PPC::X0) 1130 .addImm(NegFrameSize); 1131 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 1132 .addReg(PPC::X1) 1133 .addReg(PPC::X1) 1134 .addReg(PPC::X0); 1135 } else if (isInt16(NegFrameSize)) { 1136 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) 1137 .addReg(PPC::X1) 1138 .addImm(NegFrameSize / 4) 1139 .addReg(PPC::X1); 1140 } else { 1141 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0) 1142 .addImm(NegFrameSize >> 16); 1143 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0) 1144 .addReg(PPC::X0, false, false, true) 1145 .addImm(NegFrameSize & 0xFFFF); 1146 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 1147 .addReg(PPC::X1) 1148 .addReg(PPC::X1) 1149 .addReg(PPC::X0); 1150 } 1151 } 1152 1153 if (needsFrameMoves) { 1154 std::vector<MachineMove> &Moves = MMI->getFrameMoves(); 1155 1156 if (NegFrameSize) { 1157 // Show update of SP. 1158 MachineLocation SPDst(MachineLocation::VirtualFP); 1159 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 1160 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); 1161 } else { 1162 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31); 1163 Moves.push_back(MachineMove(FrameLabelId, SP, SP)); 1164 } 1165 1166 if (HasFP) { 1167 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 1168 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31); 1169 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); 1170 } 1171 1172 // Add callee saved registers to move list. 1173 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1174 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1175 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1176 unsigned Reg = CSI[I].getReg(); 1177 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 1178 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 1179 MachineLocation CSSrc(Reg); 1180 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); 1181 } 1182 1183 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 1184 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR); 1185 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc)); 1186 1187 // Mark effective beginning of when frame pointer is ready. 1188 unsigned ReadyLabelId = MMI->NextLabelID(); 1189 BuildMI(MBB, MBBI, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId); 1190 1191 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : 1192 (IsPPC64 ? PPC::X1 : PPC::R1)); 1193 MachineLocation FPSrc(MachineLocation::VirtualFP); 1194 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); 1195 } 1196 1197 // If there is a frame pointer, copy R1 into R31 1198 if (HasFP) { 1199 if (!IsPPC64) { 1200 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31) 1201 .addReg(PPC::R1) 1202 .addReg(PPC::R1); 1203 } else { 1204 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31) 1205 .addReg(PPC::X1) 1206 .addReg(PPC::X1); 1207 } 1208 } 1209 } 1210 1211 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 1212 MachineBasicBlock &MBB) const { 1213 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1214 unsigned RetOpcode = MBBI->getOpcode(); 1215 1216 assert( (RetOpcode == PPC::BLR || 1217 RetOpcode == PPC::TCRETURNri || 1218 RetOpcode == PPC::TCRETURNdi || 1219 RetOpcode == PPC::TCRETURNai || 1220 RetOpcode == PPC::TCRETURNri8 || 1221 RetOpcode == PPC::TCRETURNdi8 || 1222 RetOpcode == PPC::TCRETURNai8) && 1223 "Can only insert epilog into returning blocks"); 1224 1225 // Get alignment info so we know how to restore r1 1226 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1227 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1228 unsigned MaxAlign = MFI->getMaxAlignment(); 1229 1230 // Get the number of bytes allocated from the FrameInfo. 1231 int FrameSize = MFI->getStackSize(); 1232 1233 // Get processor type. 1234 bool IsPPC64 = Subtarget.isPPC64(); 1235 // Get operating system 1236 bool IsMachoABI = Subtarget.isMachoABI(); 1237 // Check if the link register (LR) has been saved. 1238 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1239 bool MustSaveLR = FI->mustSaveLR(); 1240 // Do we have a frame pointer for this function? 1241 bool HasFP = hasFP(MF) && FrameSize; 1242 1243 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 1244 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 1245 1246 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 1247 RetOpcode == PPC::TCRETURNdi || 1248 RetOpcode == PPC::TCRETURNai || 1249 RetOpcode == PPC::TCRETURNri8 || 1250 RetOpcode == PPC::TCRETURNdi8 || 1251 RetOpcode == PPC::TCRETURNai8; 1252 1253 if (UsesTCRet) { 1254 int MaxTCRetDelta = FI->getTailCallSPDelta(); 1255 MachineOperand &StackAdjust = MBBI->getOperand(1); 1256 assert(StackAdjust.isImm() && "Expecting immediate value."); 1257 // Adjust stack pointer. 1258 int StackAdj = StackAdjust.getImm(); 1259 int Delta = StackAdj - MaxTCRetDelta; 1260 assert((Delta >= 0) && "Delta must be positive"); 1261 if (MaxTCRetDelta>0) 1262 FrameSize += (StackAdj +Delta); 1263 else 1264 FrameSize += StackAdj; 1265 } 1266 1267 if (FrameSize) { 1268 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 1269 // on entry to the function. Add this offset back now. 1270 if (!IsPPC64) { 1271 // If this function contained a fastcc call and PerformTailCallOpt is 1272 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 1273 // call which invalidates the stack pointer value in SP(0). So we use the 1274 // value of R31 in this case. 1275 if (FI->hasFastCall() && isInt16(FrameSize)) { 1276 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 1277 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) 1278 .addReg(PPC::R31).addImm(FrameSize); 1279 } else if(FI->hasFastCall()) { 1280 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0) 1281 .addImm(FrameSize >> 16); 1282 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0) 1283 .addReg(PPC::R0, false, false, true) 1284 .addImm(FrameSize & 0xFFFF); 1285 BuildMI(MBB, MBBI, TII.get(PPC::ADD4)) 1286 .addReg(PPC::R1) 1287 .addReg(PPC::R31) 1288 .addReg(PPC::R0); 1289 } else if (isInt16(FrameSize) && 1290 (!ALIGN_STACK || TargetAlign >= MaxAlign) && 1291 !MFI->hasVarSizedObjects()) { 1292 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) 1293 .addReg(PPC::R1).addImm(FrameSize); 1294 } else { 1295 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); 1296 } 1297 } else { 1298 if (FI->hasFastCall() && isInt16(FrameSize)) { 1299 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 1300 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) 1301 .addReg(PPC::X31).addImm(FrameSize); 1302 } else if(FI->hasFastCall()) { 1303 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0) 1304 .addImm(FrameSize >> 16); 1305 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0) 1306 .addReg(PPC::X0, false, false, true) 1307 .addImm(FrameSize & 0xFFFF); 1308 BuildMI(MBB, MBBI, TII.get(PPC::ADD8)) 1309 .addReg(PPC::X1) 1310 .addReg(PPC::X31) 1311 .addReg(PPC::X0); 1312 } else if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1313 !MFI->hasVarSizedObjects()) { 1314 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) 1315 .addReg(PPC::X1).addImm(FrameSize); 1316 } else { 1317 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); 1318 } 1319 } 1320 } 1321 1322 if (IsPPC64) { 1323 if (MustSaveLR) 1324 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) 1325 .addImm(LROffset/4).addReg(PPC::X1); 1326 1327 if (HasFP) 1328 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) 1329 .addImm(FPOffset/4).addReg(PPC::X1); 1330 1331 if (MustSaveLR) 1332 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); 1333 } else { 1334 if (MustSaveLR) 1335 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) 1336 .addImm(LROffset).addReg(PPC::R1); 1337 1338 if (HasFP) 1339 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) 1340 .addImm(FPOffset).addReg(PPC::R1); 1341 1342 if (MustSaveLR) 1343 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); 1344 } 1345 1346 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 1347 // call optimization 1348 if (PerformTailCallOpt && RetOpcode == PPC::BLR && 1349 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 1350 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1351 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 1352 unsigned StackReg = IsPPC64 ? PPC::X1 : PPC::R1; 1353 unsigned FPReg = IsPPC64 ? PPC::X31 : PPC::R31; 1354 unsigned TmpReg = IsPPC64 ? PPC::X0 : PPC::R0; 1355 unsigned ADDIInstr = IsPPC64 ? PPC::ADDI8 : PPC::ADDI; 1356 unsigned ADDInstr = IsPPC64 ? PPC::ADD8 : PPC::ADD4; 1357 unsigned LISInstr = IsPPC64 ? PPC::LIS8 : PPC::LIS; 1358 unsigned ORIInstr = IsPPC64 ? PPC::ORI8 : PPC::ORI; 1359 1360 if (CallerAllocatedAmt && isInt16(CallerAllocatedAmt)) { 1361 BuildMI(MBB, MBBI, TII.get(ADDIInstr), StackReg) 1362 .addReg(StackReg).addImm(CallerAllocatedAmt); 1363 } else { 1364 BuildMI(MBB, MBBI, TII.get(LISInstr), TmpReg) 1365 .addImm(CallerAllocatedAmt >> 16); 1366 BuildMI(MBB, MBBI, TII.get(ORIInstr), TmpReg) 1367 .addReg(TmpReg, false, false, true) 1368 .addImm(CallerAllocatedAmt & 0xFFFF); 1369 BuildMI(MBB, MBBI, TII.get(ADDInstr)) 1370 .addReg(StackReg) 1371 .addReg(FPReg) 1372 .addReg(TmpReg); 1373 } 1374 } else if (RetOpcode == PPC::TCRETURNdi) { 1375 MBBI = prior(MBB.end()); 1376 MachineOperand &JumpTarget = MBBI->getOperand(0); 1377 BuildMI(MBB, MBBI, TII.get(PPC::TAILB)). 1378 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1379 } else if (RetOpcode == PPC::TCRETURNri) { 1380 MBBI = prior(MBB.end()); 1381 MachineOperand &JumpTarget = MBBI->getOperand(0); 1382 assert(JumpTarget.isReg() && "Expecting register operand."); 1383 BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR)); 1384 } else if (RetOpcode == PPC::TCRETURNai) { 1385 MBBI = prior(MBB.end()); 1386 MachineOperand &JumpTarget = MBBI->getOperand(0); 1387 BuildMI(MBB, MBBI, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 1388 } else if (RetOpcode == PPC::TCRETURNdi8) { 1389 MBBI = prior(MBB.end()); 1390 MachineOperand &JumpTarget = MBBI->getOperand(0); 1391 BuildMI(MBB, MBBI, TII.get(PPC::TAILB8)). 1392 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1393 } else if (RetOpcode == PPC::TCRETURNri8) { 1394 MBBI = prior(MBB.end()); 1395 MachineOperand &JumpTarget = MBBI->getOperand(0); 1396 assert(JumpTarget.isReg() && "Expecting register operand."); 1397 BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR8)); 1398 } else if (RetOpcode == PPC::TCRETURNai8) { 1399 MBBI = prior(MBB.end()); 1400 MachineOperand &JumpTarget = MBBI->getOperand(0); 1401 BuildMI(MBB, MBBI, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 1402 } 1403 } 1404 1405 unsigned PPCRegisterInfo::getRARegister() const { 1406 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1407 } 1408 1409 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1410 if (!Subtarget.isPPC64()) 1411 return hasFP(MF) ? PPC::R31 : PPC::R1; 1412 else 1413 return hasFP(MF) ? PPC::X31 : PPC::X1; 1414 } 1415 1416 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1417 const { 1418 // Initial state of the frame pointer is R1. 1419 MachineLocation Dst(MachineLocation::VirtualFP); 1420 MachineLocation Src(PPC::R1, 0); 1421 Moves.push_back(MachineMove(0, Dst, Src)); 1422 } 1423 1424 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 1425 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 1426 } 1427 1428 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 1429 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 1430 } 1431 1432 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1433 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 1434 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 1435 } 1436 1437 #include "PPCGenRegisterInfo.inc" 1438 1439