1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPCRegisterInfo.h" 17 #include "PPC.h" 18 #include "PPCFrameLowering.h" 19 #include "PPCInstrBuilder.h" 20 #include "PPCMachineFunctionInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineModuleInfo.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/RegisterScavenging.h" 30 #include "llvm/CodeGen/ValueTypes.h" 31 #include "llvm/IR/CallingConv.h" 32 #include "llvm/IR/Constants.h" 33 #include "llvm/IR/Function.h" 34 #include "llvm/IR/Type.h" 35 #include "llvm/Support/CommandLine.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/MathExtras.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include "llvm/Target/TargetFrameLowering.h" 41 #include "llvm/Target/TargetInstrInfo.h" 42 #include "llvm/Target/TargetMachine.h" 43 #include "llvm/Target/TargetOptions.h" 44 #include <cstdlib> 45 46 #define GET_REGINFO_TARGET_DESC 47 #include "PPCGenRegisterInfo.inc" 48 49 using namespace llvm; 50 51 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 52 const TargetInstrInfo &tii) 53 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 54 ST.isPPC64() ? 0 : 1, 55 ST.isPPC64() ? 0 : 1), 56 Subtarget(ST), TII(tii) { 57 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 58 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 59 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 60 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 61 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 62 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 63 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 64 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 65 66 // 64-bit 67 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 68 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 69 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 70 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 71 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 72 } 73 74 /// getPointerRegClass - Return the register class to use to hold pointers. 75 /// This is used for addressing modes. 76 const TargetRegisterClass * 77 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 78 const { 79 if (Kind == 1) { 80 if (Subtarget.isPPC64()) 81 return &PPC::G8RC_NOX0RegClass; 82 return &PPC::GPRC_NOR0RegClass; 83 } 84 85 if (Subtarget.isPPC64()) 86 return &PPC::G8RCRegClass; 87 return &PPC::GPRCRegClass; 88 } 89 90 const uint16_t* 91 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 92 if (Subtarget.isDarwinABI()) 93 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList : 94 CSR_Darwin32_SaveList; 95 96 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList; 97 } 98 99 const uint32_t* 100 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 101 if (Subtarget.isDarwinABI()) 102 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask : 103 CSR_Darwin32_RegMask; 104 105 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask; 106 } 107 108 const uint32_t* 109 PPCRegisterInfo::getNoPreservedMask() const { 110 // The naming here is inverted: The CSR_NoRegs_Altivec has the 111 // Altivec registers masked so that they're not saved and restored around 112 // instructions with this preserved mask. 113 114 if (!Subtarget.hasAltivec()) 115 return CSR_NoRegs_Altivec_RegMask; 116 117 if (Subtarget.isDarwin()) 118 return CSR_NoRegs_Darwin_RegMask; 119 return CSR_NoRegs_RegMask; 120 } 121 122 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 123 BitVector Reserved(getNumRegs()); 124 const PPCFrameLowering *PPCFI = 125 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 126 127 // The ZERO register is not really a register, but the representation of r0 128 // when used in instructions that treat r0 as the constant 0. 129 Reserved.set(PPC::ZERO); 130 Reserved.set(PPC::ZERO8); 131 132 // The FP register is also not really a register, but is the representation 133 // of the frame pointer register used by ISD::FRAMEADDR. 134 Reserved.set(PPC::FP); 135 Reserved.set(PPC::FP8); 136 137 Reserved.set(PPC::R1); 138 Reserved.set(PPC::LR); 139 Reserved.set(PPC::LR8); 140 Reserved.set(PPC::RM); 141 142 // The SVR4 ABI reserves r2 and r13 143 if (Subtarget.isSVR4ABI()) { 144 Reserved.set(PPC::R2); // System-reserved register 145 Reserved.set(PPC::R13); // Small Data Area pointer register 146 } 147 148 // On PPC64, r13 is the thread pointer. Never allocate this register. 149 if (Subtarget.isPPC64()) { 150 Reserved.set(PPC::R13); 151 152 Reserved.set(PPC::X1); 153 Reserved.set(PPC::X13); 154 155 if (PPCFI->needsFP(MF)) 156 Reserved.set(PPC::X31); 157 158 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 159 if (Subtarget.isSVR4ABI()) { 160 Reserved.set(PPC::X2); 161 } 162 } 163 164 if (PPCFI->needsFP(MF)) 165 Reserved.set(PPC::R31); 166 167 return Reserved; 168 } 169 170 unsigned 171 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 172 MachineFunction &MF) const { 173 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 174 const unsigned DefaultSafety = 1; 175 176 switch (RC->getID()) { 177 default: 178 return 0; 179 case PPC::G8RC_NOX0RegClassID: 180 case PPC::GPRC_NOR0RegClassID: 181 case PPC::G8RCRegClassID: 182 case PPC::GPRCRegClassID: { 183 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 184 return 32 - FP - DefaultSafety; 185 } 186 case PPC::F8RCRegClassID: 187 case PPC::F4RCRegClassID: 188 case PPC::VRRCRegClassID: 189 return 32 - DefaultSafety; 190 case PPC::CRRCRegClassID: 191 return 8 - DefaultSafety; 192 } 193 } 194 195 //===----------------------------------------------------------------------===// 196 // Stack Frame Processing methods 197 //===----------------------------------------------------------------------===// 198 199 /// lowerDynamicAlloc - Generate the code for allocating an object in the 200 /// current frame. The sequence of code with be in the general form 201 /// 202 /// addi R0, SP, \#frameSize ; get the address of the previous frame 203 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 204 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 205 /// 206 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 207 // Get the instruction. 208 MachineInstr &MI = *II; 209 // Get the instruction's basic block. 210 MachineBasicBlock &MBB = *MI.getParent(); 211 // Get the basic block's function. 212 MachineFunction &MF = *MBB.getParent(); 213 // Get the frame info. 214 MachineFrameInfo *MFI = MF.getFrameInfo(); 215 // Determine whether 64-bit pointers are used. 216 bool LP64 = Subtarget.isPPC64(); 217 DebugLoc dl = MI.getDebugLoc(); 218 219 // Get the maximum call stack size. 220 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 221 // Get the total frame size. 222 unsigned FrameSize = MFI->getStackSize(); 223 224 // Get stack alignments. 225 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 226 unsigned MaxAlign = MFI->getMaxAlignment(); 227 if (MaxAlign > TargetAlign) 228 report_fatal_error("Dynamic alloca with large aligns not supported"); 229 230 // Determine the previous frame's address. If FrameSize can't be 231 // represented as 16 bits or we need special alignment, then we load the 232 // previous frame's address from 0(SP). Why not do an addis of the hi? 233 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 234 // Constructing the constant and adding would take 3 instructions. 235 // Fortunately, a frame greater than 32K is rare. 236 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 237 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 238 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 239 240 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 241 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 242 .addReg(PPC::R31) 243 .addImm(FrameSize); 244 } else if (LP64) { 245 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 246 .addImm(0) 247 .addReg(PPC::X1); 248 } else { 249 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 250 .addImm(0) 251 .addReg(PPC::R1); 252 } 253 254 // Grow the stack and update the stack pointer link, then determine the 255 // address of new allocated space. 256 if (LP64) { 257 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 258 .addReg(Reg, RegState::Kill) 259 .addReg(PPC::X1) 260 .addReg(MI.getOperand(1).getReg()); 261 if (!MI.getOperand(1).isKill()) 262 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 263 .addReg(PPC::X1) 264 .addImm(maxCallFrameSize); 265 else 266 // Implicitly kill the register. 267 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 268 .addReg(PPC::X1) 269 .addImm(maxCallFrameSize) 270 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 271 } else { 272 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 273 .addReg(Reg, RegState::Kill) 274 .addReg(PPC::R1) 275 .addReg(MI.getOperand(1).getReg()); 276 277 if (!MI.getOperand(1).isKill()) 278 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 279 .addReg(PPC::R1) 280 .addImm(maxCallFrameSize); 281 else 282 // Implicitly kill the register. 283 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 284 .addReg(PPC::R1) 285 .addImm(maxCallFrameSize) 286 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 287 } 288 289 // Discard the DYNALLOC instruction. 290 MBB.erase(II); 291 } 292 293 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 294 /// reserving a whole register (R0), we scrounge for one here. This generates 295 /// code like this: 296 /// 297 /// mfcr rA ; Move the conditional register into GPR rA. 298 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 299 /// stw rA, FI ; Store rA to the frame. 300 /// 301 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 302 unsigned FrameIndex) const { 303 // Get the instruction. 304 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 305 // Get the instruction's basic block. 306 MachineBasicBlock &MBB = *MI.getParent(); 307 MachineFunction &MF = *MBB.getParent(); 308 DebugLoc dl = MI.getDebugLoc(); 309 310 bool LP64 = Subtarget.isPPC64(); 311 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 312 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 313 314 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 315 unsigned SrcReg = MI.getOperand(0).getReg(); 316 317 // We need to store the CR in the low 4-bits of the saved value. First, issue 318 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 319 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg) 320 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 321 322 // If the saved register wasn't CR0, shift the bits left so that they are in 323 // CR0's slot. 324 if (SrcReg != PPC::CR0) { 325 unsigned Reg1 = Reg; 326 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 327 328 // rlwinm rA, rA, ShiftBits, 0, 31. 329 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 330 .addReg(Reg1, RegState::Kill) 331 .addImm(getEncodingValue(SrcReg) * 4) 332 .addImm(0) 333 .addImm(31); 334 } 335 336 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 337 .addReg(Reg, RegState::Kill), 338 FrameIndex); 339 340 // Discard the pseudo instruction. 341 MBB.erase(II); 342 } 343 344 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 345 unsigned FrameIndex) const { 346 // Get the instruction. 347 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 348 // Get the instruction's basic block. 349 MachineBasicBlock &MBB = *MI.getParent(); 350 MachineFunction &MF = *MBB.getParent(); 351 DebugLoc dl = MI.getDebugLoc(); 352 353 bool LP64 = Subtarget.isPPC64(); 354 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 355 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 356 357 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 358 unsigned DestReg = MI.getOperand(0).getReg(); 359 assert(MI.definesRegister(DestReg) && 360 "RESTORE_CR does not define its destination"); 361 362 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 363 Reg), FrameIndex); 364 365 // If the reloaded register isn't CR0, shift the bits right so that they are 366 // in the right CR's slot. 367 if (DestReg != PPC::CR0) { 368 unsigned Reg1 = Reg; 369 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 370 371 unsigned ShiftBits = getEncodingValue(DestReg)*4; 372 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 373 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 374 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 375 .addImm(31); 376 } 377 378 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg) 379 .addReg(Reg, RegState::Kill); 380 381 // Discard the pseudo instruction. 382 MBB.erase(II); 383 } 384 385 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, 386 unsigned FrameIndex) const { 387 // Get the instruction. 388 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> 389 // Get the instruction's basic block. 390 MachineBasicBlock &MBB = *MI.getParent(); 391 MachineFunction &MF = *MBB.getParent(); 392 DebugLoc dl = MI.getDebugLoc(); 393 394 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 395 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 396 unsigned SrcReg = MI.getOperand(0).getReg(); 397 398 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) 399 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 400 401 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 402 .addReg(Reg, RegState::Kill), 403 FrameIndex); 404 405 // Discard the pseudo instruction. 406 MBB.erase(II); 407 } 408 409 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, 410 unsigned FrameIndex) const { 411 // Get the instruction. 412 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> 413 // Get the instruction's basic block. 414 MachineBasicBlock &MBB = *MI.getParent(); 415 MachineFunction &MF = *MBB.getParent(); 416 DebugLoc dl = MI.getDebugLoc(); 417 418 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 419 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 420 unsigned DestReg = MI.getOperand(0).getReg(); 421 assert(MI.definesRegister(DestReg) && 422 "RESTORE_VRSAVE does not define its destination"); 423 424 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), 425 Reg), FrameIndex); 426 427 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) 428 .addReg(Reg, RegState::Kill); 429 430 // Discard the pseudo instruction. 431 MBB.erase(II); 432 } 433 434 bool 435 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 436 unsigned Reg, int &FrameIdx) const { 437 438 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 439 // ABI, return true to prevent allocating an additional frame slot. 440 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 441 // is arbitrary and will be subsequently ignored. For 32-bit, we have 442 // previously created the stack slot if needed, so return its FrameIdx. 443 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 444 if (Subtarget.isPPC64()) 445 FrameIdx = 0; 446 else { 447 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 448 FrameIdx = FI->getCRSpillFrameIndex(); 449 } 450 return true; 451 } 452 return false; 453 } 454 455 void 456 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 457 int SPAdj, unsigned FIOperandNum, 458 RegScavenger *RS) const { 459 assert(SPAdj == 0 && "Unexpected"); 460 461 // Get the instruction. 462 MachineInstr &MI = *II; 463 // Get the instruction's basic block. 464 MachineBasicBlock &MBB = *MI.getParent(); 465 // Get the basic block's function. 466 MachineFunction &MF = *MBB.getParent(); 467 // Get the frame info. 468 MachineFrameInfo *MFI = MF.getFrameInfo(); 469 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 470 DebugLoc dl = MI.getDebugLoc(); 471 472 // Take into account whether it's an add or mem instruction 473 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 474 if (MI.isInlineAsm()) 475 OffsetOperandNo = FIOperandNum-1; 476 477 // Get the frame index. 478 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 479 480 // Get the frame pointer save index. Users of this index are primarily 481 // DYNALLOC instructions. 482 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 483 int FPSI = FI->getFramePointerSaveIndex(); 484 // Get the instruction opcode. 485 unsigned OpC = MI.getOpcode(); 486 487 // Special case for dynamic alloca. 488 if (FPSI && FrameIndex == FPSI && 489 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 490 lowerDynamicAlloc(II); 491 return; 492 } 493 494 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 495 if (OpC == PPC::SPILL_CR) { 496 lowerCRSpilling(II, FrameIndex); 497 return; 498 } else if (OpC == PPC::RESTORE_CR) { 499 lowerCRRestore(II, FrameIndex); 500 return; 501 } else if (OpC == PPC::SPILL_VRSAVE) { 502 lowerVRSAVESpilling(II, FrameIndex); 503 return; 504 } else if (OpC == PPC::RESTORE_VRSAVE) { 505 lowerVRSAVERestore(II, FrameIndex); 506 return; 507 } 508 509 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 510 511 bool is64Bit = Subtarget.isPPC64(); 512 MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ? 513 (is64Bit ? PPC::X31 : PPC::R31) : 514 (is64Bit ? PPC::X1 : PPC::R1), 515 false); 516 517 // Figure out if the offset in the instruction is shifted right two bits. This 518 // is true for instructions like "STD", which the machine implicitly adds two 519 // low zeros to. 520 bool isIXAddr = false; 521 switch (OpC) { 522 case PPC::LWA: 523 case PPC::LD: 524 case PPC::STD: 525 case PPC::STD_32: 526 isIXAddr = true; 527 break; 528 } 529 530 bool noImmForm = false; 531 switch (OpC) { 532 case PPC::LVEBX: 533 case PPC::LVEHX: 534 case PPC::LVEWX: 535 case PPC::LVX: 536 case PPC::LVXL: 537 case PPC::LVSL: 538 case PPC::LVSR: 539 case PPC::STVEBX: 540 case PPC::STVEHX: 541 case PPC::STVEWX: 542 case PPC::STVX: 543 case PPC::STVXL: 544 noImmForm = true; 545 break; 546 } 547 548 // Now add the frame object offset to the offset from r1. 549 int Offset = MFI->getObjectOffset(FrameIndex); 550 if (!isIXAddr) 551 Offset += MI.getOperand(OffsetOperandNo).getImm(); 552 else 553 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 554 555 // If we're not using a Frame Pointer that has been set to the value of the 556 // SP before having the stack size subtracted from it, then add the stack size 557 // to Offset to get the correct offset. 558 // Naked functions have stack size 0, although getStackSize may not reflect that 559 // because we didn't call all the pieces that compute it for naked functions. 560 if (!MF.getFunction()->getAttributes(). 561 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked)) 562 Offset += MFI->getStackSize(); 563 564 // If we can, encode the offset directly into the instruction. If this is a 565 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 566 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 567 // clear can be encoded. This is extremely uncommon, because normally you 568 // only "std" to a stack slot that is at least 4-byte aligned, but it can 569 // happen in invalid code. 570 if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 571 (!noImmForm && 572 isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) { 573 if (isIXAddr) 574 Offset >>= 2; // The actual encoded value has the low two bits zero. 575 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 576 return; 577 } 578 579 // The offset doesn't fit into a single register, scavenge one to build the 580 // offset in. 581 582 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 583 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 584 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; 585 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), 586 SReg = MF.getRegInfo().createVirtualRegister(RC); 587 588 // Insert a set of rA with the full offset value before the ld, st, or add 589 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) 590 .addImm(Offset >> 16); 591 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 592 .addReg(SRegHi, RegState::Kill) 593 .addImm(Offset); 594 595 // Convert into indexed form of the instruction: 596 // 597 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 598 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 599 unsigned OperandBase; 600 601 if (noImmForm) 602 OperandBase = 1; 603 else if (OpC != TargetOpcode::INLINEASM) { 604 assert(ImmToIdxMap.count(OpC) && 605 "No indexed form of load or store available!"); 606 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 607 MI.setDesc(TII.get(NewOpcode)); 608 OperandBase = 1; 609 } else { 610 OperandBase = OffsetOperandNo; 611 } 612 613 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 614 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 615 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 616 } 617 618 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 619 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 620 621 if (!Subtarget.isPPC64()) 622 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 623 else 624 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 625 } 626 627 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 628 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 629 } 630 631 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 632 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 633 } 634