1 //===-------------- PPCMIPeephole.cpp - MI Peephole Cleanups -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===---------------------------------------------------------------------===// 8 // 9 // This pass performs peephole optimizations to clean up ugly code 10 // sequences at the MachineInstruction layer. It runs at the end of 11 // the SSA phases, following VSX swap removal. A pass of dead code 12 // elimination follows this one for quick clean-up of any dead 13 // instructions introduced here. Although we could do this as callbacks 14 // from the generic peephole pass, this would have a couple of bad 15 // effects: it might remove optimization opportunities for VSX swap 16 // removal, and it would miss cleanups made possible following VSX 17 // swap removal. 18 // 19 //===---------------------------------------------------------------------===// 20 21 #include "MCTargetDesc/PPCMCTargetDesc.h" 22 #include "MCTargetDesc/PPCPredicates.h" 23 #include "PPC.h" 24 #include "PPCInstrBuilder.h" 25 #include "PPCInstrInfo.h" 26 #include "PPCMachineFunctionInfo.h" 27 #include "PPCTargetMachine.h" 28 #include "llvm/ADT/Statistic.h" 29 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h" 30 #include "llvm/CodeGen/MachineDominators.h" 31 #include "llvm/CodeGen/MachineFunctionPass.h" 32 #include "llvm/CodeGen/MachineInstrBuilder.h" 33 #include "llvm/CodeGen/MachinePostDominators.h" 34 #include "llvm/CodeGen/MachineRegisterInfo.h" 35 #include "llvm/InitializePasses.h" 36 #include "llvm/Support/Debug.h" 37 38 using namespace llvm; 39 40 #define DEBUG_TYPE "ppc-mi-peepholes" 41 42 STATISTIC(RemoveTOCSave, "Number of TOC saves removed"); 43 STATISTIC(MultiTOCSaves, 44 "Number of functions with multiple TOC saves that must be kept"); 45 STATISTIC(NumTOCSavesInPrologue, "Number of TOC saves placed in the prologue"); 46 STATISTIC(NumEliminatedSExt, "Number of eliminated sign-extensions"); 47 STATISTIC(NumEliminatedZExt, "Number of eliminated zero-extensions"); 48 STATISTIC(NumOptADDLIs, "Number of optimized ADD instruction fed by LI"); 49 STATISTIC(NumConvertedToImmediateForm, 50 "Number of instructions converted to their immediate form"); 51 STATISTIC(NumFunctionsEnteredInMIPeephole, 52 "Number of functions entered in PPC MI Peepholes"); 53 STATISTIC(NumFixedPointIterations, 54 "Number of fixed-point iterations converting reg-reg instructions " 55 "to reg-imm ones"); 56 STATISTIC(NumRotatesCollapsed, 57 "Number of pairs of rotate left, clear left/right collapsed"); 58 STATISTIC(NumEXTSWAndSLDICombined, 59 "Number of pairs of EXTSW and SLDI combined as EXTSWSLI"); 60 61 static cl::opt<bool> 62 FixedPointRegToImm("ppc-reg-to-imm-fixed-point", cl::Hidden, cl::init(true), 63 cl::desc("Iterate to a fixed point when attempting to " 64 "convert reg-reg instructions to reg-imm")); 65 66 static cl::opt<bool> 67 ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true), 68 cl::desc("Convert eligible reg+reg instructions to reg+imm")); 69 70 static cl::opt<bool> 71 EnableSExtElimination("ppc-eliminate-signext", 72 cl::desc("enable elimination of sign-extensions"), 73 cl::init(false), cl::Hidden); 74 75 static cl::opt<bool> 76 EnableZExtElimination("ppc-eliminate-zeroext", 77 cl::desc("enable elimination of zero-extensions"), 78 cl::init(false), cl::Hidden); 79 80 namespace { 81 82 struct PPCMIPeephole : public MachineFunctionPass { 83 84 static char ID; 85 const PPCInstrInfo *TII; 86 MachineFunction *MF; 87 MachineRegisterInfo *MRI; 88 89 PPCMIPeephole() : MachineFunctionPass(ID) { 90 initializePPCMIPeepholePass(*PassRegistry::getPassRegistry()); 91 } 92 93 private: 94 MachineDominatorTree *MDT; 95 MachinePostDominatorTree *MPDT; 96 MachineBlockFrequencyInfo *MBFI; 97 uint64_t EntryFreq; 98 99 // Initialize class variables. 100 void initialize(MachineFunction &MFParm); 101 102 // Perform peepholes. 103 bool simplifyCode(void); 104 105 // Perform peepholes. 106 bool eliminateRedundantCompare(void); 107 bool eliminateRedundantTOCSaves(std::map<MachineInstr *, bool> &TOCSaves); 108 bool combineSEXTAndSHL(MachineInstr &MI, MachineInstr *&ToErase); 109 bool emitRLDICWhenLoweringJumpTables(MachineInstr &MI); 110 void UpdateTOCSaves(std::map<MachineInstr *, bool> &TOCSaves, 111 MachineInstr *MI); 112 113 public: 114 115 void getAnalysisUsage(AnalysisUsage &AU) const override { 116 AU.addRequired<MachineDominatorTree>(); 117 AU.addRequired<MachinePostDominatorTree>(); 118 AU.addRequired<MachineBlockFrequencyInfo>(); 119 AU.addPreserved<MachineDominatorTree>(); 120 AU.addPreserved<MachinePostDominatorTree>(); 121 AU.addPreserved<MachineBlockFrequencyInfo>(); 122 MachineFunctionPass::getAnalysisUsage(AU); 123 } 124 125 // Main entry point for this pass. 126 bool runOnMachineFunction(MachineFunction &MF) override { 127 if (skipFunction(MF.getFunction())) 128 return false; 129 initialize(MF); 130 return simplifyCode(); 131 } 132 }; 133 134 // Initialize class variables. 135 void PPCMIPeephole::initialize(MachineFunction &MFParm) { 136 MF = &MFParm; 137 MRI = &MF->getRegInfo(); 138 MDT = &getAnalysis<MachineDominatorTree>(); 139 MPDT = &getAnalysis<MachinePostDominatorTree>(); 140 MBFI = &getAnalysis<MachineBlockFrequencyInfo>(); 141 EntryFreq = MBFI->getEntryFreq(); 142 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo(); 143 LLVM_DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n"); 144 LLVM_DEBUG(MF->dump()); 145 } 146 147 static MachineInstr *getVRegDefOrNull(MachineOperand *Op, 148 MachineRegisterInfo *MRI) { 149 assert(Op && "Invalid Operand!"); 150 if (!Op->isReg()) 151 return nullptr; 152 153 Register Reg = Op->getReg(); 154 if (!Register::isVirtualRegister(Reg)) 155 return nullptr; 156 157 return MRI->getVRegDef(Reg); 158 } 159 160 // This function returns number of known zero bits in output of MI 161 // starting from the most significant bit. 162 static unsigned 163 getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) { 164 unsigned Opcode = MI->getOpcode(); 165 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo || 166 Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo) 167 return MI->getOperand(3).getImm(); 168 169 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) && 170 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) 171 return MI->getOperand(3).getImm(); 172 173 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo || 174 Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo || 175 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && 176 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) 177 return 32 + MI->getOperand(3).getImm(); 178 179 if (Opcode == PPC::ANDIo) { 180 uint16_t Imm = MI->getOperand(2).getImm(); 181 return 48 + countLeadingZeros(Imm); 182 } 183 184 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo || 185 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo || 186 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8) 187 // The result ranges from 0 to 32. 188 return 58; 189 190 if (Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo || 191 Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo) 192 // The result ranges from 0 to 64. 193 return 57; 194 195 if (Opcode == PPC::LHZ || Opcode == PPC::LHZX || 196 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || 197 Opcode == PPC::LHZU || Opcode == PPC::LHZUX || 198 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8) 199 return 48; 200 201 if (Opcode == PPC::LBZ || Opcode == PPC::LBZX || 202 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || 203 Opcode == PPC::LBZU || Opcode == PPC::LBZUX || 204 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8) 205 return 56; 206 207 if (TII->isZeroExtended(*MI)) 208 return 32; 209 210 return 0; 211 } 212 213 // This function maintains a map for the pairs <TOC Save Instr, Keep> 214 // Each time a new TOC save is encountered, it checks if any of the existing 215 // ones are dominated by the new one. If so, it marks the existing one as 216 // redundant by setting it's entry in the map as false. It then adds the new 217 // instruction to the map with either true or false depending on if any 218 // existing instructions dominated the new one. 219 void PPCMIPeephole::UpdateTOCSaves( 220 std::map<MachineInstr *, bool> &TOCSaves, MachineInstr *MI) { 221 assert(TII->isTOCSaveMI(*MI) && "Expecting a TOC save instruction here"); 222 assert(MF->getSubtarget<PPCSubtarget>().isELFv2ABI() && 223 "TOC-save removal only supported on ELFv2"); 224 PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>(); 225 226 MachineBasicBlock *Entry = &MF->front(); 227 uint64_t CurrBlockFreq = MBFI->getBlockFreq(MI->getParent()).getFrequency(); 228 229 // If the block in which the TOC save resides is in a block that 230 // post-dominates Entry, or a block that is hotter than entry (keep in mind 231 // that early MachineLICM has already run so the TOC save won't be hoisted) 232 // we can just do the save in the prologue. 233 if (CurrBlockFreq > EntryFreq || MPDT->dominates(MI->getParent(), Entry)) 234 FI->setMustSaveTOC(true); 235 236 // If we are saving the TOC in the prologue, all the TOC saves can be removed 237 // from the code. 238 if (FI->mustSaveTOC()) { 239 for (auto &TOCSave : TOCSaves) 240 TOCSave.second = false; 241 // Add new instruction to map. 242 TOCSaves[MI] = false; 243 return; 244 } 245 246 bool Keep = true; 247 for (auto It = TOCSaves.begin(); It != TOCSaves.end(); It++ ) { 248 MachineInstr *CurrInst = It->first; 249 // If new instruction dominates an existing one, mark existing one as 250 // redundant. 251 if (It->second && MDT->dominates(MI, CurrInst)) 252 It->second = false; 253 // Check if the new instruction is redundant. 254 if (MDT->dominates(CurrInst, MI)) { 255 Keep = false; 256 break; 257 } 258 } 259 // Add new instruction to map. 260 TOCSaves[MI] = Keep; 261 } 262 263 // Perform peephole optimizations. 264 bool PPCMIPeephole::simplifyCode(void) { 265 bool Simplified = false; 266 MachineInstr* ToErase = nullptr; 267 std::map<MachineInstr *, bool> TOCSaves; 268 const TargetRegisterInfo *TRI = &TII->getRegisterInfo(); 269 NumFunctionsEnteredInMIPeephole++; 270 if (ConvertRegReg) { 271 // Fixed-point conversion of reg/reg instructions fed by load-immediate 272 // into reg/imm instructions. FIXME: This is expensive, control it with 273 // an option. 274 bool SomethingChanged = false; 275 do { 276 NumFixedPointIterations++; 277 SomethingChanged = false; 278 for (MachineBasicBlock &MBB : *MF) { 279 for (MachineInstr &MI : MBB) { 280 if (MI.isDebugInstr()) 281 continue; 282 283 if (TII->convertToImmediateForm(MI)) { 284 // We don't erase anything in case the def has other uses. Let DCE 285 // remove it if it can be removed. 286 LLVM_DEBUG(dbgs() << "Converted instruction to imm form: "); 287 LLVM_DEBUG(MI.dump()); 288 NumConvertedToImmediateForm++; 289 SomethingChanged = true; 290 Simplified = true; 291 continue; 292 } 293 } 294 } 295 } while (SomethingChanged && FixedPointRegToImm); 296 } 297 298 for (MachineBasicBlock &MBB : *MF) { 299 for (MachineInstr &MI : MBB) { 300 301 // If the previous instruction was marked for elimination, 302 // remove it now. 303 if (ToErase) { 304 ToErase->eraseFromParent(); 305 ToErase = nullptr; 306 } 307 308 // Ignore debug instructions. 309 if (MI.isDebugInstr()) 310 continue; 311 312 // Per-opcode peepholes. 313 switch (MI.getOpcode()) { 314 315 default: 316 break; 317 318 case PPC::STD: { 319 MachineFrameInfo &MFI = MF->getFrameInfo(); 320 if (MFI.hasVarSizedObjects() || 321 !MF->getSubtarget<PPCSubtarget>().isELFv2ABI()) 322 break; 323 // When encountering a TOC save instruction, call UpdateTOCSaves 324 // to add it to the TOCSaves map and mark any existing TOC saves 325 // it dominates as redundant. 326 if (TII->isTOCSaveMI(MI)) 327 UpdateTOCSaves(TOCSaves, &MI); 328 break; 329 } 330 case PPC::XXPERMDI: { 331 // Perform simplifications of 2x64 vector swaps and splats. 332 // A swap is identified by an immediate value of 2, and a splat 333 // is identified by an immediate value of 0 or 3. 334 int Immed = MI.getOperand(3).getImm(); 335 336 if (Immed != 1) { 337 338 // For each of these simplifications, we need the two source 339 // regs to match. Unfortunately, MachineCSE ignores COPY and 340 // SUBREG_TO_REG, so for example we can see 341 // XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), immed. 342 // We have to look through chains of COPY and SUBREG_TO_REG 343 // to find the real source values for comparison. 344 unsigned TrueReg1 = 345 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); 346 unsigned TrueReg2 = 347 TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI); 348 349 if (TrueReg1 == TrueReg2 && Register::isVirtualRegister(TrueReg1)) { 350 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); 351 unsigned DefOpc = DefMI ? DefMI->getOpcode() : 0; 352 353 // If this is a splat fed by a splatting load, the splat is 354 // redundant. Replace with a copy. This doesn't happen directly due 355 // to code in PPCDAGToDAGISel.cpp, but it can happen when converting 356 // a load of a double to a vector of 64-bit integers. 357 auto isConversionOfLoadAndSplat = [=]() -> bool { 358 if (DefOpc != PPC::XVCVDPSXDS && DefOpc != PPC::XVCVDPUXDS) 359 return false; 360 unsigned DefReg = 361 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); 362 if (Register::isVirtualRegister(DefReg)) { 363 MachineInstr *LoadMI = MRI->getVRegDef(DefReg); 364 if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX) 365 return true; 366 } 367 return false; 368 }; 369 if (DefMI && (Immed == 0 || Immed == 3)) { 370 if (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat()) { 371 LLVM_DEBUG(dbgs() << "Optimizing load-and-splat/splat " 372 "to load-and-splat/copy: "); 373 LLVM_DEBUG(MI.dump()); 374 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 375 MI.getOperand(0).getReg()) 376 .add(MI.getOperand(1)); 377 ToErase = &MI; 378 Simplified = true; 379 } 380 } 381 382 // If this is a splat or a swap fed by another splat, we 383 // can replace it with a copy. 384 if (DefOpc == PPC::XXPERMDI) { 385 unsigned FeedImmed = DefMI->getOperand(3).getImm(); 386 unsigned FeedReg1 = 387 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); 388 unsigned FeedReg2 = 389 TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI); 390 391 if ((FeedImmed == 0 || FeedImmed == 3) && FeedReg1 == FeedReg2) { 392 LLVM_DEBUG(dbgs() << "Optimizing splat/swap or splat/splat " 393 "to splat/copy: "); 394 LLVM_DEBUG(MI.dump()); 395 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 396 MI.getOperand(0).getReg()) 397 .add(MI.getOperand(1)); 398 ToErase = &MI; 399 Simplified = true; 400 } 401 402 // If this is a splat fed by a swap, we can simplify modify 403 // the splat to splat the other value from the swap's input 404 // parameter. 405 else if ((Immed == 0 || Immed == 3) 406 && FeedImmed == 2 && FeedReg1 == FeedReg2) { 407 LLVM_DEBUG(dbgs() << "Optimizing swap/splat => splat: "); 408 LLVM_DEBUG(MI.dump()); 409 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg()); 410 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg()); 411 MI.getOperand(3).setImm(3 - Immed); 412 Simplified = true; 413 } 414 415 // If this is a swap fed by a swap, we can replace it 416 // with a copy from the first swap's input. 417 else if (Immed == 2 && FeedImmed == 2 && FeedReg1 == FeedReg2) { 418 LLVM_DEBUG(dbgs() << "Optimizing swap/swap => copy: "); 419 LLVM_DEBUG(MI.dump()); 420 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 421 MI.getOperand(0).getReg()) 422 .add(DefMI->getOperand(1)); 423 ToErase = &MI; 424 Simplified = true; 425 } 426 } else if ((Immed == 0 || Immed == 3) && DefOpc == PPC::XXPERMDIs && 427 (DefMI->getOperand(2).getImm() == 0 || 428 DefMI->getOperand(2).getImm() == 3)) { 429 // Splat fed by another splat - switch the output of the first 430 // and remove the second. 431 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 432 ToErase = &MI; 433 Simplified = true; 434 LLVM_DEBUG(dbgs() << "Removing redundant splat: "); 435 LLVM_DEBUG(MI.dump()); 436 } 437 } 438 } 439 break; 440 } 441 case PPC::VSPLTB: 442 case PPC::VSPLTH: 443 case PPC::XXSPLTW: { 444 unsigned MyOpcode = MI.getOpcode(); 445 unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2; 446 unsigned TrueReg = 447 TRI->lookThruCopyLike(MI.getOperand(OpNo).getReg(), MRI); 448 if (!Register::isVirtualRegister(TrueReg)) 449 break; 450 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); 451 if (!DefMI) 452 break; 453 unsigned DefOpcode = DefMI->getOpcode(); 454 auto isConvertOfSplat = [=]() -> bool { 455 if (DefOpcode != PPC::XVCVSPSXWS && DefOpcode != PPC::XVCVSPUXWS) 456 return false; 457 Register ConvReg = DefMI->getOperand(1).getReg(); 458 if (!Register::isVirtualRegister(ConvReg)) 459 return false; 460 MachineInstr *Splt = MRI->getVRegDef(ConvReg); 461 return Splt && (Splt->getOpcode() == PPC::LXVWSX || 462 Splt->getOpcode() == PPC::XXSPLTW); 463 }; 464 bool AlreadySplat = (MyOpcode == DefOpcode) || 465 (MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) || 466 (MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) || 467 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs) || 468 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::LXVWSX) || 469 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::MTVSRWS)|| 470 (MyOpcode == PPC::XXSPLTW && isConvertOfSplat()); 471 // If the instruction[s] that feed this splat have already splat 472 // the value, this splat is redundant. 473 if (AlreadySplat) { 474 LLVM_DEBUG(dbgs() << "Changing redundant splat to a copy: "); 475 LLVM_DEBUG(MI.dump()); 476 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 477 MI.getOperand(0).getReg()) 478 .add(MI.getOperand(OpNo)); 479 ToErase = &MI; 480 Simplified = true; 481 } 482 // Splat fed by a shift. Usually when we align value to splat into 483 // vector element zero. 484 if (DefOpcode == PPC::XXSLDWI) { 485 Register ShiftRes = DefMI->getOperand(0).getReg(); 486 Register ShiftOp1 = DefMI->getOperand(1).getReg(); 487 Register ShiftOp2 = DefMI->getOperand(2).getReg(); 488 unsigned ShiftImm = DefMI->getOperand(3).getImm(); 489 unsigned SplatImm = MI.getOperand(2).getImm(); 490 if (ShiftOp1 == ShiftOp2) { 491 unsigned NewElem = (SplatImm + ShiftImm) & 0x3; 492 if (MRI->hasOneNonDBGUse(ShiftRes)) { 493 LLVM_DEBUG(dbgs() << "Removing redundant shift: "); 494 LLVM_DEBUG(DefMI->dump()); 495 ToErase = DefMI; 496 } 497 Simplified = true; 498 LLVM_DEBUG(dbgs() << "Changing splat immediate from " << SplatImm 499 << " to " << NewElem << " in instruction: "); 500 LLVM_DEBUG(MI.dump()); 501 MI.getOperand(1).setReg(ShiftOp1); 502 MI.getOperand(2).setImm(NewElem); 503 } 504 } 505 break; 506 } 507 case PPC::XVCVDPSP: { 508 // If this is a DP->SP conversion fed by an FRSP, the FRSP is redundant. 509 unsigned TrueReg = 510 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); 511 if (!Register::isVirtualRegister(TrueReg)) 512 break; 513 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); 514 515 // This can occur when building a vector of single precision or integer 516 // values. 517 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) { 518 unsigned DefsReg1 = 519 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); 520 unsigned DefsReg2 = 521 TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI); 522 if (!Register::isVirtualRegister(DefsReg1) || 523 !Register::isVirtualRegister(DefsReg2)) 524 break; 525 MachineInstr *P1 = MRI->getVRegDef(DefsReg1); 526 MachineInstr *P2 = MRI->getVRegDef(DefsReg2); 527 528 if (!P1 || !P2) 529 break; 530 531 // Remove the passed FRSP instruction if it only feeds this MI and 532 // set any uses of that FRSP (in this MI) to the source of the FRSP. 533 auto removeFRSPIfPossible = [&](MachineInstr *RoundInstr) { 534 if (RoundInstr->getOpcode() == PPC::FRSP && 535 MRI->hasOneNonDBGUse(RoundInstr->getOperand(0).getReg())) { 536 Simplified = true; 537 Register ConvReg1 = RoundInstr->getOperand(1).getReg(); 538 Register FRSPDefines = RoundInstr->getOperand(0).getReg(); 539 MachineInstr &Use = *(MRI->use_instr_begin(FRSPDefines)); 540 for (int i = 0, e = Use.getNumOperands(); i < e; ++i) 541 if (Use.getOperand(i).isReg() && 542 Use.getOperand(i).getReg() == FRSPDefines) 543 Use.getOperand(i).setReg(ConvReg1); 544 LLVM_DEBUG(dbgs() << "Removing redundant FRSP:\n"); 545 LLVM_DEBUG(RoundInstr->dump()); 546 LLVM_DEBUG(dbgs() << "As it feeds instruction:\n"); 547 LLVM_DEBUG(MI.dump()); 548 LLVM_DEBUG(dbgs() << "Through instruction:\n"); 549 LLVM_DEBUG(DefMI->dump()); 550 RoundInstr->eraseFromParent(); 551 } 552 }; 553 554 // If the input to XVCVDPSP is a vector that was built (even 555 // partially) out of FRSP's, the FRSP(s) can safely be removed 556 // since this instruction performs the same operation. 557 if (P1 != P2) { 558 removeFRSPIfPossible(P1); 559 removeFRSPIfPossible(P2); 560 break; 561 } 562 removeFRSPIfPossible(P1); 563 } 564 break; 565 } 566 case PPC::EXTSH: 567 case PPC::EXTSH8: 568 case PPC::EXTSH8_32_64: { 569 if (!EnableSExtElimination) break; 570 Register NarrowReg = MI.getOperand(1).getReg(); 571 if (!Register::isVirtualRegister(NarrowReg)) 572 break; 573 574 MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg); 575 // If we've used a zero-extending load that we will sign-extend, 576 // just do a sign-extending load. 577 if (SrcMI->getOpcode() == PPC::LHZ || 578 SrcMI->getOpcode() == PPC::LHZX) { 579 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg())) 580 break; 581 auto is64Bit = [] (unsigned Opcode) { 582 return Opcode == PPC::EXTSH8; 583 }; 584 auto isXForm = [] (unsigned Opcode) { 585 return Opcode == PPC::LHZX; 586 }; 587 auto getSextLoadOp = [] (bool is64Bit, bool isXForm) { 588 if (is64Bit) 589 if (isXForm) return PPC::LHAX8; 590 else return PPC::LHA8; 591 else 592 if (isXForm) return PPC::LHAX; 593 else return PPC::LHA; 594 }; 595 unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()), 596 isXForm(SrcMI->getOpcode())); 597 LLVM_DEBUG(dbgs() << "Zero-extending load\n"); 598 LLVM_DEBUG(SrcMI->dump()); 599 LLVM_DEBUG(dbgs() << "and sign-extension\n"); 600 LLVM_DEBUG(MI.dump()); 601 LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n"); 602 SrcMI->setDesc(TII->get(Opc)); 603 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 604 ToErase = &MI; 605 Simplified = true; 606 NumEliminatedSExt++; 607 } 608 break; 609 } 610 case PPC::EXTSW: 611 case PPC::EXTSW_32: 612 case PPC::EXTSW_32_64: { 613 if (!EnableSExtElimination) break; 614 Register NarrowReg = MI.getOperand(1).getReg(); 615 if (!Register::isVirtualRegister(NarrowReg)) 616 break; 617 618 MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg); 619 // If we've used a zero-extending load that we will sign-extend, 620 // just do a sign-extending load. 621 if (SrcMI->getOpcode() == PPC::LWZ || 622 SrcMI->getOpcode() == PPC::LWZX) { 623 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg())) 624 break; 625 auto is64Bit = [] (unsigned Opcode) { 626 return Opcode == PPC::EXTSW || Opcode == PPC::EXTSW_32_64; 627 }; 628 auto isXForm = [] (unsigned Opcode) { 629 return Opcode == PPC::LWZX; 630 }; 631 auto getSextLoadOp = [] (bool is64Bit, bool isXForm) { 632 if (is64Bit) 633 if (isXForm) return PPC::LWAX; 634 else return PPC::LWA; 635 else 636 if (isXForm) return PPC::LWAX_32; 637 else return PPC::LWA_32; 638 }; 639 unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()), 640 isXForm(SrcMI->getOpcode())); 641 LLVM_DEBUG(dbgs() << "Zero-extending load\n"); 642 LLVM_DEBUG(SrcMI->dump()); 643 LLVM_DEBUG(dbgs() << "and sign-extension\n"); 644 LLVM_DEBUG(MI.dump()); 645 LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n"); 646 SrcMI->setDesc(TII->get(Opc)); 647 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 648 ToErase = &MI; 649 Simplified = true; 650 NumEliminatedSExt++; 651 } else if (MI.getOpcode() == PPC::EXTSW_32_64 && 652 TII->isSignExtended(*SrcMI)) { 653 // We can eliminate EXTSW if the input is known to be already 654 // sign-extended. 655 LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n"); 656 Register TmpReg = 657 MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass); 658 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), 659 TmpReg); 660 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG), 661 MI.getOperand(0).getReg()) 662 .addReg(TmpReg) 663 .addReg(NarrowReg) 664 .addImm(PPC::sub_32); 665 ToErase = &MI; 666 Simplified = true; 667 NumEliminatedSExt++; 668 } 669 break; 670 } 671 case PPC::RLDICL: { 672 // We can eliminate RLDICL (e.g. for zero-extension) 673 // if all bits to clear are already zero in the input. 674 // This code assume following code sequence for zero-extension. 675 // %6 = COPY %5:sub_32; (optional) 676 // %8 = IMPLICIT_DEF; 677 // %7<def,tied1> = INSERT_SUBREG %8<tied0>, %6, sub_32; 678 if (!EnableZExtElimination) break; 679 680 if (MI.getOperand(2).getImm() != 0) 681 break; 682 683 Register SrcReg = MI.getOperand(1).getReg(); 684 if (!Register::isVirtualRegister(SrcReg)) 685 break; 686 687 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 688 if (!(SrcMI && SrcMI->getOpcode() == PPC::INSERT_SUBREG && 689 SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg())) 690 break; 691 692 MachineInstr *ImpDefMI, *SubRegMI; 693 ImpDefMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg()); 694 SubRegMI = MRI->getVRegDef(SrcMI->getOperand(2).getReg()); 695 if (ImpDefMI->getOpcode() != PPC::IMPLICIT_DEF) break; 696 697 SrcMI = SubRegMI; 698 if (SubRegMI->getOpcode() == PPC::COPY) { 699 Register CopyReg = SubRegMI->getOperand(1).getReg(); 700 if (Register::isVirtualRegister(CopyReg)) 701 SrcMI = MRI->getVRegDef(CopyReg); 702 } 703 704 unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII); 705 if (MI.getOperand(3).getImm() <= KnownZeroCount) { 706 LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n"); 707 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 708 MI.getOperand(0).getReg()) 709 .addReg(SrcReg); 710 ToErase = &MI; 711 Simplified = true; 712 NumEliminatedZExt++; 713 } 714 break; 715 } 716 717 // TODO: Any instruction that has an immediate form fed only by a PHI 718 // whose operands are all load immediate can be folded away. We currently 719 // do this for ADD instructions, but should expand it to arithmetic and 720 // binary instructions with immediate forms in the future. 721 case PPC::ADD4: 722 case PPC::ADD8: { 723 auto isSingleUsePHI = [&](MachineOperand *PhiOp) { 724 assert(PhiOp && "Invalid Operand!"); 725 MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI); 726 727 return DefPhiMI && (DefPhiMI->getOpcode() == PPC::PHI) && 728 MRI->hasOneNonDBGUse(DefPhiMI->getOperand(0).getReg()); 729 }; 730 731 auto dominatesAllSingleUseLIs = [&](MachineOperand *DominatorOp, 732 MachineOperand *PhiOp) { 733 assert(PhiOp && "Invalid Operand!"); 734 assert(DominatorOp && "Invalid Operand!"); 735 MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI); 736 MachineInstr *DefDomMI = getVRegDefOrNull(DominatorOp, MRI); 737 738 // Note: the vregs only show up at odd indices position of PHI Node, 739 // the even indices position save the BB info. 740 for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) { 741 MachineInstr *LiMI = 742 getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI); 743 if (!LiMI || 744 (LiMI->getOpcode() != PPC::LI && LiMI->getOpcode() != PPC::LI8) 745 || !MRI->hasOneNonDBGUse(LiMI->getOperand(0).getReg()) || 746 !MDT->dominates(DefDomMI, LiMI)) 747 return false; 748 } 749 750 return true; 751 }; 752 753 MachineOperand Op1 = MI.getOperand(1); 754 MachineOperand Op2 = MI.getOperand(2); 755 if (isSingleUsePHI(&Op2) && dominatesAllSingleUseLIs(&Op1, &Op2)) 756 std::swap(Op1, Op2); 757 else if (!isSingleUsePHI(&Op1) || !dominatesAllSingleUseLIs(&Op2, &Op1)) 758 break; // We don't have an ADD fed by LI's that can be transformed 759 760 // Now we know that Op1 is the PHI node and Op2 is the dominator 761 Register DominatorReg = Op2.getReg(); 762 763 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 764 ? &PPC::G8RC_and_G8RC_NOX0RegClass 765 : &PPC::GPRC_and_GPRC_NOR0RegClass; 766 MRI->setRegClass(DominatorReg, TRC); 767 768 // replace LIs with ADDIs 769 MachineInstr *DefPhiMI = getVRegDefOrNull(&Op1, MRI); 770 for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) { 771 MachineInstr *LiMI = getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI); 772 LLVM_DEBUG(dbgs() << "Optimizing LI to ADDI: "); 773 LLVM_DEBUG(LiMI->dump()); 774 775 // There could be repeated registers in the PHI, e.g: %1 = 776 // PHI %6, <%bb.2>, %8, <%bb.3>, %8, <%bb.6>; So if we've 777 // already replaced the def instruction, skip. 778 if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8) 779 continue; 780 781 assert((LiMI->getOpcode() == PPC::LI || 782 LiMI->getOpcode() == PPC::LI8) && 783 "Invalid Opcode!"); 784 auto LiImm = LiMI->getOperand(1).getImm(); // save the imm of LI 785 LiMI->RemoveOperand(1); // remove the imm of LI 786 LiMI->setDesc(TII->get(LiMI->getOpcode() == PPC::LI ? PPC::ADDI 787 : PPC::ADDI8)); 788 MachineInstrBuilder(*LiMI->getParent()->getParent(), *LiMI) 789 .addReg(DominatorReg) 790 .addImm(LiImm); // restore the imm of LI 791 LLVM_DEBUG(LiMI->dump()); 792 } 793 794 // Replace ADD with COPY 795 LLVM_DEBUG(dbgs() << "Optimizing ADD to COPY: "); 796 LLVM_DEBUG(MI.dump()); 797 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 798 MI.getOperand(0).getReg()) 799 .add(Op1); 800 ToErase = &MI; 801 Simplified = true; 802 NumOptADDLIs++; 803 break; 804 } 805 case PPC::RLDICR: { 806 Simplified |= emitRLDICWhenLoweringJumpTables(MI) || 807 combineSEXTAndSHL(MI, ToErase); 808 break; 809 } 810 case PPC::RLWINM: 811 case PPC::RLWINMo: 812 case PPC::RLWINM8: 813 case PPC::RLWINM8o: { 814 unsigned FoldingReg = MI.getOperand(1).getReg(); 815 if (!Register::isVirtualRegister(FoldingReg)) 816 break; 817 818 MachineInstr *SrcMI = MRI->getVRegDef(FoldingReg); 819 if (SrcMI->getOpcode() != PPC::RLWINM && 820 SrcMI->getOpcode() != PPC::RLWINMo && 821 SrcMI->getOpcode() != PPC::RLWINM8 && 822 SrcMI->getOpcode() != PPC::RLWINM8o) 823 break; 824 assert((MI.getOperand(2).isImm() && MI.getOperand(3).isImm() && 825 MI.getOperand(4).isImm() && SrcMI->getOperand(2).isImm() && 826 SrcMI->getOperand(3).isImm() && SrcMI->getOperand(4).isImm()) && 827 "Invalid PPC::RLWINM Instruction!"); 828 uint64_t SHSrc = SrcMI->getOperand(2).getImm(); 829 uint64_t SHMI = MI.getOperand(2).getImm(); 830 uint64_t MBSrc = SrcMI->getOperand(3).getImm(); 831 uint64_t MBMI = MI.getOperand(3).getImm(); 832 uint64_t MESrc = SrcMI->getOperand(4).getImm(); 833 uint64_t MEMI = MI.getOperand(4).getImm(); 834 835 assert((MEMI < 32 && MESrc < 32 && MBMI < 32 && MBSrc < 32) && 836 "Invalid PPC::RLWINM Instruction!"); 837 838 // If MBMI is bigger than MEMI, we always can not get run of ones. 839 // RotatedSrcMask non-wrap: 840 // 0........31|32........63 841 // RotatedSrcMask: B---E B---E 842 // MaskMI: -----------|--E B------ 843 // Result: ----- --- (Bad candidate) 844 // 845 // RotatedSrcMask wrap: 846 // 0........31|32........63 847 // RotatedSrcMask: --E B----|--E B---- 848 // MaskMI: -----------|--E B------ 849 // Result: --- -----|--- ----- (Bad candidate) 850 // 851 // One special case is RotatedSrcMask is a full set mask. 852 // RotatedSrcMask full: 853 // 0........31|32........63 854 // RotatedSrcMask: ------EB---|-------EB--- 855 // MaskMI: -----------|--E B------ 856 // Result: -----------|--- ------- (Good candidate) 857 858 // Mark special case. 859 bool SrcMaskFull = (MBSrc - MESrc == 1) || (MBSrc == 0 && MESrc == 31); 860 861 // For other MBMI > MEMI cases, just return. 862 if ((MBMI > MEMI) && !SrcMaskFull) 863 break; 864 865 // Handle MBMI <= MEMI cases. 866 APInt MaskMI = APInt::getBitsSetWithWrap(32, 32 - MEMI - 1, 32 - MBMI); 867 // In MI, we only need low 32 bits of SrcMI, just consider about low 32 868 // bit of SrcMI mask. Note that in APInt, lowerest bit is at index 0, 869 // while in PowerPC ISA, lowerest bit is at index 63. 870 APInt MaskSrc = 871 APInt::getBitsSetWithWrap(32, 32 - MESrc - 1, 32 - MBSrc); 872 // Current APInt::getBitsSetWithWrap sets all bits to 0 if loBit is 873 // equal to highBit. 874 // If MBSrc - MESrc == 1, we expect a full set mask instead of Null. 875 if (SrcMaskFull && (MBSrc - MESrc == 1)) 876 MaskSrc.setAllBits(); 877 878 APInt RotatedSrcMask = MaskSrc.rotl(SHMI); 879 APInt FinalMask = RotatedSrcMask & MaskMI; 880 uint32_t NewMB, NewME; 881 882 // If final mask is 0, MI result should be 0 too. 883 if (FinalMask.isNullValue()) { 884 bool Is64Bit = (MI.getOpcode() == PPC::RLWINM8 || 885 MI.getOpcode() == PPC::RLWINM8o); 886 887 LLVM_DEBUG(dbgs() << "Replace Instr: "); 888 LLVM_DEBUG(MI.dump()); 889 890 if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8) { 891 // Replace MI with "LI 0" 892 MI.RemoveOperand(4); 893 MI.RemoveOperand(3); 894 MI.RemoveOperand(2); 895 MI.getOperand(1).ChangeToImmediate(0); 896 MI.setDesc(TII->get(Is64Bit ? PPC::LI8 : PPC::LI)); 897 } else { 898 // Replace MI with "ANDIo reg, 0" 899 MI.RemoveOperand(4); 900 MI.RemoveOperand(3); 901 MI.getOperand(2).setImm(0); 902 MI.setDesc(TII->get(Is64Bit ? PPC::ANDIo8 : PPC::ANDIo)); 903 } 904 Simplified = true; 905 NumRotatesCollapsed++; 906 907 LLVM_DEBUG(dbgs() << "With: "); 908 LLVM_DEBUG(MI.dump()); 909 } else if (isRunOfOnes((unsigned)(FinalMask.getZExtValue()), NewMB, 910 NewME) || SrcMaskFull) { 911 // If FoldingReg has only one use and it it not RLWINMo and 912 // RLWINM8o, safe to delete its def SrcMI. Otherwise keep it. 913 if (MRI->hasOneNonDBGUse(FoldingReg) && 914 (SrcMI->getOpcode() == PPC::RLWINM || 915 SrcMI->getOpcode() == PPC::RLWINM8)) { 916 ToErase = SrcMI; 917 LLVM_DEBUG(dbgs() << "Delete dead instruction: "); 918 LLVM_DEBUG(SrcMI->dump()); 919 } 920 921 LLVM_DEBUG(dbgs() << "Converting Instr: "); 922 LLVM_DEBUG(MI.dump()); 923 924 uint16_t NewSH = (SHSrc + SHMI) % 32; 925 MI.getOperand(2).setImm(NewSH); 926 // If SrcMI mask is full, no need to update MBMI and MEMI. 927 if (!SrcMaskFull) { 928 MI.getOperand(3).setImm(NewMB); 929 MI.getOperand(4).setImm(NewME); 930 } 931 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); 932 if (SrcMI->getOperand(1).isKill()) { 933 MI.getOperand(1).setIsKill(true); 934 SrcMI->getOperand(1).setIsKill(false); 935 } else 936 // About to replace MI.getOperand(1), clear its kill flag. 937 MI.getOperand(1).setIsKill(false); 938 939 Simplified = true; 940 NumRotatesCollapsed++; 941 942 LLVM_DEBUG(dbgs() << "To: "); 943 LLVM_DEBUG(MI.dump()); 944 } 945 break; 946 } 947 } 948 } 949 950 // If the last instruction was marked for elimination, 951 // remove it now. 952 if (ToErase) { 953 ToErase->eraseFromParent(); 954 ToErase = nullptr; 955 } 956 } 957 958 // Eliminate all the TOC save instructions which are redundant. 959 Simplified |= eliminateRedundantTOCSaves(TOCSaves); 960 PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>(); 961 if (FI->mustSaveTOC()) 962 NumTOCSavesInPrologue++; 963 964 // We try to eliminate redundant compare instruction. 965 Simplified |= eliminateRedundantCompare(); 966 967 return Simplified; 968 } 969 970 // helper functions for eliminateRedundantCompare 971 static bool isEqOrNe(MachineInstr *BI) { 972 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); 973 unsigned PredCond = PPC::getPredicateCondition(Pred); 974 return (PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE); 975 } 976 977 static bool isSupportedCmpOp(unsigned opCode) { 978 return (opCode == PPC::CMPLD || opCode == PPC::CMPD || 979 opCode == PPC::CMPLW || opCode == PPC::CMPW || 980 opCode == PPC::CMPLDI || opCode == PPC::CMPDI || 981 opCode == PPC::CMPLWI || opCode == PPC::CMPWI); 982 } 983 984 static bool is64bitCmpOp(unsigned opCode) { 985 return (opCode == PPC::CMPLD || opCode == PPC::CMPD || 986 opCode == PPC::CMPLDI || opCode == PPC::CMPDI); 987 } 988 989 static bool isSignedCmpOp(unsigned opCode) { 990 return (opCode == PPC::CMPD || opCode == PPC::CMPW || 991 opCode == PPC::CMPDI || opCode == PPC::CMPWI); 992 } 993 994 static unsigned getSignedCmpOpCode(unsigned opCode) { 995 if (opCode == PPC::CMPLD) return PPC::CMPD; 996 if (opCode == PPC::CMPLW) return PPC::CMPW; 997 if (opCode == PPC::CMPLDI) return PPC::CMPDI; 998 if (opCode == PPC::CMPLWI) return PPC::CMPWI; 999 return opCode; 1000 } 1001 1002 // We can decrement immediate x in (GE x) by changing it to (GT x-1) or 1003 // (LT x) to (LE x-1) 1004 static unsigned getPredicateToDecImm(MachineInstr *BI, MachineInstr *CMPI) { 1005 uint64_t Imm = CMPI->getOperand(2).getImm(); 1006 bool SignedCmp = isSignedCmpOp(CMPI->getOpcode()); 1007 if ((!SignedCmp && Imm == 0) || (SignedCmp && Imm == 0x8000)) 1008 return 0; 1009 1010 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); 1011 unsigned PredCond = PPC::getPredicateCondition(Pred); 1012 unsigned PredHint = PPC::getPredicateHint(Pred); 1013 if (PredCond == PPC::PRED_GE) 1014 return PPC::getPredicate(PPC::PRED_GT, PredHint); 1015 if (PredCond == PPC::PRED_LT) 1016 return PPC::getPredicate(PPC::PRED_LE, PredHint); 1017 1018 return 0; 1019 } 1020 1021 // We can increment immediate x in (GT x) by changing it to (GE x+1) or 1022 // (LE x) to (LT x+1) 1023 static unsigned getPredicateToIncImm(MachineInstr *BI, MachineInstr *CMPI) { 1024 uint64_t Imm = CMPI->getOperand(2).getImm(); 1025 bool SignedCmp = isSignedCmpOp(CMPI->getOpcode()); 1026 if ((!SignedCmp && Imm == 0xFFFF) || (SignedCmp && Imm == 0x7FFF)) 1027 return 0; 1028 1029 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); 1030 unsigned PredCond = PPC::getPredicateCondition(Pred); 1031 unsigned PredHint = PPC::getPredicateHint(Pred); 1032 if (PredCond == PPC::PRED_GT) 1033 return PPC::getPredicate(PPC::PRED_GE, PredHint); 1034 if (PredCond == PPC::PRED_LE) 1035 return PPC::getPredicate(PPC::PRED_LT, PredHint); 1036 1037 return 0; 1038 } 1039 1040 // This takes a Phi node and returns a register value for the specified BB. 1041 static unsigned getIncomingRegForBlock(MachineInstr *Phi, 1042 MachineBasicBlock *MBB) { 1043 for (unsigned I = 2, E = Phi->getNumOperands() + 1; I != E; I += 2) { 1044 MachineOperand &MO = Phi->getOperand(I); 1045 if (MO.getMBB() == MBB) 1046 return Phi->getOperand(I-1).getReg(); 1047 } 1048 llvm_unreachable("invalid src basic block for this Phi node\n"); 1049 return 0; 1050 } 1051 1052 // This function tracks the source of the register through register copy. 1053 // If BB1 and BB2 are non-NULL, we also track PHI instruction in BB2 1054 // assuming that the control comes from BB1 into BB2. 1055 static unsigned getSrcVReg(unsigned Reg, MachineBasicBlock *BB1, 1056 MachineBasicBlock *BB2, MachineRegisterInfo *MRI) { 1057 unsigned SrcReg = Reg; 1058 while (1) { 1059 unsigned NextReg = SrcReg; 1060 MachineInstr *Inst = MRI->getVRegDef(SrcReg); 1061 if (BB1 && Inst->getOpcode() == PPC::PHI && Inst->getParent() == BB2) { 1062 NextReg = getIncomingRegForBlock(Inst, BB1); 1063 // We track through PHI only once to avoid infinite loop. 1064 BB1 = nullptr; 1065 } 1066 else if (Inst->isFullCopy()) 1067 NextReg = Inst->getOperand(1).getReg(); 1068 if (NextReg == SrcReg || !Register::isVirtualRegister(NextReg)) 1069 break; 1070 SrcReg = NextReg; 1071 } 1072 return SrcReg; 1073 } 1074 1075 static bool eligibleForCompareElimination(MachineBasicBlock &MBB, 1076 MachineBasicBlock *&PredMBB, 1077 MachineBasicBlock *&MBBtoMoveCmp, 1078 MachineRegisterInfo *MRI) { 1079 1080 auto isEligibleBB = [&](MachineBasicBlock &BB) { 1081 auto BII = BB.getFirstInstrTerminator(); 1082 // We optimize BBs ending with a conditional branch. 1083 // We check only for BCC here, not BCCLR, because BCCLR 1084 // will be formed only later in the pipeline. 1085 if (BB.succ_size() == 2 && 1086 BII != BB.instr_end() && 1087 (*BII).getOpcode() == PPC::BCC && 1088 (*BII).getOperand(1).isReg()) { 1089 // We optimize only if the condition code is used only by one BCC. 1090 Register CndReg = (*BII).getOperand(1).getReg(); 1091 if (!Register::isVirtualRegister(CndReg) || !MRI->hasOneNonDBGUse(CndReg)) 1092 return false; 1093 1094 MachineInstr *CMPI = MRI->getVRegDef(CndReg); 1095 // We assume compare and branch are in the same BB for ease of analysis. 1096 if (CMPI->getParent() != &BB) 1097 return false; 1098 1099 // We skip this BB if a physical register is used in comparison. 1100 for (MachineOperand &MO : CMPI->operands()) 1101 if (MO.isReg() && !Register::isVirtualRegister(MO.getReg())) 1102 return false; 1103 1104 return true; 1105 } 1106 return false; 1107 }; 1108 1109 // If this BB has more than one successor, we can create a new BB and 1110 // move the compare instruction in the new BB. 1111 // So far, we do not move compare instruction to a BB having multiple 1112 // successors to avoid potentially increasing code size. 1113 auto isEligibleForMoveCmp = [](MachineBasicBlock &BB) { 1114 return BB.succ_size() == 1; 1115 }; 1116 1117 if (!isEligibleBB(MBB)) 1118 return false; 1119 1120 unsigned NumPredBBs = MBB.pred_size(); 1121 if (NumPredBBs == 1) { 1122 MachineBasicBlock *TmpMBB = *MBB.pred_begin(); 1123 if (isEligibleBB(*TmpMBB)) { 1124 PredMBB = TmpMBB; 1125 MBBtoMoveCmp = nullptr; 1126 return true; 1127 } 1128 } 1129 else if (NumPredBBs == 2) { 1130 // We check for partially redundant case. 1131 // So far, we support cases with only two predecessors 1132 // to avoid increasing the number of instructions. 1133 MachineBasicBlock::pred_iterator PI = MBB.pred_begin(); 1134 MachineBasicBlock *Pred1MBB = *PI; 1135 MachineBasicBlock *Pred2MBB = *(PI+1); 1136 1137 if (isEligibleBB(*Pred1MBB) && isEligibleForMoveCmp(*Pred2MBB)) { 1138 // We assume Pred1MBB is the BB containing the compare to be merged and 1139 // Pred2MBB is the BB to which we will append a compare instruction. 1140 // Hence we can proceed as is. 1141 } 1142 else if (isEligibleBB(*Pred2MBB) && isEligibleForMoveCmp(*Pred1MBB)) { 1143 // We need to swap Pred1MBB and Pred2MBB to canonicalize. 1144 std::swap(Pred1MBB, Pred2MBB); 1145 } 1146 else return false; 1147 1148 // Here, Pred2MBB is the BB to which we need to append a compare inst. 1149 // We cannot move the compare instruction if operands are not available 1150 // in Pred2MBB (i.e. defined in MBB by an instruction other than PHI). 1151 MachineInstr *BI = &*MBB.getFirstInstrTerminator(); 1152 MachineInstr *CMPI = MRI->getVRegDef(BI->getOperand(1).getReg()); 1153 for (int I = 1; I <= 2; I++) 1154 if (CMPI->getOperand(I).isReg()) { 1155 MachineInstr *Inst = MRI->getVRegDef(CMPI->getOperand(I).getReg()); 1156 if (Inst->getParent() == &MBB && Inst->getOpcode() != PPC::PHI) 1157 return false; 1158 } 1159 1160 PredMBB = Pred1MBB; 1161 MBBtoMoveCmp = Pred2MBB; 1162 return true; 1163 } 1164 1165 return false; 1166 } 1167 1168 // This function will iterate over the input map containing a pair of TOC save 1169 // instruction and a flag. The flag will be set to false if the TOC save is 1170 // proven redundant. This function will erase from the basic block all the TOC 1171 // saves marked as redundant. 1172 bool PPCMIPeephole::eliminateRedundantTOCSaves( 1173 std::map<MachineInstr *, bool> &TOCSaves) { 1174 bool Simplified = false; 1175 int NumKept = 0; 1176 for (auto TOCSave : TOCSaves) { 1177 if (!TOCSave.second) { 1178 TOCSave.first->eraseFromParent(); 1179 RemoveTOCSave++; 1180 Simplified = true; 1181 } else { 1182 NumKept++; 1183 } 1184 } 1185 1186 if (NumKept > 1) 1187 MultiTOCSaves++; 1188 1189 return Simplified; 1190 } 1191 1192 // If multiple conditional branches are executed based on the (essentially) 1193 // same comparison, we merge compare instructions into one and make multiple 1194 // conditional branches on this comparison. 1195 // For example, 1196 // if (a == 0) { ... } 1197 // else if (a < 0) { ... } 1198 // can be executed by one compare and two conditional branches instead of 1199 // two pairs of a compare and a conditional branch. 1200 // 1201 // This method merges two compare instructions in two MBBs and modifies the 1202 // compare and conditional branch instructions if needed. 1203 // For the above example, the input for this pass looks like: 1204 // cmplwi r3, 0 1205 // beq 0, .LBB0_3 1206 // cmpwi r3, -1 1207 // bgt 0, .LBB0_4 1208 // So, before merging two compares, we need to modify these instructions as 1209 // cmpwi r3, 0 ; cmplwi and cmpwi yield same result for beq 1210 // beq 0, .LBB0_3 1211 // cmpwi r3, 0 ; greather than -1 means greater or equal to 0 1212 // bge 0, .LBB0_4 1213 1214 bool PPCMIPeephole::eliminateRedundantCompare(void) { 1215 bool Simplified = false; 1216 1217 for (MachineBasicBlock &MBB2 : *MF) { 1218 MachineBasicBlock *MBB1 = nullptr, *MBBtoMoveCmp = nullptr; 1219 1220 // For fully redundant case, we select two basic blocks MBB1 and MBB2 1221 // as an optimization target if 1222 // - both MBBs end with a conditional branch, 1223 // - MBB1 is the only predecessor of MBB2, and 1224 // - compare does not take a physical register as a operand in both MBBs. 1225 // In this case, eligibleForCompareElimination sets MBBtoMoveCmp nullptr. 1226 // 1227 // As partially redundant case, we additionally handle if MBB2 has one 1228 // additional predecessor, which has only one successor (MBB2). 1229 // In this case, we move the compare instruction originally in MBB2 into 1230 // MBBtoMoveCmp. This partially redundant case is typically appear by 1231 // compiling a while loop; here, MBBtoMoveCmp is the loop preheader. 1232 // 1233 // Overview of CFG of related basic blocks 1234 // Fully redundant case Partially redundant case 1235 // -------- ---------------- -------- 1236 // | MBB1 | (w/ 2 succ) | MBBtoMoveCmp | | MBB1 | (w/ 2 succ) 1237 // -------- ---------------- -------- 1238 // | \ (w/ 1 succ) \ | \ 1239 // | \ \ | \ 1240 // | \ | 1241 // -------- -------- 1242 // | MBB2 | (w/ 1 pred | MBB2 | (w/ 2 pred 1243 // -------- and 2 succ) -------- and 2 succ) 1244 // | \ | \ 1245 // | \ | \ 1246 // 1247 if (!eligibleForCompareElimination(MBB2, MBB1, MBBtoMoveCmp, MRI)) 1248 continue; 1249 1250 MachineInstr *BI1 = &*MBB1->getFirstInstrTerminator(); 1251 MachineInstr *CMPI1 = MRI->getVRegDef(BI1->getOperand(1).getReg()); 1252 1253 MachineInstr *BI2 = &*MBB2.getFirstInstrTerminator(); 1254 MachineInstr *CMPI2 = MRI->getVRegDef(BI2->getOperand(1).getReg()); 1255 bool IsPartiallyRedundant = (MBBtoMoveCmp != nullptr); 1256 1257 // We cannot optimize an unsupported compare opcode or 1258 // a mix of 32-bit and 64-bit comaprisons 1259 if (!isSupportedCmpOp(CMPI1->getOpcode()) || 1260 !isSupportedCmpOp(CMPI2->getOpcode()) || 1261 is64bitCmpOp(CMPI1->getOpcode()) != is64bitCmpOp(CMPI2->getOpcode())) 1262 continue; 1263 1264 unsigned NewOpCode = 0; 1265 unsigned NewPredicate1 = 0, NewPredicate2 = 0; 1266 int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0; 1267 bool SwapOperands = false; 1268 1269 if (CMPI1->getOpcode() != CMPI2->getOpcode()) { 1270 // Typically, unsigned comparison is used for equality check, but 1271 // we replace it with a signed comparison if the comparison 1272 // to be merged is a signed comparison. 1273 // In other cases of opcode mismatch, we cannot optimize this. 1274 1275 // We cannot change opcode when comparing against an immediate 1276 // if the most significant bit of the immediate is one 1277 // due to the difference in sign extension. 1278 auto CmpAgainstImmWithSignBit = [](MachineInstr *I) { 1279 if (!I->getOperand(2).isImm()) 1280 return false; 1281 int16_t Imm = (int16_t)I->getOperand(2).getImm(); 1282 return Imm < 0; 1283 }; 1284 1285 if (isEqOrNe(BI2) && !CmpAgainstImmWithSignBit(CMPI2) && 1286 CMPI1->getOpcode() == getSignedCmpOpCode(CMPI2->getOpcode())) 1287 NewOpCode = CMPI1->getOpcode(); 1288 else if (isEqOrNe(BI1) && !CmpAgainstImmWithSignBit(CMPI1) && 1289 getSignedCmpOpCode(CMPI1->getOpcode()) == CMPI2->getOpcode()) 1290 NewOpCode = CMPI2->getOpcode(); 1291 else continue; 1292 } 1293 1294 if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) { 1295 // In case of comparisons between two registers, these two registers 1296 // must be same to merge two comparisons. 1297 unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(), 1298 nullptr, nullptr, MRI); 1299 unsigned Cmp1Operand2 = getSrcVReg(CMPI1->getOperand(2).getReg(), 1300 nullptr, nullptr, MRI); 1301 unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(), 1302 MBB1, &MBB2, MRI); 1303 unsigned Cmp2Operand2 = getSrcVReg(CMPI2->getOperand(2).getReg(), 1304 MBB1, &MBB2, MRI); 1305 1306 if (Cmp1Operand1 == Cmp2Operand1 && Cmp1Operand2 == Cmp2Operand2) { 1307 // Same pair of registers in the same order; ready to merge as is. 1308 } 1309 else if (Cmp1Operand1 == Cmp2Operand2 && Cmp1Operand2 == Cmp2Operand1) { 1310 // Same pair of registers in different order. 1311 // We reverse the predicate to merge compare instructions. 1312 PPC::Predicate Pred = (PPC::Predicate)BI2->getOperand(0).getImm(); 1313 NewPredicate2 = (unsigned)PPC::getSwappedPredicate(Pred); 1314 // In case of partial redundancy, we need to swap operands 1315 // in another compare instruction. 1316 SwapOperands = true; 1317 } 1318 else continue; 1319 } 1320 else if (CMPI1->getOperand(2).isImm() && CMPI2->getOperand(2).isImm()) { 1321 // In case of comparisons between a register and an immediate, 1322 // the operand register must be same for two compare instructions. 1323 unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(), 1324 nullptr, nullptr, MRI); 1325 unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(), 1326 MBB1, &MBB2, MRI); 1327 if (Cmp1Operand1 != Cmp2Operand1) 1328 continue; 1329 1330 NewImm1 = Imm1 = (int16_t)CMPI1->getOperand(2).getImm(); 1331 NewImm2 = Imm2 = (int16_t)CMPI2->getOperand(2).getImm(); 1332 1333 // If immediate are not same, we try to adjust by changing predicate; 1334 // e.g. GT imm means GE (imm+1). 1335 if (Imm1 != Imm2 && (!isEqOrNe(BI2) || !isEqOrNe(BI1))) { 1336 int Diff = Imm1 - Imm2; 1337 if (Diff < -2 || Diff > 2) 1338 continue; 1339 1340 unsigned PredToInc1 = getPredicateToIncImm(BI1, CMPI1); 1341 unsigned PredToDec1 = getPredicateToDecImm(BI1, CMPI1); 1342 unsigned PredToInc2 = getPredicateToIncImm(BI2, CMPI2); 1343 unsigned PredToDec2 = getPredicateToDecImm(BI2, CMPI2); 1344 if (Diff == 2) { 1345 if (PredToInc2 && PredToDec1) { 1346 NewPredicate2 = PredToInc2; 1347 NewPredicate1 = PredToDec1; 1348 NewImm2++; 1349 NewImm1--; 1350 } 1351 } 1352 else if (Diff == 1) { 1353 if (PredToInc2) { 1354 NewImm2++; 1355 NewPredicate2 = PredToInc2; 1356 } 1357 else if (PredToDec1) { 1358 NewImm1--; 1359 NewPredicate1 = PredToDec1; 1360 } 1361 } 1362 else if (Diff == -1) { 1363 if (PredToDec2) { 1364 NewImm2--; 1365 NewPredicate2 = PredToDec2; 1366 } 1367 else if (PredToInc1) { 1368 NewImm1++; 1369 NewPredicate1 = PredToInc1; 1370 } 1371 } 1372 else if (Diff == -2) { 1373 if (PredToDec2 && PredToInc1) { 1374 NewPredicate2 = PredToDec2; 1375 NewPredicate1 = PredToInc1; 1376 NewImm2--; 1377 NewImm1++; 1378 } 1379 } 1380 } 1381 1382 // We cannot merge two compares if the immediates are not same. 1383 if (NewImm2 != NewImm1) 1384 continue; 1385 } 1386 1387 LLVM_DEBUG(dbgs() << "Optimize two pairs of compare and branch:\n"); 1388 LLVM_DEBUG(CMPI1->dump()); 1389 LLVM_DEBUG(BI1->dump()); 1390 LLVM_DEBUG(CMPI2->dump()); 1391 LLVM_DEBUG(BI2->dump()); 1392 1393 // We adjust opcode, predicates and immediate as we determined above. 1394 if (NewOpCode != 0 && NewOpCode != CMPI1->getOpcode()) { 1395 CMPI1->setDesc(TII->get(NewOpCode)); 1396 } 1397 if (NewPredicate1) { 1398 BI1->getOperand(0).setImm(NewPredicate1); 1399 } 1400 if (NewPredicate2) { 1401 BI2->getOperand(0).setImm(NewPredicate2); 1402 } 1403 if (NewImm1 != Imm1) { 1404 CMPI1->getOperand(2).setImm(NewImm1); 1405 } 1406 1407 if (IsPartiallyRedundant) { 1408 // We touch up the compare instruction in MBB2 and move it to 1409 // a previous BB to handle partially redundant case. 1410 if (SwapOperands) { 1411 Register Op1 = CMPI2->getOperand(1).getReg(); 1412 Register Op2 = CMPI2->getOperand(2).getReg(); 1413 CMPI2->getOperand(1).setReg(Op2); 1414 CMPI2->getOperand(2).setReg(Op1); 1415 } 1416 if (NewImm2 != Imm2) 1417 CMPI2->getOperand(2).setImm(NewImm2); 1418 1419 for (int I = 1; I <= 2; I++) { 1420 if (CMPI2->getOperand(I).isReg()) { 1421 MachineInstr *Inst = MRI->getVRegDef(CMPI2->getOperand(I).getReg()); 1422 if (Inst->getParent() != &MBB2) 1423 continue; 1424 1425 assert(Inst->getOpcode() == PPC::PHI && 1426 "We cannot support if an operand comes from this BB."); 1427 unsigned SrcReg = getIncomingRegForBlock(Inst, MBBtoMoveCmp); 1428 CMPI2->getOperand(I).setReg(SrcReg); 1429 } 1430 } 1431 auto I = MachineBasicBlock::iterator(MBBtoMoveCmp->getFirstTerminator()); 1432 MBBtoMoveCmp->splice(I, &MBB2, MachineBasicBlock::iterator(CMPI2)); 1433 1434 DebugLoc DL = CMPI2->getDebugLoc(); 1435 Register NewVReg = MRI->createVirtualRegister(&PPC::CRRCRegClass); 1436 BuildMI(MBB2, MBB2.begin(), DL, 1437 TII->get(PPC::PHI), NewVReg) 1438 .addReg(BI1->getOperand(1).getReg()).addMBB(MBB1) 1439 .addReg(BI2->getOperand(1).getReg()).addMBB(MBBtoMoveCmp); 1440 BI2->getOperand(1).setReg(NewVReg); 1441 } 1442 else { 1443 // We finally eliminate compare instruction in MBB2. 1444 BI2->getOperand(1).setReg(BI1->getOperand(1).getReg()); 1445 CMPI2->eraseFromParent(); 1446 } 1447 BI2->getOperand(1).setIsKill(true); 1448 BI1->getOperand(1).setIsKill(false); 1449 1450 LLVM_DEBUG(dbgs() << "into a compare and two branches:\n"); 1451 LLVM_DEBUG(CMPI1->dump()); 1452 LLVM_DEBUG(BI1->dump()); 1453 LLVM_DEBUG(BI2->dump()); 1454 if (IsPartiallyRedundant) { 1455 LLVM_DEBUG(dbgs() << "The following compare is moved into " 1456 << printMBBReference(*MBBtoMoveCmp) 1457 << " to handle partial redundancy.\n"); 1458 LLVM_DEBUG(CMPI2->dump()); 1459 } 1460 1461 Simplified = true; 1462 } 1463 1464 return Simplified; 1465 } 1466 1467 // We miss the opportunity to emit an RLDIC when lowering jump tables 1468 // since ISEL sees only a single basic block. When selecting, the clear 1469 // and shift left will be in different blocks. 1470 bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) { 1471 if (MI.getOpcode() != PPC::RLDICR) 1472 return false; 1473 1474 Register SrcReg = MI.getOperand(1).getReg(); 1475 if (!Register::isVirtualRegister(SrcReg)) 1476 return false; 1477 1478 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 1479 if (SrcMI->getOpcode() != PPC::RLDICL) 1480 return false; 1481 1482 MachineOperand MOpSHSrc = SrcMI->getOperand(2); 1483 MachineOperand MOpMBSrc = SrcMI->getOperand(3); 1484 MachineOperand MOpSHMI = MI.getOperand(2); 1485 MachineOperand MOpMEMI = MI.getOperand(3); 1486 if (!(MOpSHSrc.isImm() && MOpMBSrc.isImm() && MOpSHMI.isImm() && 1487 MOpMEMI.isImm())) 1488 return false; 1489 1490 uint64_t SHSrc = MOpSHSrc.getImm(); 1491 uint64_t MBSrc = MOpMBSrc.getImm(); 1492 uint64_t SHMI = MOpSHMI.getImm(); 1493 uint64_t MEMI = MOpMEMI.getImm(); 1494 uint64_t NewSH = SHSrc + SHMI; 1495 uint64_t NewMB = MBSrc - SHMI; 1496 if (NewMB > 63 || NewSH > 63) 1497 return false; 1498 1499 // The bits cleared with RLDICL are [0, MBSrc). 1500 // The bits cleared with RLDICR are (MEMI, 63]. 1501 // After the sequence, the bits cleared are: 1502 // [0, MBSrc-SHMI) and (MEMI, 63). 1503 // 1504 // The bits cleared with RLDIC are [0, NewMB) and (63-NewSH, 63]. 1505 if ((63 - NewSH) != MEMI) 1506 return false; 1507 1508 LLVM_DEBUG(dbgs() << "Converting pair: "); 1509 LLVM_DEBUG(SrcMI->dump()); 1510 LLVM_DEBUG(MI.dump()); 1511 1512 MI.setDesc(TII->get(PPC::RLDIC)); 1513 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); 1514 MI.getOperand(2).setImm(NewSH); 1515 MI.getOperand(3).setImm(NewMB); 1516 1517 LLVM_DEBUG(dbgs() << "To: "); 1518 LLVM_DEBUG(MI.dump()); 1519 NumRotatesCollapsed++; 1520 return true; 1521 } 1522 1523 // For case in LLVM IR 1524 // entry: 1525 // %iconv = sext i32 %index to i64 1526 // br i1 undef label %true, label %false 1527 // true: 1528 // %ptr = getelementptr inbounds i32, i32* null, i64 %iconv 1529 // ... 1530 // PPCISelLowering::combineSHL fails to combine, because sext and shl are in 1531 // different BBs when conducting instruction selection. We can do a peephole 1532 // optimization to combine these two instructions into extswsli after 1533 // instruction selection. 1534 bool PPCMIPeephole::combineSEXTAndSHL(MachineInstr &MI, 1535 MachineInstr *&ToErase) { 1536 if (MI.getOpcode() != PPC::RLDICR) 1537 return false; 1538 1539 if (!MF->getSubtarget<PPCSubtarget>().isISA3_0()) 1540 return false; 1541 1542 assert(MI.getNumOperands() == 4 && "RLDICR should have 4 operands"); 1543 1544 MachineOperand MOpSHMI = MI.getOperand(2); 1545 MachineOperand MOpMEMI = MI.getOperand(3); 1546 if (!(MOpSHMI.isImm() && MOpMEMI.isImm())) 1547 return false; 1548 1549 uint64_t SHMI = MOpSHMI.getImm(); 1550 uint64_t MEMI = MOpMEMI.getImm(); 1551 if (SHMI + MEMI != 63) 1552 return false; 1553 1554 Register SrcReg = MI.getOperand(1).getReg(); 1555 if (!Register::isVirtualRegister(SrcReg)) 1556 return false; 1557 1558 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 1559 if (SrcMI->getOpcode() != PPC::EXTSW && 1560 SrcMI->getOpcode() != PPC::EXTSW_32_64) 1561 return false; 1562 1563 // If the register defined by extsw has more than one use, combination is not 1564 // needed. 1565 if (!MRI->hasOneNonDBGUse(SrcReg)) 1566 return false; 1567 1568 assert(SrcMI->getNumOperands() == 2 && "EXTSW should have 2 operands"); 1569 assert(SrcMI->getOperand(1).isReg() && 1570 "EXTSW's second operand should be a register"); 1571 if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg())) 1572 return false; 1573 1574 LLVM_DEBUG(dbgs() << "Combining pair: "); 1575 LLVM_DEBUG(SrcMI->dump()); 1576 LLVM_DEBUG(MI.dump()); 1577 1578 MachineInstr *NewInstr = 1579 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), 1580 SrcMI->getOpcode() == PPC::EXTSW ? TII->get(PPC::EXTSWSLI) 1581 : TII->get(PPC::EXTSWSLI_32_64), 1582 MI.getOperand(0).getReg()) 1583 .add(SrcMI->getOperand(1)) 1584 .add(MOpSHMI); 1585 (void)NewInstr; 1586 1587 LLVM_DEBUG(dbgs() << "TO: "); 1588 LLVM_DEBUG(NewInstr->dump()); 1589 ++NumEXTSWAndSLDICombined; 1590 ToErase = &MI; 1591 // SrcMI, which is extsw, is of no use now, erase it. 1592 SrcMI->eraseFromParent(); 1593 return true; 1594 } 1595 1596 } // end default namespace 1597 1598 INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE, 1599 "PowerPC MI Peephole Optimization", false, false) 1600 INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfo) 1601 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) 1602 INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree) 1603 INITIALIZE_PASS_END(PPCMIPeephole, DEBUG_TYPE, 1604 "PowerPC MI Peephole Optimization", false, false) 1605 1606 char PPCMIPeephole::ID = 0; 1607 FunctionPass* 1608 llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); } 1609 1610