1 //===-------------- PPCMIPeephole.cpp - MI Peephole Cleanups -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===---------------------------------------------------------------------===// 8 // 9 // This pass performs peephole optimizations to clean up ugly code 10 // sequences at the MachineInstruction layer. It runs at the end of 11 // the SSA phases, following VSX swap removal. A pass of dead code 12 // elimination follows this one for quick clean-up of any dead 13 // instructions introduced here. Although we could do this as callbacks 14 // from the generic peephole pass, this would have a couple of bad 15 // effects: it might remove optimization opportunities for VSX swap 16 // removal, and it would miss cleanups made possible following VSX 17 // swap removal. 18 // 19 //===---------------------------------------------------------------------===// 20 21 #include "MCTargetDesc/PPCMCTargetDesc.h" 22 #include "MCTargetDesc/PPCPredicates.h" 23 #include "PPC.h" 24 #include "PPCInstrBuilder.h" 25 #include "PPCInstrInfo.h" 26 #include "PPCMachineFunctionInfo.h" 27 #include "PPCTargetMachine.h" 28 #include "llvm/ADT/Statistic.h" 29 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h" 30 #include "llvm/CodeGen/MachineDominators.h" 31 #include "llvm/CodeGen/MachineFunctionPass.h" 32 #include "llvm/CodeGen/MachineInstrBuilder.h" 33 #include "llvm/CodeGen/MachinePostDominators.h" 34 #include "llvm/CodeGen/MachineRegisterInfo.h" 35 #include "llvm/InitializePasses.h" 36 #include "llvm/Support/Debug.h" 37 38 using namespace llvm; 39 40 #define DEBUG_TYPE "ppc-mi-peepholes" 41 42 STATISTIC(RemoveTOCSave, "Number of TOC saves removed"); 43 STATISTIC(MultiTOCSaves, 44 "Number of functions with multiple TOC saves that must be kept"); 45 STATISTIC(NumTOCSavesInPrologue, "Number of TOC saves placed in the prologue"); 46 STATISTIC(NumEliminatedSExt, "Number of eliminated sign-extensions"); 47 STATISTIC(NumEliminatedZExt, "Number of eliminated zero-extensions"); 48 STATISTIC(NumOptADDLIs, "Number of optimized ADD instruction fed by LI"); 49 STATISTIC(NumConvertedToImmediateForm, 50 "Number of instructions converted to their immediate form"); 51 STATISTIC(NumFunctionsEnteredInMIPeephole, 52 "Number of functions entered in PPC MI Peepholes"); 53 STATISTIC(NumFixedPointIterations, 54 "Number of fixed-point iterations converting reg-reg instructions " 55 "to reg-imm ones"); 56 STATISTIC(NumRotatesCollapsed, 57 "Number of pairs of rotate left, clear left/right collapsed"); 58 STATISTIC(NumEXTSWAndSLDICombined, 59 "Number of pairs of EXTSW and SLDI combined as EXTSWSLI"); 60 61 static cl::opt<bool> 62 FixedPointRegToImm("ppc-reg-to-imm-fixed-point", cl::Hidden, cl::init(true), 63 cl::desc("Iterate to a fixed point when attempting to " 64 "convert reg-reg instructions to reg-imm")); 65 66 static cl::opt<bool> 67 ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true), 68 cl::desc("Convert eligible reg+reg instructions to reg+imm")); 69 70 static cl::opt<bool> 71 EnableSExtElimination("ppc-eliminate-signext", 72 cl::desc("enable elimination of sign-extensions"), 73 cl::init(false), cl::Hidden); 74 75 static cl::opt<bool> 76 EnableZExtElimination("ppc-eliminate-zeroext", 77 cl::desc("enable elimination of zero-extensions"), 78 cl::init(false), cl::Hidden); 79 80 namespace { 81 82 struct PPCMIPeephole : public MachineFunctionPass { 83 84 static char ID; 85 const PPCInstrInfo *TII; 86 MachineFunction *MF; 87 MachineRegisterInfo *MRI; 88 89 PPCMIPeephole() : MachineFunctionPass(ID) { 90 initializePPCMIPeepholePass(*PassRegistry::getPassRegistry()); 91 } 92 93 private: 94 MachineDominatorTree *MDT; 95 MachinePostDominatorTree *MPDT; 96 MachineBlockFrequencyInfo *MBFI; 97 uint64_t EntryFreq; 98 99 // Initialize class variables. 100 void initialize(MachineFunction &MFParm); 101 102 // Perform peepholes. 103 bool simplifyCode(void); 104 105 // Perform peepholes. 106 bool eliminateRedundantCompare(void); 107 bool eliminateRedundantTOCSaves(std::map<MachineInstr *, bool> &TOCSaves); 108 bool combineSEXTAndSHL(MachineInstr &MI, MachineInstr *&ToErase); 109 bool emitRLDICWhenLoweringJumpTables(MachineInstr &MI); 110 void UpdateTOCSaves(std::map<MachineInstr *, bool> &TOCSaves, 111 MachineInstr *MI); 112 113 public: 114 115 void getAnalysisUsage(AnalysisUsage &AU) const override { 116 AU.addRequired<MachineDominatorTree>(); 117 AU.addRequired<MachinePostDominatorTree>(); 118 AU.addRequired<MachineBlockFrequencyInfo>(); 119 AU.addPreserved<MachineDominatorTree>(); 120 AU.addPreserved<MachinePostDominatorTree>(); 121 AU.addPreserved<MachineBlockFrequencyInfo>(); 122 MachineFunctionPass::getAnalysisUsage(AU); 123 } 124 125 // Main entry point for this pass. 126 bool runOnMachineFunction(MachineFunction &MF) override { 127 if (skipFunction(MF.getFunction())) 128 return false; 129 initialize(MF); 130 return simplifyCode(); 131 } 132 }; 133 134 // Initialize class variables. 135 void PPCMIPeephole::initialize(MachineFunction &MFParm) { 136 MF = &MFParm; 137 MRI = &MF->getRegInfo(); 138 MDT = &getAnalysis<MachineDominatorTree>(); 139 MPDT = &getAnalysis<MachinePostDominatorTree>(); 140 MBFI = &getAnalysis<MachineBlockFrequencyInfo>(); 141 EntryFreq = MBFI->getEntryFreq(); 142 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo(); 143 LLVM_DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n"); 144 LLVM_DEBUG(MF->dump()); 145 } 146 147 static MachineInstr *getVRegDefOrNull(MachineOperand *Op, 148 MachineRegisterInfo *MRI) { 149 assert(Op && "Invalid Operand!"); 150 if (!Op->isReg()) 151 return nullptr; 152 153 Register Reg = Op->getReg(); 154 if (!Register::isVirtualRegister(Reg)) 155 return nullptr; 156 157 return MRI->getVRegDef(Reg); 158 } 159 160 // This function returns number of known zero bits in output of MI 161 // starting from the most significant bit. 162 static unsigned 163 getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) { 164 unsigned Opcode = MI->getOpcode(); 165 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo || 166 Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo) 167 return MI->getOperand(3).getImm(); 168 169 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) && 170 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) 171 return MI->getOperand(3).getImm(); 172 173 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo || 174 Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo || 175 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && 176 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) 177 return 32 + MI->getOperand(3).getImm(); 178 179 if (Opcode == PPC::ANDIo) { 180 uint16_t Imm = MI->getOperand(2).getImm(); 181 return 48 + countLeadingZeros(Imm); 182 } 183 184 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo || 185 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo || 186 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8) 187 // The result ranges from 0 to 32. 188 return 58; 189 190 if (Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo || 191 Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo) 192 // The result ranges from 0 to 64. 193 return 57; 194 195 if (Opcode == PPC::LHZ || Opcode == PPC::LHZX || 196 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || 197 Opcode == PPC::LHZU || Opcode == PPC::LHZUX || 198 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8) 199 return 48; 200 201 if (Opcode == PPC::LBZ || Opcode == PPC::LBZX || 202 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || 203 Opcode == PPC::LBZU || Opcode == PPC::LBZUX || 204 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8) 205 return 56; 206 207 if (TII->isZeroExtended(*MI)) 208 return 32; 209 210 return 0; 211 } 212 213 // This function maintains a map for the pairs <TOC Save Instr, Keep> 214 // Each time a new TOC save is encountered, it checks if any of the existing 215 // ones are dominated by the new one. If so, it marks the existing one as 216 // redundant by setting it's entry in the map as false. It then adds the new 217 // instruction to the map with either true or false depending on if any 218 // existing instructions dominated the new one. 219 void PPCMIPeephole::UpdateTOCSaves( 220 std::map<MachineInstr *, bool> &TOCSaves, MachineInstr *MI) { 221 assert(TII->isTOCSaveMI(*MI) && "Expecting a TOC save instruction here"); 222 assert(MF->getSubtarget<PPCSubtarget>().isELFv2ABI() && 223 "TOC-save removal only supported on ELFv2"); 224 PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>(); 225 226 MachineBasicBlock *Entry = &MF->front(); 227 uint64_t CurrBlockFreq = MBFI->getBlockFreq(MI->getParent()).getFrequency(); 228 229 // If the block in which the TOC save resides is in a block that 230 // post-dominates Entry, or a block that is hotter than entry (keep in mind 231 // that early MachineLICM has already run so the TOC save won't be hoisted) 232 // we can just do the save in the prologue. 233 if (CurrBlockFreq > EntryFreq || MPDT->dominates(MI->getParent(), Entry)) 234 FI->setMustSaveTOC(true); 235 236 // If we are saving the TOC in the prologue, all the TOC saves can be removed 237 // from the code. 238 if (FI->mustSaveTOC()) { 239 for (auto &TOCSave : TOCSaves) 240 TOCSave.second = false; 241 // Add new instruction to map. 242 TOCSaves[MI] = false; 243 return; 244 } 245 246 bool Keep = true; 247 for (auto It = TOCSaves.begin(); It != TOCSaves.end(); It++ ) { 248 MachineInstr *CurrInst = It->first; 249 // If new instruction dominates an existing one, mark existing one as 250 // redundant. 251 if (It->second && MDT->dominates(MI, CurrInst)) 252 It->second = false; 253 // Check if the new instruction is redundant. 254 if (MDT->dominates(CurrInst, MI)) { 255 Keep = false; 256 break; 257 } 258 } 259 // Add new instruction to map. 260 TOCSaves[MI] = Keep; 261 } 262 263 // Perform peephole optimizations. 264 bool PPCMIPeephole::simplifyCode(void) { 265 bool Simplified = false; 266 MachineInstr* ToErase = nullptr; 267 std::map<MachineInstr *, bool> TOCSaves; 268 const TargetRegisterInfo *TRI = &TII->getRegisterInfo(); 269 NumFunctionsEnteredInMIPeephole++; 270 if (ConvertRegReg) { 271 // Fixed-point conversion of reg/reg instructions fed by load-immediate 272 // into reg/imm instructions. FIXME: This is expensive, control it with 273 // an option. 274 bool SomethingChanged = false; 275 do { 276 NumFixedPointIterations++; 277 SomethingChanged = false; 278 for (MachineBasicBlock &MBB : *MF) { 279 for (MachineInstr &MI : MBB) { 280 if (MI.isDebugInstr()) 281 continue; 282 283 if (TII->convertToImmediateForm(MI)) { 284 // We don't erase anything in case the def has other uses. Let DCE 285 // remove it if it can be removed. 286 LLVM_DEBUG(dbgs() << "Converted instruction to imm form: "); 287 LLVM_DEBUG(MI.dump()); 288 NumConvertedToImmediateForm++; 289 SomethingChanged = true; 290 Simplified = true; 291 continue; 292 } 293 } 294 } 295 } while (SomethingChanged && FixedPointRegToImm); 296 } 297 298 for (MachineBasicBlock &MBB : *MF) { 299 for (MachineInstr &MI : MBB) { 300 301 // If the previous instruction was marked for elimination, 302 // remove it now. 303 if (ToErase) { 304 ToErase->eraseFromParent(); 305 ToErase = nullptr; 306 } 307 308 // Ignore debug instructions. 309 if (MI.isDebugInstr()) 310 continue; 311 312 // Per-opcode peepholes. 313 switch (MI.getOpcode()) { 314 315 default: 316 break; 317 318 case PPC::STD: { 319 MachineFrameInfo &MFI = MF->getFrameInfo(); 320 if (MFI.hasVarSizedObjects() || 321 !MF->getSubtarget<PPCSubtarget>().isELFv2ABI()) 322 break; 323 // When encountering a TOC save instruction, call UpdateTOCSaves 324 // to add it to the TOCSaves map and mark any existing TOC saves 325 // it dominates as redundant. 326 if (TII->isTOCSaveMI(MI)) 327 UpdateTOCSaves(TOCSaves, &MI); 328 break; 329 } 330 case PPC::XXPERMDI: { 331 // Perform simplifications of 2x64 vector swaps and splats. 332 // A swap is identified by an immediate value of 2, and a splat 333 // is identified by an immediate value of 0 or 3. 334 int Immed = MI.getOperand(3).getImm(); 335 336 if (Immed != 1) { 337 338 // For each of these simplifications, we need the two source 339 // regs to match. Unfortunately, MachineCSE ignores COPY and 340 // SUBREG_TO_REG, so for example we can see 341 // XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), immed. 342 // We have to look through chains of COPY and SUBREG_TO_REG 343 // to find the real source values for comparison. 344 unsigned TrueReg1 = 345 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); 346 unsigned TrueReg2 = 347 TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI); 348 349 if (TrueReg1 == TrueReg2 && Register::isVirtualRegister(TrueReg1)) { 350 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); 351 unsigned DefOpc = DefMI ? DefMI->getOpcode() : 0; 352 353 // If this is a splat fed by a splatting load, the splat is 354 // redundant. Replace with a copy. This doesn't happen directly due 355 // to code in PPCDAGToDAGISel.cpp, but it can happen when converting 356 // a load of a double to a vector of 64-bit integers. 357 auto isConversionOfLoadAndSplat = [=]() -> bool { 358 if (DefOpc != PPC::XVCVDPSXDS && DefOpc != PPC::XVCVDPUXDS) 359 return false; 360 unsigned DefReg = 361 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); 362 if (Register::isVirtualRegister(DefReg)) { 363 MachineInstr *LoadMI = MRI->getVRegDef(DefReg); 364 if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX) 365 return true; 366 } 367 return false; 368 }; 369 if (DefMI && (Immed == 0 || Immed == 3)) { 370 if (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat()) { 371 LLVM_DEBUG(dbgs() << "Optimizing load-and-splat/splat " 372 "to load-and-splat/copy: "); 373 LLVM_DEBUG(MI.dump()); 374 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 375 MI.getOperand(0).getReg()) 376 .add(MI.getOperand(1)); 377 ToErase = &MI; 378 Simplified = true; 379 } 380 } 381 382 // If this is a splat or a swap fed by another splat, we 383 // can replace it with a copy. 384 if (DefOpc == PPC::XXPERMDI) { 385 unsigned DefReg1 = DefMI->getOperand(1).getReg(); 386 unsigned DefReg2 = DefMI->getOperand(2).getReg(); 387 unsigned DefImmed = DefMI->getOperand(3).getImm(); 388 389 // If the two inputs are not the same register, check to see if 390 // they originate from the same virtual register after only 391 // copy-like instructions. 392 if (DefReg1 != DefReg2) { 393 unsigned FeedReg1 = TRI->lookThruCopyLike(DefReg1, MRI); 394 unsigned FeedReg2 = TRI->lookThruCopyLike(DefReg2, MRI); 395 396 if (FeedReg1 != FeedReg2 || 397 Register::isPhysicalRegister(FeedReg1)) 398 break; 399 } 400 401 if (DefImmed == 0 || DefImmed == 3) { 402 LLVM_DEBUG(dbgs() << "Optimizing splat/swap or splat/splat " 403 "to splat/copy: "); 404 LLVM_DEBUG(MI.dump()); 405 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 406 MI.getOperand(0).getReg()) 407 .add(MI.getOperand(1)); 408 ToErase = &MI; 409 Simplified = true; 410 } 411 412 // If this is a splat fed by a swap, we can simplify modify 413 // the splat to splat the other value from the swap's input 414 // parameter. 415 else if ((Immed == 0 || Immed == 3) && DefImmed == 2) { 416 LLVM_DEBUG(dbgs() << "Optimizing swap/splat => splat: "); 417 LLVM_DEBUG(MI.dump()); 418 MI.getOperand(1).setReg(DefReg1); 419 MI.getOperand(2).setReg(DefReg2); 420 MI.getOperand(3).setImm(3 - Immed); 421 Simplified = true; 422 } 423 424 // If this is a swap fed by a swap, we can replace it 425 // with a copy from the first swap's input. 426 else if (Immed == 2 && DefImmed == 2) { 427 LLVM_DEBUG(dbgs() << "Optimizing swap/swap => copy: "); 428 LLVM_DEBUG(MI.dump()); 429 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 430 MI.getOperand(0).getReg()) 431 .add(DefMI->getOperand(1)); 432 ToErase = &MI; 433 Simplified = true; 434 } 435 } else if ((Immed == 0 || Immed == 3) && DefOpc == PPC::XXPERMDIs && 436 (DefMI->getOperand(2).getImm() == 0 || 437 DefMI->getOperand(2).getImm() == 3)) { 438 // Splat fed by another splat - switch the output of the first 439 // and remove the second. 440 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 441 ToErase = &MI; 442 Simplified = true; 443 LLVM_DEBUG(dbgs() << "Removing redundant splat: "); 444 LLVM_DEBUG(MI.dump()); 445 } 446 } 447 } 448 break; 449 } 450 case PPC::VSPLTB: 451 case PPC::VSPLTH: 452 case PPC::XXSPLTW: { 453 unsigned MyOpcode = MI.getOpcode(); 454 unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2; 455 unsigned TrueReg = 456 TRI->lookThruCopyLike(MI.getOperand(OpNo).getReg(), MRI); 457 if (!Register::isVirtualRegister(TrueReg)) 458 break; 459 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); 460 if (!DefMI) 461 break; 462 unsigned DefOpcode = DefMI->getOpcode(); 463 auto isConvertOfSplat = [=]() -> bool { 464 if (DefOpcode != PPC::XVCVSPSXWS && DefOpcode != PPC::XVCVSPUXWS) 465 return false; 466 Register ConvReg = DefMI->getOperand(1).getReg(); 467 if (!Register::isVirtualRegister(ConvReg)) 468 return false; 469 MachineInstr *Splt = MRI->getVRegDef(ConvReg); 470 return Splt && (Splt->getOpcode() == PPC::LXVWSX || 471 Splt->getOpcode() == PPC::XXSPLTW); 472 }; 473 bool AlreadySplat = (MyOpcode == DefOpcode) || 474 (MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) || 475 (MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) || 476 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs) || 477 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::LXVWSX) || 478 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::MTVSRWS)|| 479 (MyOpcode == PPC::XXSPLTW && isConvertOfSplat()); 480 // If the instruction[s] that feed this splat have already splat 481 // the value, this splat is redundant. 482 if (AlreadySplat) { 483 LLVM_DEBUG(dbgs() << "Changing redundant splat to a copy: "); 484 LLVM_DEBUG(MI.dump()); 485 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 486 MI.getOperand(0).getReg()) 487 .add(MI.getOperand(OpNo)); 488 ToErase = &MI; 489 Simplified = true; 490 } 491 // Splat fed by a shift. Usually when we align value to splat into 492 // vector element zero. 493 if (DefOpcode == PPC::XXSLDWI) { 494 Register ShiftRes = DefMI->getOperand(0).getReg(); 495 Register ShiftOp1 = DefMI->getOperand(1).getReg(); 496 Register ShiftOp2 = DefMI->getOperand(2).getReg(); 497 unsigned ShiftImm = DefMI->getOperand(3).getImm(); 498 unsigned SplatImm = MI.getOperand(2).getImm(); 499 if (ShiftOp1 == ShiftOp2) { 500 unsigned NewElem = (SplatImm + ShiftImm) & 0x3; 501 if (MRI->hasOneNonDBGUse(ShiftRes)) { 502 LLVM_DEBUG(dbgs() << "Removing redundant shift: "); 503 LLVM_DEBUG(DefMI->dump()); 504 ToErase = DefMI; 505 } 506 Simplified = true; 507 LLVM_DEBUG(dbgs() << "Changing splat immediate from " << SplatImm 508 << " to " << NewElem << " in instruction: "); 509 LLVM_DEBUG(MI.dump()); 510 MI.getOperand(1).setReg(ShiftOp1); 511 MI.getOperand(2).setImm(NewElem); 512 } 513 } 514 break; 515 } 516 case PPC::XVCVDPSP: { 517 // If this is a DP->SP conversion fed by an FRSP, the FRSP is redundant. 518 unsigned TrueReg = 519 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); 520 if (!Register::isVirtualRegister(TrueReg)) 521 break; 522 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); 523 524 // This can occur when building a vector of single precision or integer 525 // values. 526 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) { 527 unsigned DefsReg1 = 528 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); 529 unsigned DefsReg2 = 530 TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI); 531 if (!Register::isVirtualRegister(DefsReg1) || 532 !Register::isVirtualRegister(DefsReg2)) 533 break; 534 MachineInstr *P1 = MRI->getVRegDef(DefsReg1); 535 MachineInstr *P2 = MRI->getVRegDef(DefsReg2); 536 537 if (!P1 || !P2) 538 break; 539 540 // Remove the passed FRSP instruction if it only feeds this MI and 541 // set any uses of that FRSP (in this MI) to the source of the FRSP. 542 auto removeFRSPIfPossible = [&](MachineInstr *RoundInstr) { 543 if (RoundInstr->getOpcode() == PPC::FRSP && 544 MRI->hasOneNonDBGUse(RoundInstr->getOperand(0).getReg())) { 545 Simplified = true; 546 Register ConvReg1 = RoundInstr->getOperand(1).getReg(); 547 Register FRSPDefines = RoundInstr->getOperand(0).getReg(); 548 MachineInstr &Use = *(MRI->use_instr_begin(FRSPDefines)); 549 for (int i = 0, e = Use.getNumOperands(); i < e; ++i) 550 if (Use.getOperand(i).isReg() && 551 Use.getOperand(i).getReg() == FRSPDefines) 552 Use.getOperand(i).setReg(ConvReg1); 553 LLVM_DEBUG(dbgs() << "Removing redundant FRSP:\n"); 554 LLVM_DEBUG(RoundInstr->dump()); 555 LLVM_DEBUG(dbgs() << "As it feeds instruction:\n"); 556 LLVM_DEBUG(MI.dump()); 557 LLVM_DEBUG(dbgs() << "Through instruction:\n"); 558 LLVM_DEBUG(DefMI->dump()); 559 RoundInstr->eraseFromParent(); 560 } 561 }; 562 563 // If the input to XVCVDPSP is a vector that was built (even 564 // partially) out of FRSP's, the FRSP(s) can safely be removed 565 // since this instruction performs the same operation. 566 if (P1 != P2) { 567 removeFRSPIfPossible(P1); 568 removeFRSPIfPossible(P2); 569 break; 570 } 571 removeFRSPIfPossible(P1); 572 } 573 break; 574 } 575 case PPC::EXTSH: 576 case PPC::EXTSH8: 577 case PPC::EXTSH8_32_64: { 578 if (!EnableSExtElimination) break; 579 Register NarrowReg = MI.getOperand(1).getReg(); 580 if (!Register::isVirtualRegister(NarrowReg)) 581 break; 582 583 MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg); 584 // If we've used a zero-extending load that we will sign-extend, 585 // just do a sign-extending load. 586 if (SrcMI->getOpcode() == PPC::LHZ || 587 SrcMI->getOpcode() == PPC::LHZX) { 588 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg())) 589 break; 590 auto is64Bit = [] (unsigned Opcode) { 591 return Opcode == PPC::EXTSH8; 592 }; 593 auto isXForm = [] (unsigned Opcode) { 594 return Opcode == PPC::LHZX; 595 }; 596 auto getSextLoadOp = [] (bool is64Bit, bool isXForm) { 597 if (is64Bit) 598 if (isXForm) return PPC::LHAX8; 599 else return PPC::LHA8; 600 else 601 if (isXForm) return PPC::LHAX; 602 else return PPC::LHA; 603 }; 604 unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()), 605 isXForm(SrcMI->getOpcode())); 606 LLVM_DEBUG(dbgs() << "Zero-extending load\n"); 607 LLVM_DEBUG(SrcMI->dump()); 608 LLVM_DEBUG(dbgs() << "and sign-extension\n"); 609 LLVM_DEBUG(MI.dump()); 610 LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n"); 611 SrcMI->setDesc(TII->get(Opc)); 612 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 613 ToErase = &MI; 614 Simplified = true; 615 NumEliminatedSExt++; 616 } 617 break; 618 } 619 case PPC::EXTSW: 620 case PPC::EXTSW_32: 621 case PPC::EXTSW_32_64: { 622 if (!EnableSExtElimination) break; 623 Register NarrowReg = MI.getOperand(1).getReg(); 624 if (!Register::isVirtualRegister(NarrowReg)) 625 break; 626 627 MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg); 628 // If we've used a zero-extending load that we will sign-extend, 629 // just do a sign-extending load. 630 if (SrcMI->getOpcode() == PPC::LWZ || 631 SrcMI->getOpcode() == PPC::LWZX) { 632 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg())) 633 break; 634 auto is64Bit = [] (unsigned Opcode) { 635 return Opcode == PPC::EXTSW || Opcode == PPC::EXTSW_32_64; 636 }; 637 auto isXForm = [] (unsigned Opcode) { 638 return Opcode == PPC::LWZX; 639 }; 640 auto getSextLoadOp = [] (bool is64Bit, bool isXForm) { 641 if (is64Bit) 642 if (isXForm) return PPC::LWAX; 643 else return PPC::LWA; 644 else 645 if (isXForm) return PPC::LWAX_32; 646 else return PPC::LWA_32; 647 }; 648 unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()), 649 isXForm(SrcMI->getOpcode())); 650 LLVM_DEBUG(dbgs() << "Zero-extending load\n"); 651 LLVM_DEBUG(SrcMI->dump()); 652 LLVM_DEBUG(dbgs() << "and sign-extension\n"); 653 LLVM_DEBUG(MI.dump()); 654 LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n"); 655 SrcMI->setDesc(TII->get(Opc)); 656 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 657 ToErase = &MI; 658 Simplified = true; 659 NumEliminatedSExt++; 660 } else if (MI.getOpcode() == PPC::EXTSW_32_64 && 661 TII->isSignExtended(*SrcMI)) { 662 // We can eliminate EXTSW if the input is known to be already 663 // sign-extended. 664 LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n"); 665 Register TmpReg = 666 MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass); 667 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), 668 TmpReg); 669 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG), 670 MI.getOperand(0).getReg()) 671 .addReg(TmpReg) 672 .addReg(NarrowReg) 673 .addImm(PPC::sub_32); 674 ToErase = &MI; 675 Simplified = true; 676 NumEliminatedSExt++; 677 } 678 break; 679 } 680 case PPC::RLDICL: { 681 // We can eliminate RLDICL (e.g. for zero-extension) 682 // if all bits to clear are already zero in the input. 683 // This code assume following code sequence for zero-extension. 684 // %6 = COPY %5:sub_32; (optional) 685 // %8 = IMPLICIT_DEF; 686 // %7<def,tied1> = INSERT_SUBREG %8<tied0>, %6, sub_32; 687 if (!EnableZExtElimination) break; 688 689 if (MI.getOperand(2).getImm() != 0) 690 break; 691 692 Register SrcReg = MI.getOperand(1).getReg(); 693 if (!Register::isVirtualRegister(SrcReg)) 694 break; 695 696 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 697 if (!(SrcMI && SrcMI->getOpcode() == PPC::INSERT_SUBREG && 698 SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg())) 699 break; 700 701 MachineInstr *ImpDefMI, *SubRegMI; 702 ImpDefMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg()); 703 SubRegMI = MRI->getVRegDef(SrcMI->getOperand(2).getReg()); 704 if (ImpDefMI->getOpcode() != PPC::IMPLICIT_DEF) break; 705 706 SrcMI = SubRegMI; 707 if (SubRegMI->getOpcode() == PPC::COPY) { 708 Register CopyReg = SubRegMI->getOperand(1).getReg(); 709 if (Register::isVirtualRegister(CopyReg)) 710 SrcMI = MRI->getVRegDef(CopyReg); 711 } 712 713 unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII); 714 if (MI.getOperand(3).getImm() <= KnownZeroCount) { 715 LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n"); 716 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 717 MI.getOperand(0).getReg()) 718 .addReg(SrcReg); 719 ToErase = &MI; 720 Simplified = true; 721 NumEliminatedZExt++; 722 } 723 break; 724 } 725 726 // TODO: Any instruction that has an immediate form fed only by a PHI 727 // whose operands are all load immediate can be folded away. We currently 728 // do this for ADD instructions, but should expand it to arithmetic and 729 // binary instructions with immediate forms in the future. 730 case PPC::ADD4: 731 case PPC::ADD8: { 732 auto isSingleUsePHI = [&](MachineOperand *PhiOp) { 733 assert(PhiOp && "Invalid Operand!"); 734 MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI); 735 736 return DefPhiMI && (DefPhiMI->getOpcode() == PPC::PHI) && 737 MRI->hasOneNonDBGUse(DefPhiMI->getOperand(0).getReg()); 738 }; 739 740 auto dominatesAllSingleUseLIs = [&](MachineOperand *DominatorOp, 741 MachineOperand *PhiOp) { 742 assert(PhiOp && "Invalid Operand!"); 743 assert(DominatorOp && "Invalid Operand!"); 744 MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI); 745 MachineInstr *DefDomMI = getVRegDefOrNull(DominatorOp, MRI); 746 747 // Note: the vregs only show up at odd indices position of PHI Node, 748 // the even indices position save the BB info. 749 for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) { 750 MachineInstr *LiMI = 751 getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI); 752 if (!LiMI || 753 (LiMI->getOpcode() != PPC::LI && LiMI->getOpcode() != PPC::LI8) 754 || !MRI->hasOneNonDBGUse(LiMI->getOperand(0).getReg()) || 755 !MDT->dominates(DefDomMI, LiMI)) 756 return false; 757 } 758 759 return true; 760 }; 761 762 MachineOperand Op1 = MI.getOperand(1); 763 MachineOperand Op2 = MI.getOperand(2); 764 if (isSingleUsePHI(&Op2) && dominatesAllSingleUseLIs(&Op1, &Op2)) 765 std::swap(Op1, Op2); 766 else if (!isSingleUsePHI(&Op1) || !dominatesAllSingleUseLIs(&Op2, &Op1)) 767 break; // We don't have an ADD fed by LI's that can be transformed 768 769 // Now we know that Op1 is the PHI node and Op2 is the dominator 770 Register DominatorReg = Op2.getReg(); 771 772 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 773 ? &PPC::G8RC_and_G8RC_NOX0RegClass 774 : &PPC::GPRC_and_GPRC_NOR0RegClass; 775 MRI->setRegClass(DominatorReg, TRC); 776 777 // replace LIs with ADDIs 778 MachineInstr *DefPhiMI = getVRegDefOrNull(&Op1, MRI); 779 for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) { 780 MachineInstr *LiMI = getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI); 781 LLVM_DEBUG(dbgs() << "Optimizing LI to ADDI: "); 782 LLVM_DEBUG(LiMI->dump()); 783 784 // There could be repeated registers in the PHI, e.g: %1 = 785 // PHI %6, <%bb.2>, %8, <%bb.3>, %8, <%bb.6>; So if we've 786 // already replaced the def instruction, skip. 787 if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8) 788 continue; 789 790 assert((LiMI->getOpcode() == PPC::LI || 791 LiMI->getOpcode() == PPC::LI8) && 792 "Invalid Opcode!"); 793 auto LiImm = LiMI->getOperand(1).getImm(); // save the imm of LI 794 LiMI->RemoveOperand(1); // remove the imm of LI 795 LiMI->setDesc(TII->get(LiMI->getOpcode() == PPC::LI ? PPC::ADDI 796 : PPC::ADDI8)); 797 MachineInstrBuilder(*LiMI->getParent()->getParent(), *LiMI) 798 .addReg(DominatorReg) 799 .addImm(LiImm); // restore the imm of LI 800 LLVM_DEBUG(LiMI->dump()); 801 } 802 803 // Replace ADD with COPY 804 LLVM_DEBUG(dbgs() << "Optimizing ADD to COPY: "); 805 LLVM_DEBUG(MI.dump()); 806 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 807 MI.getOperand(0).getReg()) 808 .add(Op1); 809 ToErase = &MI; 810 Simplified = true; 811 NumOptADDLIs++; 812 break; 813 } 814 case PPC::RLDICR: { 815 Simplified |= emitRLDICWhenLoweringJumpTables(MI) || 816 combineSEXTAndSHL(MI, ToErase); 817 break; 818 } 819 case PPC::RLWINM: 820 case PPC::RLWINMo: 821 case PPC::RLWINM8: 822 case PPC::RLWINM8o: { 823 unsigned FoldingReg = MI.getOperand(1).getReg(); 824 if (!Register::isVirtualRegister(FoldingReg)) 825 break; 826 827 MachineInstr *SrcMI = MRI->getVRegDef(FoldingReg); 828 if (SrcMI->getOpcode() != PPC::RLWINM && 829 SrcMI->getOpcode() != PPC::RLWINMo && 830 SrcMI->getOpcode() != PPC::RLWINM8 && 831 SrcMI->getOpcode() != PPC::RLWINM8o) 832 break; 833 assert((MI.getOperand(2).isImm() && MI.getOperand(3).isImm() && 834 MI.getOperand(4).isImm() && SrcMI->getOperand(2).isImm() && 835 SrcMI->getOperand(3).isImm() && SrcMI->getOperand(4).isImm()) && 836 "Invalid PPC::RLWINM Instruction!"); 837 uint64_t SHSrc = SrcMI->getOperand(2).getImm(); 838 uint64_t SHMI = MI.getOperand(2).getImm(); 839 uint64_t MBSrc = SrcMI->getOperand(3).getImm(); 840 uint64_t MBMI = MI.getOperand(3).getImm(); 841 uint64_t MESrc = SrcMI->getOperand(4).getImm(); 842 uint64_t MEMI = MI.getOperand(4).getImm(); 843 844 assert((MEMI < 32 && MESrc < 32 && MBMI < 32 && MBSrc < 32) && 845 "Invalid PPC::RLWINM Instruction!"); 846 847 // If MBMI is bigger than MEMI, we always can not get run of ones. 848 // RotatedSrcMask non-wrap: 849 // 0........31|32........63 850 // RotatedSrcMask: B---E B---E 851 // MaskMI: -----------|--E B------ 852 // Result: ----- --- (Bad candidate) 853 // 854 // RotatedSrcMask wrap: 855 // 0........31|32........63 856 // RotatedSrcMask: --E B----|--E B---- 857 // MaskMI: -----------|--E B------ 858 // Result: --- -----|--- ----- (Bad candidate) 859 // 860 // One special case is RotatedSrcMask is a full set mask. 861 // RotatedSrcMask full: 862 // 0........31|32........63 863 // RotatedSrcMask: ------EB---|-------EB--- 864 // MaskMI: -----------|--E B------ 865 // Result: -----------|--- ------- (Good candidate) 866 867 // Mark special case. 868 bool SrcMaskFull = (MBSrc - MESrc == 1) || (MBSrc == 0 && MESrc == 31); 869 870 // For other MBMI > MEMI cases, just return. 871 if ((MBMI > MEMI) && !SrcMaskFull) 872 break; 873 874 // Handle MBMI <= MEMI cases. 875 APInt MaskMI = APInt::getBitsSetWithWrap(32, 32 - MEMI - 1, 32 - MBMI); 876 // In MI, we only need low 32 bits of SrcMI, just consider about low 32 877 // bit of SrcMI mask. Note that in APInt, lowerest bit is at index 0, 878 // while in PowerPC ISA, lowerest bit is at index 63. 879 APInt MaskSrc = 880 APInt::getBitsSetWithWrap(32, 32 - MESrc - 1, 32 - MBSrc); 881 // Current APInt::getBitsSetWithWrap sets all bits to 0 if loBit is 882 // equal to highBit. 883 // If MBSrc - MESrc == 1, we expect a full set mask instead of Null. 884 if (SrcMaskFull && (MBSrc - MESrc == 1)) 885 MaskSrc.setAllBits(); 886 887 APInt RotatedSrcMask = MaskSrc.rotl(SHMI); 888 APInt FinalMask = RotatedSrcMask & MaskMI; 889 uint32_t NewMB, NewME; 890 891 // If final mask is 0, MI result should be 0 too. 892 if (FinalMask.isNullValue()) { 893 bool Is64Bit = (MI.getOpcode() == PPC::RLWINM8 || 894 MI.getOpcode() == PPC::RLWINM8o); 895 896 LLVM_DEBUG(dbgs() << "Replace Instr: "); 897 LLVM_DEBUG(MI.dump()); 898 899 if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8) { 900 // Replace MI with "LI 0" 901 MI.RemoveOperand(4); 902 MI.RemoveOperand(3); 903 MI.RemoveOperand(2); 904 MI.getOperand(1).ChangeToImmediate(0); 905 MI.setDesc(TII->get(Is64Bit ? PPC::LI8 : PPC::LI)); 906 } else { 907 // Replace MI with "ANDIo reg, 0" 908 MI.RemoveOperand(4); 909 MI.RemoveOperand(3); 910 MI.getOperand(2).setImm(0); 911 MI.setDesc(TII->get(Is64Bit ? PPC::ANDIo8 : PPC::ANDIo)); 912 } 913 Simplified = true; 914 NumRotatesCollapsed++; 915 916 LLVM_DEBUG(dbgs() << "With: "); 917 LLVM_DEBUG(MI.dump()); 918 } else if (isRunOfOnes((unsigned)(FinalMask.getZExtValue()), NewMB, 919 NewME) || SrcMaskFull) { 920 // If FoldingReg has only one use and it it not RLWINMo and 921 // RLWINM8o, safe to delete its def SrcMI. Otherwise keep it. 922 if (MRI->hasOneNonDBGUse(FoldingReg) && 923 (SrcMI->getOpcode() == PPC::RLWINM || 924 SrcMI->getOpcode() == PPC::RLWINM8)) { 925 ToErase = SrcMI; 926 LLVM_DEBUG(dbgs() << "Delete dead instruction: "); 927 LLVM_DEBUG(SrcMI->dump()); 928 } 929 930 LLVM_DEBUG(dbgs() << "Converting Instr: "); 931 LLVM_DEBUG(MI.dump()); 932 933 uint16_t NewSH = (SHSrc + SHMI) % 32; 934 MI.getOperand(2).setImm(NewSH); 935 // If SrcMI mask is full, no need to update MBMI and MEMI. 936 if (!SrcMaskFull) { 937 MI.getOperand(3).setImm(NewMB); 938 MI.getOperand(4).setImm(NewME); 939 } 940 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); 941 if (SrcMI->getOperand(1).isKill()) { 942 MI.getOperand(1).setIsKill(true); 943 SrcMI->getOperand(1).setIsKill(false); 944 } else 945 // About to replace MI.getOperand(1), clear its kill flag. 946 MI.getOperand(1).setIsKill(false); 947 948 Simplified = true; 949 NumRotatesCollapsed++; 950 951 LLVM_DEBUG(dbgs() << "To: "); 952 LLVM_DEBUG(MI.dump()); 953 } 954 break; 955 } 956 } 957 } 958 959 // If the last instruction was marked for elimination, 960 // remove it now. 961 if (ToErase) { 962 ToErase->eraseFromParent(); 963 ToErase = nullptr; 964 } 965 } 966 967 // Eliminate all the TOC save instructions which are redundant. 968 Simplified |= eliminateRedundantTOCSaves(TOCSaves); 969 PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>(); 970 if (FI->mustSaveTOC()) 971 NumTOCSavesInPrologue++; 972 973 // We try to eliminate redundant compare instruction. 974 Simplified |= eliminateRedundantCompare(); 975 976 return Simplified; 977 } 978 979 // helper functions for eliminateRedundantCompare 980 static bool isEqOrNe(MachineInstr *BI) { 981 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); 982 unsigned PredCond = PPC::getPredicateCondition(Pred); 983 return (PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE); 984 } 985 986 static bool isSupportedCmpOp(unsigned opCode) { 987 return (opCode == PPC::CMPLD || opCode == PPC::CMPD || 988 opCode == PPC::CMPLW || opCode == PPC::CMPW || 989 opCode == PPC::CMPLDI || opCode == PPC::CMPDI || 990 opCode == PPC::CMPLWI || opCode == PPC::CMPWI); 991 } 992 993 static bool is64bitCmpOp(unsigned opCode) { 994 return (opCode == PPC::CMPLD || opCode == PPC::CMPD || 995 opCode == PPC::CMPLDI || opCode == PPC::CMPDI); 996 } 997 998 static bool isSignedCmpOp(unsigned opCode) { 999 return (opCode == PPC::CMPD || opCode == PPC::CMPW || 1000 opCode == PPC::CMPDI || opCode == PPC::CMPWI); 1001 } 1002 1003 static unsigned getSignedCmpOpCode(unsigned opCode) { 1004 if (opCode == PPC::CMPLD) return PPC::CMPD; 1005 if (opCode == PPC::CMPLW) return PPC::CMPW; 1006 if (opCode == PPC::CMPLDI) return PPC::CMPDI; 1007 if (opCode == PPC::CMPLWI) return PPC::CMPWI; 1008 return opCode; 1009 } 1010 1011 // We can decrement immediate x in (GE x) by changing it to (GT x-1) or 1012 // (LT x) to (LE x-1) 1013 static unsigned getPredicateToDecImm(MachineInstr *BI, MachineInstr *CMPI) { 1014 uint64_t Imm = CMPI->getOperand(2).getImm(); 1015 bool SignedCmp = isSignedCmpOp(CMPI->getOpcode()); 1016 if ((!SignedCmp && Imm == 0) || (SignedCmp && Imm == 0x8000)) 1017 return 0; 1018 1019 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); 1020 unsigned PredCond = PPC::getPredicateCondition(Pred); 1021 unsigned PredHint = PPC::getPredicateHint(Pred); 1022 if (PredCond == PPC::PRED_GE) 1023 return PPC::getPredicate(PPC::PRED_GT, PredHint); 1024 if (PredCond == PPC::PRED_LT) 1025 return PPC::getPredicate(PPC::PRED_LE, PredHint); 1026 1027 return 0; 1028 } 1029 1030 // We can increment immediate x in (GT x) by changing it to (GE x+1) or 1031 // (LE x) to (LT x+1) 1032 static unsigned getPredicateToIncImm(MachineInstr *BI, MachineInstr *CMPI) { 1033 uint64_t Imm = CMPI->getOperand(2).getImm(); 1034 bool SignedCmp = isSignedCmpOp(CMPI->getOpcode()); 1035 if ((!SignedCmp && Imm == 0xFFFF) || (SignedCmp && Imm == 0x7FFF)) 1036 return 0; 1037 1038 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); 1039 unsigned PredCond = PPC::getPredicateCondition(Pred); 1040 unsigned PredHint = PPC::getPredicateHint(Pred); 1041 if (PredCond == PPC::PRED_GT) 1042 return PPC::getPredicate(PPC::PRED_GE, PredHint); 1043 if (PredCond == PPC::PRED_LE) 1044 return PPC::getPredicate(PPC::PRED_LT, PredHint); 1045 1046 return 0; 1047 } 1048 1049 // This takes a Phi node and returns a register value for the specified BB. 1050 static unsigned getIncomingRegForBlock(MachineInstr *Phi, 1051 MachineBasicBlock *MBB) { 1052 for (unsigned I = 2, E = Phi->getNumOperands() + 1; I != E; I += 2) { 1053 MachineOperand &MO = Phi->getOperand(I); 1054 if (MO.getMBB() == MBB) 1055 return Phi->getOperand(I-1).getReg(); 1056 } 1057 llvm_unreachable("invalid src basic block for this Phi node\n"); 1058 return 0; 1059 } 1060 1061 // This function tracks the source of the register through register copy. 1062 // If BB1 and BB2 are non-NULL, we also track PHI instruction in BB2 1063 // assuming that the control comes from BB1 into BB2. 1064 static unsigned getSrcVReg(unsigned Reg, MachineBasicBlock *BB1, 1065 MachineBasicBlock *BB2, MachineRegisterInfo *MRI) { 1066 unsigned SrcReg = Reg; 1067 while (1) { 1068 unsigned NextReg = SrcReg; 1069 MachineInstr *Inst = MRI->getVRegDef(SrcReg); 1070 if (BB1 && Inst->getOpcode() == PPC::PHI && Inst->getParent() == BB2) { 1071 NextReg = getIncomingRegForBlock(Inst, BB1); 1072 // We track through PHI only once to avoid infinite loop. 1073 BB1 = nullptr; 1074 } 1075 else if (Inst->isFullCopy()) 1076 NextReg = Inst->getOperand(1).getReg(); 1077 if (NextReg == SrcReg || !Register::isVirtualRegister(NextReg)) 1078 break; 1079 SrcReg = NextReg; 1080 } 1081 return SrcReg; 1082 } 1083 1084 static bool eligibleForCompareElimination(MachineBasicBlock &MBB, 1085 MachineBasicBlock *&PredMBB, 1086 MachineBasicBlock *&MBBtoMoveCmp, 1087 MachineRegisterInfo *MRI) { 1088 1089 auto isEligibleBB = [&](MachineBasicBlock &BB) { 1090 auto BII = BB.getFirstInstrTerminator(); 1091 // We optimize BBs ending with a conditional branch. 1092 // We check only for BCC here, not BCCLR, because BCCLR 1093 // will be formed only later in the pipeline. 1094 if (BB.succ_size() == 2 && 1095 BII != BB.instr_end() && 1096 (*BII).getOpcode() == PPC::BCC && 1097 (*BII).getOperand(1).isReg()) { 1098 // We optimize only if the condition code is used only by one BCC. 1099 Register CndReg = (*BII).getOperand(1).getReg(); 1100 if (!Register::isVirtualRegister(CndReg) || !MRI->hasOneNonDBGUse(CndReg)) 1101 return false; 1102 1103 MachineInstr *CMPI = MRI->getVRegDef(CndReg); 1104 // We assume compare and branch are in the same BB for ease of analysis. 1105 if (CMPI->getParent() != &BB) 1106 return false; 1107 1108 // We skip this BB if a physical register is used in comparison. 1109 for (MachineOperand &MO : CMPI->operands()) 1110 if (MO.isReg() && !Register::isVirtualRegister(MO.getReg())) 1111 return false; 1112 1113 return true; 1114 } 1115 return false; 1116 }; 1117 1118 // If this BB has more than one successor, we can create a new BB and 1119 // move the compare instruction in the new BB. 1120 // So far, we do not move compare instruction to a BB having multiple 1121 // successors to avoid potentially increasing code size. 1122 auto isEligibleForMoveCmp = [](MachineBasicBlock &BB) { 1123 return BB.succ_size() == 1; 1124 }; 1125 1126 if (!isEligibleBB(MBB)) 1127 return false; 1128 1129 unsigned NumPredBBs = MBB.pred_size(); 1130 if (NumPredBBs == 1) { 1131 MachineBasicBlock *TmpMBB = *MBB.pred_begin(); 1132 if (isEligibleBB(*TmpMBB)) { 1133 PredMBB = TmpMBB; 1134 MBBtoMoveCmp = nullptr; 1135 return true; 1136 } 1137 } 1138 else if (NumPredBBs == 2) { 1139 // We check for partially redundant case. 1140 // So far, we support cases with only two predecessors 1141 // to avoid increasing the number of instructions. 1142 MachineBasicBlock::pred_iterator PI = MBB.pred_begin(); 1143 MachineBasicBlock *Pred1MBB = *PI; 1144 MachineBasicBlock *Pred2MBB = *(PI+1); 1145 1146 if (isEligibleBB(*Pred1MBB) && isEligibleForMoveCmp(*Pred2MBB)) { 1147 // We assume Pred1MBB is the BB containing the compare to be merged and 1148 // Pred2MBB is the BB to which we will append a compare instruction. 1149 // Hence we can proceed as is. 1150 } 1151 else if (isEligibleBB(*Pred2MBB) && isEligibleForMoveCmp(*Pred1MBB)) { 1152 // We need to swap Pred1MBB and Pred2MBB to canonicalize. 1153 std::swap(Pred1MBB, Pred2MBB); 1154 } 1155 else return false; 1156 1157 // Here, Pred2MBB is the BB to which we need to append a compare inst. 1158 // We cannot move the compare instruction if operands are not available 1159 // in Pred2MBB (i.e. defined in MBB by an instruction other than PHI). 1160 MachineInstr *BI = &*MBB.getFirstInstrTerminator(); 1161 MachineInstr *CMPI = MRI->getVRegDef(BI->getOperand(1).getReg()); 1162 for (int I = 1; I <= 2; I++) 1163 if (CMPI->getOperand(I).isReg()) { 1164 MachineInstr *Inst = MRI->getVRegDef(CMPI->getOperand(I).getReg()); 1165 if (Inst->getParent() == &MBB && Inst->getOpcode() != PPC::PHI) 1166 return false; 1167 } 1168 1169 PredMBB = Pred1MBB; 1170 MBBtoMoveCmp = Pred2MBB; 1171 return true; 1172 } 1173 1174 return false; 1175 } 1176 1177 // This function will iterate over the input map containing a pair of TOC save 1178 // instruction and a flag. The flag will be set to false if the TOC save is 1179 // proven redundant. This function will erase from the basic block all the TOC 1180 // saves marked as redundant. 1181 bool PPCMIPeephole::eliminateRedundantTOCSaves( 1182 std::map<MachineInstr *, bool> &TOCSaves) { 1183 bool Simplified = false; 1184 int NumKept = 0; 1185 for (auto TOCSave : TOCSaves) { 1186 if (!TOCSave.second) { 1187 TOCSave.first->eraseFromParent(); 1188 RemoveTOCSave++; 1189 Simplified = true; 1190 } else { 1191 NumKept++; 1192 } 1193 } 1194 1195 if (NumKept > 1) 1196 MultiTOCSaves++; 1197 1198 return Simplified; 1199 } 1200 1201 // If multiple conditional branches are executed based on the (essentially) 1202 // same comparison, we merge compare instructions into one and make multiple 1203 // conditional branches on this comparison. 1204 // For example, 1205 // if (a == 0) { ... } 1206 // else if (a < 0) { ... } 1207 // can be executed by one compare and two conditional branches instead of 1208 // two pairs of a compare and a conditional branch. 1209 // 1210 // This method merges two compare instructions in two MBBs and modifies the 1211 // compare and conditional branch instructions if needed. 1212 // For the above example, the input for this pass looks like: 1213 // cmplwi r3, 0 1214 // beq 0, .LBB0_3 1215 // cmpwi r3, -1 1216 // bgt 0, .LBB0_4 1217 // So, before merging two compares, we need to modify these instructions as 1218 // cmpwi r3, 0 ; cmplwi and cmpwi yield same result for beq 1219 // beq 0, .LBB0_3 1220 // cmpwi r3, 0 ; greather than -1 means greater or equal to 0 1221 // bge 0, .LBB0_4 1222 1223 bool PPCMIPeephole::eliminateRedundantCompare(void) { 1224 bool Simplified = false; 1225 1226 for (MachineBasicBlock &MBB2 : *MF) { 1227 MachineBasicBlock *MBB1 = nullptr, *MBBtoMoveCmp = nullptr; 1228 1229 // For fully redundant case, we select two basic blocks MBB1 and MBB2 1230 // as an optimization target if 1231 // - both MBBs end with a conditional branch, 1232 // - MBB1 is the only predecessor of MBB2, and 1233 // - compare does not take a physical register as a operand in both MBBs. 1234 // In this case, eligibleForCompareElimination sets MBBtoMoveCmp nullptr. 1235 // 1236 // As partially redundant case, we additionally handle if MBB2 has one 1237 // additional predecessor, which has only one successor (MBB2). 1238 // In this case, we move the compare instruction originally in MBB2 into 1239 // MBBtoMoveCmp. This partially redundant case is typically appear by 1240 // compiling a while loop; here, MBBtoMoveCmp is the loop preheader. 1241 // 1242 // Overview of CFG of related basic blocks 1243 // Fully redundant case Partially redundant case 1244 // -------- ---------------- -------- 1245 // | MBB1 | (w/ 2 succ) | MBBtoMoveCmp | | MBB1 | (w/ 2 succ) 1246 // -------- ---------------- -------- 1247 // | \ (w/ 1 succ) \ | \ 1248 // | \ \ | \ 1249 // | \ | 1250 // -------- -------- 1251 // | MBB2 | (w/ 1 pred | MBB2 | (w/ 2 pred 1252 // -------- and 2 succ) -------- and 2 succ) 1253 // | \ | \ 1254 // | \ | \ 1255 // 1256 if (!eligibleForCompareElimination(MBB2, MBB1, MBBtoMoveCmp, MRI)) 1257 continue; 1258 1259 MachineInstr *BI1 = &*MBB1->getFirstInstrTerminator(); 1260 MachineInstr *CMPI1 = MRI->getVRegDef(BI1->getOperand(1).getReg()); 1261 1262 MachineInstr *BI2 = &*MBB2.getFirstInstrTerminator(); 1263 MachineInstr *CMPI2 = MRI->getVRegDef(BI2->getOperand(1).getReg()); 1264 bool IsPartiallyRedundant = (MBBtoMoveCmp != nullptr); 1265 1266 // We cannot optimize an unsupported compare opcode or 1267 // a mix of 32-bit and 64-bit comaprisons 1268 if (!isSupportedCmpOp(CMPI1->getOpcode()) || 1269 !isSupportedCmpOp(CMPI2->getOpcode()) || 1270 is64bitCmpOp(CMPI1->getOpcode()) != is64bitCmpOp(CMPI2->getOpcode())) 1271 continue; 1272 1273 unsigned NewOpCode = 0; 1274 unsigned NewPredicate1 = 0, NewPredicate2 = 0; 1275 int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0; 1276 bool SwapOperands = false; 1277 1278 if (CMPI1->getOpcode() != CMPI2->getOpcode()) { 1279 // Typically, unsigned comparison is used for equality check, but 1280 // we replace it with a signed comparison if the comparison 1281 // to be merged is a signed comparison. 1282 // In other cases of opcode mismatch, we cannot optimize this. 1283 1284 // We cannot change opcode when comparing against an immediate 1285 // if the most significant bit of the immediate is one 1286 // due to the difference in sign extension. 1287 auto CmpAgainstImmWithSignBit = [](MachineInstr *I) { 1288 if (!I->getOperand(2).isImm()) 1289 return false; 1290 int16_t Imm = (int16_t)I->getOperand(2).getImm(); 1291 return Imm < 0; 1292 }; 1293 1294 if (isEqOrNe(BI2) && !CmpAgainstImmWithSignBit(CMPI2) && 1295 CMPI1->getOpcode() == getSignedCmpOpCode(CMPI2->getOpcode())) 1296 NewOpCode = CMPI1->getOpcode(); 1297 else if (isEqOrNe(BI1) && !CmpAgainstImmWithSignBit(CMPI1) && 1298 getSignedCmpOpCode(CMPI1->getOpcode()) == CMPI2->getOpcode()) 1299 NewOpCode = CMPI2->getOpcode(); 1300 else continue; 1301 } 1302 1303 if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) { 1304 // In case of comparisons between two registers, these two registers 1305 // must be same to merge two comparisons. 1306 unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(), 1307 nullptr, nullptr, MRI); 1308 unsigned Cmp1Operand2 = getSrcVReg(CMPI1->getOperand(2).getReg(), 1309 nullptr, nullptr, MRI); 1310 unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(), 1311 MBB1, &MBB2, MRI); 1312 unsigned Cmp2Operand2 = getSrcVReg(CMPI2->getOperand(2).getReg(), 1313 MBB1, &MBB2, MRI); 1314 1315 if (Cmp1Operand1 == Cmp2Operand1 && Cmp1Operand2 == Cmp2Operand2) { 1316 // Same pair of registers in the same order; ready to merge as is. 1317 } 1318 else if (Cmp1Operand1 == Cmp2Operand2 && Cmp1Operand2 == Cmp2Operand1) { 1319 // Same pair of registers in different order. 1320 // We reverse the predicate to merge compare instructions. 1321 PPC::Predicate Pred = (PPC::Predicate)BI2->getOperand(0).getImm(); 1322 NewPredicate2 = (unsigned)PPC::getSwappedPredicate(Pred); 1323 // In case of partial redundancy, we need to swap operands 1324 // in another compare instruction. 1325 SwapOperands = true; 1326 } 1327 else continue; 1328 } 1329 else if (CMPI1->getOperand(2).isImm() && CMPI2->getOperand(2).isImm()) { 1330 // In case of comparisons between a register and an immediate, 1331 // the operand register must be same for two compare instructions. 1332 unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(), 1333 nullptr, nullptr, MRI); 1334 unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(), 1335 MBB1, &MBB2, MRI); 1336 if (Cmp1Operand1 != Cmp2Operand1) 1337 continue; 1338 1339 NewImm1 = Imm1 = (int16_t)CMPI1->getOperand(2).getImm(); 1340 NewImm2 = Imm2 = (int16_t)CMPI2->getOperand(2).getImm(); 1341 1342 // If immediate are not same, we try to adjust by changing predicate; 1343 // e.g. GT imm means GE (imm+1). 1344 if (Imm1 != Imm2 && (!isEqOrNe(BI2) || !isEqOrNe(BI1))) { 1345 int Diff = Imm1 - Imm2; 1346 if (Diff < -2 || Diff > 2) 1347 continue; 1348 1349 unsigned PredToInc1 = getPredicateToIncImm(BI1, CMPI1); 1350 unsigned PredToDec1 = getPredicateToDecImm(BI1, CMPI1); 1351 unsigned PredToInc2 = getPredicateToIncImm(BI2, CMPI2); 1352 unsigned PredToDec2 = getPredicateToDecImm(BI2, CMPI2); 1353 if (Diff == 2) { 1354 if (PredToInc2 && PredToDec1) { 1355 NewPredicate2 = PredToInc2; 1356 NewPredicate1 = PredToDec1; 1357 NewImm2++; 1358 NewImm1--; 1359 } 1360 } 1361 else if (Diff == 1) { 1362 if (PredToInc2) { 1363 NewImm2++; 1364 NewPredicate2 = PredToInc2; 1365 } 1366 else if (PredToDec1) { 1367 NewImm1--; 1368 NewPredicate1 = PredToDec1; 1369 } 1370 } 1371 else if (Diff == -1) { 1372 if (PredToDec2) { 1373 NewImm2--; 1374 NewPredicate2 = PredToDec2; 1375 } 1376 else if (PredToInc1) { 1377 NewImm1++; 1378 NewPredicate1 = PredToInc1; 1379 } 1380 } 1381 else if (Diff == -2) { 1382 if (PredToDec2 && PredToInc1) { 1383 NewPredicate2 = PredToDec2; 1384 NewPredicate1 = PredToInc1; 1385 NewImm2--; 1386 NewImm1++; 1387 } 1388 } 1389 } 1390 1391 // We cannot merge two compares if the immediates are not same. 1392 if (NewImm2 != NewImm1) 1393 continue; 1394 } 1395 1396 LLVM_DEBUG(dbgs() << "Optimize two pairs of compare and branch:\n"); 1397 LLVM_DEBUG(CMPI1->dump()); 1398 LLVM_DEBUG(BI1->dump()); 1399 LLVM_DEBUG(CMPI2->dump()); 1400 LLVM_DEBUG(BI2->dump()); 1401 1402 // We adjust opcode, predicates and immediate as we determined above. 1403 if (NewOpCode != 0 && NewOpCode != CMPI1->getOpcode()) { 1404 CMPI1->setDesc(TII->get(NewOpCode)); 1405 } 1406 if (NewPredicate1) { 1407 BI1->getOperand(0).setImm(NewPredicate1); 1408 } 1409 if (NewPredicate2) { 1410 BI2->getOperand(0).setImm(NewPredicate2); 1411 } 1412 if (NewImm1 != Imm1) { 1413 CMPI1->getOperand(2).setImm(NewImm1); 1414 } 1415 1416 if (IsPartiallyRedundant) { 1417 // We touch up the compare instruction in MBB2 and move it to 1418 // a previous BB to handle partially redundant case. 1419 if (SwapOperands) { 1420 Register Op1 = CMPI2->getOperand(1).getReg(); 1421 Register Op2 = CMPI2->getOperand(2).getReg(); 1422 CMPI2->getOperand(1).setReg(Op2); 1423 CMPI2->getOperand(2).setReg(Op1); 1424 } 1425 if (NewImm2 != Imm2) 1426 CMPI2->getOperand(2).setImm(NewImm2); 1427 1428 for (int I = 1; I <= 2; I++) { 1429 if (CMPI2->getOperand(I).isReg()) { 1430 MachineInstr *Inst = MRI->getVRegDef(CMPI2->getOperand(I).getReg()); 1431 if (Inst->getParent() != &MBB2) 1432 continue; 1433 1434 assert(Inst->getOpcode() == PPC::PHI && 1435 "We cannot support if an operand comes from this BB."); 1436 unsigned SrcReg = getIncomingRegForBlock(Inst, MBBtoMoveCmp); 1437 CMPI2->getOperand(I).setReg(SrcReg); 1438 } 1439 } 1440 auto I = MachineBasicBlock::iterator(MBBtoMoveCmp->getFirstTerminator()); 1441 MBBtoMoveCmp->splice(I, &MBB2, MachineBasicBlock::iterator(CMPI2)); 1442 1443 DebugLoc DL = CMPI2->getDebugLoc(); 1444 Register NewVReg = MRI->createVirtualRegister(&PPC::CRRCRegClass); 1445 BuildMI(MBB2, MBB2.begin(), DL, 1446 TII->get(PPC::PHI), NewVReg) 1447 .addReg(BI1->getOperand(1).getReg()).addMBB(MBB1) 1448 .addReg(BI2->getOperand(1).getReg()).addMBB(MBBtoMoveCmp); 1449 BI2->getOperand(1).setReg(NewVReg); 1450 } 1451 else { 1452 // We finally eliminate compare instruction in MBB2. 1453 BI2->getOperand(1).setReg(BI1->getOperand(1).getReg()); 1454 CMPI2->eraseFromParent(); 1455 } 1456 BI2->getOperand(1).setIsKill(true); 1457 BI1->getOperand(1).setIsKill(false); 1458 1459 LLVM_DEBUG(dbgs() << "into a compare and two branches:\n"); 1460 LLVM_DEBUG(CMPI1->dump()); 1461 LLVM_DEBUG(BI1->dump()); 1462 LLVM_DEBUG(BI2->dump()); 1463 if (IsPartiallyRedundant) { 1464 LLVM_DEBUG(dbgs() << "The following compare is moved into " 1465 << printMBBReference(*MBBtoMoveCmp) 1466 << " to handle partial redundancy.\n"); 1467 LLVM_DEBUG(CMPI2->dump()); 1468 } 1469 1470 Simplified = true; 1471 } 1472 1473 return Simplified; 1474 } 1475 1476 // We miss the opportunity to emit an RLDIC when lowering jump tables 1477 // since ISEL sees only a single basic block. When selecting, the clear 1478 // and shift left will be in different blocks. 1479 bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) { 1480 if (MI.getOpcode() != PPC::RLDICR) 1481 return false; 1482 1483 Register SrcReg = MI.getOperand(1).getReg(); 1484 if (!Register::isVirtualRegister(SrcReg)) 1485 return false; 1486 1487 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 1488 if (SrcMI->getOpcode() != PPC::RLDICL) 1489 return false; 1490 1491 MachineOperand MOpSHSrc = SrcMI->getOperand(2); 1492 MachineOperand MOpMBSrc = SrcMI->getOperand(3); 1493 MachineOperand MOpSHMI = MI.getOperand(2); 1494 MachineOperand MOpMEMI = MI.getOperand(3); 1495 if (!(MOpSHSrc.isImm() && MOpMBSrc.isImm() && MOpSHMI.isImm() && 1496 MOpMEMI.isImm())) 1497 return false; 1498 1499 uint64_t SHSrc = MOpSHSrc.getImm(); 1500 uint64_t MBSrc = MOpMBSrc.getImm(); 1501 uint64_t SHMI = MOpSHMI.getImm(); 1502 uint64_t MEMI = MOpMEMI.getImm(); 1503 uint64_t NewSH = SHSrc + SHMI; 1504 uint64_t NewMB = MBSrc - SHMI; 1505 if (NewMB > 63 || NewSH > 63) 1506 return false; 1507 1508 // The bits cleared with RLDICL are [0, MBSrc). 1509 // The bits cleared with RLDICR are (MEMI, 63]. 1510 // After the sequence, the bits cleared are: 1511 // [0, MBSrc-SHMI) and (MEMI, 63). 1512 // 1513 // The bits cleared with RLDIC are [0, NewMB) and (63-NewSH, 63]. 1514 if ((63 - NewSH) != MEMI) 1515 return false; 1516 1517 LLVM_DEBUG(dbgs() << "Converting pair: "); 1518 LLVM_DEBUG(SrcMI->dump()); 1519 LLVM_DEBUG(MI.dump()); 1520 1521 MI.setDesc(TII->get(PPC::RLDIC)); 1522 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); 1523 MI.getOperand(2).setImm(NewSH); 1524 MI.getOperand(3).setImm(NewMB); 1525 1526 LLVM_DEBUG(dbgs() << "To: "); 1527 LLVM_DEBUG(MI.dump()); 1528 NumRotatesCollapsed++; 1529 return true; 1530 } 1531 1532 // For case in LLVM IR 1533 // entry: 1534 // %iconv = sext i32 %index to i64 1535 // br i1 undef label %true, label %false 1536 // true: 1537 // %ptr = getelementptr inbounds i32, i32* null, i64 %iconv 1538 // ... 1539 // PPCISelLowering::combineSHL fails to combine, because sext and shl are in 1540 // different BBs when conducting instruction selection. We can do a peephole 1541 // optimization to combine these two instructions into extswsli after 1542 // instruction selection. 1543 bool PPCMIPeephole::combineSEXTAndSHL(MachineInstr &MI, 1544 MachineInstr *&ToErase) { 1545 if (MI.getOpcode() != PPC::RLDICR) 1546 return false; 1547 1548 if (!MF->getSubtarget<PPCSubtarget>().isISA3_0()) 1549 return false; 1550 1551 assert(MI.getNumOperands() == 4 && "RLDICR should have 4 operands"); 1552 1553 MachineOperand MOpSHMI = MI.getOperand(2); 1554 MachineOperand MOpMEMI = MI.getOperand(3); 1555 if (!(MOpSHMI.isImm() && MOpMEMI.isImm())) 1556 return false; 1557 1558 uint64_t SHMI = MOpSHMI.getImm(); 1559 uint64_t MEMI = MOpMEMI.getImm(); 1560 if (SHMI + MEMI != 63) 1561 return false; 1562 1563 Register SrcReg = MI.getOperand(1).getReg(); 1564 if (!Register::isVirtualRegister(SrcReg)) 1565 return false; 1566 1567 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 1568 if (SrcMI->getOpcode() != PPC::EXTSW && 1569 SrcMI->getOpcode() != PPC::EXTSW_32_64) 1570 return false; 1571 1572 // If the register defined by extsw has more than one use, combination is not 1573 // needed. 1574 if (!MRI->hasOneNonDBGUse(SrcReg)) 1575 return false; 1576 1577 assert(SrcMI->getNumOperands() == 2 && "EXTSW should have 2 operands"); 1578 assert(SrcMI->getOperand(1).isReg() && 1579 "EXTSW's second operand should be a register"); 1580 if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg())) 1581 return false; 1582 1583 LLVM_DEBUG(dbgs() << "Combining pair: "); 1584 LLVM_DEBUG(SrcMI->dump()); 1585 LLVM_DEBUG(MI.dump()); 1586 1587 MachineInstr *NewInstr = 1588 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), 1589 SrcMI->getOpcode() == PPC::EXTSW ? TII->get(PPC::EXTSWSLI) 1590 : TII->get(PPC::EXTSWSLI_32_64), 1591 MI.getOperand(0).getReg()) 1592 .add(SrcMI->getOperand(1)) 1593 .add(MOpSHMI); 1594 (void)NewInstr; 1595 1596 LLVM_DEBUG(dbgs() << "TO: "); 1597 LLVM_DEBUG(NewInstr->dump()); 1598 ++NumEXTSWAndSLDICombined; 1599 ToErase = &MI; 1600 // SrcMI, which is extsw, is of no use now, erase it. 1601 SrcMI->eraseFromParent(); 1602 return true; 1603 } 1604 1605 } // end default namespace 1606 1607 INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE, 1608 "PowerPC MI Peephole Optimization", false, false) 1609 INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfo) 1610 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) 1611 INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree) 1612 INITIALIZE_PASS_END(PPCMIPeephole, DEBUG_TYPE, 1613 "PowerPC MI Peephole Optimization", false, false) 1614 1615 char PPCMIPeephole::ID = 0; 1616 FunctionPass* 1617 llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); } 1618 1619