1 //===-------------- PPCMIPeephole.cpp - MI Peephole Cleanups -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===---------------------------------------------------------------------===// 9 // 10 // This pass performs peephole optimizations to clean up ugly code 11 // sequences at the MachineInstruction layer. It runs at the end of 12 // the SSA phases, following VSX swap removal. A pass of dead code 13 // elimination follows this one for quick clean-up of any dead 14 // instructions introduced here. Although we could do this as callbacks 15 // from the generic peephole pass, this would have a couple of bad 16 // effects: it might remove optimization opportunities for VSX swap 17 // removal, and it would miss cleanups made possible following VSX 18 // swap removal. 19 // 20 //===---------------------------------------------------------------------===// 21 22 #include "PPCInstrInfo.h" 23 #include "PPC.h" 24 #include "PPCInstrBuilder.h" 25 #include "PPCTargetMachine.h" 26 #include "llvm/CodeGen/MachineFunctionPass.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/Support/Debug.h" 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "ppc-mi-peepholes" 34 35 namespace llvm { 36 void initializePPCMIPeepholePass(PassRegistry&); 37 } 38 39 namespace { 40 41 struct PPCMIPeephole : public MachineFunctionPass { 42 43 static char ID; 44 const PPCInstrInfo *TII; 45 MachineFunction *MF; 46 MachineRegisterInfo *MRI; 47 48 PPCMIPeephole() : MachineFunctionPass(ID) { 49 initializePPCMIPeepholePass(*PassRegistry::getPassRegistry()); 50 } 51 52 private: 53 // Initialize class variables. 54 void initialize(MachineFunction &MFParm); 55 56 // Perform peepholes. 57 bool simplifyCode(void); 58 59 // Find the "true" register represented by SrcReg (following chains 60 // of copies and subreg_to_reg operations). 61 unsigned lookThruCopyLike(unsigned SrcReg); 62 63 public: 64 // Main entry point for this pass. 65 bool runOnMachineFunction(MachineFunction &MF) override { 66 if (skipFunction(*MF.getFunction())) 67 return false; 68 initialize(MF); 69 return simplifyCode(); 70 } 71 }; 72 73 // Initialize class variables. 74 void PPCMIPeephole::initialize(MachineFunction &MFParm) { 75 MF = &MFParm; 76 MRI = &MF->getRegInfo(); 77 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo(); 78 DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n"); 79 DEBUG(MF->dump()); 80 } 81 82 // Perform peephole optimizations. 83 bool PPCMIPeephole::simplifyCode(void) { 84 bool Simplified = false; 85 MachineInstr* ToErase = nullptr; 86 87 for (MachineBasicBlock &MBB : *MF) { 88 for (MachineInstr &MI : MBB) { 89 90 // If the previous instruction was marked for elimination, 91 // remove it now. 92 if (ToErase) { 93 ToErase->eraseFromParent(); 94 ToErase = nullptr; 95 } 96 97 // Ignore debug instructions. 98 if (MI.isDebugValue()) 99 continue; 100 101 // Per-opcode peepholes. 102 switch (MI.getOpcode()) { 103 104 default: 105 break; 106 107 case PPC::XXPERMDI: { 108 // Perform simplifications of 2x64 vector swaps and splats. 109 // A swap is identified by an immediate value of 2, and a splat 110 // is identified by an immediate value of 0 or 3. 111 int Immed = MI.getOperand(3).getImm(); 112 113 if (Immed != 1) { 114 115 // For each of these simplifications, we need the two source 116 // regs to match. Unfortunately, MachineCSE ignores COPY and 117 // SUBREG_TO_REG, so for example we can see 118 // XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), immed. 119 // We have to look through chains of COPY and SUBREG_TO_REG 120 // to find the real source values for comparison. 121 unsigned TrueReg1 = lookThruCopyLike(MI.getOperand(1).getReg()); 122 unsigned TrueReg2 = lookThruCopyLike(MI.getOperand(2).getReg()); 123 124 if (TrueReg1 == TrueReg2 125 && TargetRegisterInfo::isVirtualRegister(TrueReg1)) { 126 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); 127 128 // If this is a splat or a swap fed by another splat, we 129 // can replace it with a copy. 130 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) { 131 unsigned FeedImmed = DefMI->getOperand(3).getImm(); 132 unsigned FeedReg1 133 = lookThruCopyLike(DefMI->getOperand(1).getReg()); 134 unsigned FeedReg2 135 = lookThruCopyLike(DefMI->getOperand(2).getReg()); 136 137 if ((FeedImmed == 0 || FeedImmed == 3) && FeedReg1 == FeedReg2) { 138 DEBUG(dbgs() 139 << "Optimizing splat/swap or splat/splat " 140 "to splat/copy: "); 141 DEBUG(MI.dump()); 142 BuildMI(MBB, &MI, MI.getDebugLoc(), 143 TII->get(PPC::COPY), MI.getOperand(0).getReg()) 144 .addOperand(MI.getOperand(1)); 145 ToErase = &MI; 146 Simplified = true; 147 } 148 149 // If this is a splat fed by a swap, we can simplify modify 150 // the splat to splat the other value from the swap's input 151 // parameter. 152 else if ((Immed == 0 || Immed == 3) 153 && FeedImmed == 2 && FeedReg1 == FeedReg2) { 154 DEBUG(dbgs() << "Optimizing swap/splat => splat: "); 155 DEBUG(MI.dump()); 156 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg()); 157 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg()); 158 MI.getOperand(3).setImm(3 - Immed); 159 Simplified = true; 160 } 161 162 // If this is a swap fed by a swap, we can replace it 163 // with a copy from the first swap's input. 164 else if (Immed == 2 && FeedImmed == 2 && FeedReg1 == FeedReg2) { 165 DEBUG(dbgs() << "Optimizing swap/swap => copy: "); 166 DEBUG(MI.dump()); 167 BuildMI(MBB, &MI, MI.getDebugLoc(), 168 TII->get(PPC::COPY), MI.getOperand(0).getReg()) 169 .addOperand(DefMI->getOperand(1)); 170 ToErase = &MI; 171 Simplified = true; 172 } 173 } else if ((Immed == 0 || Immed == 3) && 174 DefMI && DefMI->getOpcode() == PPC::XXPERMDIs) { 175 // Splat fed by another splat - switch the output of the first 176 // and remove the second. 177 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 178 ToErase = &MI; 179 Simplified = true; 180 DEBUG(dbgs() << "Removing redundant splat: "); 181 DEBUG(MI.dump()); 182 } 183 } 184 } 185 break; 186 } 187 case PPC::VSPLTB: 188 case PPC::VSPLTH: 189 case PPC::XXSPLTW: { 190 unsigned MyOpcode = MI.getOpcode(); 191 unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2; 192 unsigned TrueReg = lookThruCopyLike(MI.getOperand(OpNo).getReg()); 193 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); 194 if (!DefMI) 195 break; 196 unsigned DefOpcode = DefMI->getOpcode(); 197 bool SameOpcode = (MyOpcode == DefOpcode) || 198 (MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) || 199 (MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) || 200 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs); 201 // Splat fed by another splat - switch the output of the first 202 // and remove the second. 203 if (SameOpcode) { 204 DEBUG(dbgs() << "Changing redundant splat to a copy: "); 205 DEBUG(MI.dump()); 206 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 207 MI.getOperand(0).getReg()) 208 .addOperand(MI.getOperand(OpNo)); 209 ToErase = &MI; 210 Simplified = true; 211 } 212 // Splat fed by a shift. Usually when we align value to splat into 213 // vector element zero. 214 if (DefOpcode == PPC::XXSLDWI) { 215 unsigned ShiftRes = DefMI->getOperand(0).getReg(); 216 unsigned ShiftOp1 = DefMI->getOperand(1).getReg(); 217 unsigned ShiftOp2 = DefMI->getOperand(2).getReg(); 218 unsigned ShiftImm = DefMI->getOperand(3).getImm(); 219 unsigned SplatImm = MI.getOperand(2).getImm(); 220 if (ShiftOp1 == ShiftOp2) { 221 unsigned NewElem = (SplatImm + ShiftImm) & 0x3; 222 if (MRI->hasOneNonDBGUse(ShiftRes)) { 223 DEBUG(dbgs() << "Removing redundant shift: "); 224 DEBUG(DefMI->dump()); 225 ToErase = DefMI; 226 } 227 Simplified = true; 228 DEBUG(dbgs() << "Changing splat immediate from " << SplatImm << 229 " to " << NewElem << " in instruction: "); 230 DEBUG(MI.dump()); 231 MI.getOperand(1).setReg(ShiftOp1); 232 MI.getOperand(2).setImm(NewElem); 233 } 234 } 235 break; 236 } 237 } 238 } 239 240 // If the last instruction was marked for elimination, 241 // remove it now. 242 if (ToErase) { 243 ToErase->eraseFromParent(); 244 ToErase = nullptr; 245 } 246 } 247 248 return Simplified; 249 } 250 251 // This is used to find the "true" source register for an 252 // XXPERMDI instruction, since MachineCSE does not handle the 253 // "copy-like" operations (Copy and SubregToReg). Returns 254 // the original SrcReg unless it is the target of a copy-like 255 // operation, in which case we chain backwards through all 256 // such operations to the ultimate source register. If a 257 // physical register is encountered, we stop the search. 258 unsigned PPCMIPeephole::lookThruCopyLike(unsigned SrcReg) { 259 260 while (true) { 261 262 MachineInstr *MI = MRI->getVRegDef(SrcReg); 263 if (!MI->isCopyLike()) 264 return SrcReg; 265 266 unsigned CopySrcReg; 267 if (MI->isCopy()) 268 CopySrcReg = MI->getOperand(1).getReg(); 269 else { 270 assert(MI->isSubregToReg() && "bad opcode for lookThruCopyLike"); 271 CopySrcReg = MI->getOperand(2).getReg(); 272 } 273 274 if (!TargetRegisterInfo::isVirtualRegister(CopySrcReg)) 275 return CopySrcReg; 276 277 SrcReg = CopySrcReg; 278 } 279 } 280 281 } // end default namespace 282 283 INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE, 284 "PowerPC MI Peephole Optimization", false, false) 285 INITIALIZE_PASS_END(PPCMIPeephole, DEBUG_TYPE, 286 "PowerPC MI Peephole Optimization", false, false) 287 288 char PPCMIPeephole::ID = 0; 289 FunctionPass* 290 llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); } 291 292