1//===-- PPCInstrP10.td - Power10 Instruction Set -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 6// See https://llvm.org/LICENSE.txt for license information. 7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 8// 9//===----------------------------------------------------------------------===// 10// 11// This file describes the instructions introduced for the Power10 CPU. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Naming convention for future instruction formats 17// 18// <INSTR_FORM>{_<OP_TYPE><OP_LENGTH>}+ 19// 20// Where: 21// <INSTR_FORM> - name of instruction format as per the ISA 22// (X-Form, VX-Form, etc.) 23// <OP_TYPE> - operand type 24// * FRT/RT/VT/XT/BT - target register 25// (FPR, GPR, VR, VSR, CR-bit respectively) 26// In some situations, the 'T' is replaced by 27// 'D' when describing the target register. 28// * [FR|R|V|X|B][A-Z] - register source (i.e. FRA, RA, XB, etc.) 29// * IMM - immediate (where signedness matters, 30// this is SI/UI for signed/unsigned) 31// * [R|X|FR]Tp - register pair target (i.e. FRTp, RTp) 32// * R - PC-Relative bit 33// (denotes that the address is computed pc-relative) 34// * VRM - Masked Registers 35// * AT - target accumulator 36// * N - the Nth bit in a VSR 37// * Additional 1-bit operands may be required for certain 38// instruction formats such as: MC, P, MP 39// * X / Y / P - mask values. In the instruction encoding, this is 40// represented as XMSK, YMSK and PMSK. 41// * MEM - indicates if the instruction format requires any memory 42// accesses. This does not have <OP_LENGTH> attached to it. 43// <OP_LENGTH> - the length of each operand in bits. 44// For operands that are 1 bit, the '1' is omitted from the name. 45// 46// Example: 8RR_XX4Form_IMM8_XTAB6 47// 8RR_XX4Form is the instruction format. 48// The operand is an 8-bit immediate (IMM), the destination (XT) 49// and sources (XA, XB) that are all 6-bits. The destination and 50// source registers are combined if they are of the same length. 51// Moreover, the order of operands reflects the order of operands 52// in the encoding. 53 54//-------------------------- Predicate definitions ---------------------------// 55def IsPPC32 : Predicate<"!Subtarget->isPPC64()">; 56 57 58//===----------------------------------------------------------------------===// 59// PowerPC ISA 3.1 specific type constraints. 60// 61 62def SDT_PPCSplat32 : SDTypeProfile<1, 3, [ SDTCisVT<0, v2i64>, 63 SDTCisVec<1>, SDTCisInt<2>, SDTCisInt<3> 64]>; 65def SDT_PPCAccBuild : SDTypeProfile<1, 4, [ 66 SDTCisVT<0, v512i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>, 67 SDTCisVT<3, v4i32>, SDTCisVT<4, v4i32> 68]>; 69def SDT_PPCPairBuild : SDTypeProfile<1, 2, [ 70 SDTCisVT<0, v256i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32> 71]>; 72def SDT_PPCAccExtractVsx : SDTypeProfile<1, 2, [ 73 SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisPtrTy<2> 74]>; 75def SDT_PPCPairExtractVsx : SDTypeProfile<1, 2, [ 76 SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisPtrTy<2> 77]>; 78def SDT_PPCxxmfacc : SDTypeProfile<1, 1, [ 79 SDTCisVT<0, v512i1>, SDTCisVT<1, v512i1> 80]>; 81 82def SDT_PPCsetbc : SDTypeProfile<1, 1, [ 83 SDTCisInt<0>, SDTCisInt<1> 84]>; 85 86//===----------------------------------------------------------------------===// 87// ISA 3.1 specific PPCISD nodes. 88// 89 90def PPCxxsplti32dx : SDNode<"PPCISD::XXSPLTI32DX", SDT_PPCSplat32, []>; 91def PPCAccBuild : SDNode<"PPCISD::ACC_BUILD", SDT_PPCAccBuild, []>; 92def PPCPairBuild : SDNode<"PPCISD::PAIR_BUILD", SDT_PPCPairBuild, []>; 93def PPCAccExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCAccExtractVsx, 94 []>; 95def PPCPairExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCPairExtractVsx, 96 []>; 97def PPCxxmfacc : SDNode<"PPCISD::XXMFACC", SDT_PPCxxmfacc, []>; 98def PPCsetbc : SDNode<"PPCISD::SETBC", SDT_PPCsetbc, []>; 99def PPCsetbcr : SDNode<"PPCISD::SETBCR", SDT_PPCsetbc, []>; 100 101//===----------------------------------------------------------------------===// 102 103// PC Relative flag (for instructions that use the address of the prefix for 104// address computations). 105class isPCRel { bit PCRel = 1; } 106 107// PowerPC specific type constraints. 108def SDT_PPCLXVRZX : SDTypeProfile<1, 2, [ 109 SDTCisVT<0, v1i128>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 110]>; 111 112// PPC Specific DAG Nodes. 113def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX, 114 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 115 116// Top-level class for prefixed instructions. 117class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr, 118 InstrItinClass itin> : Instruction { 119 field bits<64> Inst; 120 field bits<64> SoftFail = 0; 121 bit PCRel = 0; // Default value, set by isPCRel. 122 let Size = 8; 123 124 let Namespace = "PPC"; 125 let OutOperandList = OOL; 126 let InOperandList = IOL; 127 let AsmString = asmstr; 128 let Itinerary = itin; 129 let Inst{0-5} = pref; 130 let Inst{32-37} = opcode; 131 132 bits<1> PPC970_First = 0; 133 bits<1> PPC970_Single = 0; 134 bits<1> PPC970_Cracked = 0; 135 bits<3> PPC970_Unit = 0; 136 137 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 138 /// these must be reflected there! See comments there for what these are. 139 let TSFlags{0} = PPC970_First; 140 let TSFlags{1} = PPC970_Single; 141 let TSFlags{2} = PPC970_Cracked; 142 let TSFlags{5-3} = PPC970_Unit; 143 144 bits<1> Prefixed = 1; // This is a prefixed instruction. 145 let TSFlags{7} = Prefixed; 146 147 // Indicate that this instruction takes a register+immediate memory operand. 148 bits<1> MemriOp = 0; 149 let TSFlags{10} = MemriOp; 150 151 // For cases where multiple instruction definitions really represent the 152 // same underlying instruction but with one definition for 64-bit arguments 153 // and one for 32-bit arguments, this bit breaks the degeneracy between 154 // the two forms and allows TableGen to generate mapping tables. 155 bit Interpretation64Bit = 0; 156 157 // Fields used for relation models. 158 string BaseName = ""; 159} 160 161// VX-Form: [ PO VT R VB RC XO ] 162class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr, 163 InstrItinClass itin, list<dag> pattern> 164 : I<4, OOL, IOL, asmstr, itin> { 165 bits<5> VT; 166 bits<5> VB; 167 bit RC = 0; 168 169 let Pattern = pattern; 170 171 let Inst{6-10} = VT; 172 let Inst{11-15} = R; 173 let Inst{16-20} = VB; 174 let Inst{21} = RC; 175 let Inst{22-31} = xo; 176} 177 178// Multiclass definition to account for record and non-record form 179// instructions of VXRForm. 180multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL, 181 string asmbase, string asmstr, 182 InstrItinClass itin, list<dag> pattern> { 183 let BaseName = asmbase in { 184 def NAME : VXForm_VTB5_RC<xo, R, OOL, IOL, 185 !strconcat(asmbase, !strconcat(" ", asmstr)), 186 itin, pattern>, RecFormRel; 187 let Defs = [CR6] in 188 def _rec : VXForm_VTB5_RC<xo, R, OOL, IOL, 189 !strconcat(asmbase, !strconcat(". ", asmstr)), 190 itin, []>, isRecordForm, RecFormRel; 191 } 192} 193 194class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 195 InstrItinClass itin, list<dag> pattern> 196 : PI<1, opcode, OOL, IOL, asmstr, itin>, MemriOp { 197 bits<5> RST; 198 bits<5> RA; 199 bits<34> D; 200 201 let Pattern = pattern; 202 203 // The prefix. 204 let Inst{6-7} = 2; 205 let Inst{8-10} = 0; 206 let Inst{11} = PCRel; 207 let Inst{12-13} = 0; 208 let Inst{14-31} = D{33-16}; // d0 209 210 // The instruction. 211 let Inst{38-42} = RST{4-0}; 212 let Inst{43-47} = RA; 213 let Inst{48-63} = D{15-0}; // d1 214} 215 216class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 217 InstrItinClass itin, list<dag> pattern> 218 : PI<1, opcode, OOL, IOL, asmstr, itin> { 219 bits<5> RT; 220 bits<5> RA; 221 bits<34> SI; 222 223 let Pattern = pattern; 224 225 // The prefix. 226 let Inst{6-7} = 2; 227 let Inst{8-10} = 0; 228 let Inst{11} = PCRel; 229 let Inst{12-13} = 0; 230 let Inst{14-31} = SI{33-16}; 231 232 // The instruction. 233 let Inst{38-42} = RT; 234 let Inst{43-47} = RA; 235 let Inst{48-63} = SI{15-0}; 236} 237 238class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 239 InstrItinClass itin, list<dag> pattern> 240 : PI<1, opcode, OOL, IOL, asmstr, itin> { 241 bits<5> RT; 242 bits<34> SI; 243 244 let Pattern = pattern; 245 246 // The prefix. 247 let Inst{6-7} = 2; 248 let Inst{8-10} = 0; 249 let Inst{11} = 0; 250 let Inst{12-13} = 0; 251 let Inst{14-31} = SI{33-16}; 252 253 // The instruction. 254 let Inst{38-42} = RT; 255 let Inst{43-47} = 0; 256 let Inst{48-63} = SI{15-0}; 257} 258 259multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL, 260 dag PCRel_IOL, string asmstr, 261 InstrItinClass itin> { 262 def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL, 263 !strconcat(asmstr, ", 0"), itin, []>; 264 def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL, 265 !strconcat(asmstr, ", 1"), itin, []>, isPCRel; 266} 267 268class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 269 InstrItinClass itin, list<dag> pattern> 270 : PI<1, opcode, OOL, IOL, asmstr, itin>, MemriOp { 271 bits<5> RST; 272 bits<5> RA; 273 bits<34> D; 274 275 let Pattern = pattern; 276 277 // The prefix. 278 let Inst{6-10} = 0; 279 let Inst{11} = PCRel; 280 let Inst{12-13} = 0; 281 let Inst{14-31} = D{33-16}; // d0 282 283 // The instruction. 284 let Inst{38-42} = RST{4-0}; 285 let Inst{43-47} = RA; 286 let Inst{48-63} = D{15-0}; // d1 287} 288 289// 8LS:D-Form: [ 1 0 0 // R // d0 290// PO TX T RA d1 ] 291class 8LS_DForm_R_SI34_XT6_RA5_MEM<bits<5> opcode, dag OOL, dag IOL, 292 string asmstr, InstrItinClass itin, 293 list<dag> pattern> 294 : PI<1, { opcode, ? }, OOL, IOL, asmstr, itin>, MemriOp { 295 bits<6> XST; 296 bits<5> RA; 297 bits<34> D; 298 299 let Pattern = pattern; 300 301 // The prefix. 302 let Inst{6-7} = 0; 303 let Inst{8} = 0; 304 let Inst{9-10} = 0; // reserved 305 let Inst{11} = PCRel; 306 let Inst{12-13} = 0; // reserved 307 let Inst{14-31} = D{33-16}; // d0 308 309 // The instruction. 310 let Inst{37} = XST{5}; 311 let Inst{38-42} = XST{4-0}; 312 let Inst{43-47} = RA; 313 let Inst{48-63} = D{15-0}; // d1 314} 315 316// X-Form: [PO T IMM VRB XO TX] 317class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 318 string asmstr, InstrItinClass itin, list<dag> pattern> 319 : I<opcode, OOL, IOL, asmstr, itin> { 320 bits<6> XT; 321 bits<5> VRB; 322 bits<5> IMM; 323 324 let Pattern = pattern; 325 let Inst{6-10} = XT{4-0}; 326 let Inst{11-15} = IMM; 327 let Inst{16-20} = VRB; 328 let Inst{21-30} = xo; 329 let Inst{31} = XT{5}; 330} 331 332class 8RR_XX4Form_IMM8_XTAB6<bits<6> opcode, bits<2> xo, 333 dag OOL, dag IOL, string asmstr, 334 InstrItinClass itin, list<dag> pattern> 335 : PI<1, opcode, OOL, IOL, asmstr, itin> { 336 bits<6> XT; 337 bits<6> XA; 338 bits<6> XB; 339 bits<6> XC; 340 bits<8> IMM; 341 342 let Pattern = pattern; 343 344 // The prefix. 345 let Inst{6-7} = 1; 346 let Inst{8} = 0; 347 let Inst{9-11} = 0; 348 let Inst{12-13} = 0; 349 let Inst{14-23} = 0; 350 let Inst{24-31} = IMM; 351 352 // The instruction. 353 let Inst{38-42} = XT{4-0}; 354 let Inst{43-47} = XA{4-0}; 355 let Inst{48-52} = XB{4-0}; 356 let Inst{53-57} = XC{4-0}; 357 let Inst{58-59} = xo; 358 let Inst{60} = XC{5}; 359 let Inst{61} = XA{5}; 360 let Inst{62} = XB{5}; 361 let Inst{63} = XT{5}; 362} 363 364class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr, 365 InstrItinClass itin, list<dag> pattern> 366 : I<4, OOL, IOL, asmstr, itin> { 367 bits<5> RD; 368 bits<5> VB; 369 bits<3> N; 370 371 let Pattern = pattern; 372 373 let Inst{6-10} = RD; 374 let Inst{11-12} = 0; 375 let Inst{13-15} = N; 376 let Inst{16-20} = VB; 377 let Inst{21-31} = xo; 378} 379 380 381// VX-Form: [PO VRT RA VRB XO]. 382// Destructive (insert) forms are suffixed with _ins. 383class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern> 384 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, vrrc:$VB), 385 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>, 386 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 387 388// VX-Form: [PO VRT RA RB XO]. 389// Destructive (insert) forms are suffixed with _ins. 390class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern> 391 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, gprc:$VB), 392 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>, 393 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 394 395// VX-Form: [ PO BF // VRA VRB XO ] 396class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr, 397 InstrItinClass itin, list<dag> pattern> 398 : I<4, OOL, IOL, asmstr, itin> { 399 bits<3> BF; 400 bits<5> VA; 401 bits<5> VB; 402 403 let Pattern = pattern; 404 405 let Inst{6-8} = BF; 406 let Inst{9-10} = 0; 407 let Inst{11-15} = VA; 408 let Inst{16-20} = VB; 409 let Inst{21-31} = xo; 410} 411 412// VN-Form: [PO VRT VRA VRB PS SD XO] 413// SD is "Shift Direction" 414class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr, 415 InstrItinClass itin, list<dag> pattern> 416 : I<4, OOL, IOL, asmstr, itin> { 417 bits<5> VRT; 418 bits<5> VRA; 419 bits<5> VRB; 420 bits<3> SD; 421 422 let Pattern = pattern; 423 424 let Inst{6-10} = VRT; 425 let Inst{11-15} = VRA; 426 let Inst{16-20} = VRB; 427 let Inst{21-22} = ps; 428 let Inst{23-25} = SD; 429 let Inst{26-31} = xo; 430} 431 432class VXForm_RD5_MP_VB5<bits<11> xo, bits<4> eo, dag OOL, dag IOL, 433 string asmstr, InstrItinClass itin, list<dag> pattern> 434 : I<4, OOL, IOL, asmstr, itin> { 435 bits<5> RD; 436 bits<5> VB; 437 bit MP; 438 439 let Pattern = pattern; 440 441 let Inst{6-10} = RD; 442 let Inst{11-14} = eo; 443 let Inst{15} = MP; 444 let Inst{16-20} = VB; 445 let Inst{21-31} = xo; 446} 447 448// 8RR:D-Form: [ 1 1 0 // // imm0 449// PO T XO TX imm1 ]. 450class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 451 string asmstr, InstrItinClass itin, 452 list<dag> pattern> 453 : PI<1, opcode, OOL, IOL, asmstr, itin> { 454 bits<6> XT; 455 bits<32> IMM32; 456 457 let Pattern = pattern; 458 459 // The prefix. 460 let Inst{6-7} = 1; 461 let Inst{8-11} = 0; 462 let Inst{12-13} = 0; // reserved 463 let Inst{14-15} = 0; // reserved 464 let Inst{16-31} = IMM32{31-16}; 465 466 // The instruction. 467 let Inst{38-42} = XT{4-0}; 468 let Inst{43-46} = xo; 469 let Inst{47} = XT{5}; 470 let Inst{48-63} = IMM32{15-0}; 471} 472 473// 8RR:D-Form: [ 1 1 0 // // imm0 474// PO T XO IX TX imm1 ]. 475class 8RR_DForm_IMM32_XT6_IX<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 476 string asmstr, InstrItinClass itin, 477 list<dag> pattern> 478 : PI<1, opcode, OOL, IOL, asmstr, itin> { 479 bits<6> XT; 480 bit IX; 481 bits<32> IMM32; 482 483 let Pattern = pattern; 484 485 // The prefix. 486 let Inst{6-7} = 1; 487 let Inst{8-11} = 0; 488 let Inst{12-13} = 0; // reserved 489 let Inst{14-15} = 0; // reserved 490 let Inst{16-31} = IMM32{31-16}; 491 492 // The instruction. 493 let Inst{38-42} = XT{4-0}; 494 let Inst{43-45} = xo; 495 let Inst{46} = IX; 496 let Inst{47} = XT{5}; 497 let Inst{48-63} = IMM32{15-0}; 498} 499 500class 8RR_XX4Form_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, 501 string asmstr, InstrItinClass itin, list<dag> pattern> 502 : PI<1, opcode, OOL, IOL, asmstr, itin> { 503 bits<6> XT; 504 bits<6> XA; 505 bits<6> XB; 506 bits<6> XC; 507 508 let Pattern = pattern; 509 510 // The prefix. 511 let Inst{6-7} = 1; 512 let Inst{8-11} = 0; 513 let Inst{12-13} = 0; 514 let Inst{14-31} = 0; 515 516 // The instruction. 517 let Inst{38-42} = XT{4-0}; 518 let Inst{43-47} = XA{4-0}; 519 let Inst{48-52} = XB{4-0}; 520 let Inst{53-57} = XC{4-0}; 521 let Inst{58-59} = xo; 522 let Inst{60} = XC{5}; 523 let Inst{61} = XA{5}; 524 let Inst{62} = XB{5}; 525 let Inst{63} = XT{5}; 526} 527 528class 8RR_XX4Form_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, 529 string asmstr, InstrItinClass itin, 530 list<dag> pattern> 531 : PI<1, opcode, OOL, IOL, asmstr, itin> { 532 bits<6> XT; 533 bits<6> XA; 534 bits<6> XB; 535 bits<6> XC; 536 bits<3> IMM; 537 538 let Pattern = pattern; 539 540 // The prefix. 541 let Inst{6-7} = 1; 542 let Inst{8-11} = 0; 543 let Inst{12-13} = 0; 544 let Inst{14-28} = 0; 545 let Inst{29-31} = IMM; 546 547 // The instruction. 548 let Inst{38-42} = XT{4-0}; 549 let Inst{43-47} = XA{4-0}; 550 let Inst{48-52} = XB{4-0}; 551 let Inst{53-57} = XC{4-0}; 552 let Inst{58-59} = xo; 553 let Inst{60} = XC{5}; 554 let Inst{61} = XA{5}; 555 let Inst{62} = XB{5}; 556 let Inst{63} = XT{5}; 557} 558 559// [PO BF / XO2 B XO BX /] 560class XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, 561 dag IOL, string asmstr, InstrItinClass itin, 562 list<dag> pattern> 563 : I<opcode, OOL, IOL, asmstr, itin> { 564 bits<3> BF; 565 bits<6> XB; 566 567 let Pattern = pattern; 568 569 let Inst{6-8} = BF; 570 let Inst{9-10} = 0; 571 let Inst{11-15} = xo2; 572 let Inst{16-20} = XB{4-0}; 573 let Inst{21-29} = xo; 574 let Inst{30} = XB{5}; 575 let Inst{31} = 0; 576} 577 578// X-Form: [ PO RT BI /// XO / ] 579class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 580 string asmstr, InstrItinClass itin, list<dag> pattern> 581 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 582 bits<5> BI; 583 let RA = BI; 584 let RB = 0; 585} 586 587multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL, 588 dag PCRel_IOL, dag PCRelOnly_IOL, 589 string asmstr, string asmstr_pcext, 590 InstrItinClass itin> { 591 def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, 592 !strconcat(asmstr, ", 0"), itin, []>; 593 def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL, 594 !strconcat(asmstr, ", 1"), itin, []>, 595 isPCRel; 596 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in { 597 def nopc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>; 598 let RA = 0, MemriOp = 0 in 599 def onlypc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL, 600 asmstr_pcext, itin, []>, isPCRel; 601 } 602} 603 604multiclass 8LS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL, 605 dag PCRel_IOL, dag PCRelOnly_IOL, 606 string asmstr, string asmstr_pcext, 607 InstrItinClass itin> { 608 def NAME : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, 609 !strconcat(asmstr, ", 0"), itin, []>; 610 def pc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL, 611 !strconcat(asmstr, ", 1"), itin, []>, 612 isPCRel; 613 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in { 614 def nopc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>; 615 let RA = 0, MemriOp = 0 in 616 def onlypc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL, 617 asmstr_pcext, itin, []>, isPCRel; 618 } 619} 620 621multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL, 622 dag PCRel_IOL, dag PCRelOnly_IOL, 623 string asmstr, string asmstr_pcext, 624 InstrItinClass itin> { 625 def NAME : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL, 626 !strconcat(asmstr, ", 0"), itin, []>; 627 def pc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRel_IOL, 628 !strconcat(asmstr, ", 1"), itin, []>, 629 isPCRel; 630 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in { 631 def nopc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL, asmstr, itin, []>; 632 let RA = 0, MemriOp = 0 in 633 def onlypc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRelOnly_IOL, 634 asmstr_pcext, itin, []>, isPCRel; 635 } 636} 637 638def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">; 639def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">; 640def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">; 641def RCCp { 642 dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC); 643 dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC); 644} 645 646let Predicates = [PrefixInstrs] in { 647 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 648 defm PADDI8 : 649 MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc_nox0:$RA, s34imm:$SI), 650 (ins immZero:$RA, s34imm_pcrel:$SI), 651 "paddi $RT, $RA, $SI", IIC_LdStLFD>; 652 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 653 def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT), 654 (ins s34imm:$SI), 655 "pli $RT, $SI", IIC_IntSimple, []>; 656 } 657 } 658 defm PADDI : 659 MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc_nor0:$RA, s34imm:$SI), 660 (ins immZero:$RA, s34imm_pcrel:$SI), 661 "paddi $RT, $RA, $SI", IIC_LdStLFD>; 662 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 663 def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT), 664 (ins s34imm:$SI), 665 "pli $RT, $SI", IIC_IntSimple, []>; 666 } 667 668 let mayLoad = 1, mayStore = 0 in { 669 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 670 defm PLBZ8 : 671 MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 672 (ins (memri34_pcrel $D, $RA):$addr), 673 (ins s34imm_pcrel:$D), "plbz $RST, $addr", 674 "plbz $RST, $D", IIC_LdStLFD>; 675 defm PLHZ8 : 676 MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 677 (ins (memri34_pcrel $D, $RA):$addr), 678 (ins s34imm_pcrel:$D), "plhz $RST, $addr", 679 "plhz $RST, $D", IIC_LdStLFD>; 680 defm PLHA8 : 681 MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 682 (ins (memri34_pcrel $D, $RA):$addr), 683 (ins s34imm_pcrel:$D), "plha $RST, $addr", 684 "plha $RST, $D", IIC_LdStLFD>; 685 defm PLWA8 : 686 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 687 (ins (memri34_pcrel $D, $RA):$addr), 688 (ins s34imm_pcrel:$D), 689 "plwa $RST, $addr", "plwa $RST, $D", IIC_LdStLFD>; 690 defm PLWZ8 : 691 MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 692 (ins (memri34_pcrel $D, $RA):$addr), 693 (ins s34imm_pcrel:$D), "plwz $RST, $addr", 694 "plwz $RST, $D", IIC_LdStLFD>; 695 } 696 defm PLBZ : 697 MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr), 698 (ins (memri34_pcrel $D, $RA):$addr), 699 (ins s34imm_pcrel:$D), "plbz $RST, $addr", 700 "plbz $RST, $D", IIC_LdStLFD>; 701 defm PLHZ : 702 MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr), 703 (ins (memri34_pcrel $D, $RA):$addr), 704 (ins s34imm_pcrel:$D), "plhz $RST, $addr", 705 "plhz $RST, $D", IIC_LdStLFD>; 706 defm PLHA : 707 MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr), 708 (ins (memri34_pcrel $D, $RA):$addr), 709 (ins s34imm_pcrel:$D), "plha $RST, $addr", 710 "plha $RST, $D", IIC_LdStLFD>; 711 defm PLWZ : 712 MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr), 713 (ins (memri34_pcrel $D, $RA):$addr), 714 (ins s34imm_pcrel:$D), "plwz $RST, $addr", 715 "plwz $RST, $D", IIC_LdStLFD>; 716 defm PLWA : 717 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr), 718 (ins (memri34_pcrel $D, $RA):$addr), 719 (ins s34imm_pcrel:$D), 720 "plwa $RST, $addr", "plwa $RST, $D", 721 IIC_LdStLFD>; 722 defm PLD : 723 8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 724 (ins (memri34_pcrel $D, $RA):$addr), 725 (ins s34imm_pcrel:$D), 726 "pld $RST, $addr", "pld $RST, $D", 727 IIC_LdStLFD>; 728 } 729 730 let mayStore = 1, mayLoad = 0 in { 731 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 732 defm PSTB8 : 733 MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr), 734 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr), 735 (ins g8rc:$RST, s34imm_pcrel:$D), 736 "pstb $RST, $addr", "pstb $RST, $D", IIC_LdStLFD>; 737 defm PSTH8 : 738 MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr), 739 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr), 740 (ins g8rc:$RST, s34imm_pcrel:$D), 741 "psth $RST, $addr", "psth $RST, $D", IIC_LdStLFD>; 742 defm PSTW8 : 743 MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr), 744 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr), 745 (ins g8rc:$RST, s34imm_pcrel:$D), 746 "pstw $RST, $addr", "pstw $RST, $D", IIC_LdStLFD>; 747 } 748 defm PSTB : 749 MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr), 750 (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr), 751 (ins gprc:$RST, s34imm_pcrel:$D), 752 "pstb $RST, $addr", "pstb $RST, $D", IIC_LdStLFD>; 753 defm PSTH : 754 MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr), 755 (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr), 756 (ins gprc:$RST, s34imm_pcrel:$D), 757 "psth $RST, $addr", "psth $RST, $D", IIC_LdStLFD>; 758 defm PSTW : 759 MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr), 760 (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr), 761 (ins gprc:$RST, s34imm_pcrel:$D), 762 "pstw $RST, $addr", "pstw $RST, $D", IIC_LdStLFD>; 763 defm PSTD : 764 8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr), 765 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr), 766 (ins g8rc:$RST, s34imm_pcrel:$D), 767 "pstd $RST, $addr", "pstd $RST, $D", IIC_LdStLFD>; 768 } 769} 770 771let Predicates = [PrefixInstrs, HasFPU] in { 772 let mayLoad = 1, mayStore = 0 in { 773 defm PLFS : 774 MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$RST), (ins (memri34 $D, $RA):$addr), 775 (ins (memri34_pcrel $D, $RA):$addr), 776 (ins s34imm_pcrel:$D), "plfs $RST, $addr", 777 "plfs $RST, $D", IIC_LdStLFD>; 778 defm PLFD : 779 MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$RST), (ins (memri34 $D, $RA):$addr), 780 (ins (memri34_pcrel $D, $RA):$addr), 781 (ins s34imm_pcrel:$D), "plfd $RST, $addr", 782 "plfd $RST, $D", IIC_LdStLFD>; 783 } 784 let mayStore = 1, mayLoad = 0 in { 785 defm PSTFS : 786 MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, (memri34 $D, $RA):$addr), 787 (ins f4rc:$RST, (memri34_pcrel $D, $RA):$addr), 788 (ins f4rc:$RST, s34imm_pcrel:$D), 789 "pstfs $RST, $addr", "pstfs $RST, $D", IIC_LdStLFD>; 790 defm PSTFD : 791 MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, (memri34 $D, $RA):$addr), 792 (ins f8rc:$RST, (memri34_pcrel $D, $RA):$addr), 793 (ins f8rc:$RST, s34imm_pcrel:$D), 794 "pstfd $RST, $addr", "pstfd $RST, $D", IIC_LdStLFD>; 795 } 796} 797 798let Predicates = [PrefixInstrs, HasP10Vector] in { 799 let mayLoad = 1, mayStore = 0 in { 800 defm PLXV : 801 8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins (memri34 $D, $RA):$addr), 802 (ins (memri34_pcrel $D, $RA):$addr), 803 (ins s34imm_pcrel:$D), 804 "plxv $XST, $addr", "plxv $XST, $D", IIC_LdStLFD>; 805 defm PLXSSP : 806 8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr), 807 (ins (memri34_pcrel $D, $RA):$addr), 808 (ins s34imm_pcrel:$D), 809 "plxssp $RST, $addr", "plxssp $RST, $D", 810 IIC_LdStLFD>; 811 defm PLXSD : 812 8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr), 813 (ins (memri34_pcrel $D, $RA):$addr), 814 (ins s34imm_pcrel:$D), 815 "plxsd $RST, $addr", "plxsd $RST, $D", 816 IIC_LdStLFD>; 817 } 818 let mayStore = 1, mayLoad = 0 in { 819 defm PSTXV : 820 8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, (memri34 $D, $RA):$addr), 821 (ins vsrc:$XST, (memri34_pcrel $D, $RA):$addr), 822 (ins vsrc:$XST, s34imm_pcrel:$D), 823 "pstxv $XST, $addr", "pstxv $XST, $D", IIC_LdStLFD>; 824 defm PSTXSSP : 825 8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr), 826 (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr), 827 (ins vfrc:$RST, s34imm_pcrel:$D), 828 "pstxssp $RST, $addr", "pstxssp $RST, $D", IIC_LdStLFD>; 829 defm PSTXSD : 830 8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr), 831 (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr), 832 (ins vfrc:$RST, s34imm_pcrel:$D), 833 "pstxsd $RST, $addr", "pstxsd $RST, $D", IIC_LdStLFD>; 834 } 835 def XXPERMX : 836 8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 837 vsrc:$XC, u3imm:$IMM), 838 "xxpermx $XT, $XA, $XB, $XC, $IMM", 839 IIC_VecPerm, []>; 840 def XXBLENDVB : 841 8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 842 vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC", 843 IIC_VecGeneral, []>; 844 def XXBLENDVH : 845 8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 846 vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC", 847 IIC_VecGeneral, []>; 848 def XXBLENDVW : 849 8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 850 vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC", 851 IIC_VecGeneral, []>; 852 def XXBLENDVD : 853 8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 854 vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC", 855 IIC_VecGeneral, []>; 856} 857 858class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 859 string asmstr, InstrItinClass itin, list<dag> pattern> 860 : I<opcode, OOL, IOL, asmstr, itin>, MemriOp { 861 bits<5> XTp; 862 bits<5> RA; 863 bits<12> DQ; 864 865 let Pattern = pattern; 866 867 let Inst{6-9} = XTp{3-0}; 868 let Inst{10} = XTp{4}; 869 let Inst{11-15} = RA; 870 let Inst{16-27} = DQ; 871 let Inst{28-31} = xo; 872} 873 874class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 875 string asmstr, InstrItinClass itin, list<dag> pattern> 876 : I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp { 877 bits<5> XTp; 878 bits<5> RA; 879 bits<5> RB; 880 881 let Pattern = pattern; 882 let Inst{6-9} = XTp{3-0}; 883 let Inst{10} = XTp{4}; 884 let Inst{11-15} = RA; 885 let Inst{16-20} = RB; 886 let Inst{21-30} = xo; 887 let Inst{31} = 0; 888} 889 890class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 891 InstrItinClass itin, list<dag> pattern> 892 : PI<1, opcode, OOL, IOL, asmstr, itin>, MemriOp { 893 bits<5> XTp; 894 bits<5> RA; 895 bits<34> D; 896 897 let Pattern = pattern; 898 899 // The prefix. 900 let Inst{6-10} = 0; 901 let Inst{11} = PCRel; 902 let Inst{12-13} = 0; 903 let Inst{14-31} = D{33-16}; // Imm18 904 905 // The instruction. 906 let Inst{38-41} = XTp{3-0}; 907 let Inst{42} = XTp{4}; 908 let Inst{43-47} = RA; 909 let Inst{48-63} = D{15-0}; 910} 911 912multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> opcode, dag OOL, 913 dag IOL, dag PCRel_IOL, dag PCRelOnly_IOL, 914 string asmstr, string asmstr_pcext, 915 InstrItinClass itin> { 916 def NAME : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL, 917 !strconcat(asmstr, ", 0"), itin, []>; 918 def pc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRel_IOL, 919 !strconcat(asmstr, ", 1"), itin, []>, 920 isPCRel; 921 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in { 922 def nopc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL, asmstr, itin, []>; 923 let RA = 0, MemriOp = 0 in 924 def onlypc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRelOnly_IOL, 925 asmstr_pcext, itin, []>, isPCRel; 926 } 927} 928 929 930 931// [PO AS XO2 XO] 932class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 933 string asmstr, InstrItinClass itin, list<dag> pattern> 934 : I<opcode, OOL, IOL, asmstr, itin> { 935 bits<3> AT; 936 937 let Pattern = pattern; 938 939 let Inst{6-8} = AT; 940 let Inst{9-10} = 0; 941 let Inst{11-15} = xo2; 942 let Inst{16-20} = 0; 943 let Inst{21-30} = xo; 944 let Inst{31} = 0; 945} 946 947// X-Form: [ PO T EO UIM XO TX ] 948class XForm_XT6_IMM5<bits<6> opcode, bits<5> eo, bits<10> xo, dag OOL, dag IOL, 949 string asmstr, InstrItinClass itin, list<dag> pattern> 950 : I<opcode, OOL, IOL, asmstr, itin> { 951 bits<6> XT; 952 bits<5> UIM; 953 954 let Pattern = pattern; 955 956 let Inst{6-10} = XT{4-0}; 957 let Inst{11-15} = eo; 958 let Inst{16-20} = UIM; 959 let Inst{21-30} = xo; 960 let Inst{31} = XT{5}; 961} 962 963class XX3Form_AT3_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 964 string asmstr, InstrItinClass itin, 965 list<dag> pattern> 966 : I<opcode, OOL, IOL, asmstr, itin> { 967 bits<3> AT; 968 bits<6> XA; 969 bits<6> XB; 970 971 let Pattern = pattern; 972 973 let Inst{6-8} = AT; 974 let Inst{9-10} = 0; 975 let Inst{11-15} = XA{4-0}; 976 let Inst{16-20} = XB{4-0}; 977 let Inst{21-28} = xo; 978 let Inst{29} = XA{5}; 979 let Inst{30} = XB{5}; 980 let Inst{31} = 0; 981} 982 983class MMIRR_XX3Form_XY4P2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 984 string asmstr, InstrItinClass itin, 985 list<dag> pattern> 986 : PI<1, opcode, OOL, IOL, asmstr, itin> { 987 bits<3> AT; 988 bits<6> XA; 989 bits<6> XB; 990 bits<4> XMSK; 991 bits<4> YMSK; 992 bits<2> PMSK; 993 994 let Pattern = pattern; 995 996 // The prefix. 997 let Inst{6-7} = 3; 998 let Inst{8-11} = 9; 999 let Inst{12-15} = 0; 1000 let Inst{16-17} = PMSK; 1001 let Inst{18-23} = 0; 1002 let Inst{24-27} = XMSK; 1003 let Inst{28-31} = YMSK; 1004 1005 // The instruction. 1006 let Inst{38-40} = AT; 1007 let Inst{41-42} = 0; 1008 let Inst{43-47} = XA{4-0}; 1009 let Inst{48-52} = XB{4-0}; 1010 let Inst{53-60} = xo; 1011 let Inst{61} = XA{5}; 1012 let Inst{62} = XB{5}; 1013 let Inst{63} = 0; 1014} 1015 1016class MMIRR_XX3Form_XY4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1017 string asmstr, InstrItinClass itin, 1018 list<dag> pattern> 1019 : PI<1, opcode, OOL, IOL, asmstr, itin> { 1020 bits<3> AT; 1021 bits<6> XA; 1022 bits<6> XB; 1023 bits<4> XMSK; 1024 bits<4> YMSK; 1025 1026 let Pattern = pattern; 1027 1028 // The prefix. 1029 let Inst{6-7} = 3; 1030 let Inst{8-11} = 9; 1031 let Inst{12-23} = 0; 1032 let Inst{24-27} = XMSK; 1033 let Inst{28-31} = YMSK; 1034 1035 // The instruction. 1036 let Inst{38-40} = AT; 1037 let Inst{41-42} = 0; 1038 let Inst{43-47} = XA{4-0}; 1039 let Inst{48-52} = XB{4-0}; 1040 let Inst{53-60} = xo; 1041 let Inst{61} = XA{5}; 1042 let Inst{62} = XB{5}; 1043 let Inst{63} = 0; 1044} 1045 1046class MMIRR_XX3Form_X4Y2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1047 string asmstr, InstrItinClass itin, 1048 list<dag> pattern> 1049 : PI<1, opcode, OOL, IOL, asmstr, itin> { 1050 bits<3> AT; 1051 bits<6> XA; 1052 bits<6> XB; 1053 bits<4> XMSK; 1054 bits<2> YMSK; 1055 1056 let Pattern = pattern; 1057 1058 // The prefix. 1059 let Inst{6-7} = 3; 1060 let Inst{8-11} = 9; 1061 let Inst{12-23} = 0; 1062 let Inst{24-27} = XMSK; 1063 let Inst{28-29} = YMSK; 1064 let Inst{30-31} = 0; 1065 1066 // The instruction. 1067 let Inst{38-40} = AT; 1068 let Inst{41-42} = 0; 1069 let Inst{43-47} = XA{4-0}; 1070 let Inst{48-52} = XB{4-0}; 1071 let Inst{53-60} = xo; 1072 let Inst{61} = XA{5}; 1073 let Inst{62} = XB{5}; 1074 let Inst{63} = 0; 1075} 1076 1077class MMIRR_XX3Form_XY4P8_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1078 string asmstr, InstrItinClass itin, 1079 list<dag> pattern> 1080 : PI<1, opcode, OOL, IOL, asmstr, itin> { 1081 bits<3> AT; 1082 bits<6> XA; 1083 bits<6> XB; 1084 bits<4> XMSK; 1085 bits<4> YMSK; 1086 bits<8> PMSK; 1087 1088 let Pattern = pattern; 1089 1090 // The prefix. 1091 let Inst{6-7} = 3; 1092 let Inst{8-11} = 9; 1093 let Inst{12-15} = 0; 1094 let Inst{16-23} = PMSK; 1095 let Inst{24-27} = XMSK; 1096 let Inst{28-31} = YMSK; 1097 1098 // The instruction. 1099 let Inst{38-40} = AT; 1100 let Inst{41-42} = 0; 1101 let Inst{43-47} = XA{4-0}; 1102 let Inst{48-52} = XB{4-0}; 1103 let Inst{53-60} = xo; 1104 let Inst{61} = XA{5}; 1105 let Inst{62} = XB{5}; 1106 let Inst{63} = 0; 1107} 1108 1109class MMIRR_XX3Form_XYP4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1110 string asmstr, InstrItinClass itin, 1111 list<dag> pattern> 1112 : PI<1, opcode, OOL, IOL, asmstr, itin> { 1113 bits<3> AT; 1114 bits<6> XA; 1115 bits<6> XB; 1116 bits<4> XMSK; 1117 bits<4> YMSK; 1118 bits<4> PMSK; 1119 1120 let Pattern = pattern; 1121 1122 // The prefix. 1123 let Inst{6-7} = 3; 1124 let Inst{8-11} = 9; 1125 let Inst{12-15} = 0; 1126 let Inst{16-19} = PMSK; 1127 let Inst{20-23} = 0; 1128 let Inst{24-27} = XMSK; 1129 let Inst{28-31} = YMSK; 1130 1131 // The instruction. 1132 let Inst{38-40} = AT; 1133 let Inst{41-42} = 0; 1134 let Inst{43-47} = XA{4-0}; 1135 let Inst{48-52} = XB{4-0}; 1136 let Inst{53-60} = xo; 1137 let Inst{61} = XA{5}; 1138 let Inst{62} = XB{5}; 1139 let Inst{63} = 0; 1140} 1141 1142 1143 1144def Concats { 1145 dag VecsToVecPair0 = 1146 (v256i1 (INSERT_SUBREG 1147 (INSERT_SUBREG (IMPLICIT_DEF), $vs0, sub_vsx1), 1148 $vs1, sub_vsx0)); 1149 dag VecsToVecPair1 = 1150 (v256i1 (INSERT_SUBREG 1151 (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1), 1152 $vs3, sub_vsx0)); 1153} 1154 1155let Predicates = [PairedVectorMemops] in { 1156 def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)), 1157 Concats.VecsToVecPair0>; 1158 def : Pat<(v256i1 (int_ppc_vsx_assemble_pair v16i8:$vs1, v16i8:$vs0)), 1159 Concats.VecsToVecPair0>; 1160 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 0)), 1161 (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>; 1162 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 1)), 1163 (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>; 1164 1165 let mayLoad = 1, mayStore = 0 in { 1166 def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp), 1167 (ins (memrix16 $DQ, $RA):$addr), "lxvp $XTp, $addr", 1168 IIC_LdStLFD, []>; 1169 def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins (memrr $RA, $RB):$addr), 1170 "lxvpx $XTp, $addr", IIC_LdStLFD, 1171 []>; 1172 } 1173 1174 let mayLoad = 0, mayStore = 1 in { 1175 def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp, 1176 (memrix16 $DQ, $RA):$addr), "stxvp $XTp, $addr", 1177 IIC_LdStLFD, []>; 1178 def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, (memrr $RA, $RB):$addr), 1179 "stxvpx $XTp, $addr", IIC_LdStLFD, 1180 []>; 1181 } 1182} 1183let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in { 1184 defm PLXVP : 1185 8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins (memri34 $D, $RA):$addr), 1186 (ins (memri34_pcrel $D, $RA):$addr), 1187 (ins s34imm_pcrel:$D), 1188 "plxvp $XTp, $addr", "plxvp $XTp, $D", 1189 IIC_LdStLFD>; 1190} 1191 1192let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in { 1193 defm PSTXVP : 1194 8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, (memri34 $D, $RA):$addr), 1195 (ins vsrprc:$XTp, (memri34_pcrel $D, $RA):$addr), 1196 (ins vsrprc:$XTp, s34imm_pcrel:$D), 1197 "pstxvp $XTp, $addr", "pstxvp $XTp, $D", IIC_LdStLFD>; 1198} 1199 1200let Predicates = [PairedVectorMemops] in { 1201 // Intrinsics for Paired Vector Loads. 1202 def : Pat<(v256i1 (int_ppc_vsx_lxvp DQForm:$src)), (LXVP memrix16:$src)>; 1203 def : Pat<(v256i1 (int_ppc_vsx_lxvp XForm:$src)), (LXVPX XForm:$src)>; 1204 let Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in { 1205 def : Pat<(v256i1 (int_ppc_vsx_lxvp PDForm:$src)), (PLXVP memri34:$src)>; 1206 } 1207 // Intrinsics for Paired Vector Stores. 1208 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, DQForm:$dst), 1209 (STXVP $XSp, memrix16:$dst)>; 1210 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, XForm:$dst), 1211 (STXVPX $XSp, XForm:$dst)>; 1212 let Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in { 1213 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, PDForm:$dst), 1214 (PSTXVP $XSp, memri34:$dst)>; 1215 } 1216} 1217 1218let Predicates = [IsISA3_1] in { 1219 def XSCMPEQQP : X_VT5_VA5_VB5<63, 68, "xscmpeqqp", []>; 1220 def XSCMPGEQP : X_VT5_VA5_VB5<63, 196, "xscmpgeqp", []>; 1221 def XSCMPGTQP : X_VT5_VA5_VB5<63, 228, "xscmpgtqp", []>; 1222} 1223 1224let Predicates = [PCRelativeMemops] in { 1225 // Load i32 1226 def : Pat<(i32 (zextloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1227 (PLBZpc $ga, 0)>; 1228 def : Pat<(i32 (extloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1229 (PLBZpc $ga, 0)>; 1230 def : Pat<(i32 (zextloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1231 (PLBZpc $ga, 0)>; 1232 def : Pat<(i32 (extloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1233 (PLBZpc $ga, 0)>; 1234 def : Pat<(i32 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1235 (PLHApc $ga, 0)>; 1236 def : Pat<(i32 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1237 (PLHZpc $ga, 0)>; 1238 def : Pat<(i32 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1239 (PLHZpc $ga, 0)>; 1240 def : Pat<(i32 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLWZpc $ga, 0)>; 1241 1242 // Store i32 1243 def : Pat<(truncstorei8 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1244 (PSTBpc $RS, $ga, 0)>; 1245 def : Pat<(truncstorei16 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1246 (PSTHpc $RS, $ga, 0)>; 1247 def : Pat<(store i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1248 (PSTWpc $RS, $ga, 0)>; 1249 1250 // Load i64 1251 def : Pat<(i64 (zextloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1252 (PLBZ8pc $ga, 0)>; 1253 def : Pat<(i64 (extloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1254 (PLBZ8pc $ga, 0)>; 1255 def : Pat<(i64 (zextloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1256 (PLBZ8pc $ga, 0)>; 1257 def : Pat<(i64 (extloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1258 (PLBZ8pc $ga, 0)>; 1259 def : Pat<(i64 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1260 (PLHA8pc $ga, 0)>; 1261 def : Pat<(i64 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1262 (PLHZ8pc $ga, 0)>; 1263 def : Pat<(i64 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1264 (PLHZ8pc $ga, 0)>; 1265 def : Pat<(i64 (zextloadi32 (PPCmatpcreladdr PCRelForm:$ga))), 1266 (PLWZ8pc $ga, 0)>; 1267 def : Pat<(i64 (sextloadi32 (PPCmatpcreladdr PCRelForm:$ga))), 1268 (PLWA8pc $ga, 0)>; 1269 def : Pat<(i64 (extloadi32 (PPCmatpcreladdr PCRelForm:$ga))), 1270 (PLWZ8pc $ga, 0)>; 1271 def : Pat<(i64 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLDpc $ga, 0)>; 1272 1273 // Store i64 1274 def : Pat<(truncstorei8 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1275 (PSTB8pc $RS, $ga, 0)>; 1276 def : Pat<(truncstorei16 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1277 (PSTH8pc $RS, $ga, 0)>; 1278 def : Pat<(truncstorei32 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1279 (PSTW8pc $RS, $ga, 0)>; 1280 def : Pat<(store i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1281 (PSTDpc $RS, $ga, 0)>; 1282 1283 // Atomic Load 1284 def : Pat<(i32 (atomic_load_8 (PPCmatpcreladdr PCRelForm:$ga))), 1285 (PLBZpc $ga, 0)>; 1286 def : Pat<(i32 (atomic_load_16 (PPCmatpcreladdr PCRelForm:$ga))), 1287 (PLHZpc $ga, 0)>; 1288 def : Pat<(i32 (atomic_load_32 (PPCmatpcreladdr PCRelForm:$ga))), 1289 (PLWZpc $ga, 0)>; 1290 def : Pat<(i64 (atomic_load_64 (PPCmatpcreladdr PCRelForm:$ga))), 1291 (PLDpc $ga, 0)>; 1292 1293 // Atomic Store 1294 def : Pat<(atomic_store_8 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1295 (PSTBpc $RS, $ga, 0)>; 1296 def : Pat<(atomic_store_16 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1297 (PSTHpc $RS, $ga, 0)>; 1298 def : Pat<(atomic_store_32 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1299 (PSTWpc $RS, $ga, 0)>; 1300 def : Pat<(atomic_store_8 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1301 (PSTB8pc $RS, $ga, 0)>; 1302 def : Pat<(atomic_store_16 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1303 (PSTH8pc $RS, $ga, 0)>; 1304 def : Pat<(atomic_store_32 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1305 (PSTW8pc $RS, $ga, 0)>; 1306 def : Pat<(atomic_store_64 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1307 (PSTDpc $RS, $ga, 0)>; 1308 1309 // If the PPCmatpcreladdr node is not caught by any other pattern it should be 1310 // caught here and turned into a paddi instruction to materialize the address. 1311 def : Pat<(PPCmatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>; 1312 // PPCtlsdynamatpcreladdr node is used for TLS dynamic models to materialize 1313 // tls global address with paddi instruction. 1314 def : Pat<(PPCtlsdynamatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>; 1315 // PPCtlslocalexecmataddr node is used for TLS local exec models to 1316 // materialize tls global address with paddi instruction. 1317 def : Pat<(PPCaddTls i64:$in, (PPCtlslocalexecmataddr tglobaltlsaddr:$addr)), 1318 (PADDI8 $in, $addr)>; 1319} 1320 1321let Predicates = [PCRelativeMemops, HasFPU] in { 1322 // Load f32 1323 def : Pat<(f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFSpc $addr, 0)>; 1324 1325 // Store f32 1326 def : Pat<(store f32:$FRS, (PPCmatpcreladdr PCRelForm:$ga)), 1327 (PSTFSpc $FRS, $ga, 0)>; 1328 1329 // Load f64 1330 def : Pat<(f64 (extloadf32 (PPCmatpcreladdr PCRelForm:$addr))), 1331 (COPY_TO_REGCLASS (PLFSpc $addr, 0), VSFRC)>; 1332 def : Pat<(f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFDpc $addr, 0)>; 1333 1334 // Store f64 1335 def : Pat<(store f64:$FRS, (PPCmatpcreladdr PCRelForm:$ga)), 1336 (PSTFDpc $FRS, $ga, 0)>; 1337 1338 def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))), 1339 (SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>; 1340} 1341 1342let Predicates = [PCRelativeMemops, HasP10Vector] in { 1343 // Load f128 1344 def : Pat<(f128 (load (PPCmatpcreladdr PCRelForm:$addr))), 1345 (COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>; 1346 1347 // Store f128 1348 def : Pat<(store f128:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1349 (PSTXVpc (COPY_TO_REGCLASS $XS, VSRC), $ga, 0)>; 1350 1351 // Load v4i32 1352 def : Pat<(v4i32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1353 1354 // Store v4i32 1355 def : Pat<(store v4i32:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1356 (PSTXVpc $XS, $ga, 0)>; 1357 1358 // Load v2i64 1359 def : Pat<(v2i64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1360 1361 // Store v2i64 1362 def : Pat<(store v2i64:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1363 (PSTXVpc $XS, $ga, 0)>; 1364 1365 // Load v4f32 1366 def : Pat<(v4f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1367 1368 // Store v4f32 1369 def : Pat<(store v4f32:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1370 (PSTXVpc $XS, $ga, 0)>; 1371 1372 // Load v2f64 1373 def : Pat<(v2f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1374 1375 // Store v2f64 1376 def : Pat<(store v2f64:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1377 (PSTXVpc $XS, $ga, 0)>; 1378 1379 // Special Cases For PPCstore_scal_int_from_vsr 1380 def : Pat<(PPCstore_scal_int_from_vsr f64:$src, (PPCmatpcreladdr PCRelForm:$dst), 8), 1381 (PSTXSDpc $src, $dst, 0)>; 1382 def : Pat<(PPCstore_scal_int_from_vsr f128:$src, (PPCmatpcreladdr PCRelForm:$dst), 8), 1383 (PSTXSDpc (COPY_TO_REGCLASS $src, VFRC), $dst, 0)>; 1384} 1385 1386// XXSPLTIW/DP/32DX need extra flags to make sure the compiler does not attempt 1387// to spill part of the instruction when the values are similar. 1388let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, Predicates = [PrefixInstrs] in { 1389 def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT), 1390 (ins i32imm:$IMM32), 1391 "xxspltiw $XT, $IMM32", IIC_VecGeneral, 1392 []>; 1393 def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT), 1394 (ins i32imm:$IMM32), 1395 "xxspltidp $XT, $IMM32", IIC_VecGeneral, 1396 [(set v2f64:$XT, 1397 (PPCxxspltidp i32:$IMM32))]>; 1398 def XXSPLTI32DX : 1399 8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT), 1400 (ins vsrc:$XTi, u1imm:$IX, i32imm:$IMM32), 1401 "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral, 1402 [(set v2i64:$XT, 1403 (PPCxxsplti32dx v2i64:$XTi, i32:$IX, 1404 i32:$IMM32))]>, 1405 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; 1406} 1407 1408let Predicates = [IsISA3_1] in { 1409 def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RST), (ins crbitrc:$BI), 1410 "setbc $RST, $BI", IIC_IntCompare, 1411 [(set i32:$RST, (PPCsetbc i1:$BI))]>, 1412 SExt32To64, ZExt32To64; 1413 def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RST), (ins crbitrc:$BI), 1414 "setbcr $RST, $BI", IIC_IntCompare, 1415 [(set i32:$RST, (PPCsetbcr i1:$BI))]>, 1416 SExt32To64, ZExt32To64; 1417 def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RST), (ins crbitrc:$BI), 1418 "setnbc $RST, $BI", IIC_IntCompare, []>, 1419 SExt32To64; 1420 def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RST), (ins crbitrc:$BI), 1421 "setnbcr $RST, $BI", IIC_IntCompare, []>, 1422 SExt32To64; 1423 1424 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1425 def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RST), (ins crbitrc:$BI), 1426 "setbc $RST, $BI", IIC_IntCompare, []>, 1427 SExt32To64, ZExt32To64; 1428 def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RST), (ins crbitrc:$BI), 1429 "setbcr $RST, $BI", IIC_IntCompare, []>, 1430 SExt32To64, ZExt32To64; 1431 def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RST), (ins crbitrc:$BI), 1432 "setnbc $RST, $BI", IIC_IntCompare, []>, 1433 SExt32To64; 1434 def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RST), (ins crbitrc:$BI), 1435 "setnbcr $RST, $BI", IIC_IntCompare, []>, 1436 SExt32To64; 1437 } 1438 1439 def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT), 1440 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SD), 1441 "vsldbi $VRT, $VRA, $VRB, $SD", 1442 IIC_VecGeneral, 1443 [(set v16i8:$VRT, 1444 (int_ppc_altivec_vsldbi v16i8:$VRA, 1445 v16i8:$VRB, 1446 timm:$SD))]>; 1447 def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT), 1448 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SD), 1449 "vsrdbi $VRT, $VRA, $VRB, $SD", 1450 IIC_VecGeneral, 1451 [(set v16i8:$VRT, 1452 (int_ppc_altivec_vsrdbi v16i8:$VRA, 1453 v16i8:$VRB, 1454 timm:$SD))]>; 1455 defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$VT), (ins vrrc:$VB), 1456 "vstribr", "$VT, $VB", IIC_VecGeneral, 1457 [(set v16i8:$VT, 1458 (int_ppc_altivec_vstribr v16i8:$VB))]>; 1459 defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$VT), (ins vrrc:$VB), 1460 "vstribl", "$VT, $VB", IIC_VecGeneral, 1461 [(set v16i8:$VT, 1462 (int_ppc_altivec_vstribl v16i8:$VB))]>; 1463 defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$VT), (ins vrrc:$VB), 1464 "vstrihr", "$VT, $VB", IIC_VecGeneral, 1465 [(set v8i16:$VT, 1466 (int_ppc_altivec_vstrihr v8i16:$VB))]>; 1467 defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$VT), (ins vrrc:$VB), 1468 "vstrihl", "$VT, $VB", IIC_VecGeneral, 1469 [(set v8i16:$VT, 1470 (int_ppc_altivec_vstrihl v8i16:$VB))]>; 1471 def VINSW : 1472 VXForm_1<207, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, gprc:$VB), 1473 "vinsw $VD, $VB, $VA", IIC_VecGeneral, 1474 [(set v4i32:$VD, 1475 (int_ppc_altivec_vinsw v4i32:$VDi, i32:$VB, timm:$VA))]>, 1476 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 1477 def VINSD : 1478 VXForm_1<463, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, g8rc:$VB), 1479 "vinsd $VD, $VB, $VA", IIC_VecGeneral, 1480 [(set v2i64:$VD, 1481 (int_ppc_altivec_vinsd v2i64:$VDi, i64:$VB, timm:$VA))]>, 1482 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 1483 def VINSBVLX : 1484 VXForm_VTB5_RA5_ins<15, "vinsbvlx", 1485 [(set v16i8:$VD, 1486 (int_ppc_altivec_vinsbvlx v16i8:$VDi, i32:$VA, 1487 v16i8:$VB))]>; 1488 def VINSBVRX : 1489 VXForm_VTB5_RA5_ins<271, "vinsbvrx", 1490 [(set v16i8:$VD, 1491 (int_ppc_altivec_vinsbvrx v16i8:$VDi, i32:$VA, 1492 v16i8:$VB))]>; 1493 def VINSHVLX : 1494 VXForm_VTB5_RA5_ins<79, "vinshvlx", 1495 [(set v8i16:$VD, 1496 (int_ppc_altivec_vinshvlx v8i16:$VDi, i32:$VA, 1497 v8i16:$VB))]>; 1498 def VINSHVRX : 1499 VXForm_VTB5_RA5_ins<335, "vinshvrx", 1500 [(set v8i16:$VD, 1501 (int_ppc_altivec_vinshvrx v8i16:$VDi, i32:$VA, 1502 v8i16:$VB))]>; 1503 def VINSWVLX : 1504 VXForm_VTB5_RA5_ins<143, "vinswvlx", 1505 [(set v4i32:$VD, 1506 (int_ppc_altivec_vinswvlx v4i32:$VDi, i32:$VA, 1507 v4i32:$VB))]>; 1508 def VINSWVRX : 1509 VXForm_VTB5_RA5_ins<399, "vinswvrx", 1510 [(set v4i32:$VD, 1511 (int_ppc_altivec_vinswvrx v4i32:$VDi, i32:$VA, 1512 v4i32:$VB))]>; 1513 def VINSBLX : 1514 VXForm_VRT5_RAB5_ins<527, "vinsblx", 1515 [(set v16i8:$VD, 1516 (int_ppc_altivec_vinsblx v16i8:$VDi, i32:$VA, 1517 i32:$VB))]>; 1518 def VINSBRX : 1519 VXForm_VRT5_RAB5_ins<783, "vinsbrx", 1520 [(set v16i8:$VD, 1521 (int_ppc_altivec_vinsbrx v16i8:$VDi, i32:$VA, 1522 i32:$VB))]>; 1523 def VINSHLX : 1524 VXForm_VRT5_RAB5_ins<591, "vinshlx", 1525 [(set v8i16:$VD, 1526 (int_ppc_altivec_vinshlx v8i16:$VDi, i32:$VA, 1527 i32:$VB))]>; 1528 def VINSHRX : 1529 VXForm_VRT5_RAB5_ins<847, "vinshrx", 1530 [(set v8i16:$VD, 1531 (int_ppc_altivec_vinshrx v8i16:$VDi, i32:$VA, 1532 i32:$VB))]>; 1533 def VINSWLX : 1534 VXForm_VRT5_RAB5_ins<655, "vinswlx", 1535 [(set v4i32:$VD, 1536 (int_ppc_altivec_vinswlx v4i32:$VDi, i32:$VA, 1537 i32:$VB))]>; 1538 def VINSWRX : 1539 VXForm_VRT5_RAB5_ins<911, "vinswrx", 1540 [(set v4i32:$VD, 1541 (int_ppc_altivec_vinswrx v4i32:$VDi, i32:$VA, 1542 i32:$VB))]>; 1543 def VINSDLX : 1544 VXForm_1<719, (outs vrrc:$VD), (ins vrrc:$VDi, g8rc:$VA, g8rc:$VB), 1545 "vinsdlx $VD, $VA, $VB", IIC_VecGeneral, 1546 [(set v2i64:$VD, 1547 (int_ppc_altivec_vinsdlx v2i64:$VDi, i64:$VA, i64:$VB))]>, 1548 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 1549 def VINSDRX : 1550 VXForm_1<975, (outs vrrc:$VD), (ins vrrc:$VDi, g8rc:$VA, g8rc:$VB), 1551 "vinsdrx $VD, $VA, $VB", IIC_VecGeneral, 1552 [(set v2i64:$VD, 1553 (int_ppc_altivec_vinsdrx v2i64:$VDi, i64:$VA, i64:$VB))]>, 1554 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 1555 def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$VD), (ins vrrc:$VB), 1556 "vextractbm $VD, $VB", IIC_VecGeneral, 1557 [(set i32:$VD, 1558 (int_ppc_altivec_vextractbm v16i8:$VB))]>, 1559 ZExt32To64; 1560 def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$VD), (ins vrrc:$VB), 1561 "vextracthm $VD, $VB", IIC_VecGeneral, 1562 [(set i32:$VD, 1563 (int_ppc_altivec_vextracthm v8i16:$VB))]>, 1564 ZExt32To64; 1565 def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$VD), (ins vrrc:$VB), 1566 "vextractwm $VD, $VB", IIC_VecGeneral, 1567 [(set i32:$VD, 1568 (int_ppc_altivec_vextractwm v4i32:$VB))]>, 1569 ZExt32To64; 1570 def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$VD), (ins vrrc:$VB), 1571 "vextractdm $VD, $VB", IIC_VecGeneral, 1572 [(set i32:$VD, 1573 (int_ppc_altivec_vextractdm v2i64:$VB))]>, 1574 ZExt32To64; 1575 def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$VD), (ins vrrc:$VB), 1576 "vextractqm $VD, $VB", IIC_VecGeneral, 1577 [(set i32:$VD, 1578 (int_ppc_altivec_vextractqm v1i128:$VB))]>; 1579 def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$VD), (ins vrrc:$VB), 1580 "vexpandbm $VD, $VB", IIC_VecGeneral, 1581 [(set v16i8:$VD, (int_ppc_altivec_vexpandbm 1582 v16i8:$VB))]>; 1583 def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$VD), (ins vrrc:$VB), 1584 "vexpandhm $VD, $VB", IIC_VecGeneral, 1585 [(set v8i16:$VD, (int_ppc_altivec_vexpandhm 1586 v8i16:$VB))]>; 1587 def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$VD), (ins vrrc:$VB), 1588 "vexpandwm $VD, $VB", IIC_VecGeneral, 1589 [(set v4i32:$VD, (int_ppc_altivec_vexpandwm 1590 v4i32:$VB))]>; 1591 def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$VD), (ins vrrc:$VB), 1592 "vexpanddm $VD, $VB", IIC_VecGeneral, 1593 [(set v2i64:$VD, (int_ppc_altivec_vexpanddm 1594 v2i64:$VB))]>; 1595 def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$VD), (ins vrrc:$VB), 1596 "vexpandqm $VD, $VB", IIC_VecGeneral, 1597 [(set v1i128:$VD, (int_ppc_altivec_vexpandqm 1598 v1i128:$VB))]>; 1599 def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$VD), (ins g8rc:$VB), 1600 "mtvsrbm $VD, $VB", IIC_VecGeneral, 1601 [(set v16i8:$VD, 1602 (int_ppc_altivec_mtvsrbm i64:$VB))]>; 1603 def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$VD), (ins g8rc:$VB), 1604 "mtvsrhm $VD, $VB", IIC_VecGeneral, 1605 [(set v8i16:$VD, 1606 (int_ppc_altivec_mtvsrhm i64:$VB))]>; 1607 def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$VD), (ins g8rc:$VB), 1608 "mtvsrwm $VD, $VB", IIC_VecGeneral, 1609 [(set v4i32:$VD, 1610 (int_ppc_altivec_mtvsrwm i64:$VB))]>; 1611 def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$VD), (ins g8rc:$VB), 1612 "mtvsrdm $VD, $VB", IIC_VecGeneral, 1613 [(set v2i64:$VD, 1614 (int_ppc_altivec_mtvsrdm i64:$VB))]>; 1615 def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$VD), (ins g8rc:$VB), 1616 "mtvsrqm $VD, $VB", IIC_VecGeneral, 1617 [(set v1i128:$VD, 1618 (int_ppc_altivec_mtvsrqm i64:$VB))]>; 1619 def MTVSRBMI : DXForm<4, 10, (outs vrrc:$RT), (ins u16imm64:$D), 1620 "mtvsrbmi $RT, $D", IIC_VecGeneral, 1621 [(set v16i8:$RT, 1622 (int_ppc_altivec_mtvsrbm imm:$D))]>; 1623 def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$RD), 1624 (ins vrrc:$VB, u1imm:$MP), 1625 "vcntmbb $RD, $VB, $MP", IIC_VecGeneral, 1626 [(set i64:$RD, (int_ppc_altivec_vcntmbb 1627 v16i8:$VB, timm:$MP))]>; 1628 def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$RD), 1629 (ins vrrc:$VB, u1imm:$MP), 1630 "vcntmbh $RD, $VB, $MP", IIC_VecGeneral, 1631 [(set i64:$RD, (int_ppc_altivec_vcntmbh 1632 v8i16:$VB, timm:$MP))]>; 1633 def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$RD), 1634 (ins vrrc:$VB, u1imm:$MP), 1635 "vcntmbw $RD, $VB, $MP", IIC_VecGeneral, 1636 [(set i64:$RD, (int_ppc_altivec_vcntmbw 1637 v4i32:$VB, timm:$MP))]>; 1638 def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$RD), 1639 (ins vrrc:$VB, u1imm:$MP), 1640 "vcntmbd $RD, $VB, $MP", IIC_VecGeneral, 1641 [(set i64:$RD, (int_ppc_altivec_vcntmbd 1642 v2i64:$VB, timm:$MP))]>; 1643 def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$RT), 1644 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1645 "vextdubvlx $RT, $RA, $RB, $RC", 1646 IIC_VecGeneral, 1647 [(set v2i64:$RT, 1648 (int_ppc_altivec_vextdubvlx v16i8:$RA, 1649 v16i8:$RB, 1650 i32:$RC))]>; 1651 def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$RT), 1652 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1653 "vextdubvrx $RT, $RA, $RB, $RC", 1654 IIC_VecGeneral, 1655 [(set v2i64:$RT, 1656 (int_ppc_altivec_vextdubvrx v16i8:$RA, 1657 v16i8:$RB, 1658 i32:$RC))]>; 1659 def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$RT), 1660 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1661 "vextduhvlx $RT, $RA, $RB, $RC", 1662 IIC_VecGeneral, 1663 [(set v2i64:$RT, 1664 (int_ppc_altivec_vextduhvlx v8i16:$RA, 1665 v8i16:$RB, 1666 i32:$RC))]>; 1667 def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$RT), 1668 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1669 "vextduhvrx $RT, $RA, $RB, $RC", 1670 IIC_VecGeneral, 1671 [(set v2i64:$RT, 1672 (int_ppc_altivec_vextduhvrx v8i16:$RA, 1673 v8i16:$RB, 1674 i32:$RC))]>; 1675 def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$RT), 1676 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1677 "vextduwvlx $RT, $RA, $RB, $RC", 1678 IIC_VecGeneral, 1679 [(set v2i64:$RT, 1680 (int_ppc_altivec_vextduwvlx v4i32:$RA, 1681 v4i32:$RB, 1682 i32:$RC))]>; 1683 def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$RT), 1684 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1685 "vextduwvrx $RT, $RA, $RB, $RC", 1686 IIC_VecGeneral, 1687 [(set v2i64:$RT, 1688 (int_ppc_altivec_vextduwvrx v4i32:$RA, 1689 v4i32:$RB, 1690 i32:$RC))]>; 1691 def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$RT), 1692 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1693 "vextddvlx $RT, $RA, $RB, $RC", 1694 IIC_VecGeneral, 1695 [(set v2i64:$RT, 1696 (int_ppc_altivec_vextddvlx v2i64:$RA, 1697 v2i64:$RB, 1698 i32:$RC))]>; 1699 def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$RT), 1700 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1701 "vextddvrx $RT, $RA, $RB, $RC", 1702 IIC_VecGeneral, 1703 [(set v2i64:$RT, 1704 (int_ppc_altivec_vextddvrx v2i64:$RA, 1705 v2i64:$RB, 1706 i32:$RC))]>; 1707 def VPDEPD : VXForm_1<1485, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1708 "vpdepd $VD, $VA, $VB", IIC_VecGeneral, 1709 [(set v2i64:$VD, 1710 (int_ppc_altivec_vpdepd v2i64:$VA, v2i64:$VB))]>; 1711 def VPEXTD : VXForm_1<1421, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1712 "vpextd $VD, $VA, $VB", IIC_VecGeneral, 1713 [(set v2i64:$VD, 1714 (int_ppc_altivec_vpextd v2i64:$VA, v2i64:$VB))]>; 1715 def PDEPD : XForm_6<31, 156, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1716 "pdepd $RA, $RST, $RB", IIC_IntGeneral, 1717 [(set i64:$RA, (int_ppc_pdepd i64:$RST, i64:$RB))]>; 1718 def PEXTD : XForm_6<31, 188, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1719 "pextd $RA, $RST, $RB", IIC_IntGeneral, 1720 [(set i64:$RA, (int_ppc_pextd i64:$RST, i64:$RB))]>; 1721 def VCFUGED : VXForm_1<1357, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1722 "vcfuged $VD, $VA, $VB", IIC_VecGeneral, 1723 [(set v2i64:$VD, 1724 (int_ppc_altivec_vcfuged v2i64:$VA, v2i64:$VB))]>; 1725 def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$RD), (ins vrrc:$VB, u3imm:$N), 1726 "vgnb $RD, $VB, $N", IIC_VecGeneral, 1727 [(set i64:$RD, 1728 (int_ppc_altivec_vgnb v1i128:$VB, timm:$N))]>; 1729 def CFUGED : XForm_6<31, 220, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1730 "cfuged $RA, $RST, $RB", IIC_IntGeneral, 1731 [(set i64:$RA, (int_ppc_cfuged i64:$RST, i64:$RB))]>; 1732 def XXEVAL : 1733 8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1734 vsrc:$XC, u8imm:$IMM), 1735 "xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral, 1736 [(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA, 1737 v2i64:$XB, v2i64:$XC, timm:$IMM))]>; 1738 def VCLZDM : VXForm_1<1924, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1739 "vclzdm $VD, $VA, $VB", IIC_VecGeneral, 1740 [(set v2i64:$VD, 1741 (int_ppc_altivec_vclzdm v2i64:$VA, v2i64:$VB))]>; 1742 def VCTZDM : VXForm_1<1988, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1743 "vctzdm $VD, $VA, $VB", IIC_VecGeneral, 1744 [(set v2i64:$VD, 1745 (int_ppc_altivec_vctzdm v2i64:$VA, v2i64:$VB))]>; 1746 def CNTLZDM : XForm_6<31, 59, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1747 "cntlzdm $RA, $RST, $RB", IIC_IntGeneral, 1748 [(set i64:$RA, 1749 (int_ppc_cntlzdm i64:$RST, i64:$RB))]>; 1750 def CNTTZDM : XForm_6<31, 571, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1751 "cnttzdm $RA, $RST, $RB", IIC_IntGeneral, 1752 [(set i64:$RA, 1753 (int_ppc_cnttzdm i64:$RST, i64:$RB))]>; 1754 def XXGENPCVBM : 1755 XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1756 "xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1757 def XXGENPCVHM : 1758 XForm_XT6_IMM5_VB5<60, 917, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1759 "xxgenpcvhm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1760 def XXGENPCVWM : 1761 XForm_XT6_IMM5_VB5<60, 948, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1762 "xxgenpcvwm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1763 def XXGENPCVDM : 1764 XForm_XT6_IMM5_VB5<60, 949, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1765 "xxgenpcvdm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1766 def VCLRLB : VXForm_1<397, (outs vrrc:$VD), (ins vrrc:$VA, gprc:$VB), 1767 "vclrlb $VD, $VA, $VB", IIC_VecGeneral, 1768 [(set v16i8:$VD, 1769 (int_ppc_altivec_vclrlb v16i8:$VA, i32:$VB))]>; 1770 def VCLRRB : VXForm_1<461, (outs vrrc:$VD), (ins vrrc:$VA, gprc:$VB), 1771 "vclrrb $VD, $VA, $VB", IIC_VecGeneral, 1772 [(set v16i8:$VD, 1773 (int_ppc_altivec_vclrrb v16i8:$VA, i32:$VB))]>; 1774 def VMULLD : VXForm_1<457, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1775 "vmulld $VD, $VA, $VB", IIC_VecGeneral, 1776 [(set v2i64:$VD, (mul v2i64:$VA, v2i64:$VB))]>; 1777 def VMULHSW : VXForm_1<905, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1778 "vmulhsw $VD, $VA, $VB", IIC_VecGeneral, 1779 [(set v4i32:$VD, (mulhs v4i32:$VA, v4i32:$VB))]>; 1780 def VMULHUW : VXForm_1<649, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1781 "vmulhuw $VD, $VA, $VB", IIC_VecGeneral, 1782 [(set v4i32:$VD, (mulhu v4i32:$VA, v4i32:$VB))]>; 1783 def VMULHSD : VXForm_1<969, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1784 "vmulhsd $VD, $VA, $VB", IIC_VecGeneral, 1785 [(set v2i64:$VD, (mulhs v2i64:$VA, v2i64:$VB))]>; 1786 def VMULHUD : VXForm_1<713, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1787 "vmulhud $VD, $VA, $VB", IIC_VecGeneral, 1788 [(set v2i64:$VD, (mulhu v2i64:$VA, v2i64:$VB))]>; 1789 def VMODSW : VXForm_1<1931, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1790 "vmodsw $VD, $VA, $VB", IIC_VecGeneral, 1791 [(set v4i32:$VD, (srem v4i32:$VA, v4i32:$VB))]>; 1792 def VMODUW : VXForm_1<1675, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1793 "vmoduw $VD, $VA, $VB", IIC_VecGeneral, 1794 [(set v4i32:$VD, (urem v4i32:$VA, v4i32:$VB))]>; 1795 def VMODSD : VXForm_1<1995, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1796 "vmodsd $VD, $VA, $VB", IIC_VecGeneral, 1797 [(set v2i64:$VD, (srem v2i64:$VA, v2i64:$VB))]>; 1798 def VMODUD : VXForm_1<1739, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1799 "vmodud $VD, $VA, $VB", IIC_VecGeneral, 1800 [(set v2i64:$VD, (urem v2i64:$VA, v2i64:$VB))]>; 1801 def VDIVSW : VXForm_1<395, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1802 "vdivsw $VD, $VA, $VB", IIC_VecGeneral, 1803 [(set v4i32:$VD, (sdiv v4i32:$VA, v4i32:$VB))]>; 1804 def VDIVUW : VXForm_1<139, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1805 "vdivuw $VD, $VA, $VB", IIC_VecGeneral, 1806 [(set v4i32:$VD, (udiv v4i32:$VA, v4i32:$VB))]>; 1807 def VDIVSD : VXForm_1<459, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1808 "vdivsd $VD, $VA, $VB", IIC_VecGeneral, 1809 [(set v2i64:$VD, (sdiv v2i64:$VA, v2i64:$VB))]>; 1810 def VDIVUD : VXForm_1<203, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1811 "vdivud $VD, $VA, $VB", IIC_VecGeneral, 1812 [(set v2i64:$VD, (udiv v2i64:$VA, v2i64:$VB))]>; 1813 def VDIVESW : VXForm_1<907, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1814 "vdivesw $VD, $VA, $VB", IIC_VecGeneral, 1815 [(set v4i32:$VD, (int_ppc_altivec_vdivesw v4i32:$VA, 1816 v4i32:$VB))]>; 1817 def VDIVEUW : VXForm_1<651, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1818 "vdiveuw $VD, $VA, $VB", IIC_VecGeneral, 1819 [(set v4i32:$VD, (int_ppc_altivec_vdiveuw v4i32:$VA, 1820 v4i32:$VB))]>; 1821 def VDIVESD : VXForm_1<971, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1822 "vdivesd $VD, $VA, $VB", IIC_VecGeneral, 1823 [(set v2i64:$VD, (int_ppc_altivec_vdivesd v2i64:$VA, 1824 v2i64:$VB))]>; 1825 def VDIVEUD : VXForm_1<715, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1826 "vdiveud $VD, $VA, $VB", IIC_VecGeneral, 1827 [(set v2i64:$VD, (int_ppc_altivec_vdiveud v2i64:$VA, 1828 v2i64:$VB))]>; 1829 def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB), 1830 "xvtlsbb $BF, $XB", IIC_VecGeneral, []>; 1831 def BRH : XForm_11<31, 219, (outs gprc:$RA), (ins gprc:$RST), 1832 "brh $RA, $RST", IIC_IntRotate, []>; 1833 def BRW : XForm_11<31, 155, (outs gprc:$RA), (ins gprc:$RST), 1834 "brw $RA, $RST", IIC_IntRotate, 1835 [(set i32:$RA, (bswap i32:$RST))]>; 1836 let isCodeGenOnly = 1 in { 1837 def BRH8 : XForm_11<31, 219, (outs g8rc:$RA), (ins g8rc:$RST), 1838 "brh $RA, $RST", IIC_IntRotate, []>; 1839 def BRW8 : XForm_11<31, 155, (outs g8rc:$RA), (ins g8rc:$RST), 1840 "brw $RA, $RST", IIC_IntRotate, []>; 1841 } 1842 def BRD : XForm_11<31, 187, (outs g8rc:$RA), (ins g8rc:$RST), 1843 "brd $RA, $RST", IIC_IntRotate, 1844 [(set i64:$RA, (bswap i64:$RST))]>; 1845 1846 // The XFormMemOp flag for the following 8 instructions is set on 1847 // the instruction format. 1848 let mayLoad = 1, mayStore = 0 in { 1849 def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>; 1850 def LXVRHX : X_XT6_RA5_RB5<31, 45, "lxvrhx", vsrc, []>; 1851 def LXVRWX : X_XT6_RA5_RB5<31, 77, "lxvrwx", vsrc, []>; 1852 def LXVRDX : X_XT6_RA5_RB5<31, 109, "lxvrdx", vsrc, []>; 1853 } 1854 1855 let mayLoad = 0, mayStore = 1 in { 1856 def STXVRBX : X_XS6_RA5_RB5<31, 141, "stxvrbx", vsrc, []>; 1857 def STXVRHX : X_XS6_RA5_RB5<31, 173, "stxvrhx", vsrc, []>; 1858 def STXVRWX : X_XS6_RA5_RB5<31, 205, "stxvrwx", vsrc, []>; 1859 def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>; 1860 } 1861 1862 def VMULESD : VXForm_1<968, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1863 "vmulesd $VD, $VA, $VB", IIC_VecGeneral, 1864 [(set v1i128:$VD, (int_ppc_altivec_vmulesd v2i64:$VA, 1865 v2i64:$VB))]>; 1866 def VMULEUD : VXForm_1<712, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1867 "vmuleud $VD, $VA, $VB", IIC_VecGeneral, 1868 [(set v1i128:$VD, (int_ppc_altivec_vmuleud v2i64:$VA, 1869 v2i64:$VB))]>; 1870 def VMULOSD : VXForm_1<456, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1871 "vmulosd $VD, $VA, $VB", IIC_VecGeneral, 1872 [(set v1i128:$VD, (int_ppc_altivec_vmulosd v2i64:$VA, 1873 v2i64:$VB))]>; 1874 def VMULOUD : VXForm_1<200, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1875 "vmuloud $VD, $VA, $VB", IIC_VecGeneral, 1876 [(set v1i128:$VD, (int_ppc_altivec_vmuloud v2i64:$VA, 1877 v2i64:$VB))]>; 1878 def VMSUMCUD : VAForm_1a<23, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC), 1879 "vmsumcud $RT, $RA, $RB, $RC", IIC_VecGeneral, 1880 [(set v1i128:$RT, (int_ppc_altivec_vmsumcud 1881 v2i64:$RA, v2i64:$RB, v1i128:$RC))]>; 1882 def VDIVSQ : VXForm_1<267, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1883 "vdivsq $VD, $VA, $VB", IIC_VecGeneral, 1884 [(set v1i128:$VD, (sdiv v1i128:$VA, v1i128:$VB))]>; 1885 def VDIVUQ : VXForm_1<11, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1886 "vdivuq $VD, $VA, $VB", IIC_VecGeneral, 1887 [(set v1i128:$VD, (udiv v1i128:$VA, v1i128:$VB))]>; 1888 def VDIVESQ : VXForm_1<779, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1889 "vdivesq $VD, $VA, $VB", IIC_VecGeneral, 1890 [(set v1i128:$VD, (int_ppc_altivec_vdivesq v1i128:$VA, 1891 v1i128:$VB))]>; 1892 def VDIVEUQ : VXForm_1<523, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1893 "vdiveuq $VD, $VA, $VB", IIC_VecGeneral, 1894 [(set v1i128:$VD, (int_ppc_altivec_vdiveuq v1i128:$VA, 1895 v1i128:$VB))]>; 1896 def VCMPEQUQ : VCMP <455, "vcmpequq $VD, $VA, $VB" , v1i128>; 1897 def VCMPGTSQ : VCMP <903, "vcmpgtsq $VD, $VA, $VB" , v1i128>; 1898 def VCMPGTUQ : VCMP <647, "vcmpgtuq $VD, $VA, $VB" , v1i128>; 1899 def VCMPEQUQ_rec : VCMP_rec <455, "vcmpequq. $VD, $VA, $VB" , v1i128>; 1900 def VCMPGTSQ_rec : VCMP_rec <903, "vcmpgtsq. $VD, $VA, $VB" , v1i128>; 1901 def VCMPGTUQ_rec : VCMP_rec <647, "vcmpgtuq. $VD, $VA, $VB" , v1i128>; 1902 def VMODSQ : VXForm_1<1803, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1903 "vmodsq $VD, $VA, $VB", IIC_VecGeneral, 1904 [(set v1i128:$VD, (srem v1i128:$VA, v1i128:$VB))]>; 1905 def VMODUQ : VXForm_1<1547, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1906 "vmoduq $VD, $VA, $VB", IIC_VecGeneral, 1907 [(set v1i128:$VD, (urem v1i128:$VA, v1i128:$VB))]>; 1908 def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$VD), (ins vrrc:$VB), 1909 "vextsd2q $VD, $VB", IIC_VecGeneral, 1910 [(set v1i128:$VD, (int_ppc_altivec_vextsd2q v2i64:$VB))]>; 1911 def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$VA, vrrc:$VB), 1912 "vcmpuq $BF, $VA, $VB", IIC_VecGeneral, []>; 1913 def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$VA, vrrc:$VB), 1914 "vcmpsq $BF, $VA, $VB", IIC_VecGeneral, []>; 1915 def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm", 1916 [(set v1i128:$VD, 1917 (int_ppc_altivec_vrlqnm v1i128:$VA, 1918 v1i128:$VB))]>; 1919 def VRLQMI : VXForm_1<69, (outs vrrc:$VD), 1920 (ins vrrc:$VA, vrrc:$VB, vrrc:$VDi), 1921 "vrlqmi $VD, $VA, $VB", IIC_VecFP, 1922 [(set v1i128:$VD, 1923 (int_ppc_altivec_vrlqmi v1i128:$VA, v1i128:$VB, 1924 v1i128:$VDi))]>, 1925 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 1926 def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>; 1927 def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>; 1928 def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>; 1929 def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>; 1930 def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>; 1931 def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>; 1932 def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>; 1933 def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>; 1934 def LXVKQ : XForm_XT6_IMM5<60, 31, 360, (outs vsrc:$XT), (ins u5imm:$UIM), 1935 "lxvkq $XT, $UIM", IIC_VecGeneral, []>; 1936} 1937 1938let Predicates = [IsISA3_1, HasVSX] in { 1939 def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>; 1940 def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>; 1941 def XSMAXCQP : X_VT5_VA5_VB5<63, 676, "xsmaxcqp", 1942 [(set f128:$RST, (PPCxsmaxc f128:$RA, f128:$RB))]>; 1943 def XSMINCQP : X_VT5_VA5_VB5<63, 740, "xsmincqp", 1944 [(set f128:$RST, (PPCxsminc f128:$RA, f128:$RB))]>; 1945} 1946 1947let Predicates = [IsISA3_1] in { 1948 def WAITP10 : XForm_IMM2_IMM2<31, 30, (outs), (ins u2imm:$L, u2imm:$PL), 1949 "wait $L $PL", IIC_LdStLoad, []>; 1950 def SYNCP10 : XForm_IMM3_IMM2<31, 598, (outs), (ins u3imm:$L, u2imm:$SC), 1951 "sync $L, $SC", IIC_LdStSync, []>; 1952} 1953 1954// Multiclass defining patterns for Set Boolean Extension Reverse Instructions. 1955// This is analogous to the CRNotPat multiclass but specifically for Power10 1956// and newer subtargets since the extended forms use Set Boolean instructions. 1957// The first two anonymous patterns defined are actually a duplicate of those 1958// in CRNotPat, but it is preferable to define both multiclasses as complete 1959// ones rather than pulling that small common section out. 1960multiclass P10ReverseSetBool<dag pattern, dag result> { 1961 def : Pat<pattern, (crnot result)>; 1962 def : Pat<(not pattern), result>; 1963 1964 def : Pat<(i32 (zext pattern)), 1965 (SETBCR result)>; 1966 def : Pat<(i64 (zext pattern)), 1967 (SETBCR8 result)>; 1968 1969 def : Pat<(i32 (sext pattern)), 1970 (SETNBCR result)>; 1971 def : Pat<(i64 (sext pattern)), 1972 (SETNBCR8 result)>; 1973 1974 def : Pat<(i32 (anyext pattern)), 1975 (SETBCR result)>; 1976 def : Pat<(i64 (anyext pattern)), 1977 (SETBCR8 result)>; 1978} 1979 1980multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf ZExtTy, 1981 ImmLeaf SExtTy, I Cmpi, I Cmpli, 1982 I Cmp, I Cmpl> { 1983 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 1984 (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_lt)>; 1985 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 1986 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_lt)>; 1987 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 1988 (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_gt)>; 1989 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 1990 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_gt)>; 1991 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 1992 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_eq)>; 1993 1994 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)), 1995 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_lt)>; 1996 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)), 1997 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_lt)>; 1998 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)), 1999 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_gt)>; 2000 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)), 2001 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_gt)>; 2002 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETNE)), 2003 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_eq)>; 2004 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETNE)), 2005 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_eq)>; 2006} 2007 2008multiclass FSetP10RevSetBool<SDNode SetCC, ValueType Ty, I FCmp> { 2009 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 2010 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 2011 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 2012 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 2013 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 2014 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 2015 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 2016 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 2017 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)), 2018 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 2019 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 2020 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 2021 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)), 2022 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 2023} 2024 2025let Predicates = [IsISA3_1] in { 2026 def : Pat<(i32 (zext i1:$in)), 2027 (SETBC $in)>; 2028 def : Pat<(i64 (zext i1:$in)), 2029 (SETBC8 $in)>; 2030 def : Pat<(i32 (sext i1:$in)), 2031 (SETNBC $in)>; 2032 def : Pat<(i64 (sext i1:$in)), 2033 (SETNBC8 $in)>; 2034 def : Pat<(i32 (anyext i1:$in)), 2035 (SETBC $in)>; 2036 def : Pat<(i64 (anyext i1:$in)), 2037 (SETBC8 $in)>; 2038 2039 // Instantiation of the set boolean reverse patterns for 32-bit integers. 2040 defm : IntSetP10RevSetBool<setcc, i32, immZExt16, imm32SExt16, 2041 CMPWI, CMPLWI, CMPW, CMPLW>; 2042 defm : P10ReverseSetBool<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 2043 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 2044 (LO16 imm:$imm)), sub_eq)>; 2045 2046 // Instantiation of the set boolean reverse patterns for 64-bit integers. 2047 defm : IntSetP10RevSetBool<setcc, i64, immZExt16, imm64SExt16, 2048 CMPDI, CMPLDI, CMPD, CMPLD>; 2049 defm : P10ReverseSetBool<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 2050 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 2051 (LO16 imm:$imm)), sub_eq)>; 2052} 2053 2054// Instantiation of the set boolean reverse patterns for f32, f64, f128. 2055let Predicates = [IsISA3_1, HasFPU] in { 2056 defm : FSetP10RevSetBool<setcc, f32, FCMPUS>; 2057 defm : FSetP10RevSetBool<setcc, f64, FCMPUD>; 2058 defm : FSetP10RevSetBool<setcc, f128, XSCMPUQP>; 2059} 2060 2061//---------------------------- Anonymous Patterns ----------------------------// 2062let Predicates = [IsISA3_1] in { 2063 // Exploit the vector multiply high instructions using intrinsics. 2064 def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$vA, v4i32:$vB)), 2065 (v4i32 (VMULHSW $vA, $vB))>; 2066 def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$vA, v4i32:$vB)), 2067 (v4i32 (VMULHUW $vA, $vB))>; 2068 def : Pat<(v2i64 (int_ppc_altivec_vmulhsd v2i64:$vA, v2i64:$vB)), 2069 (v2i64 (VMULHSD $vA, $vB))>; 2070 def : Pat<(v2i64 (int_ppc_altivec_vmulhud v2i64:$vA, v2i64:$vB)), 2071 (v2i64 (VMULHUD $vA, $vB))>; 2072 def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)), 2073 (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>; 2074 def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)), 2075 (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>; 2076 def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)), 2077 (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>; 2078 def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)), 2079 (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>; 2080 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)), 2081 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>; 2082 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)), 2083 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>; 2084 def : Pat<(srl (bswap i32:$RS), (i32 16)), 2085 (RLDICL_32 (BRH $RS), 0, 48)>; 2086 def : Pat<(i64 (zext (i32 (srl (bswap i32:$RS), (i32 16))))), 2087 (RLDICL_32_64 (BRH $RS), 0, 48)>; 2088 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 8)), 2089 (v1i128 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VRRC))>; 2090 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 16)), 2091 (v1i128 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VRRC))>; 2092 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 32)), 2093 (v1i128 (COPY_TO_REGCLASS (LXVRWX ForceXForm:$src), VRRC))>; 2094 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 64)), 2095 (v1i128 (COPY_TO_REGCLASS (LXVRDX ForceXForm:$src), VRRC))>; 2096 2097 def : Pat<(v1i128 (rotl v1i128:$vA, v1i128:$vB)), 2098 (v1i128 (VRLQ v1i128:$vA, v1i128:$vB))>; 2099 2100 def : Pat <(v2i64 (PPCxxsplti32dx v2i64:$XT, i32:$XI, i32:$IMM32)), 2101 (v2i64 (XXSPLTI32DX v2i64:$XT, i32:$XI, i32:$IMM32))>; 2102} 2103 2104let Predicates = [IsISA3_1, HasVSX] in { 2105 def : Pat<(v16i8 (int_ppc_vsx_xvcvspbf16 v16i8:$XA)), 2106 (COPY_TO_REGCLASS (XVCVSPBF16 RCCp.AToVSRC), VRRC)>; 2107 def : Pat<(v16i8 (int_ppc_vsx_xvcvbf16spn v16i8:$XA)), 2108 (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>; 2109} 2110 2111let AddedComplexity = 400, Predicates = [IsISA3_1, IsLittleEndian] in { 2112 // Store element 0 of a VSX register to memory 2113 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$src, 0)), ForceXForm:$dst), 2114 (STXVRBX (COPY_TO_REGCLASS v16i8:$src, VSRC), ForceXForm:$dst)>; 2115 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$src, 0)), ForceXForm:$dst), 2116 (STXVRHX (COPY_TO_REGCLASS v8i16:$src, VSRC), ForceXForm:$dst)>; 2117 def : Pat<(store (i32 (extractelt v4i32:$src, 0)), ForceXForm:$dst), 2118 (STXVRWX $src, ForceXForm:$dst)>; 2119 def : Pat<(store (f32 (extractelt v4f32:$src, 0)), ForceXForm:$dst), 2120 (STXVRWX $src, ForceXForm:$dst)>; 2121 def : Pat<(store (i64 (extractelt v2i64:$src, 0)), ForceXForm:$dst), 2122 (STXVRDX $src, ForceXForm:$dst)>; 2123 def : Pat<(store (f64 (extractelt v2f64:$src, 0)), ForceXForm:$dst), 2124 (STXVRDX $src, ForceXForm:$dst)>; 2125 // Load element 0 of a VSX register to memory 2126 def : Pat<(v8i16 (scalar_to_vector (i32 (extloadi16 ForceXForm:$src)))), 2127 (v8i16 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VSRC))>; 2128 def : Pat<(v16i8 (scalar_to_vector (i32 (extloadi8 ForceXForm:$src)))), 2129 (v16i8 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VSRC))>; 2130 def : Pat<(store (i64 (extractelt v2i64:$A, 1)), ForceXForm:$src), 2131 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 2132 } 2133 2134let Predicates = [IsISA3_1, IsBigEndian] in { 2135 def : Pat<(store (i64 (extractelt v2i64:$A, 0)), ForceXForm:$src), 2136 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 2137} 2138 2139// FIXME: The swap is overkill when the shift amount is a constant. 2140// We should just fix the constant in the DAG. 2141let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in { 2142 def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)), 2143 (v1i128 (VSLQ v1i128:$VRA, 2144 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2145 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2146 def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)), 2147 (v1i128 (VSLQ v1i128:$VRA, 2148 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2149 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2150 def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)), 2151 (v1i128 (VSRQ v1i128:$VRA, 2152 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2153 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2154 def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)), 2155 (v1i128 (VSRQ v1i128:$VRA, 2156 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2157 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2158 def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)), 2159 (v1i128 (VSRAQ v1i128:$VRA, 2160 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2161 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2162 def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)), 2163 (v1i128 (VSRAQ v1i128:$VRA, 2164 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2165 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2166} 2167 2168class xxevalPattern <dag pattern, bits<8> imm> : 2169 Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {} 2170 2171let Predicates = [PrefixInstrs, HasP10Vector] in { 2172 let AddedComplexity = 400 in { 2173 def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A, 2174 i32immNonAllOneNonZero:$A, 2175 i32immNonAllOneNonZero:$A, 2176 i32immNonAllOneNonZero:$A)), 2177 (v4i32 (XXSPLTIW imm:$A))>; 2178 def : Pat<(f32 nzFPImmAsi32:$A), 2179 (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)), 2180 VSFRC)>; 2181 def : Pat<(f64 nzFPImmAsi32:$A), 2182 (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)), 2183 VSFRC)>; 2184 2185 // To replace constant pool with XXSPLTI32DX for scalars. 2186 def : Pat<(f32 nzFPImmAsi64:$A), 2187 (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX(IMPLICIT_DEF), 0, 2188 (getFPAs64BitIntHi $A)), 2189 1, (getFPAs64BitIntLo $A)), 2190 VSSRC)>; 2191 2192 def : Pat<(f64 nzFPImmAsi64:$A), 2193 (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX (IMPLICIT_DEF), 0, 2194 (getFPAs64BitIntHi $A)), 2195 1, (getFPAs64BitIntLo $A)), 2196 VSFRC)>; 2197 2198 // Anonymous patterns for XXEVAL 2199 // AND 2200 // and(A, B, C) 2201 def : xxevalPattern<(and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>; 2202 // and(A, xor(B, C)) 2203 def : xxevalPattern<(and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>; 2204 // and(A, or(B, C)) 2205 def : xxevalPattern<(and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>; 2206 // and(A, nor(B, C)) 2207 def : xxevalPattern<(and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>; 2208 // and(A, eqv(B, C)) 2209 def : xxevalPattern<(and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>; 2210 // and(A, nand(B, C)) 2211 def : xxevalPattern<(and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>; 2212 2213 // NAND 2214 // nand(A, B, C) 2215 def : xxevalPattern<(vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 2216 !sub(255, 1)>; 2217 // nand(A, xor(B, C)) 2218 def : xxevalPattern<(vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 2219 !sub(255, 6)>; 2220 // nand(A, or(B, C)) 2221 def : xxevalPattern<(vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 2222 !sub(255, 7)>; 2223 // nand(A, nor(B, C)) 2224 def : xxevalPattern<(or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 2225 !sub(255, 8)>; 2226 // nand(A, eqv(B, C)) 2227 def : xxevalPattern<(or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 2228 !sub(255, 9)>; 2229 // nand(A, nand(B, C)) 2230 def : xxevalPattern<(or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 2231 !sub(255, 14)>; 2232 2233 // EQV 2234 // (eqv A, B, C) 2235 def : xxevalPattern<(or (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 2236 (vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)))), 2237 150>; 2238 // (eqv A, (and B, C)) 2239 def : xxevalPattern<(vnot (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 225>; 2240 // (eqv A, (or B, C)) 2241 def : xxevalPattern<(vnot (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 135>; 2242 2243 // NOR 2244 // (nor A, B, C) 2245 def : xxevalPattern<(vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 128>; 2246 // (nor A, (and B, C)) 2247 def : xxevalPattern<(vnot (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 224>; 2248 // (nor A, (eqv B, C)) 2249 def : xxevalPattern<(and (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 96>; 2250 // (nor A, (nand B, C)) 2251 def : xxevalPattern<(and (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 16>; 2252 // (nor A, (nor B, C)) 2253 def : xxevalPattern<(and (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 112>; 2254 // (nor A, (xor B, C)) 2255 def : xxevalPattern<(vnot (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 144>; 2256 2257 // OR 2258 // (or A, B, C) 2259 def : xxevalPattern<(or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 127>; 2260 // (or A, (and B, C)) 2261 def : xxevalPattern<(or v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 31>; 2262 // (or A, (eqv B, C)) 2263 def : xxevalPattern<(or v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 159>; 2264 // (or A, (nand B, C)) 2265 def : xxevalPattern<(or v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 239>; 2266 // (or A, (nor B, C)) 2267 def : xxevalPattern<(or v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 143>; 2268 // (or A, (xor B, C)) 2269 def : xxevalPattern<(or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 111>; 2270 2271 // XOR 2272 // (xor A, B, C) 2273 def : xxevalPattern<(xor v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 105>; 2274 // (xor A, (and B, C)) 2275 def : xxevalPattern<(xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 30>; 2276 // (xor A, (or B, C)) 2277 def : xxevalPattern<(xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 120>; 2278 2279 // Anonymous patterns to select prefixed VSX loads and stores. 2280 // Load / Store f128 2281 def : Pat<(f128 (load PDForm:$src)), 2282 (COPY_TO_REGCLASS (PLXV memri34:$src), VRRC)>; 2283 def : Pat<(store f128:$XS, PDForm:$dst), 2284 (PSTXV (COPY_TO_REGCLASS $XS, VSRC), memri34:$dst)>; 2285 2286 // Load / Store v4i32 2287 def : Pat<(v4i32 (load PDForm:$src)), (PLXV memri34:$src)>; 2288 def : Pat<(store v4i32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2289 2290 // Load / Store v2i64 2291 def : Pat<(v2i64 (load PDForm:$src)), (PLXV memri34:$src)>; 2292 def : Pat<(store v2i64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2293 2294 // Load / Store v4f32 2295 def : Pat<(v4f32 (load PDForm:$src)), (PLXV memri34:$src)>; 2296 def : Pat<(store v4f32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2297 2298 // Load / Store v2f64 2299 def : Pat<(v2f64 (load PDForm:$src)), (PLXV memri34:$src)>; 2300 def : Pat<(store v2f64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2301 2302 // Cases For PPCstore_scal_int_from_vsr 2303 def : Pat<(PPCstore_scal_int_from_vsr f64:$src, PDForm:$dst, 8), 2304 (PSTXSD $src, PDForm:$dst)>; 2305 def : Pat<(PPCstore_scal_int_from_vsr f128:$src, PDForm:$dst, 8), 2306 (PSTXSD (COPY_TO_REGCLASS $src, VFRC), PDForm:$dst)>; 2307 } 2308 2309 2310 def : Pat<(i32 imm34:$imm), (PLI (getImmAs64BitInt imm:$imm))>; 2311 def : Pat<(i64 imm34:$imm), (PLI8 (getImmAs64BitInt imm:$imm))>; 2312 def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)), 2313 (COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC), 2314 (COPY_TO_REGCLASS $B, VSRC), 2315 (COPY_TO_REGCLASS $C, VSRC), $D), VSRC)>; 2316 def : Pat<(v16i8 (int_ppc_vsx_xxblendvb v16i8:$A, v16i8:$B, v16i8:$C)), 2317 (COPY_TO_REGCLASS 2318 (XXBLENDVB (COPY_TO_REGCLASS $A, VSRC), 2319 (COPY_TO_REGCLASS $B, VSRC), 2320 (COPY_TO_REGCLASS $C, VSRC)), VSRC)>; 2321 def : Pat<(v8i16 (int_ppc_vsx_xxblendvh v8i16:$A, v8i16:$B, v8i16:$C)), 2322 (COPY_TO_REGCLASS 2323 (XXBLENDVH (COPY_TO_REGCLASS $A, VSRC), 2324 (COPY_TO_REGCLASS $B, VSRC), 2325 (COPY_TO_REGCLASS $C, VSRC)), VSRC)>; 2326 def : Pat<(int_ppc_vsx_xxblendvw v4i32:$A, v4i32:$B, v4i32:$C), 2327 (XXBLENDVW $A, $B, $C)>; 2328 def : Pat<(int_ppc_vsx_xxblendvd v2i64:$A, v2i64:$B, v2i64:$C), 2329 (XXBLENDVD $A, $B, $C)>; 2330} 2331 2332let Predicates = [PrefixInstrs] in { 2333 // Anonymous patterns to select prefixed loads and stores. 2334 // Load i32 2335 def : Pat<(i32 (extloadi1 PDForm:$src)), (PLBZ memri34:$src)>; 2336 def : Pat<(i32 (zextloadi1 PDForm:$src)), (PLBZ memri34:$src)>; 2337 def : Pat<(i32 (extloadi8 PDForm:$src)), (PLBZ memri34:$src)>; 2338 def : Pat<(i32 (zextloadi8 PDForm:$src)), (PLBZ memri34:$src)>; 2339 def : Pat<(i32 (extloadi16 PDForm:$src)), (PLHZ memri34:$src)>; 2340 def : Pat<(i32 (zextloadi16 PDForm:$src)), (PLHZ memri34:$src)>; 2341 def : Pat<(i32 (sextloadi16 PDForm:$src)), (PLHA memri34:$src)>; 2342 def : Pat<(i32 (load PDForm:$src)), (PLWZ memri34:$src)>; 2343 2344 // Store i32 2345 def : Pat<(truncstorei8 i32:$rS, PDForm:$dst), (PSTB gprc:$rS, memri34:$dst)>; 2346 def : Pat<(truncstorei16 i32:$rS, PDForm:$dst), (PSTH gprc:$rS, memri34:$dst)>; 2347 def : Pat<(store i32:$rS, PDForm:$dst), (PSTW gprc:$rS, memri34:$dst)>; 2348 2349 // Load i64 2350 def : Pat<(i64 (extloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>; 2351 def : Pat<(i64 (zextloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>; 2352 def : Pat<(i64 (extloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>; 2353 def : Pat<(i64 (zextloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>; 2354 def : Pat<(i64 (extloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>; 2355 def : Pat<(i64 (zextloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>; 2356 def : Pat<(i64 (sextloadi16 PDForm:$src)), (PLHA8 memri34:$src)>; 2357 def : Pat<(i64 (extloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>; 2358 def : Pat<(i64 (zextloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>; 2359 def : Pat<(i64 (sextloadi32 PDForm:$src)), (PLWA8 memri34:$src)>; 2360 def : Pat<(i64 (load PDForm:$src)), (PLD memri34:$src)>; 2361 2362 // Store i64 2363 def : Pat<(truncstorei8 i64:$rS, PDForm:$dst), (PSTB8 g8rc:$rS, memri34:$dst)>; 2364 def : Pat<(truncstorei16 i64:$rS, PDForm:$dst), (PSTH8 g8rc:$rS, memri34:$dst)>; 2365 def : Pat<(truncstorei32 i64:$rS, PDForm:$dst), (PSTW8 g8rc:$rS, memri34:$dst)>; 2366 def : Pat<(store i64:$rS, PDForm:$dst), (PSTD g8rc:$rS, memri34:$dst)>; 2367 2368 // Atomic Load 2369 def : Pat<(i32 (atomic_load_8 PDForm:$src)), (PLBZ memri34:$src)>; 2370 def : Pat<(i32 (atomic_load_16 PDForm:$src)), (PLHZ memri34:$src)>; 2371 def : Pat<(i32 (atomic_load_32 PDForm:$src)), (PLWZ memri34:$src)>; 2372 def : Pat<(i64 (atomic_load_64 PDForm:$src)), (PLD memri34:$src)>; 2373 2374 // Atomic Store 2375 def : Pat<(atomic_store_8 i32:$RS, PDForm:$dst), (PSTB $RS, memri34:$dst)>; 2376 def : Pat<(atomic_store_16 i32:$RS, PDForm:$dst), (PSTH $RS, memri34:$dst)>; 2377 def : Pat<(atomic_store_32 i32:$RS, PDForm:$dst), (PSTW $RS, memri34:$dst)>; 2378 def : Pat<(atomic_store_64 i64:$RS, PDForm:$dst), (PSTD $RS, memri34:$dst)>; 2379} 2380 2381let Predicates = [PrefixInstrs, HasFPU] in { 2382 // Load / Store f32 2383 def : Pat<(f32 (load PDForm:$src)), (PLFS memri34:$src)>; 2384 def : Pat<(store f32:$FRS, PDForm:$dst), (PSTFS $FRS, memri34:$dst)>; 2385 2386 // Load / Store f64 2387 def : Pat<(f64 (extloadf32 PDForm:$src)), 2388 (COPY_TO_REGCLASS (PLFS memri34:$src), VSFRC)>; 2389 def : Pat<(f64 (load PDForm:$src)), (PLFD memri34:$src)>; 2390 def : Pat<(store f64:$FRS, PDForm:$dst), (PSTFD $FRS, memri34:$dst)>; 2391 // Prefixed fpext to v2f64 2392 def : Pat<(v4f32 (PPCldvsxlh PDForm:$src)), 2393 (SUBREG_TO_REG (i64 1), (PLFD PDForm:$src), sub_64)>; 2394 2395} 2396 2397def InsertEltShift { 2398 dag Sub32 = (i32 (EXTRACT_SUBREG $rB, sub_32)); 2399 dag Sub32Left1 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 1, 0, 30); 2400 dag Sub32Left2 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 2, 0, 29); 2401 dag Left1 = (RLWINM $rB, 1, 0, 30); 2402 dag Left2 = (RLWINM $rB, 2, 0, 29); 2403 dag Left3 = (RLWINM8 $rB, 3, 0, 28); 2404} 2405 2406let Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in { 2407 // Indexed vector insert element 2408 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)), 2409 (VINSBRX $vDi, InsertEltShift.Sub32, $rA)>; 2410 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)), 2411 (VINSHRX $vDi, InsertEltShift.Sub32Left1, $rA)>; 2412 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)), 2413 (VINSWRX $vDi, InsertEltShift.Sub32Left2, $rA)>; 2414 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)), 2415 (VINSDRX $vDi, InsertEltShift.Left3, $rA)>; 2416 2417 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)), 2418 (VINSWVRX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>; 2419 2420 def : Pat<(v2f64 (insertelt v2f64:$vDi, f64:$A, i64:$rB)), 2421 (VINSDRX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>; 2422 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)), 2423 (VINSDRX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>; 2424 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)), 2425 (VINSDRX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>; 2426 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)), 2427 (VINSDRX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>; 2428 let AddedComplexity = 400 in { 2429 // Immediate vector insert element 2430 foreach Idx = [0, 1, 2, 3] in { 2431 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, Idx)), 2432 (VINSW $vDi, !mul(!sub(3, Idx), 4), $rA)>; 2433 } 2434 foreach i = [0, 1] in 2435 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, (i64 i))), 2436 (VINSD $vDi, !mul(!sub(1, i), 8), $rA)>; 2437 } 2438} 2439 2440let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC32] in { 2441 // Indexed vector insert element 2442 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i32:$rB)), 2443 (VINSBLX $vDi, $rB, $rA)>; 2444 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i32:$rB)), 2445 (VINSHLX $vDi, InsertEltShift.Left1, $rA)>; 2446 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i32:$rB)), 2447 (VINSWLX $vDi, InsertEltShift.Left2, $rA)>; 2448 2449 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i32:$rB)), 2450 (VINSWVLX $vDi, InsertEltShift.Left2, (XSCVDPSPN $rA))>; 2451} 2452 2453let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC64] in { 2454 // Indexed vector insert element 2455 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)), 2456 (VINSBLX $vDi, InsertEltShift.Sub32, $rA)>; 2457 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)), 2458 (VINSHLX $vDi, InsertEltShift.Sub32Left1, $rA)>; 2459 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)), 2460 (VINSWLX $vDi, InsertEltShift.Sub32Left2, $rA)>; 2461 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)), 2462 (VINSDLX $vDi, InsertEltShift.Left3, $rA)>; 2463 2464 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)), 2465 (VINSWVLX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>; 2466 2467 def : Pat<(v2f64 (insertelt v2f64:$vDi, f64:$A, i64:$rB)), 2468 (VINSDLX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>; 2469 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)), 2470 (VINSDLX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>; 2471 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)), 2472 (VINSDLX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>; 2473 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)), 2474 (VINSDLX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>; 2475} 2476 2477let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX, IsBigEndian] in { 2478 // Immediate vector insert element 2479 foreach Ty = [i32, i64] in { 2480 foreach Idx = [0, 1, 2, 3] in { 2481 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, (Ty Idx))), 2482 (VINSW $vDi, !mul(Idx, 4), $rA)>; 2483 } 2484 } 2485 2486 foreach Idx = [0, 1] in 2487 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, Idx)), 2488 (VINSD $vDi, !mul(Idx, 8), $rA)>; 2489} 2490 2491 2492//===----------------------------------------------------------------------===// 2493// PowerPC ISA 3.1 Extended Mnemonics. 2494// 2495 2496let Predicates = [IsISA3_1] in { 2497 def : InstAlias<"wait", (WAITP10 0, 0)>; 2498 def : InstAlias<"wait 0", (WAITP10 0, 0), 0>; 2499 def : InstAlias<"wait 1", (WAITP10 1, 0), 0>; 2500 def : InstAlias<"waitrsv", (WAITP10 1, 0)>; 2501 def : InstAlias<"pause_short", (WAITP10 2, 0), 0>; 2502 2503 def : InstAlias<"sync", (SYNCP10 0, 0)>; 2504 def : InstAlias<"hwsync", (SYNCP10 0, 0), 0>; 2505 def : InstAlias<"wsync", (SYNCP10 1, 0), 0>; 2506 def : InstAlias<"ptesync", (SYNCP10 2, 0)>; 2507 def : InstAlias<"phwsync", (SYNCP10 4, 0)>; 2508 def : InstAlias<"plwsync", (SYNCP10 5, 0)>; 2509 def : InstAlias<"sync $L", (SYNCP10 u3imm:$L, 0)>; 2510 def : InstAlias<"stncisync", (SYNCP10 1, 1)>; 2511 def : InstAlias<"stcisync", (SYNCP10 0, 2)>; 2512 def : InstAlias<"stsync", (SYNCP10 0, 3)>; 2513 2514 def : InstAlias<"paddi $RT, $RA, $SI", (PADDI8 g8rc:$RT, g8rc_nox0:$RA, s34imm:$SI)>; 2515} 2516 2517let Predicates = [IsISA3_1, PrefixInstrs], isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in { 2518 let Interpretation64Bit = 1 in { 2519 def PLA8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT), 2520 (ins g8rc_nox0:$RA, s34imm:$SI), 2521 "pla $RT, ${SI} ${RA}", IIC_IntSimple, []>, MemriOp; 2522 def PLA8pc : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT), 2523 (ins s34imm_pcrel:$SI), 2524 "pla $RT, $SI", IIC_IntSimple, []>, isPCRel; 2525 } 2526 2527 def PSUBI : PPCAsmPseudo<"psubi $RT, $RA, $SI", 2528 (ins g8rc:$RT, g8rc_nox0:$RA, s34imm:$SI)>; 2529 2530 def PLA : MLS_DForm_SI34_RT5<14, (outs gprc:$RT), 2531 (ins gprc_nor0:$RA, s34imm:$SI), 2532 "pla $RT, ${SI} ${RA}", IIC_IntSimple, []>, MemriOp; 2533 def PLApc : MLS_DForm_SI34_RT5<14, (outs gprc:$RT), 2534 (ins s34imm_pcrel:$SI), 2535 "pla $RT, $SI", IIC_IntSimple, []>, isPCRel; 2536} 2537