1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the subset of the 32-bit PowerPC instruction set, as used 10// by the PowerPC instruction selector. 11// 12//===----------------------------------------------------------------------===// 13 14include "PPCInstrFormats.td" 15 16//===----------------------------------------------------------------------===// 17// PowerPC specific type constraints. 18// 19def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 20 SDTCisVT<0, f64>, SDTCisPtrTy<1> 21]>; 22def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 23 SDTCisVT<0, f64>, SDTCisPtrTy<1> 24]>; 25def SDT_PPCLxsizx : SDTypeProfile<1, 2, [ 26 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 27]>; 28def SDT_PPCstxsix : SDTypeProfile<0, 3, [ 29 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 30]>; 31def SDT_PPCcv_fp_to_int : SDTypeProfile<1, 1, [ 32 SDTCisFP<0>, SDTCisFP<1> 33 ]>; 34def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [ 35 SDTCisFP<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 36]>; 37def SDT_PPCVexts : SDTypeProfile<1, 2, [ 38 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2> 39]>; 40 41def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 42 SDTCisVT<1, i32> ]>; 43def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 44 SDTCisVT<1, i32> ]>; 45def SDT_PPCvperm : SDTypeProfile<1, 3, [ 46 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 47]>; 48 49def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>, 50 SDTCisVec<1>, SDTCisInt<2> 51]>; 52 53def SDT_PPCSpToDp : SDTypeProfile<1, 1, [ SDTCisVT<0, v2f64>, 54 SDTCisInt<1> 55]>; 56 57def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>, 58 SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3> 59]>; 60 61def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>, 62 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 63]>; 64 65def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>, 66 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 67]>; 68 69def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 70 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 71]>; 72 73def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 74 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 75]>; 76 77def SDT_PPCFtsqrt : SDTypeProfile<1, 1, [ 78 SDTCisVT<0, i32>]>; 79 80def SDT_PPClbrx : SDTypeProfile<1, 2, [ 81 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 82]>; 83def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 84 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 85]>; 86def SDT_StoreCond : SDTypeProfile<0, 3, [ 87 SDTCisPtrTy<0>, SDTCisInt<1>, SDTCisPtrTy<2> 88]>; 89 90def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 91 SDTCisPtrTy<0>, SDTCisVT<1, i32> 92]>; 93 94def tocentry32 : Operand<iPTR> { 95 let MIOperandInfo = (ops i32imm:$imm); 96} 97 98def SDT_PPCqvfperm : SDTypeProfile<1, 3, [ 99 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3> 100]>; 101def SDT_PPCqvgpci : SDTypeProfile<1, 1, [ 102 SDTCisVec<0>, SDTCisInt<1> 103]>; 104def SDT_PPCqvaligni : SDTypeProfile<1, 3, [ 105 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> 106]>; 107def SDT_PPCqvesplati : SDTypeProfile<1, 2, [ 108 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 109]>; 110 111def SDT_PPCqbflt : SDTypeProfile<1, 1, [ 112 SDTCisVec<0>, SDTCisVec<1> 113]>; 114 115def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [ 116 SDTCisVec<0>, SDTCisPtrTy<1> 117]>; 118 119def SDT_PPCextswsli : SDTypeProfile<1, 2, [ // extswsli 120 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2> 121]>; 122 123def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [ 124 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 125]>; 126 127//===----------------------------------------------------------------------===// 128// PowerPC specific DAG Nodes. 129// 130 131def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 132def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 133def PPCfsqrt : SDNode<"PPCISD::FSQRT", SDTFPUnaryOp, []>; 134def PPCftsqrt : SDNode<"PPCISD::FTSQRT", SDT_PPCFtsqrt,[]>; 135 136def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 137def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 138def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 139def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 140def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 141def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 142def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 143def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 144 145def PPCstrict_fcfid : SDNode<"PPCISD::STRICT_FCFID", 146 SDTFPUnaryOp, [SDNPHasChain]>; 147def PPCstrict_fcfidu : SDNode<"PPCISD::STRICT_FCFIDU", 148 SDTFPUnaryOp, [SDNPHasChain]>; 149def PPCstrict_fcfids : SDNode<"PPCISD::STRICT_FCFIDS", 150 SDTFPRoundOp, [SDNPHasChain]>; 151def PPCstrict_fcfidus : SDNode<"PPCISD::STRICT_FCFIDUS", 152 SDTFPRoundOp, [SDNPHasChain]>; 153 154def PPCany_fcfid : PatFrags<(ops node:$op), 155 [(PPCfcfid node:$op), 156 (PPCstrict_fcfid node:$op)]>; 157def PPCany_fcfidu : PatFrags<(ops node:$op), 158 [(PPCfcfidu node:$op), 159 (PPCstrict_fcfidu node:$op)]>; 160def PPCany_fcfids : PatFrags<(ops node:$op), 161 [(PPCfcfids node:$op), 162 (PPCstrict_fcfids node:$op)]>; 163def PPCany_fcfidus : PatFrags<(ops node:$op), 164 [(PPCfcfidus node:$op), 165 (PPCstrict_fcfidus node:$op)]>; 166 167def PPCstore_scal_int_from_vsr: 168 SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr, 169 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 170def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 171 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 172def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 173 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 174def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 175 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 176def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx, 177 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 178def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix, 179 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 180def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>; 181 182// Extract FPSCR (not modeled at the DAG level). 183def PPCmffs : SDNode<"PPCISD::MFFS", 184 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 185 [SDNPHasChain]>; 186 187// Perform FADD in round-to-zero mode. 188def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 189def PPCstrict_faddrtz: SDNode<"PPCISD::STRICT_FADDRTZ", SDTFPBinOp, 190 [SDNPHasChain]>; 191 192def PPCany_faddrtz: PatFrags<(ops node:$lhs, node:$rhs), 193 [(PPCfaddrtz node:$lhs, node:$rhs), 194 (PPCstrict_faddrtz node:$lhs, node:$rhs)]>; 195 196def PPCfsel : SDNode<"PPCISD::FSEL", 197 // Type constraint for fsel. 198 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 199 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 200def PPCxsmaxc : SDNode<"PPCISD::XSMAXC", SDT_PPCFPMinMax, []>; 201def PPCxsminc : SDNode<"PPCISD::XSMINC", SDT_PPCFPMinMax, []>; 202def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 203def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 204def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, 205 [SDNPMayLoad, SDNPMemOperand]>; 206 207def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 208 209def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 210def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 211 [SDNPMayLoad]>; 212def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 213def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 214def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 215def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 216def PPCgetTlsMod : SDNode<"PPCISD::GET_TLS_MOD_AIX", SDTIntUnaryOp>; 217def PPCgetTpointer : SDNode<"PPCISD::GET_TPOINTER", SDTIntLeaf, []>; 218def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", 219 SDTypeProfile<1, 3, [ 220 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 221 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 222def PPCTlsgdAIX : SDNode<"PPCISD::TLSGD_AIX", SDTIntBinOp>; 223def PPCTlsldAIX : SDNode<"PPCISD::TLSLD_AIX", SDTIntUnaryOp>; 224def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 225def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 226def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 227def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR", 228 SDTypeProfile<1, 3, [ 229 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 230 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 231def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>; 232def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 233def PPCpaddiDtprel : SDNode<"PPCISD::PADDI_DTPREL", SDTIntBinOp>; 234 235def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 236def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>; 237def PPCxxspltidp : SDNode<"PPCISD::XXSPLTI_SP_TO_DP", SDT_PPCSpToDp, []>; 238def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>; 239def PPCxxpermdi : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>; 240def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>; 241 242def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>; 243 244// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 245// amounts. These nodes are generated by the multi-precision shift code. 246def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 247def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 248def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 249 250def PPCfnmsub : SDNode<"PPCISD::FNMSUB" , SDTFPTernaryOp>; 251 252def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>; 253 254def PPCstrict_fctidz : SDNode<"PPCISD::STRICT_FCTIDZ", 255 SDTFPUnaryOp, [SDNPHasChain]>; 256def PPCstrict_fctiwz : SDNode<"PPCISD::STRICT_FCTIWZ", 257 SDTFPUnaryOp, [SDNPHasChain]>; 258def PPCstrict_fctiduz : SDNode<"PPCISD::STRICT_FCTIDUZ", 259 SDTFPUnaryOp, [SDNPHasChain]>; 260def PPCstrict_fctiwuz : SDNode<"PPCISD::STRICT_FCTIWUZ", 261 SDTFPUnaryOp, [SDNPHasChain]>; 262 263def PPCany_fctidz : PatFrags<(ops node:$op), 264 [(PPCstrict_fctidz node:$op), 265 (PPCfctidz node:$op)]>; 266def PPCany_fctiwz : PatFrags<(ops node:$op), 267 [(PPCstrict_fctiwz node:$op), 268 (PPCfctiwz node:$op)]>; 269def PPCany_fctiduz : PatFrags<(ops node:$op), 270 [(PPCstrict_fctiduz node:$op), 271 (PPCfctiduz node:$op)]>; 272def PPCany_fctiwuz : PatFrags<(ops node:$op), 273 [(PPCstrict_fctiwuz node:$op), 274 (PPCfctiwuz node:$op)]>; 275 276// Move 2 i64 values into a VSX register 277def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128", 278 SDTypeProfile<1, 2, 279 [SDTCisFP<0>, SDTCisSameSizeAs<1,2>, 280 SDTCisSameAs<1,2>]>, 281 []>; 282 283def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64", 284 SDTypeProfile<1, 2, 285 [SDTCisVT<0, f64>, SDTCisVT<1,i32>, 286 SDTCisVT<1,i32>]>, 287 []>; 288 289def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE", 290 SDTypeProfile<1, 2, 291 [SDTCisVT<0, i32>, SDTCisVT<1, f64>, 292 SDTCisPtrTy<2>]>, 293 []>; 294 295// These are target-independent nodes, but have target-specific formats. 296def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 297 [SDNPHasChain, SDNPOutGlue]>; 298def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 299 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 300 301def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 302def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 303 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 304 SDNPVariadic]>; 305def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 306 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 307 SDNPVariadic]>; 308def PPCcall_notoc : SDNode<"PPCISD::CALL_NOTOC", SDT_PPCCall, 309 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 310 SDNPVariadic]>; 311def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 312 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 313def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 314 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 315 SDNPVariadic]>; 316def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC", 317 SDTypeProfile<0, 1, []>, 318 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 319 SDNPVariadic]>; 320 321// Call nodes for strictfp calls (that define RM). 322def PPCcall_rm : SDNode<"PPCISD::CALL_RM", SDT_PPCCall, 323 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 324 SDNPVariadic]>; 325def PPCcall_nop_rm : SDNode<"PPCISD::CALL_NOP_RM", SDT_PPCCall, 326 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 327 SDNPVariadic]>; 328def PPCcall_notoc_rm : SDNode<"PPCISD::CALL_NOTOC_RM", SDT_PPCCall, 329 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 330 SDNPVariadic]>; 331def PPCbctrl_rm : SDNode<"PPCISD::BCTRL_RM", SDTNone, 332 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 333 SDNPVariadic]>; 334def PPCbctrl_load_toc_rm : SDNode<"PPCISD::BCTRL_LOAD_TOC_RM", 335 SDTypeProfile<0, 1, []>, 336 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 337 SDNPVariadic]>; 338 339def PPCretglue : SDNode<"PPCISD::RET_GLUE", SDTNone, 340 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 341 342def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 343 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 344 345def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 346 SDTypeProfile<1, 1, [SDTCisInt<0>, 347 SDTCisPtrTy<1>]>, 348 [SDNPHasChain, SDNPSideEffect]>; 349def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 350 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 351 [SDNPHasChain, SDNPSideEffect]>; 352 353def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 354def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 355 [SDNPHasChain, SDNPSideEffect]>; 356 357def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone, 358 [SDNPHasChain, SDNPSideEffect]>; 359def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>; 360def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc, 361 [SDNPHasChain, SDNPSideEffect]>; 362 363def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 364def PPCvcmp_rec : SDNode<"PPCISD::VCMP_rec", SDT_PPCvcmp, [SDNPOutGlue]>; 365 366def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 367 [SDNPHasChain, SDNPOptInGlue]>; 368 369// PPC-specific atomic operations. 370def PPCatomicCmpSwap_8 : 371 SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3, 372 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 373def PPCatomicCmpSwap_16 : 374 SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3, 375 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 376def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 377 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 378def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 379 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 380def PPCStoreCond : SDNode<"PPCISD::STORE_COND", SDT_StoreCond, 381 [SDNPHasChain, SDNPMayStore, 382 SDNPMemOperand, SDNPOutGlue]>; 383 384// Instructions to set/unset CR bit 6 for SVR4 vararg calls 385def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 386 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 387def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 388 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 389 390// Instructions to support dynamic alloca. 391def SDTDynOp : SDTypeProfile<1, 2, []>; 392def SDTDynAreaOp : SDTypeProfile<1, 1, []>; 393def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 394def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>; 395def PPCprobedalloca : SDNode<"PPCISD::PROBED_ALLOCA", SDTDynOp, [SDNPHasChain]>; 396 397// PC Relative Specific Nodes 398def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>; 399def PPCtlsdynamatpcreladdr : SDNode<"PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR", 400 SDTIntUnaryOp, []>; 401def PPCtlslocalexecmataddr : SDNode<"PPCISD::TLS_LOCAL_EXEC_MAT_ADDR", 402 SDTIntUnaryOp, []>; 403 404//===----------------------------------------------------------------------===// 405// PowerPC specific transformation functions and pattern fragments. 406// 407 408// A floating point immediate that is not a positive zero and can be converted 409// to a single precision floating point non-denormal immediate without loss of 410// information. 411def nzFPImmAsi32 : PatLeaf<(fpimm), [{ 412 APFloat APFloatOfN = N->getValueAPF(); 413 return convertToNonDenormSingle(APFloatOfN) && !N->isExactlyValue(+0.0); 414}]>; 415 416// A floating point immediate that is exactly an integer (for example 3.0, -5.0) 417// and can be represented in 5 bits (range of [-16, 15]). 418def nzFPImmExactInti5 : PatLeaf<(fpimm), [{ 419 APFloat FloatValue = N->getValueAPF(); 420 bool IsExact; 421 APSInt IntResult(16, false); 422 FloatValue.convertToInteger(IntResult, APFloat::rmTowardZero, &IsExact); 423 return IsExact && IntResult <= 15 && IntResult >= -16 && !FloatValue.isZero(); 424}]>; 425 426def getFPAs5BitExactInt : SDNodeXForm<fpimm, [{ 427 APFloat FloatValue = N->getValueAPF(); 428 bool IsExact; 429 APSInt IntResult(32, false); 430 FloatValue.convertToInteger(IntResult, APFloat::rmTowardZero, &IsExact); 431 return CurDAG->getTargetConstant(IntResult, SDLoc(N), MVT::i32); 432}]>; 433 434// Convert the floating point immediate into a 32 bit floating point immediate 435// and get a i32 with the resulting bits. 436def getFPAs32BitInt : SDNodeXForm<fpimm, [{ 437 APFloat APFloatOfN = N->getValueAPF(); 438 convertToNonDenormSingle(APFloatOfN); 439 return CurDAG->getTargetConstant(APFloatOfN.bitcastToAPInt().getZExtValue(), 440 SDLoc(N), MVT::i32); 441}]>; 442 443// Check if the value can be converted to be single precision immediate, which 444// can be exploited by XXSPLTIDP. Ensure that it cannot be converted to single 445// precision before exploiting with XXSPLTI32DX. 446def nzFPImmAsi64 : PatLeaf<(fpimm), [{ 447 APFloat APFloatOfN = N->getValueAPF(); 448 return !N->isExactlyValue(+0.0) && !checkConvertToNonDenormSingle(APFloatOfN); 449}]>; 450 451// Get the Hi bits of a 64 bit immediate. 452def getFPAs64BitIntHi : SDNodeXForm<fpimm, [{ 453 APFloat APFloatOfN = N->getValueAPF(); 454 bool Unused; 455 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 456 &Unused); 457 uint32_t Hi = (uint32_t)((APFloatOfN.bitcastToAPInt().getZExtValue() & 458 0xFFFFFFFF00000000LL) >> 32); 459 return CurDAG->getTargetConstant(Hi, SDLoc(N), MVT::i32); 460}]>; 461 462// Get the Lo bits of a 64 bit immediate. 463def getFPAs64BitIntLo : SDNodeXForm<fpimm, [{ 464 APFloat APFloatOfN = N->getValueAPF(); 465 bool Unused; 466 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 467 &Unused); 468 uint32_t Lo = (uint32_t)(APFloatOfN.bitcastToAPInt().getZExtValue() & 469 0xFFFFFFFF); 470 return CurDAG->getTargetConstant(Lo, SDLoc(N), MVT::i32); 471}]>; 472 473def imm34 : PatLeaf<(imm), [{ 474 return isInt<34>(N->getSExtValue()); 475}]>; 476 477def getImmAs64BitInt : SDNodeXForm<imm, [{ 478 return getI64Imm(N->getSExtValue(), SDLoc(N)); 479}]>; 480 481def SHL32 : SDNodeXForm<imm, [{ 482 // Transformation function: 31 - imm 483 return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); 484}]>; 485 486def SRL32 : SDNodeXForm<imm, [{ 487 // Transformation function: 32 - imm 488 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) 489 : getI32Imm(0, SDLoc(N)); 490}]>; 491 492def LO16 : SDNodeXForm<imm, [{ 493 // Transformation function: get the low 16 bits. 494 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); 495}]>; 496 497def HI16 : SDNodeXForm<imm, [{ 498 // Transformation function: shift the immediate value down into the low bits. 499 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); 500}]>; 501 502def HA16 : SDNodeXForm<imm, [{ 503 // Transformation function: shift the immediate value down into the low bits. 504 int64_t Val = N->getZExtValue(); 505 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); 506}]>; 507def MB : SDNodeXForm<imm, [{ 508 // Transformation function: get the start bit of a mask 509 unsigned mb = 0, me; 510 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 511 return getI32Imm(mb, SDLoc(N)); 512}]>; 513 514def ME : SDNodeXForm<imm, [{ 515 // Transformation function: get the end bit of a mask 516 unsigned mb, me = 0; 517 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 518 return getI32Imm(me, SDLoc(N)); 519}]>; 520def maskimm32 : PatLeaf<(imm), [{ 521 // maskImm predicate - True if immediate is a run of ones. 522 unsigned mb, me; 523 if (N->getValueType(0) == MVT::i32) 524 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 525 else 526 return false; 527}]>; 528 529def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 530 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 531 // sign extended field. Used by instructions like 'addi'. 532 return (int32_t)Imm == (short)Imm; 533}]>; 534def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 535 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 536 // sign extended field. Used by instructions like 'addi'. 537 return (int64_t)Imm == (short)Imm; 538}]>; 539def immZExt16 : PatLeaf<(imm), [{ 540 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 541 // field. Used by instructions like 'ori'. 542 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 543}], LO16>; 544def immNonAllOneAnyExt8 : ImmLeaf<i32, [{ 545 return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); 546}]>; 547def i32immNonAllOneNonZero : ImmLeaf<i32, [{ return Imm && (Imm != -1); }]>; 548def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>; 549 550// imm16Shifted* - These match immediates where the low 16-bits are zero. There 551// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 552// identical in 32-bit mode, but in 64-bit mode, they return true if the 553// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 554// clear). 555def imm16ShiftedZExt : PatLeaf<(imm), [{ 556 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 557 // immediate are set. Used by instructions like 'xoris'. 558 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 559}], HI16>; 560 561def imm16ShiftedSExt : PatLeaf<(imm), [{ 562 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 563 // immediate are set. Used by instructions like 'addis'. Identical to 564 // imm16ShiftedZExt in 32-bit mode. 565 if (N->getZExtValue() & 0xFFFF) return false; 566 if (N->getValueType(0) == MVT::i32) 567 return true; 568 // For 64-bit, make sure it is sext right. 569 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 570}], HI16>; 571 572def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 573 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 574 // zero extended field. 575 return isUInt<32>(Imm); 576}]>; 577 578// This is a somewhat weaker condition than actually checking for 4-byte 579// alignment. It is simply checking that the displacement can be represented 580// as an immediate that is a multiple of 4 (i.e. the requirements for DS-Form 581// instructions). 582// But some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 583// restricted memrix (4-aligned) constants are alignment sensitive. If these 584// offsets are hidden behind TOC entries than the values of the lower-order 585// bits cannot be checked directly. As a result, we need to also incorporate 586// an alignment check into the relevant patterns. 587 588def DSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 589 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlign() >= 4; 590}]>; 591def DSFormStore : PatFrag<(ops node:$val, node:$ptr), 592 (store node:$val, node:$ptr), [{ 593 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlign() >= 4; 594}]>; 595def DSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 596 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlign() >= 4; 597}]>; 598def DSFormPreStore : PatFrag< 599 (ops node:$val, node:$base, node:$offset), 600 (pre_store node:$val, node:$base, node:$offset), [{ 601 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlign() >= 4; 602}]>; 603 604def NonDSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 605 return cast<LoadSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4); 606}]>; 607def NonDSFormStore : PatFrag<(ops node:$val, node:$ptr), 608 (store node:$val, node:$ptr), [{ 609 return cast<StoreSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4); 610}]>; 611def NonDSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 612 return cast<LoadSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4); 613}]>; 614 615// This is a somewhat weaker condition than actually checking for 16-byte 616// alignment. It is simply checking that the displacement can be represented 617// as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form 618// instructions). 619def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 620 return isOffsetMultipleOf(N, 16); 621}]>; 622def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 623 (store node:$val, node:$ptr), [{ 624 return isOffsetMultipleOf(N, 16); 625}]>; 626def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 627 return !isOffsetMultipleOf(N, 16); 628}]>; 629def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 630 (store node:$val, node:$ptr), [{ 631 return !isOffsetMultipleOf(N, 16); 632}]>; 633 634// PatFrag for binary operation whose operands are both non-constant 635class BinOpWithoutSImm16Operand<SDNode opcode> : 636 PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{ 637 int16_t Imm; 638 return !isIntS16Immediate(N->getOperand(0), Imm) 639 && !isIntS16Immediate(N->getOperand(1), Imm); 640}]>; 641 642def add_without_simm16 : BinOpWithoutSImm16Operand<add>; 643def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>; 644 645//===----------------------------------------------------------------------===// 646// PowerPC Flag Definitions. 647 648class isPPC64 { bit PPC64 = 1; } 649class isRecordForm { bit RC = 1; } 650 651class RegConstraint<string C> { 652 string Constraints = C; 653} 654class NoEncode<string E> { 655 string DisableEncoding = E; 656} 657 658 659// Define PowerPC specific addressing mode. 660 661// d-form 662def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; // "stb" 663// ds-form 664def iaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 665// dq-form 666def iaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrImmX16", [], []>; // "stxv" 667// 8LS:d-form 668def iaddrX34 : ComplexPattern<iPTR, 2, "SelectAddrImmX34", [], []>; // "pstxvp" 669 670// Below forms are all x-form addressing mode, use three different ones so we 671// can make a accurate check for x-form instructions in ISEL. 672// x-form addressing mode whose associated displacement form is D. 673def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; // "stbx" 674// x-form addressing mode whose associated displacement form is DS. 675def xaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrIdxX4", [], []>; // "stdx" 676// x-form addressing mode whose associated displacement form is DQ. 677def xaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrIdxX16", [], []>; // "stxvx" 678 679def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 680 681// The address in a single register. This is used with the SjLj 682// pseudo-instructions. 683def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 684 685/// This is just the offset part of iaddr, used for preinc. 686def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 687 688// Load and Store Instruction Selection addressing modes. 689let WantsParent = true in { 690 def DForm : ComplexPattern<iPTR, 2, "SelectDForm">; 691 def DSForm : ComplexPattern<iPTR, 2, "SelectDSForm">; 692 def DQForm : ComplexPattern<iPTR, 2, "SelectDQForm">; 693 def XForm : ComplexPattern<iPTR, 2, "SelectXForm">; 694 def ForceXForm : ComplexPattern<iPTR, 2, "SelectForceXForm">; 695 def PCRelForm : ComplexPattern<iPTR, 2, "SelectPCRelForm">; 696 def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm">; 697} 698 699//===----------------------------------------------------------------------===// 700// PowerPC Instruction Predicate Definitions. 701def In32BitMode : Predicate<"!Subtarget->isPPC64()">; 702def In64BitMode : Predicate<"Subtarget->isPPC64()">; 703def IsBookE : Predicate<"Subtarget->isBookE()">; 704def IsNotBookE : Predicate<"!Subtarget->isBookE()">; 705def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">; 706def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">; 707def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">; 708def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">; 709def IsE500 : Predicate<"Subtarget->isE500()">; 710def HasSPE : Predicate<"Subtarget->hasSPE()">; 711def HasICBT : Predicate<"Subtarget->hasICBT()">; 712def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">; 713def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">; 714def NoNaNsFPMath 715 : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 716def NaNsFPMath 717 : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 718def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; 719def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; 720def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">; 721def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">; 722def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; 723def HasFPU : Predicate<"Subtarget->hasFPU()">; 724def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; 725def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">; 726 727// AIX assembler may not be modern enough to support some extended mne. 728def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">, 729 AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>; 730def IsAIX : Predicate<"Subtarget->isAIXABI()">; 731def NotAIX : Predicate<"!Subtarget->isAIXABI()">; 732def IsISAFuture : Predicate<"Subtarget->isISAFuture()">; 733def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">; 734 735//===----------------------------------------------------------------------===// 736// PowerPC Multiclass Definitions. 737multiclass XForm_base_r3xo_r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 738 string asmbase, string asmstr, list<dag> pattern> { 739 let BaseName = asmbase in { 740 def NAME : XForm_base_r3xo<opcode, xo, OOL, IOL, 741 !strconcat(asmbase, !strconcat(" ", asmstr)), 742 NoItinerary, pattern>, RecFormRel; 743 let Defs = [CR1] in 744 def _rec : XForm_base_r3xo<opcode, xo, OOL, IOL, 745 !strconcat(asmbase, !strconcat(". ", asmstr)), 746 NoItinerary, []>, isRecordForm, RecFormRel; 747 } 748} 749 750multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 751 string asmbase, string asmstr, InstrItinClass itin, 752 list<dag> pattern> { 753 let BaseName = asmbase in { 754 def NAME : XForm_6<opcode, xo, OOL, IOL, 755 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 756 pattern>, RecFormRel; 757 let Defs = [CR0] in 758 def _rec : XForm_6<opcode, xo, OOL, IOL, 759 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 760 []>, isRecordForm, RecFormRel; 761 } 762} 763 764multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 765 string asmbase, string asmstr, InstrItinClass itin, 766 list<dag> pattern> { 767 let BaseName = asmbase in { 768 let Defs = [CARRY] in 769 def NAME : XForm_6<opcode, xo, OOL, IOL, 770 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 771 pattern>, RecFormRel; 772 let Defs = [CARRY, CR0] in 773 def _rec : XForm_6<opcode, xo, OOL, IOL, 774 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 775 []>, isRecordForm, RecFormRel; 776 } 777} 778 779multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 780 string asmbase, string asmstr, InstrItinClass itin, 781 list<dag> pattern> { 782 let BaseName = asmbase in { 783 let Defs = [CARRY] in 784 def NAME : XForm_10<opcode, xo, OOL, IOL, 785 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 786 pattern>, RecFormRel; 787 let Defs = [CARRY, CR0] in 788 def _rec : XForm_10<opcode, xo, OOL, IOL, 789 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 790 []>, isRecordForm, RecFormRel; 791 } 792} 793 794multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 795 string asmbase, string asmstr, InstrItinClass itin, 796 list<dag> pattern> { 797 let BaseName = asmbase in { 798 def NAME : XForm_11<opcode, xo, OOL, IOL, 799 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 800 pattern>, RecFormRel; 801 let Defs = [CR0] in 802 def _rec : XForm_11<opcode, xo, OOL, IOL, 803 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 804 []>, isRecordForm, RecFormRel; 805 } 806} 807 808multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 809 string asmbase, string asmstr, InstrItinClass itin, 810 list<dag> pattern> { 811 let BaseName = asmbase in { 812 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 813 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 814 pattern>, RecFormRel; 815 let Defs = [CR0] in 816 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 817 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 818 []>, isRecordForm, RecFormRel; 819 } 820} 821 822// Multiclass for instructions which have a record overflow form as well 823// as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.) 824multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 825 string asmbase, string asmstr, InstrItinClass itin, 826 list<dag> pattern> { 827 let BaseName = asmbase in { 828 def NAME : XOForm_1<opcode, xo, 0, OOL, IOL, 829 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 830 pattern>, RecFormRel; 831 let Defs = [CR0] in 832 def _rec : XOForm_1<opcode, xo, 0, OOL, IOL, 833 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 834 []>, isRecordForm, RecFormRel; 835 } 836 let BaseName = !strconcat(asmbase, "O") in { 837 let Defs = [XER] in 838 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 839 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 840 []>, RecFormRel; 841 let Defs = [XER, CR0] in 842 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 843 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 844 []>, isRecordForm, RecFormRel; 845 } 846} 847 848// Multiclass for instructions for which the non record form is not cracked 849// and the record form is cracked (i.e. divw, mullw, etc.) 850multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 851 string asmbase, string asmstr, InstrItinClass itin, 852 list<dag> pattern> { 853 let BaseName = asmbase in { 854 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 855 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 856 pattern>, RecFormRel; 857 let Defs = [CR0] in 858 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 859 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 860 []>, isRecordForm, RecFormRel, PPC970_DGroup_First, 861 PPC970_DGroup_Cracked; 862 } 863 let BaseName = !strconcat(asmbase, "O") in { 864 let Defs = [XER] in 865 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 866 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 867 []>, RecFormRel; 868 let Defs = [XER, CR0] in 869 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 870 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 871 []>, isRecordForm, RecFormRel; 872 } 873} 874 875multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 876 string asmbase, string asmstr, InstrItinClass itin, 877 list<dag> pattern> { 878 let BaseName = asmbase in { 879 let Defs = [CARRY] in 880 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 881 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 882 pattern>, RecFormRel; 883 let Defs = [CARRY, CR0] in 884 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 885 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 886 []>, isRecordForm, RecFormRel; 887 } 888 let BaseName = !strconcat(asmbase, "O") in { 889 let Defs = [CARRY, XER] in 890 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 891 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 892 []>, RecFormRel; 893 let Defs = [CARRY, XER, CR0] in 894 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 895 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 896 []>, isRecordForm, RecFormRel; 897 } 898} 899 900multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 901 string asmbase, string asmstr, InstrItinClass itin, 902 list<dag> pattern> { 903 let BaseName = asmbase in { 904 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 905 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 906 pattern>, RecFormRel; 907 let Defs = [CR0] in 908 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 909 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 910 []>, isRecordForm, RecFormRel; 911 } 912 let BaseName = !strconcat(asmbase, "O") in { 913 let Defs = [XER] in 914 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 915 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 916 []>, RecFormRel; 917 let Defs = [XER, CR0] in 918 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 919 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 920 []>, isRecordForm, RecFormRel; 921 } 922} 923 924multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 925 string asmbase, string asmstr, InstrItinClass itin, 926 list<dag> pattern> { 927 let BaseName = asmbase in { 928 let Defs = [CARRY] in 929 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 930 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 931 pattern>, RecFormRel; 932 let Defs = [CARRY, CR0] in 933 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 934 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 935 []>, isRecordForm, RecFormRel; 936 } 937 let BaseName = !strconcat(asmbase, "O") in { 938 let Defs = [CARRY, XER] in 939 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 940 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 941 []>, RecFormRel; 942 let Defs = [CARRY, XER, CR0] in 943 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 944 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 945 []>, isRecordForm, RecFormRel; 946 } 947} 948 949multiclass MForm_1r<bits<6> opcode, dag OOL, dag IOL, 950 string asmbase, string asmstr, InstrItinClass itin, 951 list<dag> pattern> { 952 let BaseName = asmbase in { 953 def NAME : MForm_1<opcode, OOL, IOL, 954 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 955 pattern>, RecFormRel; 956 let Defs = [CR0] in 957 def _rec : MForm_1<opcode, OOL, IOL, 958 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 959 []>, isRecordForm, RecFormRel; 960 } 961} 962 963multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 964 string asmbase, string asmstr, InstrItinClass itin, 965 list<dag> pattern> { 966 let BaseName = asmbase in { 967 def NAME : MForm_2<opcode, OOL, IOL, 968 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 969 pattern>, RecFormRel; 970 let Defs = [CR0] in 971 def _rec : MForm_2<opcode, OOL, IOL, 972 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 973 []>, isRecordForm, RecFormRel; 974 } 975} 976 977multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 978 string asmbase, string asmstr, InstrItinClass itin, 979 list<dag> pattern> { 980 let BaseName = asmbase in { 981 def NAME : MDForm_1<opcode, xo, OOL, IOL, 982 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 983 pattern>, RecFormRel; 984 let Defs = [CR0] in 985 def _rec : MDForm_1<opcode, xo, OOL, IOL, 986 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 987 []>, isRecordForm, RecFormRel; 988 } 989} 990 991multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 992 string asmbase, string asmstr, InstrItinClass itin, 993 list<dag> pattern> { 994 let BaseName = asmbase in { 995 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 996 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 997 pattern>, RecFormRel; 998 let Defs = [CR0] in 999 def _rec : MDSForm_1<opcode, xo, OOL, IOL, 1000 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1001 []>, isRecordForm, RecFormRel; 1002 } 1003} 1004 1005multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1006 string asmbase, string asmstr, InstrItinClass itin, 1007 list<dag> pattern> { 1008 let BaseName = asmbase in { 1009 let Defs = [CARRY] in 1010 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1011 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1012 pattern>, RecFormRel; 1013 let Defs = [CARRY, CR0] in 1014 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1015 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1016 []>, isRecordForm, RecFormRel; 1017 } 1018} 1019 1020multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1021 string asmbase, string asmstr, InstrItinClass itin, 1022 list<dag> pattern> { 1023 let BaseName = asmbase in { 1024 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1025 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1026 pattern>, RecFormRel; 1027 let Defs = [CR0] in 1028 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1029 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1030 []>, isRecordForm, RecFormRel; 1031 } 1032} 1033 1034multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1035 string asmbase, string asmstr, InstrItinClass itin, 1036 list<dag> pattern> { 1037 let BaseName = asmbase in { 1038 def NAME : XForm_26<opcode, xo, OOL, IOL, 1039 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1040 pattern>, RecFormRel; 1041 let Defs = [CR1] in 1042 def _rec : XForm_26<opcode, xo, OOL, IOL, 1043 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1044 []>, isRecordForm, RecFormRel; 1045 } 1046} 1047 1048multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1049 string asmbase, string asmstr, InstrItinClass itin, 1050 list<dag> pattern> { 1051 let BaseName = asmbase in { 1052 def NAME : XForm_28<opcode, xo, OOL, IOL, 1053 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1054 pattern>, RecFormRel; 1055 let Defs = [CR1] in 1056 def _rec : XForm_28<opcode, xo, OOL, IOL, 1057 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1058 []>, isRecordForm, RecFormRel; 1059 } 1060} 1061 1062multiclass XForm_SP2_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1063 string asmbase, string asmstr, list<dag> pattern> { 1064 let BaseName = asmbase in { 1065 def NAME : XForm_SP2_FRTB5<opcode, xo, OOL, IOL, 1066 !strconcat(asmbase, !strconcat(" ", asmstr)), 1067 pattern, NoItinerary>, RecFormRel; 1068 let Defs = [CR1] in 1069 def _rec : XForm_SP2_FRTB5<opcode, xo, OOL, IOL, 1070 !strconcat(asmbase, !strconcat(". ", asmstr)), 1071 [], NoItinerary>, isRecordForm, RecFormRel; 1072 } 1073} 1074 1075multiclass XForm_S1_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1076 string asmbase, string asmstr, list<dag> pattern> { 1077 let BaseName = asmbase in { 1078 def NAME : XForm_S1_FRTB5<opcode, xo, OOL, IOL, 1079 !strconcat(asmbase, !strconcat(" ", asmstr)), 1080 pattern, NoItinerary>, RecFormRel; 1081 let Defs = [CR1] in 1082 def _rec : XForm_S1_FRTB5<opcode, xo, OOL, IOL, 1083 !strconcat(asmbase, !strconcat(". ", asmstr)), [], 1084 NoItinerary>, isRecordForm, RecFormRel; 1085 } 1086} 1087 1088multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1089 string asmbase, string asmstr, InstrItinClass itin, 1090 list<dag> pattern> { 1091 let BaseName = asmbase in { 1092 def NAME : AForm_1<opcode, xo, OOL, IOL, 1093 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1094 pattern>, RecFormRel; 1095 let Defs = [CR1] in 1096 def _rec : AForm_1<opcode, xo, OOL, IOL, 1097 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1098 []>, isRecordForm, RecFormRel; 1099 } 1100} 1101 1102multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1103 string asmbase, string asmstr, InstrItinClass itin, 1104 list<dag> pattern> { 1105 let BaseName = asmbase in { 1106 def NAME : AForm_2<opcode, xo, OOL, IOL, 1107 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1108 pattern>, RecFormRel; 1109 let Defs = [CR1] in 1110 def _rec : AForm_2<opcode, xo, OOL, IOL, 1111 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1112 []>, isRecordForm, RecFormRel; 1113 } 1114} 1115 1116multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1117 string asmbase, string asmstr, InstrItinClass itin, 1118 list<dag> pattern> { 1119 let BaseName = asmbase in { 1120 def NAME : AForm_3<opcode, xo, OOL, IOL, 1121 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1122 pattern>, RecFormRel; 1123 let Defs = [CR1] in 1124 def _rec : AForm_3<opcode, xo, OOL, IOL, 1125 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1126 []>, isRecordForm, RecFormRel; 1127 } 1128} 1129 1130multiclass 1131 Z23Form_TE5_FRTB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1132 string asmbase, string asmstr, list<dag> pattern> { 1133 let BaseName = asmbase in { 1134 def NAME 1135 : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL, 1136 !strconcat(asmbase, !strconcat(" ", asmstr)), 1137 pattern>, RecFormRel; 1138 let Defs = [CR0] in 1139 def _rec : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL, 1140 !strconcat(asmbase, !strconcat(". ", asmstr)), 1141 []>, isRecordForm, RecFormRel; 1142 } 1143} 1144 1145multiclass 1146 Z23Form_FRTAB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1147 string asmbase, string asmstr, list<dag> pattern> { 1148 let BaseName = asmbase in { 1149 def NAME : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL, 1150 !strconcat(asmbase, !strconcat(" ", asmstr)), 1151 pattern>, RecFormRel; 1152 let Defs = [CR1] in 1153 def _rec : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL, 1154 !strconcat(asmbase, !strconcat(". ", asmstr)), 1155 []>, isRecordForm, RecFormRel; 1156 } 1157} 1158 1159multiclass 1160 Z23Form_FRTB5_R1_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1161 string asmbase, string asmstr, list<dag> pattern> { 1162 let BaseName = asmbase in { 1163 def NAME : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL, 1164 !strconcat(asmbase, !strconcat(" ", asmstr)), 1165 pattern>, RecFormRel; 1166 let Defs = [CR1] in 1167 def _rec : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL, 1168 !strconcat(asmbase, !strconcat(". ", asmstr)), 1169 []>, isRecordForm, RecFormRel; 1170 } 1171} 1172 1173multiclass Z22Form_FRTA5_SH6r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1174 string asmbase, string asmstr, list<dag> pattern> { 1175 let BaseName = asmbase in { 1176 def NAME : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL, 1177 !strconcat(asmbase, !strconcat(" ", asmstr)), 1178 pattern, NoItinerary>, RecFormRel; 1179 let Defs = [CR1] in 1180 def _rec : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL, 1181 !strconcat(asmbase, !strconcat(". ", asmstr)), 1182 [], NoItinerary>, isRecordForm, RecFormRel; 1183 } 1184} 1185 1186//===----------------------------------------------------------------------===// 1187// END OF MULTICLASS DEFINITIONS 1188//===----------------------------------------------------------------------===// 1189 1190//===----------------------------------------------------------------------===// 1191// PowerPC Instruction Definitions. 1192 1193// Pseudo instructions: 1194 1195let hasCtrlDep = 1 in { 1196let Defs = [R1], Uses = [R1] in { 1197def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1198 "#ADJCALLSTACKDOWN $amt1 $amt2", 1199 [(callseq_start timm:$amt1, timm:$amt2)]>; 1200def ADJCALLSTACKUP : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1201 "#ADJCALLSTACKUP $amt1 $amt2", 1202 [(callseq_end timm:$amt1, timm:$amt2)]>; 1203} 1204} // hasCtrlDep 1205 1206let Defs = [R1], Uses = [R1] in 1207def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 1208 [(set i32:$result, 1209 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 1210def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", 1211 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 1212// Probed alloca to support stack clash protection. 1213let Defs = [R1], Uses = [R1], hasNoSchedulingInfo = 1 in { 1214def PROBED_ALLOCA_32 : PPCCustomInserterPseudo<(outs gprc:$result), 1215 (ins gprc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_32", 1216 [(set i32:$result, 1217 (PPCprobedalloca i32:$negsize, iaddr:$fpsi))]>; 1218def PREPARE_PROBED_ALLOCA_32 : PPCEmitTimePseudo<(outs 1219 gprc:$fp, gprc:$actual_negsize), 1220 (ins gprc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_32", []>; 1221def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 : PPCEmitTimePseudo<(outs 1222 gprc:$fp, gprc:$actual_negsize), 1223 (ins gprc:$negsize, memri:$fpsi), 1224 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32", []>, 1225 RegConstraint<"$actual_negsize = $negsize">; 1226def PROBED_STACKALLOC_32 : PPCEmitTimePseudo<(outs gprc:$scratch, gprc:$temp), 1227 (ins i64imm:$stacksize), 1228 "#PROBED_STACKALLOC_32", []>; 1229} 1230 1231// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 1232// instruction selection into a branch sequence. 1233let PPC970_Single = 1 in { 1234 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 1235 // because either operand might become the first operand in an isel, and 1236 // that operand cannot be r0. 1237 def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond, 1238 gprc_nor0:$T, gprc_nor0:$F, 1239 i32imm:$BROPC), "#SELECT_CC_I4", 1240 []>; 1241 def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond, 1242 g8rc_nox0:$T, g8rc_nox0:$F, 1243 i32imm:$BROPC), "#SELECT_CC_I8", 1244 []>; 1245 def SELECT_CC_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 1246 i32imm:$BROPC), "#SELECT_CC_F4", 1247 []>; 1248 def SELECT_CC_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 1249 i32imm:$BROPC), "#SELECT_CC_F8", 1250 []>; 1251 def SELECT_CC_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1252 i32imm:$BROPC), "#SELECT_CC_F16", 1253 []>; 1254 def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1255 i32imm:$BROPC), "#SELECT_CC_VRRC", 1256 []>; 1257 1258 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 1259 // register bit directly. 1260 def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond, 1261 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 1262 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 1263 def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 1264 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 1265 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 1266let Predicates = [HasFPU] in { 1267 def SELECT_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 1268 f4rc:$T, f4rc:$F), "#SELECT_F4", 1269 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 1270 def SELECT_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 1271 f8rc:$T, f8rc:$F), "#SELECT_F8", 1272 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 1273 def SELECT_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1274 vrrc:$T, vrrc:$F), "#SELECT_F16", 1275 [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>; 1276} 1277 def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1278 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 1279 [(set v4i32:$dst, 1280 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 1281} 1282 1283// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 1284// scavenge a register for it. 1285let mayStore = 1 in { 1286def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F), 1287 "#SPILL_CR", []>; 1288def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F), 1289 "#SPILL_CRBIT", []>; 1290} 1291 1292// RESTORE_CR - Indicate that we're restoring the CR register (previously 1293// spilled), so we'll need to scavenge a register for it. 1294let mayLoad = 1 in { 1295def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F), 1296 "#RESTORE_CR", []>; 1297def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F), 1298 "#RESTORE_CRBIT", []>; 1299} 1300 1301let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 1302 let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in 1303 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 1304 [(PPCretglue)]>, Requires<[In32BitMode]>; 1305 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 1306 let isPredicable = 1 in 1307 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1308 []>; 1309 1310 let isCodeGenOnly = 1 in { 1311 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond), 1312 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 1313 []>; 1314 1315 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI), 1316 "bcctr 12, $BI, 0", IIC_BrB, []>; 1317 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI), 1318 "bcctr 4, $BI, 0", IIC_BrB, []>; 1319 } 1320 } 1321} 1322 1323// Set the float rounding mode. 1324let Uses = [RM], Defs = [RM] in { 1325def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND), 1326 "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>; 1327 1328def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in), 1329 "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>; 1330 1331def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FLM), 1332 "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>; 1333} 1334 1335let isBarrier = 1, hasSideEffects = 1, Defs = [RM] in 1336def FENCE : PPCEmitTimePseudo<(outs), (ins), "#FENCE", []>; 1337 1338let Defs = [LR] in 1339 def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>, 1340 PPC970_Unit_BRU; 1341let Defs = [LR] in 1342 def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>, 1343 PPC970_Unit_BRU; 1344 1345let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1346 hasSideEffects = 0 in { 1347 let isBarrier = 1 in { 1348 let isPredicable = 1 in 1349 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$LI), 1350 "b $LI", IIC_BrB, 1351 [(br bb:$LI)]>; 1352 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$LI), 1353 "ba $LI", IIC_BrB, []>; 1354 } 1355 1356 // BCC represents an arbitrary conditional branch on a predicate. 1357 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 1358 // a two-value operand where a dag node expects two operands. :( 1359 let isCodeGenOnly = 1 in { 1360 class BCC_class : BForm<16, 0, 0, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD), 1361 "b${cond:cc}${cond:pm} ${cond:reg}, $BD" 1362 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$BD)]*/>; 1363 def BCC : BCC_class; 1364 1365 // The same as BCC, except that it's not a terminator. Used for introducing 1366 // control flow dependency without creating new blocks. 1367 let isTerminator = 0 in def CTRL_DEP : BCC_class; 1368 1369 def BCCA : BForm<16, 1, 0, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD), 1370 "b${cond:cc}a${cond:pm} ${cond:reg}, $BD">; 1371 1372 let isReturn = 1, Uses = [LR, RM] in 1373 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins (pred $BIBO, $CR):$cond), 1374 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 1375 } 1376 1377 let isCodeGenOnly = 1 in { 1378 let Pattern = [(brcond i1:$BI, bb:$BD)] in 1379 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD), 1380 "bc 12, $BI, $BD">; 1381 1382 let Pattern = [(brcond (not i1:$BI), bb:$BD)] in 1383 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD), 1384 "bc 4, $BI, $BD">; 1385 1386 let isReturn = 1, Uses = [LR, RM] in { 1387 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$BI), 1388 "bclr 12, $BI, 0", IIC_BrB, []>; 1389 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$BI), 1390 "bclr 4, $BI, 0", IIC_BrB, []>; 1391 } 1392 } 1393 1394 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1395 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1396 "bdzlr", IIC_BrB, []>; 1397 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1398 "bdnzlr", IIC_BrB, []>; 1399 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1400 "bdzlr+", IIC_BrB, []>; 1401 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1402 "bdnzlr+", IIC_BrB, []>; 1403 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1404 "bdzlr-", IIC_BrB, []>; 1405 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1406 "bdnzlr-", IIC_BrB, []>; 1407 } 1408 1409 let Defs = [CTR], Uses = [CTR] in { 1410 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD), 1411 "bdz $BD">; 1412 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD), 1413 "bdnz $BD">; 1414 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$BD), 1415 "bdza $BD">; 1416 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$BD), 1417 "bdnza $BD">; 1418 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$BD), 1419 "bdz+ $BD">; 1420 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$BD), 1421 "bdnz+ $BD">; 1422 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$BD), 1423 "bdza+ $BD">; 1424 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$BD), 1425 "bdnza+ $BD">; 1426 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$BD), 1427 "bdz- $BD">; 1428 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$BD), 1429 "bdnz- $BD">; 1430 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$BD), 1431 "bdza- $BD">; 1432 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$BD), 1433 "bdnza- $BD">; 1434 } 1435} 1436 1437// The unconditional BCL used by the SjLj setjmp code. 1438let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7, 1439 hasSideEffects = 0 in { 1440 let Defs = [LR], Uses = [RM] in { 1441 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$BD), 1442 "bcl 20, 31, $BD">; 1443 } 1444} 1445 1446let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1447 // Convenient aliases for call instructions 1448 let Uses = [RM] in { 1449 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$LI), 1450 "bl $LI", IIC_BrB, []>; // See Pat patterns below. 1451 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), 1452 "bla $LI", IIC_BrB, [(PPCcall (i32 imm:$LI))]>; 1453 1454 let isCodeGenOnly = 1 in { 1455 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$LI), 1456 "bl $LI", IIC_BrB, []>; 1457 def BCCL : BForm<16, 0, 1, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD), 1458 "b${cond:cc}l${cond:pm} ${cond:reg}, $BD">; 1459 def BCCLA : BForm<16, 1, 1, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD), 1460 "b${cond:cc}la${cond:pm} ${cond:reg}, $BD">; 1461 1462 def BCL : BForm_4<16, 12, 0, 1, (outs), 1463 (ins crbitrc:$BI, condbrtarget:$BD), 1464 "bcl 12, $BI, $BD">; 1465 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1466 (ins crbitrc:$BI, condbrtarget:$BD), 1467 "bcl 4, $BI, $BD">; 1468 def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 1469 (outs), (ins calltarget:$LI), 1470 "bl $LI\n\tnop", IIC_BrB, []>; 1471 } 1472 } 1473 let Uses = [CTR, RM] in { 1474 let isPredicable = 1 in 1475 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1476 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1477 Requires<[In32BitMode]>; 1478 1479 let isCodeGenOnly = 1 in { 1480 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond), 1481 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1482 []>; 1483 1484 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI), 1485 "bcctrl 12, $BI, 0", IIC_BrB, []>; 1486 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI), 1487 "bcctrl 4, $BI, 0", IIC_BrB, []>; 1488 } 1489 } 1490 let Uses = [LR, RM] in { 1491 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1492 "blrl", IIC_BrB, []>; 1493 1494 let isCodeGenOnly = 1 in { 1495 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins (pred $BIBO, $CR):$cond), 1496 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1497 []>; 1498 1499 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$BI), 1500 "bclrl 12, $BI, 0", IIC_BrB, []>; 1501 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$BI), 1502 "bclrl 4, $BI, 0", IIC_BrB, []>; 1503 } 1504 } 1505 let Defs = [CTR], Uses = [CTR, RM] in { 1506 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$BD), 1507 "bdzl $BD">; 1508 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$BD), 1509 "bdnzl $BD">; 1510 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$BD), 1511 "bdzla $BD">; 1512 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$BD), 1513 "bdnzla $BD">; 1514 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$BD), 1515 "bdzl+ $BD">; 1516 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$BD), 1517 "bdnzl+ $BD">; 1518 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$BD), 1519 "bdzla+ $BD">; 1520 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$BD), 1521 "bdnzla+ $BD">; 1522 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$BD), 1523 "bdzl- $BD">; 1524 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$BD), 1525 "bdnzl- $BD">; 1526 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$BD), 1527 "bdzla- $BD">; 1528 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$BD), 1529 "bdnzla- $BD">; 1530 } 1531 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1532 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1533 "bdzlrl", IIC_BrB, []>; 1534 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1535 "bdnzlrl", IIC_BrB, []>; 1536 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1537 "bdzlrl+", IIC_BrB, []>; 1538 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1539 "bdnzlrl+", IIC_BrB, []>; 1540 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1541 "bdzlrl-", IIC_BrB, []>; 1542 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1543 "bdnzlrl-", IIC_BrB, []>; 1544 } 1545} 1546 1547let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in { 1548 // Convenient aliases for call instructions 1549 let Uses = [RM] in { 1550 def BL_RM : IForm<18, 0, 1, (outs), (ins calltarget:$LI), 1551 "bl $LI", IIC_BrB, []>; // See Pat patterns below. 1552 def BLA_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), 1553 "bla $LI", IIC_BrB, [(PPCcall_rm (i32 imm:$LI))]>; 1554 1555 def BL_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, 1556 (outs), (ins calltarget:$LI), 1557 "bl $LI\n\tnop", IIC_BrB, []>; 1558 } 1559 let Uses = [CTR, RM] in { 1560 let isPredicable = 1 in 1561 def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1562 "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, 1563 Requires<[In32BitMode]>; 1564 } 1565} 1566 1567let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1568def TCRETURNdi :PPCEmitTimePseudo< (outs), 1569 (ins calltarget:$dst, i32imm:$offset), 1570 "#TC_RETURNd $dst $offset", 1571 []>; 1572 1573 1574let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1575def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1576 "#TC_RETURNa $func $offset", 1577 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1578 1579let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1580def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1581 "#TC_RETURNr $dst $offset", 1582 []>; 1583 1584let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1585 Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in { 1586 def BCTRL_LWZinto_toc: 1587 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1588 (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB, 1589 [(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[In32BitMode]>; 1590 1591} 1592 1593let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1594 Defs = [LR, R2, RM], Uses = [CTR, RM], RST = 2 in { 1595 def BCTRL_LWZinto_toc_RM: 1596 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1597 (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB, 1598 [(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[In32BitMode]>; 1599 1600} 1601 1602let isCodeGenOnly = 1, hasSideEffects = 0 in { 1603 1604let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1605 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1606def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1607 []>, Requires<[In32BitMode]>; 1608 1609let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1610 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1611def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$LI), 1612 "b $LI", IIC_BrB, 1613 []>; 1614 1615let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1616 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1617def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$LI), 1618 "ba $LI", IIC_BrB, 1619 []>; 1620 1621} 1622 1623// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 1624// is not. 1625let hasSideEffects = 1 in { 1626 let Defs = [CTR] in 1627 def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 1628 "#EH_SJLJ_SETJMP32", 1629 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1630 Requires<[In32BitMode]>; 1631} 1632 1633let hasSideEffects = 1, isBarrier = 1 in { 1634 let isTerminator = 1 in 1635 def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 1636 "#EH_SJLJ_LONGJMP32", 1637 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1638 Requires<[In32BitMode]>; 1639} 1640 1641// This pseudo is never removed from the function, as it serves as 1642// a terminator. Size is set to 0 to prevent the builtin assembler 1643// from emitting it. 1644let isBranch = 1, isTerminator = 1, Size = 0 in { 1645 def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst), 1646 "#EH_SjLj_Setup\t$dst", []>; 1647} 1648 1649// System call. 1650let PPC970_Unit = 7 in { 1651 def SC : SCForm<17, 1, 0, (outs), (ins i32imm:$LEV), 1652 "sc $LEV", IIC_BrB, [(PPCsc (i32 imm:$LEV))]>; 1653} 1654 1655// We mark SCV as having no scheduling model since it is only meant to be used 1656// as inline assembly. If we implement a builtin pattern for it we will need to 1657// add it to the P9 and P10 scheduling models. 1658let Predicates = [IsISA3_0], hasNoSchedulingInfo = 1 in { 1659 def SCV : SCForm<17, 0, 1, (outs), (ins i32imm:$LEV), 1660 "scv $LEV", IIC_BrB, []>; 1661} 1662 1663// Branch history rolling buffer. 1664def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, 1665 [(PPCclrbhrb)]>, 1666 PPC970_DGroup_Single; 1667// The $dmy argument used for MFBHRBE is not needed; however, including 1668// it avoids automatic generation of PPCFastISel::fastEmit_i(), which 1669// interferes with necessary special handling (see PPCFastISel.cpp). 1670def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$RT), 1671 (ins u10imm:$imm, u10imm:$dmy), 1672 "mfbhrbe $RT, $imm", IIC_BrB, 1673 [(set i32:$RT, 1674 (PPCmfbhrbe imm:$imm, imm:$dmy))]>, 1675 PPC970_DGroup_First; 1676 1677def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$S), "rfebb $S", 1678 IIC_BrB, [(PPCrfebb (i32 imm:$S))]>, 1679 PPC970_DGroup_Single; 1680 1681def : InstAlias<"rfebb", (RFEBB 1)>; 1682 1683// DCB* instructions. 1684def DCBA : DCB_Form<758, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcba $addr", 1685 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$addr)]>, 1686 PPC970_DGroup_Single; 1687def DCBI : DCB_Form<470, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbi $addr", 1688 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$addr)]>, 1689 PPC970_DGroup_Single; 1690def DCBST : DCB_Form<54, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbst $addr", 1691 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$addr)]>, 1692 PPC970_DGroup_Single; 1693def DCBZ : DCB_Form<1014, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbz $addr", 1694 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$addr)]>, 1695 PPC970_DGroup_Single; 1696def DCBZL : DCB_Form<1014, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzl $addr", 1697 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$addr)]>, 1698 PPC970_DGroup_Single; 1699 1700def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, (memrr $RA, $RB):$addr), 1701 "dcbf $addr, $TH", IIC_LdStDCBF, []>, 1702 PPC970_DGroup_Single; 1703 1704let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 1705def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr), 1706 "dcbt $addr, $TH", IIC_LdStDCBF, []>, 1707 PPC970_DGroup_Single; 1708def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr), 1709 "dcbtst $addr, $TH", IIC_LdStDCBF, []>, 1710 PPC970_DGroup_Single; 1711} // hasSideEffects = 0 1712 1713def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1714 "icblc $CT, $addr", IIC_LdStStore>, Requires<[HasICBT]>; 1715def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1716 "icblq. $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; 1717def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1718 "icbt $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; 1719def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1720 "icbtls $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; 1721 1722def : Pat<(int_ppc_dcbt xoaddr:$dst), 1723 (DCBT 0, xoaddr:$dst)>; 1724def : Pat<(int_ppc_dcbtst xoaddr:$dst), 1725 (DCBTST 0, xoaddr:$dst)>; 1726def : Pat<(int_ppc_dcbf xoaddr:$dst), 1727 (DCBF 0, xoaddr:$dst)>; 1728def : Pat<(int_ppc_icbt xoaddr:$dst), 1729 (ICBT 0, xoaddr:$dst)>; 1730 1731def : Pat<(prefetch xoaddr:$dst, (i32 0), timm, (i32 1)), 1732 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads 1733def : Pat<(prefetch xoaddr:$dst, (i32 1), timm, (i32 1)), 1734 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores 1735def : Pat<(prefetch xoaddr:$dst, (i32 0), timm, (i32 0)), 1736 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) 1737 1738def : Pat<(int_ppc_dcbt_with_hint xoaddr:$dst, i32:$TH), 1739 (DCBT i32:$TH, xoaddr:$dst)>; 1740def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH), 1741 (DCBTST i32:$TH, xoaddr:$dst)>; 1742 1743// Atomic operations 1744// FIXME: some of these might be used with constant operands. This will result 1745// in constant materialization instructions that may be redundant. We currently 1746// clean this up in PPCMIPeephole with calls to 1747// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 1748// in the first place. 1749let Defs = [CR0] in { 1750 def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo< 1751 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 1752 [(set i32:$dst, (atomic_load_add_i8 ForceXForm:$ptr, i32:$incr))]>; 1753 def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo< 1754 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 1755 [(set i32:$dst, (atomic_load_sub_i8 ForceXForm:$ptr, i32:$incr))]>; 1756 def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo< 1757 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 1758 [(set i32:$dst, (atomic_load_and_i8 ForceXForm:$ptr, i32:$incr))]>; 1759 def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo< 1760 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 1761 [(set i32:$dst, (atomic_load_or_i8 ForceXForm:$ptr, i32:$incr))]>; 1762 def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo< 1763 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 1764 [(set i32:$dst, (atomic_load_xor_i8 ForceXForm:$ptr, i32:$incr))]>; 1765 def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo< 1766 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 1767 [(set i32:$dst, (atomic_load_nand_i8 ForceXForm:$ptr, i32:$incr))]>; 1768 def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo< 1769 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8", 1770 [(set i32:$dst, (atomic_load_min_i8 ForceXForm:$ptr, i32:$incr))]>; 1771 def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo< 1772 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8", 1773 [(set i32:$dst, (atomic_load_max_i8 ForceXForm:$ptr, i32:$incr))]>; 1774 def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo< 1775 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8", 1776 [(set i32:$dst, (atomic_load_umin_i8 ForceXForm:$ptr, i32:$incr))]>; 1777 def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo< 1778 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8", 1779 [(set i32:$dst, (atomic_load_umax_i8 ForceXForm:$ptr, i32:$incr))]>; 1780 def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo< 1781 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 1782 [(set i32:$dst, (atomic_load_add_i16 ForceXForm:$ptr, i32:$incr))]>; 1783 def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo< 1784 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 1785 [(set i32:$dst, (atomic_load_sub_i16 ForceXForm:$ptr, i32:$incr))]>; 1786 def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo< 1787 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 1788 [(set i32:$dst, (atomic_load_and_i16 ForceXForm:$ptr, i32:$incr))]>; 1789 def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo< 1790 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 1791 [(set i32:$dst, (atomic_load_or_i16 ForceXForm:$ptr, i32:$incr))]>; 1792 def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo< 1793 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 1794 [(set i32:$dst, (atomic_load_xor_i16 ForceXForm:$ptr, i32:$incr))]>; 1795 def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo< 1796 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 1797 [(set i32:$dst, (atomic_load_nand_i16 ForceXForm:$ptr, i32:$incr))]>; 1798 def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo< 1799 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16", 1800 [(set i32:$dst, (atomic_load_min_i16 ForceXForm:$ptr, i32:$incr))]>; 1801 def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo< 1802 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16", 1803 [(set i32:$dst, (atomic_load_max_i16 ForceXForm:$ptr, i32:$incr))]>; 1804 def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo< 1805 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16", 1806 [(set i32:$dst, (atomic_load_umin_i16 ForceXForm:$ptr, i32:$incr))]>; 1807 def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo< 1808 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16", 1809 [(set i32:$dst, (atomic_load_umax_i16 ForceXForm:$ptr, i32:$incr))]>; 1810 def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo< 1811 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 1812 [(set i32:$dst, (atomic_load_add_i32 ForceXForm:$ptr, i32:$incr))]>; 1813 def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo< 1814 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 1815 [(set i32:$dst, (atomic_load_sub_i32 ForceXForm:$ptr, i32:$incr))]>; 1816 def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo< 1817 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 1818 [(set i32:$dst, (atomic_load_and_i32 ForceXForm:$ptr, i32:$incr))]>; 1819 def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo< 1820 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 1821 [(set i32:$dst, (atomic_load_or_i32 ForceXForm:$ptr, i32:$incr))]>; 1822 def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo< 1823 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 1824 [(set i32:$dst, (atomic_load_xor_i32 ForceXForm:$ptr, i32:$incr))]>; 1825 def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo< 1826 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 1827 [(set i32:$dst, (atomic_load_nand_i32 ForceXForm:$ptr, i32:$incr))]>; 1828 def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo< 1829 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32", 1830 [(set i32:$dst, (atomic_load_min_i32 ForceXForm:$ptr, i32:$incr))]>; 1831 def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo< 1832 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32", 1833 [(set i32:$dst, (atomic_load_max_i32 ForceXForm:$ptr, i32:$incr))]>; 1834 def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo< 1835 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32", 1836 [(set i32:$dst, (atomic_load_umin_i32 ForceXForm:$ptr, i32:$incr))]>; 1837 def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo< 1838 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32", 1839 [(set i32:$dst, (atomic_load_umax_i32 ForceXForm:$ptr, i32:$incr))]>; 1840 1841 def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo< 1842 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 1843 [(set i32:$dst, (atomic_cmp_swap_i8 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1844 def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo< 1845 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 1846 [(set i32:$dst, (atomic_cmp_swap_i16 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1847 def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo< 1848 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 1849 [(set i32:$dst, (atomic_cmp_swap_i32 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1850 1851 def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo< 1852 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 1853 [(set i32:$dst, (atomic_swap_i8 ForceXForm:$ptr, i32:$new))]>; 1854 def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo< 1855 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 1856 [(set i32:$dst, (atomic_swap_i16 ForceXForm:$ptr, i32:$new))]>; 1857 def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo< 1858 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 1859 [(set i32:$dst, (atomic_swap_i32 ForceXForm:$ptr, i32:$new))]>; 1860} 1861 1862def : Pat<(PPCatomicCmpSwap_8 ForceXForm:$ptr, i32:$old, i32:$new), 1863 (ATOMIC_CMP_SWAP_I8 ForceXForm:$ptr, i32:$old, i32:$new)>; 1864def : Pat<(PPCatomicCmpSwap_16 ForceXForm:$ptr, i32:$old, i32:$new), 1865 (ATOMIC_CMP_SWAP_I16 ForceXForm:$ptr, i32:$old, i32:$new)>; 1866 1867// Instructions to support atomic operations 1868let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 1869def LBARX : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1870 "lbarx $RST, $addr", IIC_LdStLWARX, []>, 1871 Requires<[HasPartwordAtomics]>; 1872 1873def LHARX : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1874 "lharx $RST, $addr", IIC_LdStLWARX, []>, 1875 Requires<[HasPartwordAtomics]>; 1876 1877def LWARX : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1878 "lwarx $RST, $addr", IIC_LdStLWARX, []>; 1879 1880// Instructions to support lock versions of atomics 1881// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 1882def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1883 "lbarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm, 1884 Requires<[HasPartwordAtomics]>; 1885 1886def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1887 "lharx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm, 1888 Requires<[HasPartwordAtomics]>; 1889 1890def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1891 "lwarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm; 1892 1893// The atomic instructions use the destination register as well as the next one 1894// or two registers in order (modulo 31). 1895let hasExtraSrcRegAllocReq = 1 in 1896def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$RST), (ins gprc:$RA, u5imm:$RB), 1897 "lwat $RST, $RA, $RB", IIC_LdStLoad>, 1898 Requires<[IsISA3_0]>; 1899} 1900 1901let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 1902def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 1903 "stbcx. $RST, $addr", IIC_LdStSTWCX, []>, 1904 isRecordForm, Requires<[HasPartwordAtomics]>; 1905 1906def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 1907 "sthcx. $RST, $addr", IIC_LdStSTWCX, []>, 1908 isRecordForm, Requires<[HasPartwordAtomics]>; 1909 1910def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 1911 "stwcx. $RST, $addr", IIC_LdStSTWCX, []>, isRecordForm; 1912} 1913 1914let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 1915def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$RST, gprc:$RA, u5imm:$RB), 1916 "stwat $RST, $RA, $RB", IIC_LdStStore>, 1917 Requires<[IsISA3_0]>; 1918 1919let isTrap = 1, hasCtrlDep = 1 in 1920def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 1921 1922def TWI : DForm_base<3, (outs), (ins u5imm:$RST, gprc:$RA, s16imm:$D, variable_ops), 1923 "twi $RST, $RA, $D", IIC_IntTrapW, []>; 1924def TW : XForm_1<31, 4, (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB, variable_ops), 1925 "tw $RST, $RA, $RB", IIC_IntTrapW, []>; 1926def TDI : DForm_base<2, (outs), (ins u5imm:$RST, g8rc:$RA, s16imm:$D, variable_ops), 1927 "tdi $RST, $RA, $D", IIC_IntTrapD, []>; 1928def TD : XForm_1<31, 68, (outs), (ins u5imm:$RST, g8rc:$RA, g8rc:$RB, variable_ops), 1929 "td $RST, $RA, $RB", IIC_IntTrapD, []>; 1930 1931def POPCNTB : XForm_11<31, 122, (outs gprc:$RA), (ins gprc:$RST), 1932 "popcntb $RA, $RST", IIC_IntGeneral, 1933 [(set i32:$RA, (int_ppc_popcntb i32:$RST))]>; 1934 1935def CDTBCD : XForm_11<31, 282, (outs gprc:$RA), (ins gprc:$RST), 1936 "cdtbcd $RA, $RST", IIC_IntGeneral, 1937 [(set i32:$RA, (int_ppc_cdtbcd i32:$RST))]>; 1938def CBCDTD : XForm_11<31, 314, (outs gprc:$RA), (ins gprc:$RST), 1939 "cbcdtd $RA, $RST", IIC_IntGeneral, 1940 [(set i32:$RA, (int_ppc_cbcdtd i32:$RST))]>; 1941def ADDG6S : XOForm_1<31, 74, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 1942 "addg6s $RT, $RA, $RB", IIC_IntGeneral, 1943 [(set i32:$RT, (int_ppc_addg6s i32:$RA, i32:$RB))]>; 1944 1945//===----------------------------------------------------------------------===// 1946// PPC32 Load Instructions. 1947// 1948 1949// Unindexed (r+i) Loads. 1950let PPC970_Unit = 2 in { 1951def LBZ : DForm_1<34, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1952 "lbz $RST, $addr", IIC_LdStLoad, 1953 [(set i32:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64, 1954 SExt32To64; 1955def LHA : DForm_1<42, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1956 "lha $RST, $addr", IIC_LdStLHA, 1957 [(set i32:$RST, (sextloadi16 DForm:$addr))]>, 1958 PPC970_DGroup_Cracked, SExt32To64; 1959def LHZ : DForm_1<40, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1960 "lhz $RST, $addr", IIC_LdStLoad, 1961 [(set i32:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64, 1962 SExt32To64; 1963def LWZ : DForm_1<32, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1964 "lwz $RST, $addr", IIC_LdStLoad, 1965 [(set i32:$RST, (load DForm:$addr))]>, ZExt32To64; 1966 1967let Predicates = [HasFPU] in { 1968def LFS : DForm_1<48, (outs f4rc:$RST), (ins (memri $D, $RA):$addr), 1969 "lfs $RST, $addr", IIC_LdStLFD, 1970 [(set f32:$RST, (load DForm:$addr))]>; 1971def LFD : DForm_1<50, (outs f8rc:$RST), (ins (memri $D, $RA):$addr), 1972 "lfd $RST, $addr", IIC_LdStLFD, 1973 [(set f64:$RST, (load DForm:$addr))]>; 1974} 1975 1976 1977// Unindexed (r+i) Loads with Update (preinc). 1978let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 1979def LBZU : DForm_1<35, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1980 "lbzu $RST, $addr", IIC_LdStLoadUpd, 1981 []>, RegConstraint<"$RA = $ea_result">; 1982 1983def LHAU : DForm_1<43, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1984 "lhau $RST, $addr", IIC_LdStLHAU, 1985 []>, RegConstraint<"$addr.reg = $ea_result">, 1986 NoEncode<"$ea_result">; 1987 1988def LHZU : DForm_1<41, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1989 "lhzu $RST, $addr", IIC_LdStLoadUpd, 1990 []>, RegConstraint<"$addr.reg = $ea_result">, 1991 NoEncode<"$ea_result">; 1992 1993def LWZU : DForm_1<33, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1994 "lwzu $RST, $addr", IIC_LdStLoadUpd, 1995 []>, RegConstraint<"$addr.reg = $ea_result">, 1996 NoEncode<"$ea_result">; 1997 1998let Predicates = [HasFPU] in { 1999def LFSU : DForm_1<49, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 2000 "lfsu $RST, $addr", IIC_LdStLFDU, 2001 []>, RegConstraint<"$addr.reg = $ea_result">, 2002 NoEncode<"$ea_result">; 2003 2004def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 2005 "lfdu $RST, $addr", IIC_LdStLFDU, 2006 []>, RegConstraint<"$addr.reg = $ea_result">, 2007 NoEncode<"$ea_result">; 2008} 2009 2010 2011// Indexed (r+r) Loads with Update (preinc). 2012def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2013 (ins (memrr $RA, $RB):$addr), 2014 "lbzux $RST, $addr", IIC_LdStLoadUpdX, 2015 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2016 NoEncode<"$ea_result">; 2017 2018def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2019 (ins (memrr $RA, $RB):$addr), 2020 "lhaux $RST, $addr", IIC_LdStLHAUX, 2021 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2022 NoEncode<"$ea_result">; 2023 2024def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2025 (ins (memrr $RA, $RB):$addr), 2026 "lhzux $RST, $addr", IIC_LdStLoadUpdX, 2027 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2028 NoEncode<"$ea_result">; 2029 2030def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2031 (ins (memrr $RA, $RB):$addr), 2032 "lwzux $RST, $addr", IIC_LdStLoadUpdX, 2033 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2034 NoEncode<"$ea_result">; 2035 2036let Predicates = [HasFPU] in { 2037def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), 2038 (ins (memrr $RA, $RB):$addr), 2039 "lfsux $RST, $addr", IIC_LdStLFDUX, 2040 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2041 NoEncode<"$ea_result">; 2042 2043def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), 2044 (ins (memrr $RA, $RB):$addr), 2045 "lfdux $RST, $addr", IIC_LdStLFDUX, 2046 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2047 NoEncode<"$ea_result">; 2048} 2049} 2050} 2051 2052// Indexed (r+r) Loads. 2053// 2054let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { 2055def LBZX : XForm_1_memOp<31, 87, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2056 "lbzx $RST, $addr", IIC_LdStLoad, 2057 [(set i32:$RST, (zextloadi8 XForm:$addr))]>, ZExt32To64, 2058 SExt32To64; 2059def LHAX : XForm_1_memOp<31, 343, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2060 "lhax $RST, $addr", IIC_LdStLHA, 2061 [(set i32:$RST, (sextloadi16 XForm:$addr))]>, 2062 PPC970_DGroup_Cracked, SExt32To64; 2063def LHZX : XForm_1_memOp<31, 279, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2064 "lhzx $RST, $addr", IIC_LdStLoad, 2065 [(set i32:$RST, (zextloadi16 XForm:$addr))]>, ZExt32To64, 2066 SExt32To64; 2067def LWZX : XForm_1_memOp<31, 23, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2068 "lwzx $RST, $addr", IIC_LdStLoad, 2069 [(set i32:$RST, (load XForm:$addr))]>, ZExt32To64; 2070def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2071 "lhbrx $RST, $addr", IIC_LdStLoad, 2072 [(set i32:$RST, (PPClbrx ForceXForm:$addr, i16))]>, ZExt32To64; 2073def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2074 "lwbrx $RST, $addr", IIC_LdStLoad, 2075 [(set i32:$RST, (PPClbrx ForceXForm:$addr, i32))]>, ZExt32To64; 2076 2077let Predicates = [HasFPU] in { 2078def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$RST), (ins (memrr $RA, $RB):$addr), 2079 "lfsx $RST, $addr", IIC_LdStLFD, 2080 [(set f32:$RST, (load XForm:$addr))]>; 2081def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 2082 "lfdx $RST, $addr", IIC_LdStLFD, 2083 [(set f64:$RST, (load XForm:$addr))]>; 2084 2085def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 2086 "lfiwax $RST, $addr", IIC_LdStLFD, 2087 [(set f64:$RST, (PPClfiwax ForceXForm:$addr))]>; 2088def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 2089 "lfiwzx $RST, $addr", IIC_LdStLFD, 2090 [(set f64:$RST, (PPClfiwzx ForceXForm:$addr))]>; 2091} 2092} 2093 2094// Load Multiple 2095let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in 2096def LMW : DForm_1<46, (outs gprc:$RST), (ins (memri $D, $RA):$src), 2097 "lmw $RST, $src", IIC_LdStLMW, []>; 2098 2099//===----------------------------------------------------------------------===// 2100// PPC32 Store Instructions. 2101// 2102 2103// Unindexed (r+i) Stores. 2104let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2105def STB : DForm_1<38, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2106 "stb $RST, $dst", IIC_LdStStore, 2107 [(truncstorei8 i32:$RST, DForm:$dst)]>; 2108def STH : DForm_1<44, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2109 "sth $RST, $dst", IIC_LdStStore, 2110 [(truncstorei16 i32:$RST, DForm:$dst)]>; 2111def STW : DForm_1<36, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2112 "stw $RST, $dst", IIC_LdStStore, 2113 [(store i32:$RST, DForm:$dst)]>; 2114let Predicates = [HasFPU] in { 2115def STFS : DForm_1<52, (outs), (ins f4rc:$RST, (memri $D, $RA):$dst), 2116 "stfs $RST, $dst", IIC_LdStSTFD, 2117 [(store f32:$RST, DForm:$dst)]>; 2118def STFD : DForm_1<54, (outs), (ins f8rc:$RST, (memri $D, $RA):$dst), 2119 "stfd $RST, $dst", IIC_LdStSTFD, 2120 [(store f64:$RST, DForm:$dst)]>; 2121} 2122} 2123 2124// Unindexed (r+i) Stores with Update (preinc). 2125let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2126def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), 2127 "stbu $RST, $dst", IIC_LdStSTU, []>, 2128 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2129def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), 2130 "sthu $RST, $dst", IIC_LdStSTU, []>, 2131 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2132def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), 2133 "stwu $RST, $dst", IIC_LdStSTU, []>, 2134 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2135let Predicates = [HasFPU] in { 2136def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$RST, (memri $D, $RA):$dst), 2137 "stfsu $RST, $dst", IIC_LdStSTFDU, []>, 2138 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2139def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$RST, (memri $D, $RA):$dst), 2140 "stfdu $RST, $dst", IIC_LdStSTFDU, []>, 2141 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2142} 2143} 2144 2145// Patterns to match the pre-inc stores. We can't put the patterns on 2146// the instruction definitions directly as ISel wants the address base 2147// and offset to be separate operands, not a single complex operand. 2148def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2149 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 2150def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2151 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 2152def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2153 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 2154def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2155 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 2156def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2157 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 2158 2159// Indexed (r+r) Stores. 2160let PPC970_Unit = 2 in { 2161def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2162 "stbx $RST, $addr", IIC_LdStStore, 2163 [(truncstorei8 i32:$RST, XForm:$addr)]>, 2164 PPC970_DGroup_Cracked; 2165def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2166 "sthx $RST, $addr", IIC_LdStStore, 2167 [(truncstorei16 i32:$RST, XForm:$addr)]>, 2168 PPC970_DGroup_Cracked; 2169def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2170 "stwx $RST, $addr", IIC_LdStStore, 2171 [(store i32:$RST, XForm:$addr)]>, 2172 PPC970_DGroup_Cracked; 2173 2174def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2175 "sthbrx $RST, $addr", IIC_LdStStore, 2176 [(PPCstbrx i32:$RST, ForceXForm:$addr, i16)]>, 2177 PPC970_DGroup_Cracked; 2178def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2179 "stwbrx $RST, $addr", IIC_LdStStore, 2180 [(PPCstbrx i32:$RST, ForceXForm:$addr, i32)]>, 2181 PPC970_DGroup_Cracked; 2182 2183let Predicates = [HasFPU] in { 2184def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), 2185 "stfiwx $RST, $addr", IIC_LdStSTFD, 2186 [(PPCstfiwx f64:$RST, ForceXForm:$addr)]>; 2187 2188def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$RST, (memrr $RA, $RB):$addr), 2189 "stfsx $RST, $addr", IIC_LdStSTFD, 2190 [(store f32:$RST, XForm:$addr)]>; 2191def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), 2192 "stfdx $RST, $addr", IIC_LdStSTFD, 2193 [(store f64:$RST, XForm:$addr)]>; 2194} 2195} 2196 2197// Indexed (r+r) Stores with Update (preinc). 2198let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2199def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 2200 (ins gprc:$RST, (memrr $RA, $RB):$addr), 2201 "stbux $RST, $addr", IIC_LdStSTUX, []>, 2202 RegConstraint<"$addr.ptrreg = $ea_res">, 2203 NoEncode<"$ea_res">, 2204 PPC970_DGroup_Cracked; 2205def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 2206 (ins gprc:$RST, (memrr $RA, $RB):$addr), 2207 "sthux $RST, $addr", IIC_LdStSTUX, []>, 2208 RegConstraint<"$addr.ptrreg = $ea_res">, 2209 NoEncode<"$ea_res">, 2210 PPC970_DGroup_Cracked; 2211def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 2212 (ins gprc:$RST, (memrr $RA, $RB):$addr), 2213 "stwux $RST, $addr", IIC_LdStSTUX, []>, 2214 RegConstraint<"$addr.ptrreg = $ea_res">, 2215 NoEncode<"$ea_res">, 2216 PPC970_DGroup_Cracked; 2217let Predicates = [HasFPU] in { 2218def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), 2219 (ins f4rc:$RST, (memrr $RA, $RB):$addr), 2220 "stfsux $RST, $addr", IIC_LdStSTFDU, []>, 2221 RegConstraint<"$addr.ptrreg = $ea_res">, 2222 NoEncode<"$ea_res">, 2223 PPC970_DGroup_Cracked; 2224def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), 2225 (ins f8rc:$RST, (memrr $RA, $RB):$addr), 2226 "stfdux $RST, $addr", IIC_LdStSTFDU, []>, 2227 RegConstraint<"$addr.ptrreg = $ea_res">, 2228 NoEncode<"$ea_res">, 2229 PPC970_DGroup_Cracked; 2230} 2231} 2232 2233// Patterns to match the pre-inc stores. We can't put the patterns on 2234// the instruction definitions directly as ISel wants the address base 2235// and offset to be separate operands, not a single complex operand. 2236def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2237 (STBUX $rS, $ptrreg, $ptroff)>; 2238def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2239 (STHUX $rS, $ptrreg, $ptroff)>; 2240def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2241 (STWUX $rS, $ptrreg, $ptroff)>; 2242let Predicates = [HasFPU] in { 2243def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2244 (STFSUX $rS, $ptrreg, $ptroff)>; 2245def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2246 (STFDUX $rS, $ptrreg, $ptroff)>; 2247} 2248 2249// Store Multiple 2250let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2251def STMW : DForm_1<47, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2252 "stmw $RST, $dst", IIC_LdStLMW, []>; 2253 2254def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L), 2255 "sync $L", IIC_LdStSync, []>; 2256 2257let isCodeGenOnly = 1 in { 2258 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 2259 "msync", IIC_LdStSync, []> { 2260 let L = 0; 2261 } 2262} 2263 2264// We used to have EIEIO as value but E[0-9A-Z] is a reserved name 2265def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins), 2266 "eieio", IIC_LdStLoad, []>; 2267 2268def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO", 2269 [(int_ppc_eieio)]>; 2270 2271def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2272def : Pat<(int_ppc_iospace_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2273def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2274def : Pat<(int_ppc_iospace_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2275def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2276def : Pat<(int_ppc_iospace_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2277def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2278def : Pat<(int_ppc_iospace_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2279def : Pat<(int_ppc_eieio), (PseudoEIEIO)>; 2280def : Pat<(int_ppc_iospace_eieio), (PseudoEIEIO)>; 2281 2282//===----------------------------------------------------------------------===// 2283// PPC32 Arithmetic Instructions. 2284// 2285 2286let PPC970_Unit = 1 in { // FXU Operations. 2287def ADDI : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D), 2288 "addi $RST, $RA, $D", IIC_IntSimple, 2289 [(set i32:$RST, (add i32:$RA, imm32SExt16:$D))]>; 2290let BaseName = "addic" in { 2291let Defs = [CARRY] in 2292def ADDIC : DForm_2<12, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2293 "addic $RST, $RA, $D", IIC_IntGeneral, 2294 [(set i32:$RST, (addc i32:$RA, imm32SExt16:$D))]>, 2295 RecFormRel, PPC970_DGroup_Cracked; 2296let Defs = [CARRY, CR0] in 2297def ADDIC_rec : DForm_2<13, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2298 "addic. $RST, $RA, $D", IIC_IntGeneral, 2299 []>, isRecordForm, RecFormRel; 2300} 2301def ADDIS : DForm_2<15, (outs gprc:$RST), (ins gprc_nor0:$RA, s17imm:$D), 2302 "addis $RST, $RA, $D", IIC_IntSimple, 2303 [(set i32:$RST, (add i32:$RA, imm16ShiftedSExt:$D))]>; 2304let isCodeGenOnly = 1 in 2305def LA : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D), 2306 "la $RST, $D($RA)", IIC_IntGeneral, 2307 [(set i32:$RST, (add i32:$RA, 2308 (PPClo tglobaladdr:$D, 0)))]>, MemriOp; 2309def MULLI : DForm_2< 7, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2310 "mulli $RST, $RA, $D", IIC_IntMulLI, 2311 [(set i32:$RST, (mul i32:$RA, imm32SExt16:$D))]>; 2312let Defs = [CARRY] in 2313def SUBFIC : DForm_2< 8, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2314 "subfic $RST, $RA, $D", IIC_IntGeneral, 2315 [(set i32:$RST, (subc imm32SExt16:$D, i32:$RA))]>; 2316 2317let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 2318 def LI : DForm_2_r0<14, (outs gprc:$RST), (ins s16imm:$D), 2319 "li $RST, $D", IIC_IntSimple, 2320 [(set i32:$RST, imm32SExt16:$D)]>, SExt32To64; 2321 def LIS : DForm_2_r0<15, (outs gprc:$RST), (ins s17imm:$D), 2322 "lis $RST, $D", IIC_IntSimple, 2323 [(set i32:$RST, imm16ShiftedSExt:$D)]>, SExt32To64; 2324} 2325} 2326 2327def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>; 2328def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>; 2329 2330let PPC970_Unit = 1 in { // FXU Operations. 2331let Defs = [CR0] in { 2332def ANDI_rec : DForm_4<28, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2333 "andi. $RA, $RST, $D", IIC_IntGeneral, 2334 [(set i32:$RA, (and i32:$RST, immZExt16:$D))]>, 2335 isRecordForm, ZExt32To64, SExt32To64; 2336def ANDIS_rec : DForm_4<29, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2337 "andis. $RA, $RST, $D", IIC_IntGeneral, 2338 [(set i32:$RA, (and i32:$RST, imm16ShiftedZExt:$D))]>, 2339 isRecordForm, ZExt32To64; 2340} 2341def ORI : DForm_4<24, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2342 "ori $RA, $RST, $D", IIC_IntSimple, 2343 [(set i32:$RA, (or i32:$RST, immZExt16:$D))]>; 2344def ORIS : DForm_4<25, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2345 "oris $RA, $RST, $D", IIC_IntSimple, 2346 [(set i32:$RA, (or i32:$RST, imm16ShiftedZExt:$D))]>; 2347def XORI : DForm_4<26, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2348 "xori $RA, $RST, $D", IIC_IntSimple, 2349 [(set i32:$RA, (xor i32:$RST, immZExt16:$D))]>; 2350def XORIS : DForm_4<27, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2351 "xoris $RA, $RST, $D", IIC_IntSimple, 2352 [(set i32:$RA, (xor i32:$RST, imm16ShiftedZExt:$D))]>; 2353 2354def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 2355 []>; 2356let isCodeGenOnly = 1 in { 2357// The POWER6 and POWER7 have special group-terminating nops. 2358def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 2359 "ori 1, 1, 0", IIC_IntSimple, []>; 2360def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 2361 "ori 2, 2, 0", IIC_IntSimple, []>; 2362} 2363 2364let isCompare = 1, hasSideEffects = 0 in { 2365 def CMPWI : DForm_5_ext<11, (outs crrc:$BF), (ins gprc:$RA, s16imm:$D), 2366 "cmpwi $BF, $RA, $D", IIC_IntCompare>; 2367 def CMPLWI : DForm_6_ext<10, (outs crrc:$BF), (ins gprc:$RA, u16imm:$D), 2368 "cmplwi $BF, $RA, $D", IIC_IntCompare>; 2369 def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 2370 (ins u1imm:$L, gprc:$RA, gprc:$RB), 2371 "cmprb $BF, $L, $RA, $RB", IIC_IntCompare, []>, 2372 Requires<[IsISA3_0]>; 2373} 2374} 2375 2376let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2377let isCommutable = 1 in { 2378defm NAND : XForm_6r<31, 476, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2379 "nand", "$RA, $RST, $RB", IIC_IntSimple, 2380 [(set i32:$RA, (not (and i32:$RST, i32:$RB)))]>; 2381defm AND : XForm_6r<31, 28, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2382 "and", "$RA, $RST, $RB", IIC_IntSimple, 2383 [(set i32:$RA, (and i32:$RST, i32:$RB))]>; 2384} // isCommutable 2385defm ANDC : XForm_6r<31, 60, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2386 "andc", "$RA, $RST, $RB", IIC_IntSimple, 2387 [(set i32:$RA, (and i32:$RST, (not i32:$RB)))]>; 2388let isCommutable = 1 in { 2389defm OR : XForm_6r<31, 444, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2390 "or", "$RA, $RST, $RB", IIC_IntSimple, 2391 [(set i32:$RA, (or i32:$RST, i32:$RB))]>; 2392defm NOR : XForm_6r<31, 124, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2393 "nor", "$RA, $RST, $RB", IIC_IntSimple, 2394 [(set i32:$RA, (not (or i32:$RST, i32:$RB)))]>; 2395} // isCommutable 2396defm ORC : XForm_6r<31, 412, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2397 "orc", "$RA, $RST, $RB", IIC_IntSimple, 2398 [(set i32:$RA, (or i32:$RST, (not i32:$RB)))]>; 2399let isCommutable = 1 in { 2400defm EQV : XForm_6r<31, 284, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2401 "eqv", "$RA, $RST, $RB", IIC_IntSimple, 2402 [(set i32:$RA, (not (xor i32:$RST, i32:$RB)))]>; 2403defm XOR : XForm_6r<31, 316, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2404 "xor", "$RA, $RST, $RB", IIC_IntSimple, 2405 [(set i32:$RA, (xor i32:$RST, i32:$RB))]>; 2406} // isCommutable 2407defm SLW : XForm_6r<31, 24, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2408 "slw", "$RA, $RST, $RB", IIC_IntGeneral, 2409 [(set i32:$RA, (PPCshl i32:$RST, i32:$RB))]>, ZExt32To64; 2410defm SRW : XForm_6r<31, 536, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2411 "srw", "$RA, $RST, $RB", IIC_IntGeneral, 2412 [(set i32:$RA, (PPCsrl i32:$RST, i32:$RB))]>, ZExt32To64; 2413defm SRAW : XForm_6rc<31, 792, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2414 "sraw", "$RA, $RST, $RB", IIC_IntShift, 2415 [(set i32:$RA, (PPCsra i32:$RST, i32:$RB))]>, SExt32To64; 2416} 2417 2418def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>; 2419def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>; 2420 2421def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>; 2422def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>; 2423 2424def : InstAlias<"nop", (ORI R0, R0, 0)>; 2425 2426let PPC970_Unit = 1 in { // FXU Operations. 2427let hasSideEffects = 0 in { 2428defm SRAWI : XForm_10rc<31, 824, (outs gprc:$RA), (ins gprc:$RST, u5imm:$RB), 2429 "srawi", "$RA, $RST, $RB", IIC_IntShift, 2430 [(set i32:$RA, (sra i32:$RST, (i32 imm:$RB)))]>, 2431 SExt32To64; 2432defm CNTLZW : XForm_11r<31, 26, (outs gprc:$RA), (ins gprc:$RST), 2433 "cntlzw", "$RA, $RST", IIC_IntGeneral, 2434 [(set i32:$RA, (ctlz i32:$RST))]>, ZExt32To64; 2435defm CNTTZW : XForm_11r<31, 538, (outs gprc:$RA), (ins gprc:$RST), 2436 "cnttzw", "$RA, $RST", IIC_IntGeneral, 2437 [(set i32:$RA, (cttz i32:$RST))]>, Requires<[IsISA3_0]>, 2438 ZExt32To64; 2439defm EXTSB : XForm_11r<31, 954, (outs gprc:$RA), (ins gprc:$RST), 2440 "extsb", "$RA, $RST", IIC_IntSimple, 2441 [(set i32:$RA, (sext_inreg i32:$RST, i8))]>, SExt32To64; 2442defm EXTSH : XForm_11r<31, 922, (outs gprc:$RA), (ins gprc:$RST), 2443 "extsh", "$RA, $RST", IIC_IntSimple, 2444 [(set i32:$RA, (sext_inreg i32:$RST, i16))]>, SExt32To64; 2445 2446let isCommutable = 1 in 2447def CMPB : XForm_6<31, 508, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2448 "cmpb $RA, $RST, $RB", IIC_IntGeneral, 2449 [(set i32:$RA, (PPCcmpb i32:$RST, i32:$RB))]>; 2450} 2451let isCompare = 1, hasSideEffects = 0 in { 2452 def CMPW : XForm_16_ext<31, 0, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB), 2453 "cmpw $BF, $RA, $RB", IIC_IntCompare>; 2454 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB), 2455 "cmplw $BF, $RA, $RB", IIC_IntCompare>; 2456} 2457} 2458let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations. 2459let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in { 2460 def FCMPUS : XForm_17<63, 0, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB), 2461 "fcmpu $BF, $RA, $RB", IIC_FPCompare>; 2462 def FCMPOS : XForm_17<63, 32, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB), 2463 "fcmpo $BF, $RA, $RB", IIC_FPCompare>; 2464 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 2465 def FCMPUD : XForm_17<63, 0, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), 2466 "fcmpu $BF, $RA, $RB", IIC_FPCompare>; 2467 def FCMPOD : XForm_17<63, 32, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), 2468 "fcmpo $BF, $RA, $RB", IIC_FPCompare>; 2469 } 2470} 2471 2472def FTDIV: XForm_17<63, 128, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), 2473 "ftdiv $BF, $RA, $RB", IIC_FPCompare>; 2474def FTSQRT: XForm_17a<63, 160, (outs crrc:$BF), (ins f8rc:$RB), 2475 "ftsqrt $BF, $RB", IIC_FPCompare, 2476 [(set i32:$BF, (PPCftsqrt f64:$RB))]>; 2477 2478let mayRaiseFPException = 1, hasSideEffects = 0 in { 2479 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2480 defm FRIND : XForm_26r<63, 392, (outs f8rc:$RST), (ins f8rc:$RB), 2481 "frin", "$RST, $RB", IIC_FPGeneral, 2482 [(set f64:$RST, (any_fround f64:$RB))]>; 2483 defm FRINS : XForm_26r<63, 392, (outs f4rc:$RST), (ins f4rc:$RB), 2484 "frin", "$RST, $RB", IIC_FPGeneral, 2485 [(set f32:$RST, (any_fround f32:$RB))]>; 2486 2487 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2488 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$RST), (ins f8rc:$RB), 2489 "frip", "$RST, $RB", IIC_FPGeneral, 2490 [(set f64:$RST, (any_fceil f64:$RB))]>; 2491 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$RST), (ins f4rc:$RB), 2492 "frip", "$RST, $RB", IIC_FPGeneral, 2493 [(set f32:$RST, (any_fceil f32:$RB))]>; 2494 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2495 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$RST), (ins f8rc:$RB), 2496 "friz", "$RST, $RB", IIC_FPGeneral, 2497 [(set f64:$RST, (any_ftrunc f64:$RB))]>; 2498 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$RST), (ins f4rc:$RB), 2499 "friz", "$RST, $RB", IIC_FPGeneral, 2500 [(set f32:$RST, (any_ftrunc f32:$RB))]>; 2501 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2502 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$RST), (ins f8rc:$RB), 2503 "frim", "$RST, $RB", IIC_FPGeneral, 2504 [(set f64:$RST, (any_ffloor f64:$RB))]>; 2505 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$RST), (ins f4rc:$RB), 2506 "frim", "$RST, $RB", IIC_FPGeneral, 2507 [(set f32:$RST, (any_ffloor f32:$RB))]>; 2508} 2509 2510let Uses = [RM], mayRaiseFPException = 1, hasSideEffects = 0 in { 2511 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$RST), (ins f8rc:$RB), 2512 "fctiw", "$RST, $RB", IIC_FPGeneral, 2513 []>; 2514 defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$RST), (ins f8rc:$RB), 2515 "fctiwu", "$RST, $RB", IIC_FPGeneral, 2516 []>; 2517 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$RST), (ins f8rc:$RB), 2518 "fctiwz", "$RST, $RB", IIC_FPGeneral, 2519 [(set f64:$RST, (PPCany_fctiwz f64:$RB))]>; 2520 2521 defm FRSP : XForm_26r<63, 12, (outs f4rc:$RST), (ins f8rc:$RB), 2522 "frsp", "$RST, $RB", IIC_FPGeneral, 2523 [(set f32:$RST, (any_fpround f64:$RB))]>; 2524 2525 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$RST), (ins f8rc:$RB), 2526 "fsqrt", "$RST, $RB", IIC_FPSqrtD, 2527 [(set f64:$RST, (any_fsqrt f64:$RB))]>; 2528 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$RST), (ins f4rc:$RB), 2529 "fsqrts", "$RST, $RB", IIC_FPSqrtS, 2530 [(set f32:$RST, (any_fsqrt f32:$RB))]>; 2531} 2532} 2533 2534def : Pat<(PPCfsqrt f64:$frA), (FSQRT $frA)>; 2535 2536/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 2537/// often coalesced away and we don't want the dispatch group builder to think 2538/// that they will fill slots (which could cause the load of a LSU reject to 2539/// sneak into a d-group with a store). 2540let hasSideEffects = 0, Predicates = [HasFPU] in 2541defm FMR : XForm_26r<63, 72, (outs f4rc:$RST), (ins f4rc:$RB), 2542 "fmr", "$RST, $RB", IIC_FPGeneral, 2543 []>, // (set f32:$RST, f32:$RB) 2544 PPC970_Unit_Pseudo; 2545 2546let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2547// These are artificially split into two different forms, for 4/8 byte FP. 2548defm FABSS : XForm_26r<63, 264, (outs f4rc:$RST), (ins f4rc:$RB), 2549 "fabs", "$RST, $RB", IIC_FPGeneral, 2550 [(set f32:$RST, (fabs f32:$RB))]>; 2551let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2552defm FABSD : XForm_26r<63, 264, (outs f8rc:$RST), (ins f8rc:$RB), 2553 "fabs", "$RST, $RB", IIC_FPGeneral, 2554 [(set f64:$RST, (fabs f64:$RB))]>; 2555defm FNABSS : XForm_26r<63, 136, (outs f4rc:$RST), (ins f4rc:$RB), 2556 "fnabs", "$RST, $RB", IIC_FPGeneral, 2557 [(set f32:$RST, (fneg (fabs f32:$RB)))]>; 2558let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2559defm FNABSD : XForm_26r<63, 136, (outs f8rc:$RST), (ins f8rc:$RB), 2560 "fnabs", "$RST, $RB", IIC_FPGeneral, 2561 [(set f64:$RST, (fneg (fabs f64:$RB)))]>; 2562defm FNEGS : XForm_26r<63, 40, (outs f4rc:$RST), (ins f4rc:$RB), 2563 "fneg", "$RST, $RB", IIC_FPGeneral, 2564 [(set f32:$RST, (fneg f32:$RB))]>; 2565let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2566defm FNEGD : XForm_26r<63, 40, (outs f8rc:$RST), (ins f8rc:$RB), 2567 "fneg", "$RST, $RB", IIC_FPGeneral, 2568 [(set f64:$RST, (fneg f64:$RB))]>; 2569 2570defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$RST), (ins f4rc:$RA, f4rc:$RB), 2571 "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral, 2572 [(set f32:$RST, (fcopysign f32:$RB, f32:$RA))]>; 2573let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2574defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB), 2575 "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral, 2576 [(set f64:$RST, (fcopysign f64:$RB, f64:$RA))]>; 2577 2578// Reciprocal estimates. 2579let mayRaiseFPException = 1 in { 2580defm FRE : XForm_26r<63, 24, (outs f8rc:$RST), (ins f8rc:$RB), 2581 "fre", "$RST, $RB", IIC_FPGeneral, 2582 [(set f64:$RST, (PPCfre f64:$RB))]>; 2583defm FRES : XForm_26r<59, 24, (outs f4rc:$RST), (ins f4rc:$RB), 2584 "fres", "$RST, $RB", IIC_FPGeneral, 2585 [(set f32:$RST, (PPCfre f32:$RB))]>; 2586defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$RST), (ins f8rc:$RB), 2587 "frsqrte", "$RST, $RB", IIC_FPGeneral, 2588 [(set f64:$RST, (PPCfrsqrte f64:$RB))]>; 2589defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$RST), (ins f4rc:$RB), 2590 "frsqrtes", "$RST, $RB", IIC_FPGeneral, 2591 [(set f32:$RST, (PPCfrsqrte f32:$RB))]>; 2592} 2593} 2594 2595// XL-Form instructions. condition register logical ops. 2596// 2597let hasSideEffects = 0 in 2598def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 2599 "mcrf $BF, $BFA", IIC_BrMCR>, 2600 PPC970_DGroup_First, PPC970_Unit_CRU; 2601 2602// FIXME: According to the ISA (section 2.5.1 of version 2.06), the 2603// condition-register logical instructions have preferred forms. Specifically, 2604// it is preferred that the bit specified by the BT field be in the same 2605// condition register as that specified by the bit BB. We might want to account 2606// for this via hinting the register allocator and anti-dep breakers, or we 2607// could constrain the register class to force this constraint and then loosen 2608// it during register allocation via convertToThreeAddress or some similar 2609// mechanism. 2610 2611let isCommutable = 1 in { 2612def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 2613 (ins crbitrc:$CRA, crbitrc:$CRB), 2614 "crand $CRD, $CRA, $CRB", IIC_BrCR, 2615 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 2616 2617def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 2618 (ins crbitrc:$CRA, crbitrc:$CRB), 2619 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 2620 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 2621 2622def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 2623 (ins crbitrc:$CRA, crbitrc:$CRB), 2624 "cror $CRD, $CRA, $CRB", IIC_BrCR, 2625 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 2626 2627def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 2628 (ins crbitrc:$CRA, crbitrc:$CRB), 2629 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 2630 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 2631 2632def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 2633 (ins crbitrc:$CRA, crbitrc:$CRB), 2634 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 2635 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 2636def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 2637 (ins crbitrc:$CRA, crbitrc:$CRB), 2638 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 2639 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 2640} // isCommutable 2641 2642let isCodeGenOnly = 1 in 2643def CRNOT : XLForm_1s<19, 33, (outs crbitrc:$CRD), (ins crbitrc:$CRA), 2644 "crnot $CRD, $CRA", IIC_BrCR, 2645 [(set i1:$CRD, (not i1:$CRA))]>; 2646 2647def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 2648 (ins crbitrc:$CRA, crbitrc:$CRB), 2649 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 2650 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 2651 2652def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 2653 (ins crbitrc:$CRA, crbitrc:$CRB), 2654 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 2655 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 2656 2657let isCodeGenOnly = 1 in { 2658let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 2659def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$CRD), (ins), 2660 "creqv $CRD, $CRD, $CRD", IIC_BrCR, 2661 [(set i1:$CRD, 1)]>; 2662 2663def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$CRD), (ins), 2664 "crxor $CRD, $CRD, $CRD", IIC_BrCR, 2665 [(set i1:$CRD, 0)]>; 2666} 2667 2668let Defs = [CR1EQ], CRD = 6 in { 2669def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 2670 "creqv 6, 6, 6", IIC_BrCR, 2671 [(PPCcr6set)]>; 2672 2673def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 2674 "crxor 6, 6, 6", IIC_BrCR, 2675 [(PPCcr6unset)]>; 2676} 2677} 2678 2679// XFX-Form instructions. Instructions that deal with SPRs. 2680// 2681 2682def MFSPR : XFXForm_1<31, 339, (outs gprc:$RST), (ins i32imm:$SPR), 2683 "mfspr $RST, $SPR", IIC_SprMFSPR>; 2684def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RST), 2685 "mtspr $SPR, $RST", IIC_SprMTSPR>; 2686 2687def MFTB : XFXForm_1<31, 371, (outs gprc:$RST), (ins i32imm:$SPR), 2688 "mftb $RST, $SPR", IIC_SprMFTB>; 2689 2690def MFPMR : XFXForm_1<31, 334, (outs gprc:$RST), (ins i32imm:$SPR), 2691 "mfpmr $RST, $SPR", IIC_SprMFPMR>; 2692 2693def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RST), 2694 "mtpmr $SPR, $RST", IIC_SprMTPMR>; 2695 2696 2697// A pseudo-instruction used to implement the read of the 64-bit cycle counter 2698// on a 32-bit target. 2699let hasSideEffects = 1 in 2700def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins), 2701 "#ReadTB", []>; 2702 2703let Uses = [CTR] in { 2704def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$RST), (ins), 2705 "mfctr $RST", IIC_SprMFSPR>, 2706 PPC970_DGroup_First, PPC970_Unit_FXU; 2707} 2708let Defs = [CTR], Pattern = [(PPCmtctr i32:$RST)] in { 2709def MTCTR : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST), 2710 "mtctr $RST", IIC_SprMTSPR>, 2711 PPC970_DGroup_First, PPC970_Unit_FXU; 2712} 2713let hasSideEffects = 1, isCodeGenOnly = 1, isNotDuplicable = 1, Defs = [CTR] in { 2714let Pattern = [(int_set_loop_iterations i32:$RST)] in 2715def MTCTRloop : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST), 2716 "mtctr $RST", IIC_SprMTSPR>, 2717 PPC970_DGroup_First, PPC970_Unit_FXU; 2718} 2719 2720let hasSideEffects = 1, hasNoSchedulingInfo = 1, isNotDuplicable = 1, Uses = [CTR], Defs = [CTR] in 2721def DecreaseCTRloop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i32imm:$stride), 2722 "#DecreaseCTRloop", [(set i1:$rT, (int_loop_decrement (i32 imm:$stride)))]>; 2723 2724let hasSideEffects = 0 in { 2725let Defs = [LR] in { 2726def MTLR : XFXForm_1_ext<31, 467, 8, (outs), (ins gprc:$RST), 2727 "mtlr $RST", IIC_SprMTSPR>, 2728 PPC970_DGroup_First, PPC970_Unit_FXU; 2729} 2730let Uses = [LR] in { 2731def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$RST), (ins), 2732 "mflr $RST", IIC_SprMFSPR>, 2733 PPC970_DGroup_First, PPC970_Unit_FXU; 2734} 2735} 2736 2737let hasSideEffects = 1 in { 2738 def MTUDSCR : XFXForm_1_ext<31, 467, 3, (outs), (ins gprc:$RST), 2739 "mtspr 3, $RST", IIC_SprMTSPR>, 2740 PPC970_DGroup_Single, PPC970_Unit_FXU; 2741 def MFUDSCR : XFXForm_1_ext<31, 339, 3, (outs gprc:$RST), (ins), 2742 "mfspr $RST, 3", IIC_SprMFSPR>, 2743 PPC970_DGroup_First, PPC970_Unit_FXU; 2744} 2745 2746// Disable these alias on AIX since they are not supported. 2747let Predicates = [ModernAs] in { 2748// Aliases for moving to/from dscr to mtspr/mfspr 2749def : InstAlias<"mtudscr $Rx", (MTUDSCR gprc:$Rx)>; 2750def : InstAlias<"mfudscr $Rx", (MFUDSCR gprc:$Rx)>; 2751} 2752 2753let isCodeGenOnly = 1 in { 2754 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 2755 // like a GPR on the PPC970. As such, copies in and out have the same 2756 // performance characteristics as an OR instruction. 2757 def MTVRSAVE : XFXForm_1_ext<31, 467, 256, (outs), (ins gprc:$RST), 2758 "mtspr 256, $RST", IIC_IntGeneral>, 2759 PPC970_DGroup_Single, PPC970_Unit_FXU; 2760 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST), (ins), 2761 "mfspr $RST, 256", IIC_IntGeneral>, 2762 PPC970_DGroup_First, PPC970_Unit_FXU; 2763 2764 def MTVRSAVEv : XFXForm_1_ext<31, 467, 256, 2765 (outs VRSAVERC:$SPR), (ins gprc:$RST), 2766 "mtspr 256, $RST", IIC_IntGeneral>, 2767 PPC970_DGroup_Single, PPC970_Unit_FXU; 2768 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST), 2769 (ins VRSAVERC:$SPR), 2770 "mfspr $RST, 256", IIC_IntGeneral>, 2771 PPC970_DGroup_First, PPC970_Unit_FXU; 2772} 2773 2774// Aliases for mtvrsave/mfvrsave to mfspr/mtspr. 2775def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>; 2776def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>; 2777 2778let hasSideEffects = 0 in { 2779// mtocrf's input needs to be prepared by shifting by an amount dependent 2780// on the cr register selected. Thus, post-ra anti-dep breaking must not 2781// later change that register assignment. 2782let hasExtraDefRegAllocReq = 1 in { 2783def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$RST), 2784 "mtocrf $FXM, $RST", IIC_BrMCRX>, 2785 PPC970_DGroup_First, PPC970_Unit_CRU; 2786 2787// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 2788// is dependent on the cr fields being set. 2789def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$RST), 2790 "mtcrf $FXM, $RST", IIC_BrMCRX>, 2791 PPC970_MicroCode, PPC970_Unit_CRU; 2792} // hasExtraDefRegAllocReq = 1 2793 2794// mfocrf's input needs to be prepared by shifting by an amount dependent 2795// on the cr register selected. Thus, post-ra anti-dep breaking must not 2796// later change that register assignment. 2797let hasExtraSrcRegAllocReq = 1 in { 2798def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$RST), (ins crbitm:$FXM), 2799 "mfocrf $RST, $FXM", IIC_SprMFCRF>, 2800 PPC970_DGroup_First, PPC970_Unit_CRU; 2801 2802// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 2803// is dependent on the cr fields being copied. 2804def MFCR : XFXForm_3<31, 19, (outs gprc:$RT), (ins), 2805 "mfcr $RT", IIC_SprMFCR>, 2806 PPC970_MicroCode, PPC970_Unit_CRU; 2807} // hasExtraSrcRegAllocReq = 1 2808 2809def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins), 2810 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>; 2811} // hasSideEffects = 0 2812 2813def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>; 2814 2815let Predicates = [HasFPU] in { 2816// Custom inserter instruction to perform FADD in round-to-zero mode. 2817let Uses = [RM], mayRaiseFPException = 1 in { 2818 def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 2819 [(set f64:$FRT, (PPCany_faddrtz f64:$FRA, f64:$FRB))]>; 2820} 2821 2822// The above pseudo gets expanded to make use of the following instructions 2823// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 2824 2825// When FM is 30/31, we are setting the 62/63 bit of FPSCR, the implicit-def 2826// RM should be set. 2827let hasSideEffects = 1, Defs = [RM] in { 2828def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 2829 "mtfsb0 $FM", IIC_IntMTFSB0, 2830 [(int_ppc_mtfsb0 timm:$FM)]>, 2831 PPC970_DGroup_Single, PPC970_Unit_FPU; 2832def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 2833 "mtfsb1 $FM", IIC_IntMTFSB0, 2834 [(int_ppc_mtfsb1 timm:$FM)]>, 2835 PPC970_DGroup_Single, PPC970_Unit_FPU; 2836} 2837 2838let Defs = [RM], hasSideEffects = 1 in { 2839 let isCodeGenOnly = 1 in 2840 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$RT), 2841 "mtfsf $FM, $RT", IIC_IntMTFSB0, 2842 [(int_ppc_mtfsf timm:$FM, f64:$RT)]>, 2843 PPC970_DGroup_Single, PPC970_Unit_FPU; 2844} 2845let Uses = [RM], hasSideEffects = 1 in { 2846 def MFFS : XForm_42<63, 583, (outs f8rc:$RST), (ins), 2847 "mffs $RST", IIC_IntMFFS, 2848 [(set f64:$RST, (PPCmffs))]>, 2849 PPC970_DGroup_Single, PPC970_Unit_FPU; 2850 2851 let Defs = [CR1] in 2852 def MFFS_rec : XForm_42<63, 583, (outs f8rc:$RST), (ins), 2853 "mffs. $RST", IIC_IntMFFS, []>, isRecordForm; 2854 2855 def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$RST), (ins), 2856 "mffsce $RST", IIC_IntMFFS, []>, 2857 PPC970_DGroup_Single, PPC970_Unit_FPU; 2858 2859 def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$RST), 2860 (ins f8rc:$FRB), "mffscdrn $RST, $FRB", 2861 IIC_IntMFFS, []>, 2862 PPC970_DGroup_Single, PPC970_Unit_FPU; 2863 2864 def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$RST), 2865 (ins u3imm:$DRM), 2866 "mffscdrni $RST, $DRM", 2867 IIC_IntMFFS, []>, 2868 PPC970_DGroup_Single, PPC970_Unit_FPU; 2869 2870 def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$RST), 2871 (ins f8rc:$FRB), "mffscrn $RST, $FRB", 2872 IIC_IntMFFS, []>, 2873 PPC970_DGroup_Single, PPC970_Unit_FPU; 2874 2875 def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$RST), 2876 (ins u2imm:$RM), "mffscrni $RST, $RM", 2877 IIC_IntMFFS, []>, 2878 PPC970_DGroup_Single, PPC970_Unit_FPU; 2879 2880 def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$RST), (ins), 2881 "mffsl $RST", IIC_IntMFFS, []>, 2882 PPC970_DGroup_Single, PPC970_Unit_FPU; 2883} 2884} 2885 2886let Predicates = [IsISA3_0] in { 2887def MODSW : XForm_8<31, 779, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB), 2888 "modsw $RST, $RA, $RB", IIC_IntDivW, 2889 [(set i32:$RST, (srem i32:$RA, i32:$RB))]>; 2890def MODUW : XForm_8<31, 267, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB), 2891 "moduw $RST, $RA, $RB", IIC_IntDivW, 2892 [(set i32:$RST, (urem i32:$RA, i32:$RB))]>; 2893let hasSideEffects = 1 in 2894def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$RT), 2895 (ins gprc:$RA, gprc:$RB, u2imm:$CY), 2896 "addex $RT, $RA, $RB, $CY", IIC_IntGeneral, []>; 2897} 2898 2899let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2900// XO-Form instructions. Arithmetic instructions that can set overflow bit 2901let isCommutable = 1 in 2902defm ADD4 : XOForm_1rx<31, 266, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2903 "add", "$RT, $RA, $RB", IIC_IntSimple, 2904 [(set i32:$RT, (add i32:$RA, i32:$RB))]>; 2905let isCodeGenOnly = 1 in 2906def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$RT), (ins gprc:$RA, tlsreg32:$RB), 2907 "add $RT, $RA, $RB", IIC_IntSimple, 2908 [(set i32:$RT, (add i32:$RA, tglobaltlsaddr:$RB))]>; 2909let isCommutable = 1 in 2910defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2911 "addc", "$RT, $RA, $RB", IIC_IntGeneral, 2912 [(set i32:$RT, (addc i32:$RA, i32:$RB))]>, 2913 PPC970_DGroup_Cracked; 2914 2915defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2916 "divw", "$RT, $RA, $RB", IIC_IntDivW, 2917 [(set i32:$RT, (sdiv i32:$RA, i32:$RB))]>; 2918defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2919 "divwu", "$RT, $RA, $RB", IIC_IntDivW, 2920 [(set i32:$RT, (udiv i32:$RA, i32:$RB))]>; 2921defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2922 "divwe", "$RT, $RA, $RB", IIC_IntDivW, 2923 [(set i32:$RT, (int_ppc_divwe gprc:$RA, gprc:$RB))]>, 2924 Requires<[HasExtDiv]>; 2925defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2926 "divweu", "$RT, $RA, $RB", IIC_IntDivW, 2927 [(set i32:$RT, (int_ppc_divweu gprc:$RA, gprc:$RB))]>, 2928 Requires<[HasExtDiv]>; 2929let isCommutable = 1 in { 2930defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2931 "mulhw", "$RT, $RA, $RB", IIC_IntMulHW, 2932 [(set i32:$RT, (mulhs i32:$RA, i32:$RB))]>; 2933defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2934 "mulhwu", "$RT, $RA, $RB", IIC_IntMulHWU, 2935 [(set i32:$RT, (mulhu i32:$RA, i32:$RB))]>; 2936defm MULLW : XOForm_1rx<31, 235, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2937 "mullw", "$RT, $RA, $RB", IIC_IntMulHW, 2938 [(set i32:$RT, (mul i32:$RA, i32:$RB))]>; 2939} // isCommutable 2940defm SUBF : XOForm_1rx<31, 40, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2941 "subf", "$RT, $RA, $RB", IIC_IntGeneral, 2942 [(set i32:$RT, (sub i32:$RB, i32:$RA))]>; 2943defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2944 "subfc", "$RT, $RA, $RB", IIC_IntGeneral, 2945 [(set i32:$RT, (subc i32:$RB, i32:$RA))]>, 2946 PPC970_DGroup_Cracked; 2947defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$RT), (ins gprc:$RA), 2948 "neg", "$RT, $RA", IIC_IntSimple, 2949 [(set i32:$RT, (ineg i32:$RA))]>; 2950let Uses = [CARRY] in { 2951let isCommutable = 1 in 2952defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2953 "adde", "$RT, $RA, $RB", IIC_IntGeneral, 2954 [(set i32:$RT, (adde i32:$RA, i32:$RB))]>; 2955defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$RT), (ins gprc:$RA), 2956 "addme", "$RT, $RA", IIC_IntGeneral, 2957 [(set i32:$RT, (adde i32:$RA, -1))]>; 2958defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$RT), (ins gprc:$RA), 2959 "addze", "$RT, $RA", IIC_IntGeneral, 2960 [(set i32:$RT, (adde i32:$RA, 0))]>; 2961defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2962 "subfe", "$RT, $RA, $RB", IIC_IntGeneral, 2963 [(set i32:$RT, (sube i32:$RB, i32:$RA))]>; 2964defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$RT), (ins gprc:$RA), 2965 "subfme", "$RT, $RA", IIC_IntGeneral, 2966 [(set i32:$RT, (sube -1, i32:$RA))]>; 2967defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$RT), (ins gprc:$RA), 2968 "subfze", "$RT, $RA", IIC_IntGeneral, 2969 [(set i32:$RT, (sube 0, i32:$RA))]>; 2970} 2971} 2972 2973def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>; 2974def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 2975def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>; 2976def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 2977 2978// A-Form instructions. Most of the instructions executed in the FPU are of 2979// this type. 2980// 2981let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2982let mayRaiseFPException = 1, Uses = [RM] in { 2983let isCommutable = 1 in { 2984 defm FMADD : AForm_1r<63, 29, 2985 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2986 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2987 [(set f64:$FRT, (any_fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 2988 defm FMADDS : AForm_1r<59, 29, 2989 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2990 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2991 [(set f32:$FRT, (any_fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 2992 defm FMSUB : AForm_1r<63, 28, 2993 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2994 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2995 [(set f64:$FRT, 2996 (any_fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 2997 defm FMSUBS : AForm_1r<59, 28, 2998 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2999 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3000 [(set f32:$FRT, 3001 (any_fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 3002 defm FNMADD : AForm_1r<63, 31, 3003 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3004 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3005 [(set f64:$FRT, 3006 (fneg (any_fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 3007 defm FNMADDS : AForm_1r<59, 31, 3008 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3009 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3010 [(set f32:$FRT, 3011 (fneg (any_fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 3012 defm FNMSUB : AForm_1r<63, 30, 3013 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3014 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3015 [(set f64:$FRT, (fneg (any_fma f64:$FRA, f64:$FRC, 3016 (fneg f64:$FRB))))]>; 3017 defm FNMSUBS : AForm_1r<59, 30, 3018 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3019 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3020 [(set f32:$FRT, (fneg (any_fma f32:$FRA, f32:$FRC, 3021 (fneg f32:$FRB))))]>; 3022} // isCommutable 3023} 3024// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 3025// having 4 of these, force the comparison to always be an 8-byte double (code 3026// should use an FMRSD if the input comparison value really wants to be a float) 3027// and 4/8 byte forms for the result and operand type.. 3028let Interpretation64Bit = 1, isCodeGenOnly = 1 in 3029defm FSELD : AForm_1r<63, 23, 3030 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3031 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3032 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 3033defm FSELS : AForm_1r<63, 23, 3034 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3035 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3036 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 3037let Uses = [RM], mayRaiseFPException = 1 in { 3038 let isCommutable = 1 in { 3039 defm FADD : AForm_2r<63, 21, 3040 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3041 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3042 [(set f64:$FRT, (any_fadd f64:$FRA, f64:$FRB))]>; 3043 defm FADDS : AForm_2r<59, 21, 3044 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3045 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3046 [(set f32:$FRT, (any_fadd f32:$FRA, f32:$FRB))]>; 3047 } // isCommutable 3048 defm FDIV : AForm_2r<63, 18, 3049 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3050 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 3051 [(set f64:$FRT, (any_fdiv f64:$FRA, f64:$FRB))]>; 3052 defm FDIVS : AForm_2r<59, 18, 3053 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3054 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 3055 [(set f32:$FRT, (any_fdiv f32:$FRA, f32:$FRB))]>; 3056 let isCommutable = 1 in { 3057 defm FMUL : AForm_3r<63, 25, 3058 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 3059 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 3060 [(set f64:$FRT, (any_fmul f64:$FRA, f64:$FRC))]>; 3061 defm FMULS : AForm_3r<59, 25, 3062 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 3063 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 3064 [(set f32:$FRT, (any_fmul f32:$FRA, f32:$FRC))]>; 3065 } // isCommutable 3066 defm FSUB : AForm_2r<63, 20, 3067 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3068 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3069 [(set f64:$FRT, (any_fsub f64:$FRA, f64:$FRB))]>; 3070 defm FSUBS : AForm_2r<59, 20, 3071 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3072 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3073 [(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>; 3074 } 3075} 3076 3077let hasSideEffects = 0 in { 3078let PPC970_Unit = 1 in { // FXU Operations. 3079 let isSelect = 1 in 3080 def ISEL : AForm_4<31, 15, 3081 (outs gprc:$RT), (ins gprc_nor0:$RA, gprc:$RB, crbitrc:$COND), 3082 "isel $RT, $RA, $RB, $COND", IIC_IntISEL, 3083 []>; 3084} 3085 3086let PPC970_Unit = 1 in { // FXU Operations. 3087// M-Form instructions. rotate and mask instructions. 3088// 3089let isCommutable = 1 in { 3090// RLWIMI can be commuted if the rotate amount is zero. 3091defm RLWIMI : MForm_2r<20, (outs gprc:$RA), 3092 (ins gprc:$RAi, gprc:$RS, u5imm:$SH, u5imm:$MB, 3093 u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME", 3094 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 3095 RegConstraint<"$RAi = $RA">, NoEncode<"$RAi">; 3096} 3097let BaseName = "rlwinm" in { 3098def RLWINM : MForm_2<21, 3099 (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3100 "rlwinm $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral, 3101 []>, RecFormRel; 3102let Defs = [CR0] in 3103def RLWINM_rec : MForm_2<21, 3104 (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3105 "rlwinm. $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral, 3106 []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked; 3107} 3108defm RLWNM : MForm_1r<23, (outs gprc:$RA), 3109 (ins gprc:$RS, gprc:$RB, u5imm:$MB, u5imm:$ME), 3110 "rlwnm", "$RA, $RS, $RB, $MB, $ME", IIC_IntGeneral, 3111 []>; 3112} 3113} // hasSideEffects = 0 3114 3115//===----------------------------------------------------------------------===// 3116// PowerPC Instruction Patterns 3117// 3118 3119// Arbitrary immediate support. Implement in terms of LIS/ORI. 3120def : Pat<(i32 imm:$imm), 3121 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 3122 3123// Implement the 'not' operation with the NOR instruction. 3124def i32not : OutPatFrag<(ops node:$in), 3125 (NOR $in, $in)>; 3126def : Pat<(not i32:$in), 3127 (i32not $in)>; 3128 3129// ADD an arbitrary immediate. 3130def : Pat<(add i32:$in, imm:$imm), 3131 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 3132// OR an arbitrary immediate. 3133def : Pat<(or i32:$in, imm:$imm), 3134 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3135// XOR an arbitrary immediate. 3136def : Pat<(xor i32:$in, imm:$imm), 3137 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3138// SUBFIC 3139def : Pat<(sub imm32SExt16:$imm, i32:$in), 3140 (SUBFIC $in, imm:$imm)>; 3141 3142// SHL/SRL 3143def : Pat<(shl i32:$in, (i32 imm:$imm)), 3144 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 3145def : Pat<(srl i32:$in, (i32 imm:$imm)), 3146 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 3147 3148// ROTL 3149def : Pat<(rotl i32:$in, i32:$sh), 3150 (RLWNM $in, $sh, 0, 31)>; 3151def : Pat<(rotl i32:$in, (i32 imm:$imm)), 3152 (RLWINM $in, imm:$imm, 0, 31)>; 3153 3154// RLWNM 3155def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 3156 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 3157 3158// Calls 3159def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 3160 (BL tglobaladdr:$dst)>; 3161 3162def : Pat<(PPCcall (i32 texternalsym:$dst)), 3163 (BL texternalsym:$dst)>; 3164 3165def : Pat<(PPCcall_rm (i32 tglobaladdr:$dst)), 3166 (BL_RM tglobaladdr:$dst)>; 3167 3168def : Pat<(PPCcall_rm (i32 texternalsym:$dst)), 3169 (BL_RM texternalsym:$dst)>; 3170 3171// Calls for AIX only 3172def : Pat<(PPCcall (i32 mcsym:$dst)), 3173 (BL mcsym:$dst)>; 3174 3175def : Pat<(PPCcall_nop (i32 mcsym:$dst)), 3176 (BL_NOP mcsym:$dst)>; 3177 3178def : Pat<(PPCcall_nop (i32 texternalsym:$dst)), 3179 (BL_NOP texternalsym:$dst)>; 3180 3181def : Pat<(PPCcall_rm (i32 mcsym:$dst)), 3182 (BL_RM mcsym:$dst)>; 3183 3184def : Pat<(PPCcall_nop_rm (i32 mcsym:$dst)), 3185 (BL_NOP_RM mcsym:$dst)>; 3186 3187def : Pat<(PPCcall_nop_rm (i32 texternalsym:$dst)), 3188 (BL_NOP_RM texternalsym:$dst)>; 3189 3190def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 3191 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 3192 3193def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 3194 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 3195 3196def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 3197 (TCRETURNri CTRRC:$dst, imm:$imm)>; 3198 3199def : Pat<(int_ppc_fence), (FENCE)>; 3200def : Pat<(int_ppc_readflm), (MFFS)>; 3201def : Pat<(int_ppc_mffsl), (MFFSL)>; 3202 3203// Hi and Lo for Darwin Global Addresses. 3204def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 3205def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 3206def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 3207def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 3208def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 3209def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 3210def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 3211def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 3212def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 3213 (ADDIS $in, tglobaltlsaddr:$g)>; 3214def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 3215 (ADDI $in, tglobaltlsaddr:$g)>; 3216def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 3217 (ADDIS $in, tglobaladdr:$g)>; 3218def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 3219 (ADDIS $in, tconstpool:$g)>; 3220def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 3221 (ADDIS $in, tjumptable:$g)>; 3222def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 3223 (ADDIS $in, tblockaddress:$g)>; 3224 3225// Support for thread-local storage. 3226def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 3227 [(set i32:$rD, (PPCppc32GOT))]>; 3228 3229// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. 3230// This uses two output registers, the first as the real output, the second as a 3231// temporary register, used internally in code generation. 3232def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", 3233 []>, NoEncode<"$rT">; 3234 3235def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 3236 "#LDgotTprelL32", 3237 [(set i32:$rD, 3238 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 3239def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 3240 (ADD4TLS $in, tglobaltlsaddr:$g)>; 3241 3242def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3243 "#ADDItlsgdL32", 3244 [(set i32:$rD, 3245 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; 3246// LR is a true define, while the rest of the Defs are clobbers. R3 is 3247// explicitly defined when this op is created, so not mentioned here. 3248let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3249 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3250def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3251 "GETtlsADDR32", 3252 [(set i32:$rD, 3253 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>; 3254// R3 is explicitly defined when this op is created, so not mentioned here. 3255// The rest of the Defs are the exact set of registers that will be clobbered by 3256// the call. 3257let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3258 Defs = [R0,R4,R5,R11,LR,CR0] in { 3259def GETtlsADDR32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3260 "GETtlsADDR32AIX", 3261 [(set i32:$rD, 3262 (PPCgetTlsAddr i32:$offset, i32:$handle))]>; 3263def GETtlsMOD32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$handle), 3264 "GETtlsMOD32AIX", 3265 [(set i32:$rD, 3266 (PPCgetTlsMod i32:$handle))]>; 3267} 3268 3269// For local-exec accesses on 32-bit AIX, a call to .__get_tpointer is 3270// generated to retrieve the thread pointer. GETtlsTpointer32AIX clobbers both 3271// R3 and the LR (link register). 3272let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3273 Defs = [R3,LR] in 3274def GETtlsTpointer32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins), 3275 "GETtlsTpointer32AIX", 3276 [(set i32:$rD, (PPCgetTpointer))]>; 3277 3278// The following pattern matches local- and initial-exec TLS accesses on 32-bit AIX. 3279// PPCaddTls is used in local- and initial-exec accesses in order to: 3280// - Get the address of a variable (add the variable offset to the thread 3281// pointer, retrieved by calling .__get_tpointer). 3282// - Create an opportunity to optimize the user of the loaded address. 3283def : Pat<(PPCaddTls i32:$in, i32:$addr), 3284 (ADD4TLS $in, $addr)>; 3285 3286// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR 3287// are true defines while the rest of the Defs are clobbers. 3288let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3289 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3290def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3291 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3292 "#ADDItlsgdLADDR32", 3293 [(set i32:$rD, 3294 (PPCaddiTlsgdLAddr i32:$reg, 3295 tglobaltlsaddr:$disp, 3296 tglobaltlsaddr:$sym))]>; 3297def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3298 "#ADDItlsldL32", 3299 [(set i32:$rD, 3300 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; 3301// This pseudo is expanded to two copies to put the variable offset in R4 and 3302// the region handle in R3 and GETtlsADDR32AIX. 3303def TLSGDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3304 "#TLSGDAIX", 3305 [(set i32:$rD, 3306 (PPCTlsgdAIX i32:$offset, i32:$handle))]>; 3307// This pseudo is expanded to the call to GETtlsMOD32AIX. 3308def TLSLDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$handle), 3309 "#TLSLDAIX", [(set i32:$rD, (PPCTlsldAIX i32:$handle))]>; 3310// LR is a true define, while the rest of the Defs are clobbers. R3 is 3311// explicitly defined when this op is created, so not mentioned here. 3312let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3313 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3314def GETtlsldADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3315 "GETtlsldADDR32", 3316 [(set i32:$rD, 3317 (PPCgetTlsldAddr i32:$reg, 3318 tglobaltlsaddr:$sym))]>; 3319// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR 3320// are true defines while the rest of the Defs are clobbers. 3321let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3322 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3323def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3324 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3325 "#ADDItlsldLADDR32", 3326 [(set i32:$rD, 3327 (PPCaddiTlsldLAddr i32:$reg, 3328 tglobaltlsaddr:$disp, 3329 tglobaltlsaddr:$sym))]>; 3330def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3331 "#ADDIdtprelL32", 3332 [(set i32:$rD, 3333 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; 3334def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3335 "#ADDISdtprelHA32", 3336 [(set i32:$rD, 3337 (PPCaddisDtprelHA i32:$reg, 3338 tglobaltlsaddr:$disp))]>; 3339 3340// Support for Position-independent code 3341def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3342 "#LWZtoc", 3343 [(set i32:$rD, 3344 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3345def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg), 3346 "#LWZtocL", 3347 [(set i32:$rD, 3348 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3349def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), 3350 "#ADDIStocHA", []>; 3351// TOC Data Transform on AIX 3352def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tocentry32:$disp), 3353 "#ADDItoc", []>; 3354def ADDItocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), 3355 "#ADDItocL", []>; 3356 3357// Get Global (GOT) Base Register offset, from the word immediately preceding 3358// the function label. 3359def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; 3360 3361// Pseudo-instruction marked for deletion. When deleting the instruction would 3362// cause iterator invalidation in MIR transformation passes, this pseudo can be 3363// used instead. It will be removed unconditionally at pre-emit time (prior to 3364// branch selection). 3365def UNENCODED_NOP: PPCEmitTimePseudo<(outs), (ins), "#UNENCODED_NOP", []>; 3366 3367// Standard shifts. These are represented separately from the real shifts above 3368// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 3369// amounts. 3370def : Pat<(sra i32:$rS, i32:$rB), 3371 (SRAW $rS, $rB)>; 3372def : Pat<(srl i32:$rS, i32:$rB), 3373 (SRW $rS, $rB)>; 3374def : Pat<(shl i32:$rS, i32:$rB), 3375 (SLW $rS, $rB)>; 3376 3377def : Pat<(i32 (zextloadi1 DForm:$src)), 3378 (LBZ DForm:$src)>; 3379def : Pat<(i32 (zextloadi1 XForm:$src)), 3380 (LBZX XForm:$src)>; 3381def : Pat<(i32 (extloadi1 DForm:$src)), 3382 (LBZ DForm:$src)>; 3383def : Pat<(i32 (extloadi1 XForm:$src)), 3384 (LBZX XForm:$src)>; 3385def : Pat<(i32 (extloadi8 DForm:$src)), 3386 (LBZ DForm:$src)>; 3387def : Pat<(i32 (extloadi8 XForm:$src)), 3388 (LBZX XForm:$src)>; 3389def : Pat<(i32 (extloadi16 DForm:$src)), 3390 (LHZ DForm:$src)>; 3391def : Pat<(i32 (extloadi16 XForm:$src)), 3392 (LHZX XForm:$src)>; 3393let Predicates = [HasFPU] in { 3394def : Pat<(f64 (extloadf32 DForm:$src)), 3395 (COPY_TO_REGCLASS (LFS DForm:$src), F8RC)>; 3396def : Pat<(f64 (extloadf32 XForm:$src)), 3397 (COPY_TO_REGCLASS (LFSX XForm:$src), F8RC)>; 3398 3399def : Pat<(f64 (any_fpextend f32:$src)), 3400 (COPY_TO_REGCLASS $src, F8RC)>; 3401} 3402 3403// Only seq_cst fences require the heavyweight sync (SYNC 0). 3404// All others can use the lightweight sync (SYNC 1). 3405// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html 3406// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits 3407// versions of Power. 3408def : Pat<(atomic_fence (i64 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3409def : Pat<(atomic_fence (i32 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3410def : Pat<(atomic_fence (timm), (timm)), (SYNC 1)>, Requires<[HasSYNC]>; 3411def : Pat<(atomic_fence (timm), (timm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 3412 3413let Predicates = [HasFPU] in { 3414// Additional fnmsub patterns for custom node 3415def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C), 3416 (FNMSUB $A, $B, $C)>; 3417def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C), 3418 (FNMSUBS $A, $B, $C)>; 3419def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)), 3420 (FMSUB $A, $B, $C)>; 3421def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)), 3422 (FMSUBS $A, $B, $C)>; 3423def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)), 3424 (FNMADD $A, $B, $C)>; 3425def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)), 3426 (FNMADDS $A, $B, $C)>; 3427 3428// FCOPYSIGN's operand types need not agree. 3429def : Pat<(fcopysign f64:$frB, f32:$frA), 3430 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 3431def : Pat<(fcopysign f32:$frB, f64:$frA), 3432 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 3433} 3434 3435// XL Compat intrinsics. 3436def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>; 3437def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (FMSUBS $A, $B, $C)>; 3438def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (FNMADD $A, $B, $C)>; 3439def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (FNMADDS $A, $B, $C)>; 3440def : Pat<(int_ppc_fre f64:$A), (FRE $A)>; 3441def : Pat<(int_ppc_fres f32:$A), (FRES $A)>; 3442def : Pat<(int_ppc_fnabs f64:$A), (FNABSD $A)>; 3443def : Pat<(int_ppc_fnabss f32:$A), (FNABSS $A)>; 3444 3445include "PPCInstrAltivec.td" 3446include "PPCInstrSPE.td" 3447include "PPCInstr64Bit.td" 3448include "PPCInstrVSX.td" 3449include "PPCInstrHTM.td" 3450 3451def crnot : OutPatFrag<(ops node:$in), 3452 (CRNOT $in)>; 3453def : Pat<(not i1:$in), 3454 (crnot $in)>; 3455 3456// Pseudo-instructions for alternate assembly syntax (never used by codegen). 3457// These are aliases that require C++ handling to convert to the target 3458// instruction, while InstAliases can be handled directly by tblgen. 3459class PPCAsmPseudo<string asm, dag iops> 3460 : Instruction { 3461 let Namespace = "PPC"; 3462 bit PPC64 = 0; // Default value, override with isPPC64 3463 3464 let OutOperandList = (outs); 3465 let InOperandList = iops; 3466 let Pattern = []; 3467 let AsmString = asm; 3468 let isAsmParserOnly = 1; 3469 let isPseudo = 1; 3470 let hasNoSchedulingInfo = 1; 3471 3472 // Indicate that this instruction takes a register+immediate memory operand. 3473 bits<1> MemriOp = 0; 3474 let TSFlags{10} = MemriOp; 3475} 3476 3477// Prefixed instructions may require access to the above defs at a later 3478// time so we include this after the def. 3479include "PPCInstrP10.td" 3480include "PPCInstrFutureMMA.td" 3481include "PPCInstrFuture.td" 3482include "PPCInstrMMA.td" 3483include "PPCInstrDFP.td" 3484 3485// Patterns for arithmetic i1 operations. 3486def : Pat<(add i1:$a, i1:$b), 3487 (CRXOR $a, $b)>; 3488def : Pat<(sub i1:$a, i1:$b), 3489 (CRXOR $a, $b)>; 3490def : Pat<(mul i1:$a, i1:$b), 3491 (CRAND $a, $b)>; 3492 3493// We're sometimes asked to materialize i1 -1, which is just 1 in this case 3494// (-1 is used to mean all bits set). 3495def : Pat<(i1 -1), (CRSET)>; 3496 3497// i1 extensions, implemented in terms of isel. 3498def : Pat<(i32 (zext i1:$in)), 3499 (SELECT_I4 $in, (LI 1), (LI 0))>; 3500def : Pat<(i32 (sext i1:$in)), 3501 (SELECT_I4 $in, (LI -1), (LI 0))>; 3502 3503def : Pat<(i64 (zext i1:$in)), 3504 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3505def : Pat<(i64 (sext i1:$in)), 3506 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 3507 3508// FIXME: We should choose either a zext or a sext based on other constants 3509// already around. 3510def : Pat<(i32 (anyext i1:$in)), 3511 (SELECT_I4 $in, (LI 1), (LI 0))>; 3512def : Pat<(i64 (anyext i1:$in)), 3513 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3514 3515// match setcc on i1 variables. 3516// CRANDC is: 3517// 1 1 : F 3518// 1 0 : T 3519// 0 1 : F 3520// 0 0 : F 3521// 3522// LT is: 3523// -1 -1 : F 3524// -1 0 : T 3525// 0 -1 : F 3526// 0 0 : F 3527// 3528// ULT is: 3529// 1 1 : F 3530// 1 0 : F 3531// 0 1 : T 3532// 0 0 : F 3533def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 3534 (CRANDC $s1, $s2)>; 3535def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 3536 (CRANDC $s2, $s1)>; 3537// CRORC is: 3538// 1 1 : T 3539// 1 0 : T 3540// 0 1 : F 3541// 0 0 : T 3542// 3543// LE is: 3544// -1 -1 : T 3545// -1 0 : T 3546// 0 -1 : F 3547// 0 0 : T 3548// 3549// ULE is: 3550// 1 1 : T 3551// 1 0 : F 3552// 0 1 : T 3553// 0 0 : T 3554def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 3555 (CRORC $s1, $s2)>; 3556def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 3557 (CRORC $s2, $s1)>; 3558 3559def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 3560 (CREQV $s1, $s2)>; 3561 3562// GE is: 3563// -1 -1 : T 3564// -1 0 : F 3565// 0 -1 : T 3566// 0 0 : T 3567// 3568// UGE is: 3569// 1 1 : T 3570// 1 0 : T 3571// 0 1 : F 3572// 0 0 : T 3573def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 3574 (CRORC $s2, $s1)>; 3575def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 3576 (CRORC $s1, $s2)>; 3577 3578// GT is: 3579// -1 -1 : F 3580// -1 0 : F 3581// 0 -1 : T 3582// 0 0 : F 3583// 3584// UGT is: 3585// 1 1 : F 3586// 1 0 : T 3587// 0 1 : F 3588// 0 0 : F 3589def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3590 (CRANDC $s2, $s1)>; 3591def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 3592 (CRANDC $s1, $s2)>; 3593 3594def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 3595 (CRXOR $s1, $s2)>; 3596 3597// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 3598// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 3599// floating-point types. 3600 3601multiclass CRNotPat<dag pattern, dag result> { 3602 def : Pat<pattern, (crnot result)>; 3603 def : Pat<(not pattern), result>; 3604 3605 // We can also fold the crnot into an extension: 3606 def : Pat<(i32 (zext pattern)), 3607 (SELECT_I4 result, (LI 0), (LI 1))>; 3608 def : Pat<(i32 (sext pattern)), 3609 (SELECT_I4 result, (LI 0), (LI -1))>; 3610 3611 // We can also fold the crnot into an extension: 3612 def : Pat<(i64 (zext pattern)), 3613 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3614 def : Pat<(i64 (sext pattern)), 3615 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 3616 3617 // FIXME: We should choose either a zext or a sext based on other constants 3618 // already around. 3619 def : Pat<(i32 (anyext pattern)), 3620 (SELECT_I4 result, (LI 0), (LI 1))>; 3621 3622 def : Pat<(i64 (anyext pattern)), 3623 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3624} 3625 3626// FIXME: Because of what seems like a bug in TableGen's type-inference code, 3627// we need to write imm:$imm in the output patterns below, not just $imm, or 3628// else the resulting matcher will not correctly add the immediate operand 3629// (making it a register operand instead). 3630 3631// extended SETCC. 3632multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 3633 OutPatFrag rfrag, OutPatFrag rfrag8> { 3634 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 3635 (rfrag $s1)>; 3636 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 3637 (rfrag8 $s1)>; 3638 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 3639 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3640 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 3641 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3642 3643 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 3644 (rfrag $s1)>; 3645 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 3646 (rfrag8 $s1)>; 3647 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 3648 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3649 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 3650 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3651} 3652 3653// Note that we do all inversions below with i(32|64)not, instead of using 3654// (xori x, 1) because on the A2 nor has single-cycle latency while xori 3655// has 2-cycle latency. 3656 3657defm : ExtSetCCPat<SETEQ, 3658 PatFrag<(ops node:$in, node:$cc), 3659 (setcc $in, 0, $cc)>, 3660 OutPatFrag<(ops node:$in), 3661 (RLWINM (CNTLZW $in), 27, 31, 31)>, 3662 OutPatFrag<(ops node:$in), 3663 (RLDICL (CNTLZD $in), 58, 63)> >; 3664 3665defm : ExtSetCCPat<SETNE, 3666 PatFrag<(ops node:$in, node:$cc), 3667 (setcc $in, 0, $cc)>, 3668 OutPatFrag<(ops node:$in), 3669 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 3670 OutPatFrag<(ops node:$in), 3671 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 3672 3673defm : ExtSetCCPat<SETLT, 3674 PatFrag<(ops node:$in, node:$cc), 3675 (setcc $in, 0, $cc)>, 3676 OutPatFrag<(ops node:$in), 3677 (RLWINM $in, 1, 31, 31)>, 3678 OutPatFrag<(ops node:$in), 3679 (RLDICL $in, 1, 63)> >; 3680 3681defm : ExtSetCCPat<SETGE, 3682 PatFrag<(ops node:$in, node:$cc), 3683 (setcc $in, 0, $cc)>, 3684 OutPatFrag<(ops node:$in), 3685 (RLWINM (i32not $in), 1, 31, 31)>, 3686 OutPatFrag<(ops node:$in), 3687 (RLDICL (i64not $in), 1, 63)> >; 3688 3689defm : ExtSetCCPat<SETGT, 3690 PatFrag<(ops node:$in, node:$cc), 3691 (setcc $in, 0, $cc)>, 3692 OutPatFrag<(ops node:$in), 3693 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 3694 OutPatFrag<(ops node:$in), 3695 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 3696 3697defm : ExtSetCCPat<SETLE, 3698 PatFrag<(ops node:$in, node:$cc), 3699 (setcc $in, 0, $cc)>, 3700 OutPatFrag<(ops node:$in), 3701 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 3702 OutPatFrag<(ops node:$in), 3703 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 3704 3705defm : ExtSetCCPat<SETLT, 3706 PatFrag<(ops node:$in, node:$cc), 3707 (setcc $in, -1, $cc)>, 3708 OutPatFrag<(ops node:$in), 3709 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 3710 OutPatFrag<(ops node:$in), 3711 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3712 3713defm : ExtSetCCPat<SETGE, 3714 PatFrag<(ops node:$in, node:$cc), 3715 (setcc $in, -1, $cc)>, 3716 OutPatFrag<(ops node:$in), 3717 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 3718 OutPatFrag<(ops node:$in), 3719 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3720 3721defm : ExtSetCCPat<SETGT, 3722 PatFrag<(ops node:$in, node:$cc), 3723 (setcc $in, -1, $cc)>, 3724 OutPatFrag<(ops node:$in), 3725 (RLWINM (i32not $in), 1, 31, 31)>, 3726 OutPatFrag<(ops node:$in), 3727 (RLDICL (i64not $in), 1, 63)> >; 3728 3729defm : ExtSetCCPat<SETLE, 3730 PatFrag<(ops node:$in, node:$cc), 3731 (setcc $in, -1, $cc)>, 3732 OutPatFrag<(ops node:$in), 3733 (RLWINM $in, 1, 31, 31)>, 3734 OutPatFrag<(ops node:$in), 3735 (RLDICL $in, 1, 63)> >; 3736 3737// An extended SETCC with shift amount. 3738multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag, 3739 OutPatFrag rfrag, OutPatFrag rfrag8> { 3740 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3741 (rfrag $s1, $sa)>; 3742 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3743 (rfrag8 $s1, $sa)>; 3744 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3745 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3746 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3747 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3748 3749 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3750 (rfrag $s1, $sa)>; 3751 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3752 (rfrag8 $s1, $sa)>; 3753 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3754 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3755 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3756 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3757} 3758 3759defm : ExtSetCCShiftPat<SETNE, 3760 PatFrag<(ops node:$in, node:$sa, node:$cc), 3761 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3762 OutPatFrag<(ops node:$in, node:$sa), 3763 (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>, 3764 OutPatFrag<(ops node:$in, node:$sa), 3765 (RLDCL $in, (SUBFIC $sa, 64), 63)> >; 3766 3767defm : ExtSetCCShiftPat<SETEQ, 3768 PatFrag<(ops node:$in, node:$sa, node:$cc), 3769 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3770 OutPatFrag<(ops node:$in, node:$sa), 3771 (RLWNM (i32not $in), 3772 (SUBFIC $sa, 32), 31, 31)>, 3773 OutPatFrag<(ops node:$in, node:$sa), 3774 (RLDCL (i64not $in), 3775 (SUBFIC $sa, 64), 63)> >; 3776 3777// SETCC for i32. 3778def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 3779 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3780def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 3781 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3782def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 3783 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3784def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 3785 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3786def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 3787 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3788def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 3789 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3790 3791// For non-equality comparisons, the default code would materialize the 3792// constant, then compare against it, like this: 3793// lis r2, 4660 3794// ori r2, r2, 22136 3795// cmpw cr0, r3, r2 3796// beq cr0,L6 3797// Since we are just comparing for equality, we can emit this instead: 3798// xoris r0,r3,0x1234 3799// cmplwi cr0,r0,0x5678 3800// beq cr0,L6 3801 3802def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 3803 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3804 (LO16 imm:$imm)), sub_eq)>; 3805 3806def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 3807 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3808def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 3809 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3810def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 3811 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3812def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 3813 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3814def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 3815 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3816 3817// SETCC for i64. 3818def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 3819 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3820def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 3821 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3822def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 3823 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3824def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 3825 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3826def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 3827 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3828def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 3829 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3830 3831// For non-equality comparisons, the default code would materialize the 3832// constant, then compare against it, like this: 3833// lis r2, 4660 3834// ori r2, r2, 22136 3835// cmpd cr0, r3, r2 3836// beq cr0,L6 3837// Since we are just comparing for equality, we can emit this instead: 3838// xoris r0,r3,0x1234 3839// cmpldi cr0,r0,0x5678 3840// beq cr0,L6 3841 3842def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 3843 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3844 (LO16 imm:$imm)), sub_eq)>; 3845 3846def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 3847 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3848def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 3849 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3850def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 3851 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3852def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 3853 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3854def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 3855 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3856 3857let Predicates = [IsNotISA3_1] in { 3858// Instantiations of CRNotPat for i32. 3859defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 3860 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3861defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 3862 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3863defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 3864 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3865defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 3866 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3867defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 3868 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3869defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 3870 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3871 3872defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 3873 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3874 (LO16 imm:$imm)), sub_eq)>; 3875 3876defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 3877 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3878defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 3879 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3880defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 3881 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3882defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 3883 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3884defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 3885 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3886 3887// Instantiations of CRNotPat for i64. 3888defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 3889 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3890defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 3891 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3892defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 3893 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3894defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 3895 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3896defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 3897 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3898defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 3899 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3900 3901defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 3902 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3903 (LO16 imm:$imm)), sub_eq)>; 3904 3905defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 3906 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3907defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 3908 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3909defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 3910 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3911defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 3912 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3913defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 3914 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3915} 3916 3917multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> { 3918 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 3919 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3920 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 3921 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3922 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 3923 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3924 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 3925 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3926 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)), 3927 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3928 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 3929 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3930 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)), 3931 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 3932 3933 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)), 3934 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3935 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)), 3936 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3937 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)), 3938 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3939 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)), 3940 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3941 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)), 3942 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3943 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)), 3944 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3945 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUO)), 3946 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 3947} 3948 3949let Predicates = [HasFPU] in { 3950// FCMPU: If either of the operands is a Signaling NaN, then VXSNAN is set. 3951// SETCC for f32. 3952defm : FSetCCPat<any_fsetcc, f32, FCMPUS>; 3953 3954// SETCC for f64. 3955defm : FSetCCPat<any_fsetcc, f64, FCMPUD>; 3956 3957// SETCC for f128. 3958defm : FSetCCPat<any_fsetcc, f128, XSCMPUQP>; 3959 3960// FCMPO: If either of the operands is a Signaling NaN, then VXSNAN is set and, 3961// if neither operand is a Signaling NaN but at least one operand is a Quiet NaN, 3962// then VXVC is set. 3963// SETCCS for f32. 3964defm : FSetCCPat<strict_fsetccs, f32, FCMPOS>; 3965 3966// SETCCS for f64. 3967defm : FSetCCPat<strict_fsetccs, f64, FCMPOD>; 3968 3969// SETCCS for f128. 3970defm : FSetCCPat<strict_fsetccs, f128, XSCMPOQP>; 3971} 3972 3973// This must be in this file because it relies on patterns defined in this file 3974// after the inclusion of the instruction sets. 3975let Predicates = [HasSPE] in { 3976// SETCC for f32. 3977def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOLT)), 3978 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3979def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)), 3980 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3981def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOGT)), 3982 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3983def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGT)), 3984 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3985def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOEQ)), 3986 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3987def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETEQ)), 3988 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3989 3990defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUGE)), 3991 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3992defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGE)), 3993 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3994defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETULE)), 3995 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3996defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLE)), 3997 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3998defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUNE)), 3999 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4000defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETNE)), 4001 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4002 4003// SETCC for f64. 4004def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOLT)), 4005 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4006def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)), 4007 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4008def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOGT)), 4009 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4010def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGT)), 4011 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4012def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOEQ)), 4013 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4014def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETEQ)), 4015 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4016 4017defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUGE)), 4018 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4019defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGE)), 4020 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4021defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETULE)), 4022 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4023defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLE)), 4024 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4025defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUNE)), 4026 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4027defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETNE)), 4028 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4029} 4030// match select on i1 variables: 4031def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 4032 (CROR (CRAND $cond , $tval), 4033 (CRAND (crnot $cond), $fval))>; 4034 4035// match selectcc on i1 variables: 4036// select (lhs == rhs), tval, fval is: 4037// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 4038def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 4039 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4040 (CRAND (CRORC $rhs, $lhs), $fval))>; 4041def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)), 4042 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4043 (CRAND (CRORC $lhs, $rhs), $fval))>; 4044def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 4045 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4046 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4047def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)), 4048 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4049 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4050def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 4051 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 4052 (CRAND (CRXOR $lhs, $rhs), $fval))>; 4053def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 4054 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4055 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4056def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)), 4057 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4058 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4059def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 4060 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4061 (CRAND (CRORC $lhs, $rhs), $fval))>; 4062def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)), 4063 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4064 (CRAND (CRORC $rhs, $lhs), $fval))>; 4065def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 4066 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 4067 (CRAND (CRXOR $lhs, $rhs), $tval))>; 4068 4069// match selectcc on i1 variables with non-i1 output. 4070def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 4071 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4072def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)), 4073 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4074def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 4075 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4076def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)), 4077 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4078def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 4079 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 4080def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 4081 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4082def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)), 4083 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4084def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 4085 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4086def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)), 4087 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4088def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 4089 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4090 4091def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 4092 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4093def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)), 4094 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4095def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 4096 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4097def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)), 4098 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4099def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 4100 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 4101def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 4102 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4103def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)), 4104 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4105def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 4106 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4107def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), 4108 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4109def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 4110 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4111 4112let Predicates = [HasFPU] in { 4113def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 4114 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4115def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 4116 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4117def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 4118 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4119def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 4120 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4121def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 4122 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 4123def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 4124 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4125def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 4126 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4127def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 4128 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4129def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 4130 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4131def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 4132 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4133 4134def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 4135 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4136def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 4137 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4138def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 4139 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4140def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 4141 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4142def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 4143 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 4144def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 4145 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4146def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 4147 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4148def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 4149 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4150def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 4151 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4152def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 4153 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4154} 4155 4156def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)), 4157 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4158def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)), 4159 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4160def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)), 4161 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4162def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)), 4163 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4164def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)), 4165 (SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>; 4166def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)), 4167 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4168def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)), 4169 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4170def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)), 4171 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4172def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)), 4173 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4174def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)), 4175 (SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>; 4176 4177def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 4178 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4179def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)), 4180 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4181def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 4182 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4183def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)), 4184 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4185def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 4186 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 4187def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 4188 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4189def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)), 4190 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4191def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 4192 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4193def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)), 4194 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4195def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 4196 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 4197 4198let Defs = [CR0] in { 4199def ANDI_rec_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4200 "#ANDI_rec_1_EQ_BIT", 4201 [(set i1:$dst, (trunc (not i32:$in)))]>; 4202def ANDI_rec_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4203 "#ANDI_rec_1_GT_BIT", 4204 [(set i1:$dst, (trunc i32:$in))]>; 4205 4206def ANDI_rec_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4207 "#ANDI_rec_1_EQ_BIT8", 4208 [(set i1:$dst, (trunc (not i64:$in)))]>; 4209def ANDI_rec_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4210 "#ANDI_rec_1_GT_BIT8", 4211 [(set i1:$dst, (trunc i64:$in))]>; 4212} 4213 4214def : Pat<(i1 (not (trunc i32:$in))), 4215 (ANDI_rec_1_EQ_BIT $in)>; 4216def : Pat<(i1 (not (trunc i64:$in))), 4217 (ANDI_rec_1_EQ_BIT8 $in)>; 4218 4219def : Pat<(int_ppc_fsel f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (FSELD $FRA, $FRC, $FRB)>; 4220def : Pat<(int_ppc_frsqrte f8rc:$frB), (FRSQRTE $frB)>; 4221def : Pat<(int_ppc_frsqrtes f4rc:$frB), (FRSQRTES $frB)>; 4222 4223//===----------------------------------------------------------------------===// 4224// PowerPC Instructions used for assembler/disassembler only 4225// 4226 4227// FIXME: For B=0 or B > 8, the registers following RT are used. 4228// WARNING: Do not add patterns for this instruction without fixing this. 4229def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RST), 4230 (ins gprc:$RA, u5imm:$RB), 4231 "lswi $RST, $RA, $RB", IIC_LdStLoad, []>; 4232 4233// FIXME: For B=0 or B > 8, the registers following RT are used. 4234// WARNING: Do not add patterns for this instruction without fixing this. 4235def STSWI : XForm_base_r3xo_memOp<31, 725, (outs), 4236 (ins gprc:$RST, gprc:$RA, u5imm:$RB), 4237 "stswi $RST, $RA, $RB", IIC_LdStLoad, []>; 4238 4239def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 4240 "isync", IIC_SprISYNC, []>; 4241 4242def ICBI : XForm_1a<31, 982, (outs), (ins (memrr $RA, $RB):$addr), 4243 "icbi $addr", IIC_LdStICBI, []>; 4244 4245def WAIT : XForm_24_sync<31, 30, (outs), (ins u2imm:$L), 4246 "wait $L", IIC_LdStLoad, []>; 4247 4248def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO), 4249 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>; 4250 4251def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), 4252 "mtsr $SR, $RS", IIC_SprMTSR>; 4253 4254def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR), 4255 "mfsr $RS, $SR", IIC_SprMFSR>; 4256 4257def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB), 4258 "mtsrin $RS, $RB", IIC_SprMTSR>; 4259 4260def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB), 4261 "mfsrin $RS, $RB", IIC_SprMFSR>; 4262 4263def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, u1imm:$L), 4264 "mtmsr $RS, $L", IIC_SprMTMSR>; 4265 4266def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS), 4267 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> { 4268 let L = 0; 4269} 4270 4271def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>, 4272 Requires<[IsBookE]> { 4273 bits<1> E; 4274 4275 let Inst{16} = E; 4276 let Inst{21-30} = 163; 4277} 4278 4279def DCCCI : XForm_tlb<454, (outs), (ins gprc:$RA, gprc:$RB), 4280 "dccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4281def ICCCI : XForm_tlb<966, (outs), (ins gprc:$RA, gprc:$RB), 4282 "iccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4283 4284def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4285def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4286def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4287def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4288 4289def MFMSR : XForm_rs<31, 83, (outs gprc:$RST), (ins), 4290 "mfmsr $RST", IIC_SprMFMSR, []>; 4291 4292def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L), 4293 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 4294 4295def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA), 4296 "mcrfs $BF, $BFA", IIC_BrMCR>; 4297 4298// All MTFSF variants may change the rounding mode so conservatively set it 4299// as an implicit def for all of them. 4300let Predicates = [HasFPU] in { 4301let Defs = [RM], hasSideEffects = 1 in { 4302let isCodeGenOnly = 1, 4303 Pattern = [(int_ppc_mtfsfi timm:$BF, timm:$U)], W = 0 in 4304def MTFSFIb : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U), 4305 "mtfsfi $BF, $U", IIC_IntMFFS>; 4306def MTFSFI : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, i32imm:$W), 4307 "mtfsfi $BF, $U, $W", IIC_IntMFFS>; 4308let Defs = [CR1] in 4309def MTFSFI_rec : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, u1imm:$W), 4310 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm; 4311 4312def MTFSF : XFLForm_1<63, 711, (outs), 4313 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4314 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>; 4315let Defs = [CR1] in 4316def MTFSF_rec : XFLForm_1<63, 711, (outs), 4317 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4318 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm; 4319} 4320 4321def : InstAlias<"mtfsfi $BF, $U", (MTFSFI u3imm:$BF, u4imm:$U, 0)>; 4322def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec u3imm:$BF, u4imm:$U, 0)>; 4323def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4324def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4325} 4326 4327def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 4328 "slbie $RB", IIC_SprSLBIE, []>; 4329 4330def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RST, gprc:$RB), 4331 "slbmte $RST, $RB", IIC_SprSLBMTE, []>; 4332 4333def SLBMFEE : XForm_26<31, 915, (outs gprc:$RST), (ins gprc:$RB), 4334 "slbmfee $RST, $RB", IIC_SprSLBMFEE, []>; 4335 4336def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB), 4337 "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>; 4338 4339def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 4340 4341let Defs = [CR0] in 4342def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RST), (ins gprc:$RB), 4343 "slbfee. $RST, $RB", IIC_SprSLBFEE, []>, isRecordForm; 4344 4345def TLBIA : XForm_0<31, 370, (outs), (ins), 4346 "tlbia", IIC_SprTLBIA, []>; 4347 4348def TLBSYNC : XForm_0<31, 566, (outs), (ins), 4349 "tlbsync", IIC_SprTLBSYNC, []>; 4350 4351def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 4352 "tlbiel $RB", IIC_SprTLBIEL, []>; 4353 4354def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB), 4355 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4356def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), 4357 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4358 4359def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RST, gprc:$RB), 4360 "tlbie $RB,$RST", IIC_SprTLBIE, []>; 4361 4362def TLBSX : XForm_tlb<914, (outs), (ins gprc:$RA, gprc:$RB), "tlbsx $RA, $RB", 4363 IIC_LdStLoad>, Requires<[IsBookE]>; 4364 4365def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$RA, gprc:$RB), "tlbivax $RA, $RB", 4366 IIC_LdStLoad>, Requires<[IsBookE]>; 4367 4368def TLBILX : XForm_tlbilx<18, (outs), (ins u2imm:$T, gprc:$RA, gprc:$RB), 4369 "tlbilx $T, $RA, $RB", IIC_LdStLoad>, Requires<[IsBookE]>; 4370 4371def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), 4372 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4373 4374def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), 4375 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4376 4377def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RST), (ins gprc:$RA, i1imm:$WS), 4378 "tlbre $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4379 4380def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RST, gprc:$RA, i1imm:$WS), 4381 "tlbwe $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4382 4383def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$RA, gprc:$RB), 4384 "tlbsx $RST, $RA, $RB", IIC_LdStLoad, []>, 4385 Requires<[IsPPC4xx]>; 4386def TLBSX2D : XForm_base_r3xo<31, 914, (outs), 4387 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4388 "tlbsx. $RST, $RA, $RB", IIC_LdStLoad, []>, 4389 Requires<[IsPPC4xx]>, isRecordForm; 4390 4391def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; 4392 4393def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>, 4394 Requires<[IsBookE]>; 4395def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>, 4396 Requires<[IsBookE]>; 4397 4398def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>, 4399 Requires<[IsE500]>; 4400def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, 4401 Requires<[IsE500]>; 4402 4403def MFDCR : XFXForm_1<31, 323, (outs gprc:$RST), (ins i32imm:$SPR), 4404 "mfdcr $RST, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; 4405def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RST, i32imm:$SPR), 4406 "mtdcr $SPR, $RST", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; 4407 4408def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>; 4409def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>; 4410 4411def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; 4412 4413def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST), 4414 (ins gprc:$RA, gprc:$RB), 4415 "lbzcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4416def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST), 4417 (ins gprc:$RA, gprc:$RB), 4418 "lhzcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4419def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST), 4420 (ins gprc:$RA, gprc:$RB), 4421 "lwzcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4422def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST), 4423 (ins gprc:$RA, gprc:$RB), 4424 "ldcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4425 4426def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs), 4427 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4428 "stbcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4429def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs), 4430 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4431 "sthcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4432def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs), 4433 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4434 "stwcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4435def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs), 4436 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4437 "stdcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4438 4439// External PID Load Store Instructions 4440 4441def LBEPX : XForm_1<31, 95, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 4442 "lbepx $RST, $addr", IIC_LdStLoad, []>, 4443 Requires<[IsE500]>; 4444 4445def LFDEPX : XForm_25<31, 607, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 4446 "lfdepx $RST, $addr", IIC_LdStLFD, []>, 4447 Requires<[IsE500]>; 4448 4449def LHEPX : XForm_1<31, 287, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 4450 "lhepx $RST, $addr", IIC_LdStLoad, []>, 4451 Requires<[IsE500]>; 4452 4453def LWEPX : XForm_1<31, 31, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 4454 "lwepx $RST, $addr", IIC_LdStLoad, []>, 4455 Requires<[IsE500]>; 4456 4457def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 4458 "stbepx $RST, $addr", IIC_LdStStore, []>, 4459 Requires<[IsE500]>; 4460 4461def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), 4462 "stfdepx $RST, $addr", IIC_LdStSTFD, []>, 4463 Requires<[IsE500]>; 4464 4465def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 4466 "sthepx $RST, $addr", IIC_LdStStore, []>, 4467 Requires<[IsE500]>; 4468 4469def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 4470 "stwepx $RST, $addr", IIC_LdStStore, []>, 4471 Requires<[IsE500]>; 4472 4473def DCBFEP : DCB_Form<127, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbfep $addr", 4474 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4475 4476def DCBSTEP : DCB_Form<63, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbstep $addr", 4477 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4478 4479def DCBTEP : DCB_Form_hint<319, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH), 4480 "dcbtep $TH, $addr", IIC_LdStDCBF, []>, 4481 Requires<[IsE500]>; 4482 4483def DCBTSTEP : DCB_Form_hint<255, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH), 4484 "dcbtstep $TH, $addr", IIC_LdStDCBF, []>, 4485 Requires<[IsE500]>; 4486 4487def DCBZEP : DCB_Form<1023, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbzep $addr", 4488 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4489 4490def DCBZLEP : DCB_Form<1023, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzlep $addr", 4491 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4492 4493def ICBIEP : XForm_1a<31, 991, (outs), (ins (memrr $RA, $RB):$addr), "icbiep $addr", 4494 IIC_LdStICBI, []>, Requires<[IsE500]>; 4495 4496//===----------------------------------------------------------------------===// 4497// PowerPC Assembler Instruction Aliases 4498// 4499 4500def : InstAlias<"sc", (SC 0)>; 4501 4502def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>; 4503def : InstAlias<"hwsync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4504def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4505def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>; 4506def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>; 4507 4508def : InstAlias<"wait", (WAIT 0)>; 4509def : InstAlias<"waitrsv", (WAIT 1)>; 4510def : InstAlias<"waitimpl", (WAIT 2)>; 4511 4512def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>; 4513 4514def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>; 4515def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>; 4516 4517def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4518def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4519def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>; 4520 4521def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4522def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4523def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>; 4524 4525def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>; 4526def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>; 4527def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>; 4528 4529def : Pat<(int_ppc_isync), (ISYNC)>; 4530def : Pat<(int_ppc_dcbfl xoaddr:$dst), 4531 (DCBF 1, xoaddr:$dst)>; 4532def : Pat<(int_ppc_dcbflp xoaddr:$dst), 4533 (DCBF 3, xoaddr:$dst)>; 4534 4535let Predicates = [IsISA3_1] in { 4536 def DCBFPS : PPCAsmPseudo<"dcbfps $dst", (ins memrr:$dst)>; 4537 def DCBSTPS : PPCAsmPseudo<"dcbstps $dst", (ins memrr:$dst)>; 4538 4539 def : Pat<(int_ppc_dcbfps xoaddr:$dst), 4540 (DCBF 4, xoaddr:$dst)>; 4541 def : Pat<(int_ppc_dcbstps xoaddr:$dst), 4542 (DCBF 6, xoaddr:$dst)>; 4543} 4544 4545def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4546def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4547def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4548def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4549 4550def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 4551def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>; 4552def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 4553 4554def : InstAlias<"xnop", (XORI R0, R0, 0)>; 4555 4556def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 4557def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 4558 4559//Disable this alias on AIX for now because as does not support them. 4560let Predicates = [ModernAs] in { 4561 4562foreach BR = 0-7 in { 4563 def : InstAlias<"mfbr"#BR#" $Rx", 4564 (MFDCR gprc:$Rx, !add(BR, 0x80))>, 4565 Requires<[IsPPC4xx]>; 4566 def : InstAlias<"mtbr"#BR#" $Rx", 4567 (MTDCR gprc:$Rx, !add(BR, 0x80))>, 4568 Requires<[IsPPC4xx]>; 4569} 4570 4571def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 4572def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 4573def : InstAlias<"mtudscr $Rx", (MTSPR 3, gprc:$Rx)>; 4574def : InstAlias<"mfudscr $Rx", (MFSPR gprc:$Rx, 3)>; 4575 4576def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>; 4577def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>; 4578 4579def : InstAlias<"mtlr $Rx", (MTSPR 8, gprc:$Rx)>; 4580def : InstAlias<"mflr $Rx", (MFSPR gprc:$Rx, 8)>; 4581 4582def : InstAlias<"mtctr $Rx", (MTSPR 9, gprc:$Rx)>; 4583def : InstAlias<"mfctr $Rx", (MFSPR gprc:$Rx, 9)>; 4584 4585def : InstAlias<"mtuamr $Rx", (MTSPR 13, gprc:$Rx)>; 4586def : InstAlias<"mfuamr $Rx", (MFSPR gprc:$Rx, 13)>; 4587 4588def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>; 4589def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>; 4590 4591def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>; 4592def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>; 4593 4594def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>; 4595def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>; 4596 4597def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>; 4598def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>; 4599 4600def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>; 4601def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>; 4602 4603def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>; 4604def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>; 4605 4606def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>; 4607def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>; 4608 4609def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>; 4610def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>; 4611 4612def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>; 4613def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>; 4614 4615def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>; 4616def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>; 4617 4618foreach SPRG = 4-7 in { 4619 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>, 4620 Requires<[IsBookE]>; 4621 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>, 4622 Requires<[IsBookE]>; 4623 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4624 Requires<[IsBookE]>; 4625 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4626 Requires<[IsBookE]>; 4627} 4628 4629foreach SPRG = 0-3 in { 4630 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>; 4631 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>; 4632 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4633 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4634} 4635 4636def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>; 4637def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>; 4638 4639def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>; 4640def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>; 4641 4642def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 4643 4644def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>; 4645def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>; 4646 4647foreach BATR = 0-3 in { 4648 def : InstAlias<"mtdbatu "#BATR#", $Rx", 4649 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>, 4650 Requires<[IsPPC6xx]>; 4651 def : InstAlias<"mfdbatu $Rx, "#BATR, 4652 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>, 4653 Requires<[IsPPC6xx]>; 4654 def : InstAlias<"mtdbatl "#BATR#", $Rx", 4655 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>, 4656 Requires<[IsPPC6xx]>; 4657 def : InstAlias<"mfdbatl $Rx, "#BATR, 4658 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>, 4659 Requires<[IsPPC6xx]>; 4660 def : InstAlias<"mtibatu "#BATR#", $Rx", 4661 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>, 4662 Requires<[IsPPC6xx]>; 4663 def : InstAlias<"mfibatu $Rx, "#BATR, 4664 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>, 4665 Requires<[IsPPC6xx]>; 4666 def : InstAlias<"mtibatl "#BATR#", $Rx", 4667 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>, 4668 Requires<[IsPPC6xx]>; 4669 def : InstAlias<"mfibatl $Rx, "#BATR, 4670 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>, 4671 Requires<[IsPPC6xx]>; 4672} 4673 4674def : InstAlias<"mtppr $RT", (MTSPR 896, gprc:$RT)>; 4675def : InstAlias<"mfppr $RT", (MFSPR gprc:$RT, 896)>; 4676 4677def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4678def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>; 4679 4680def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4681def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>; 4682 4683def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4684def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>; 4685 4686def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>; 4687def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4688 4689def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>; 4690def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4691 4692def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4693def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>; 4694 4695def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4696def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>; 4697 4698def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4699def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>; 4700 4701def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4702def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>; 4703 4704} 4705 4706def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 4707 4708def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>, 4709 Requires<[IsPPC4xx]>; 4710def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>, 4711 Requires<[IsPPC4xx]>; 4712def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>, 4713 Requires<[IsPPC4xx]>; 4714def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>, 4715 Requires<[IsPPC4xx]>; 4716 4717def : InstAlias<"tlbilxlpid", (TLBILX 0, R0, R0)>, Requires<[IsBookE]>; 4718def : InstAlias<"tlbilxpid", (TLBILX 1, R0, R0)>, Requires<[IsBookE]>; 4719def : InstAlias<"tlbilxva $RA, $RB", (TLBILX 3, gprc:$RA, gprc:$RB)>, 4720 Requires<[IsBookE]>; 4721def : InstAlias<"tlbilxva $RB", (TLBILX 3, R0, gprc:$RB)>, Requires<[IsBookE]>; 4722 4723def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>, MemriOp; 4724 4725def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 4726 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4727def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 4728 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4729def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 4730 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4731def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm", 4732 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4733 4734def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 4735 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>, 4736 ZExt32To64; 4737def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 4738 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>, 4739 ZExt32To64; 4740def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 4741 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4742def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 4743 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4744def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 4745 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4746def INSLWI_rec : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 4747 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4748def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 4749 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4750def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 4751 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4752def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 4753 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4754def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 4755 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4756def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 4757 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4758def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n", 4759 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4760def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 4761 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4762def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n", 4763 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4764def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 4765 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4766def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 4767 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4768def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 4769 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4770def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 4771 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4772 4773def : InstAlias<"isellt $rT, $rA, $rB", 4774 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT)>; 4775def : InstAlias<"iselgt $rT, $rA, $rB", 4776 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT)>; 4777def : InstAlias<"iseleq $rT, $rA, $rB", 4778 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ)>; 4779 4780def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4781def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4782def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4783def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4784def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4785def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4786 4787def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>; 4788def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW_rec gprc:$rA, gprc:$rS)>; 4789// The POWER variant 4790def : MnemonicAlias<"cntlz", "cntlzw">; 4791def : MnemonicAlias<"cntlz.", "cntlzw.">; 4792 4793def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 4794 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4795def EXTLDI_rec : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 4796 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4797def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 4798 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4799def EXTRDI_rec : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 4800 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4801def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 4802 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4803def INSRDI_rec : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 4804 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4805def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 4806 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4807def ROTRDI_rec : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 4808 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4809def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 4810 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4811def SLDI_rec : PPCAsmPseudo<"sldi. $rA, $rS, $n", 4812 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4813def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 4814 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4815def SRDI_rec : PPCAsmPseudo<"srdi. $rA, $rS, $n", 4816 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4817def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 4818 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4819def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 4820 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4821def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 4822 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4823def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 4824 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4825def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>; 4826 4827def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4828def : InstAlias<"rotldi $rA, $rS, $n", 4829 (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0)>; 4830def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4831def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4832def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4833def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4834def : InstAlias<"clrldi $rA, $rS, $n", 4835 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>; 4836def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4837def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>; 4838 4839def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b", 4840 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4841def RLWINMbm_rec : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b", 4842 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4843def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b", 4844 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4845def RLWIMIbm_rec : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b", 4846 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4847def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b", 4848 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4849def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b", 4850 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4851def PPCLdFixedAddr : 4852 PPCPostRAExpPseudo<(outs gprc:$rT), (ins i32imm:$imm), "#FA_LOAD", 4853 [(set i32:$rT, (int_ppc_fixed_addr_ld timm:$imm))]>; 4854 4855// These generic branch instruction forms are used for the assembler parser only. 4856// Defs and Uses are conservative, since we don't know the BO value. 4857let PPC970_Unit = 7, isBranch = 1, hasSideEffects = 0 in { 4858 let Defs = [CTR], Uses = [CTR, RM] in { 4859 def gBC : BForm_3<16, 0, 0, (outs), 4860 (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD), 4861 "bc $BO, $BI, $BD">; 4862 def gBCA : BForm_3<16, 1, 0, (outs), 4863 (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD), 4864 "bca $BO, $BI, $BD">; 4865 let isAsmParserOnly = 1 in { 4866 def gBCat : BForm_3_at<16, 0, 0, (outs), 4867 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4868 condbrtarget:$BD), 4869 "bc$at $BO, $BI, $BD">; 4870 def gBCAat : BForm_3_at<16, 1, 0, (outs), 4871 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4872 abscondbrtarget:$BD), 4873 "bca$at $BO, $BI, $BD">; 4874 } // isAsmParserOnly = 1 4875 } 4876 let Defs = [LR, CTR], Uses = [CTR, RM] in { 4877 def gBCL : BForm_3<16, 0, 1, (outs), 4878 (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD), 4879 "bcl $BO, $BI, $BD">; 4880 def gBCLA : BForm_3<16, 1, 1, (outs), 4881 (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD), 4882 "bcla $BO, $BI, $BD">; 4883 let isAsmParserOnly = 1 in { 4884 def gBCLat : BForm_3_at<16, 0, 1, (outs), 4885 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4886 condbrtarget:$BD), 4887 "bcl$at $BO, $BI, $BD">; 4888 def gBCLAat : BForm_3_at<16, 1, 1, (outs), 4889 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4890 abscondbrtarget:$BD), 4891 "bcla$at $BO, $BI, $BD">; 4892 } // // isAsmParserOnly = 1 4893 } 4894 let Defs = [CTR], Uses = [CTR, LR, RM] in 4895 def gBCLR : XLForm_2<19, 16, 0, (outs), 4896 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4897 "bclr $BO, $BI, $BH", IIC_BrB, []>; 4898 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4899 def gBCLRL : XLForm_2<19, 16, 1, (outs), 4900 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4901 "bclrl $BO, $BI, $BH", IIC_BrB, []>; 4902 let Defs = [CTR], Uses = [CTR, LR, RM] in 4903 def gBCCTR : XLForm_2<19, 528, 0, (outs), 4904 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4905 "bcctr $BO, $BI, $BH", IIC_BrB, []>; 4906 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4907 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 4908 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4909 "bcctrl $BO, $BI, $BH", IIC_BrB, []>; 4910} 4911 4912multiclass BranchSimpleMnemonicAT<string pm, int at> { 4913 def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi, 4914 condbrtarget:$dst)>; 4915 def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi, 4916 condbrtarget:$dst)>; 4917 def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi, 4918 condbrtarget:$dst)>; 4919 def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi, 4920 condbrtarget:$dst)>; 4921} 4922defm : BranchSimpleMnemonicAT<"+", 3>; 4923defm : BranchSimpleMnemonicAT<"-", 2>; 4924 4925def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 4926def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 4927def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 4928def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 4929 4930multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 4931 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 4932 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4933 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 4934 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 4935 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4936 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 4937} 4938multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 4939 : BranchSimpleMnemonic1<name, pm, bo> { 4940 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 4941 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 4942} 4943defm : BranchSimpleMnemonic2<"t", "", 12>; 4944defm : BranchSimpleMnemonic2<"f", "", 4>; 4945defm : BranchSimpleMnemonic2<"t", "-", 14>; 4946defm : BranchSimpleMnemonic2<"f", "-", 6>; 4947defm : BranchSimpleMnemonic2<"t", "+", 15>; 4948defm : BranchSimpleMnemonic2<"f", "+", 7>; 4949defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 4950defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 4951defm : BranchSimpleMnemonic1<"dzt", "", 10>; 4952defm : BranchSimpleMnemonic1<"dzf", "", 2>; 4953 4954multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 4955 def : InstAlias<"b"#name#pm#" $cc, $dst", 4956 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 4957 def : InstAlias<"b"#name#pm#" $dst", 4958 (BCC bibo, CR0, condbrtarget:$dst)>; 4959 4960 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 4961 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4962 def : InstAlias<"b"#name#"a"#pm#" $dst", 4963 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 4964 4965 def : InstAlias<"b"#name#"lr"#pm#" $cc", 4966 (BCCLR bibo, crrc:$cc)>; 4967 def : InstAlias<"b"#name#"lr"#pm, 4968 (BCCLR bibo, CR0)>; 4969 4970 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 4971 (BCCCTR bibo, crrc:$cc)>; 4972 def : InstAlias<"b"#name#"ctr"#pm, 4973 (BCCCTR bibo, CR0)>; 4974 4975 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 4976 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 4977 def : InstAlias<"b"#name#"l"#pm#" $dst", 4978 (BCCL bibo, CR0, condbrtarget:$dst)>; 4979 4980 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 4981 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4982 def : InstAlias<"b"#name#"la"#pm#" $dst", 4983 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 4984 4985 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 4986 (BCCLRL bibo, crrc:$cc)>; 4987 def : InstAlias<"b"#name#"lrl"#pm, 4988 (BCCLRL bibo, CR0)>; 4989 4990 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 4991 (BCCCTRL bibo, crrc:$cc)>; 4992 def : InstAlias<"b"#name#"ctrl"#pm, 4993 (BCCCTRL bibo, CR0)>; 4994} 4995multiclass BranchExtendedMnemonic<string name, int bibo> { 4996 defm : BranchExtendedMnemonicPM<name, "", bibo>; 4997 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 4998 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 4999} 5000defm : BranchExtendedMnemonic<"lt", 12>; 5001defm : BranchExtendedMnemonic<"gt", 44>; 5002defm : BranchExtendedMnemonic<"eq", 76>; 5003defm : BranchExtendedMnemonic<"un", 108>; 5004defm : BranchExtendedMnemonic<"so", 108>; 5005defm : BranchExtendedMnemonic<"ge", 4>; 5006defm : BranchExtendedMnemonic<"nl", 4>; 5007defm : BranchExtendedMnemonic<"le", 36>; 5008defm : BranchExtendedMnemonic<"ng", 36>; 5009defm : BranchExtendedMnemonic<"ne", 68>; 5010defm : BranchExtendedMnemonic<"nu", 100>; 5011defm : BranchExtendedMnemonic<"ns", 100>; 5012 5013def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 5014def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 5015def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 5016def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 5017def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 5018def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 5019def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 5020def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 5021 5022def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 5023def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 5024def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 5025def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 5026def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 5027def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5028def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 5029def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5030 5031def : InstAlias<"trap", (TW 31, R0, R0)>; 5032 5033multiclass TrapExtendedMnemonic<string name, int to> { 5034 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 5035 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 5036 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 5037 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 5038} 5039defm : TrapExtendedMnemonic<"lt", 16>; 5040defm : TrapExtendedMnemonic<"le", 20>; 5041defm : TrapExtendedMnemonic<"eq", 4>; 5042defm : TrapExtendedMnemonic<"ge", 12>; 5043defm : TrapExtendedMnemonic<"gt", 8>; 5044defm : TrapExtendedMnemonic<"nl", 12>; 5045defm : TrapExtendedMnemonic<"ne", 24>; 5046defm : TrapExtendedMnemonic<"ng", 20>; 5047defm : TrapExtendedMnemonic<"llt", 2>; 5048defm : TrapExtendedMnemonic<"lle", 6>; 5049defm : TrapExtendedMnemonic<"lge", 5>; 5050defm : TrapExtendedMnemonic<"lgt", 1>; 5051defm : TrapExtendedMnemonic<"lnl", 5>; 5052defm : TrapExtendedMnemonic<"lng", 6>; 5053defm : TrapExtendedMnemonic<"u", 31>; 5054 5055// Atomic loads 5056def : Pat<(i32 (atomic_load_8 DForm:$src)), (LBZ memri:$src)>; 5057def : Pat<(i32 (atomic_load_16 DForm:$src)), (LHZ memri:$src)>; 5058def : Pat<(i32 (atomic_load_32 DForm:$src)), (LWZ memri:$src)>; 5059def : Pat<(i32 (atomic_load_8 XForm:$src)), (LBZX memrr:$src)>; 5060def : Pat<(i32 (atomic_load_16 XForm:$src)), (LHZX memrr:$src)>; 5061def : Pat<(i32 (atomic_load_32 XForm:$src)), (LWZX memrr:$src)>; 5062 5063// Atomic stores 5064def : Pat<(atomic_store_8 i32:$val, DForm:$ptr), (STB gprc:$val, memri:$ptr)>; 5065def : Pat<(atomic_store_16 i32:$val, DForm:$ptr), (STH gprc:$val, memri:$ptr)>; 5066def : Pat<(atomic_store_32 i32:$val, DForm:$ptr), (STW gprc:$val, memri:$ptr)>; 5067def : Pat<(atomic_store_8 i32:$val, XForm:$ptr), (STBX gprc:$val, memrr:$ptr)>; 5068def : Pat<(atomic_store_16 i32:$val, XForm:$ptr), (STHX gprc:$val, memrr:$ptr)>; 5069def : Pat<(atomic_store_32 i32:$val, XForm:$ptr), (STWX gprc:$val, memrr:$ptr)>; 5070 5071let Predicates = [IsISA3_0] in { 5072 5073// Copy-Paste Facility 5074// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to 5075// PASTE for naming consistency. 5076let mayLoad = 1 in 5077def CP_COPY : X_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>; 5078 5079let mayStore = 1, Defs = [CR0] in 5080def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm; 5081 5082def : InstAlias<"paste. $RA, $RB", (CP_PASTE_rec gprc:$RA, gprc:$RB, 1)>; 5083def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cpabort", IIC_SprABORT, []>; 5084 5085// Message Synchronize 5086def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>; 5087 5088// Power-Saving Mode Instruction: 5089def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>; 5090 5091def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 5092 "setb $RT, $BFA", IIC_IntGeneral>, SExt32To64; 5093} // IsISA3_0 5094 5095let Predicates = [IsISA3_0] in { 5096def : Pat<(i32 (int_ppc_cmprb i32:$a, gprc:$b, gprc:$c)), 5097 (i32 (SETB (CMPRB u1imm:$a, $b, $c)))>; 5098} 5099def : Pat<(i32 (int_ppc_mulhw gprc:$a, gprc:$b)), 5100 (i32 (MULHW $a, $b))>; 5101def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)), 5102 (i32 (MULHWU $a, $b))>; 5103def : Pat<(i32 (int_ppc_cmpb gprc:$a, gprc:$b)), 5104 (i32 (CMPB $a, $b))>; 5105 5106def : Pat<(int_ppc_load2r ForceXForm:$ptr), 5107 (LHBRX ForceXForm:$ptr)>; 5108def : Pat<(int_ppc_load4r ForceXForm:$ptr), 5109 (LWBRX ForceXForm:$ptr)>; 5110def : Pat<(int_ppc_store2r gprc:$a, ForceXForm:$ptr), 5111 (STHBRX gprc:$a, ForceXForm:$ptr)>; 5112def : Pat<(int_ppc_store4r gprc:$a, ForceXForm:$ptr), 5113 (STWBRX gprc:$a, ForceXForm:$ptr)>; 5114 5115 5116// Fast 32-bit reverse bits algorithm: 5117// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5118// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA); 5119// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5120// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC); 5121// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5122// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0); 5123// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]): 5124// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes): 5125// n' = (n rotl 24); After which n' = [B4, B1, B2, B3] 5126// Step 4.2: Insert B3 to the right position: 5127// n' = rlwimi n', n, 8, 8, 15; After which n' = [B4, B3, B2, B3] 5128// Step 4.3: Insert B1 to the right position: 5129// n' = rlwimi n', n, 8, 24, 31; After which n' = [B4, B3, B2, B1] 5130def MaskValues { 5131 dag Lo1 = (ORI (LIS 0x5555), 0x5555); 5132 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA); 5133 dag Lo2 = (ORI (LIS 0x3333), 0x3333); 5134 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC); 5135 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F); 5136 dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0); 5137} 5138 5139def Shift1 { 5140 dag Right = (RLWINM $A, 31, 1, 31); 5141 dag Left = (RLWINM $A, 1, 0, 30); 5142} 5143 5144def Swap1 { 5145 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1), 5146 (AND Shift1.Left, MaskValues.Hi1)); 5147} 5148 5149def Shift2 { 5150 dag Right = (RLWINM Swap1.Bit, 30, 2, 31); 5151 dag Left = (RLWINM Swap1.Bit, 2, 0, 29); 5152} 5153 5154def Swap2 { 5155 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2), 5156 (AND Shift2.Left, MaskValues.Hi2)); 5157} 5158 5159def Shift4 { 5160 dag Right = (RLWINM Swap2.Bits, 28, 4, 31); 5161 dag Left = (RLWINM Swap2.Bits, 4, 0, 27); 5162} 5163 5164def Swap4 { 5165 dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4), 5166 (AND Shift4.Left, MaskValues.Hi4)); 5167} 5168 5169def Rotate { 5170 dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31); 5171} 5172 5173def RotateInsertByte3 { 5174 dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15); 5175} 5176 5177def RotateInsertByte1 { 5178 dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31); 5179} 5180 5181// Clear the upper half of the register when in 64-bit mode 5182let Predicates = [In64BitMode] in 5183def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>; 5184let Predicates = [In32BitMode] in 5185def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>; 5186 5187// Fast 64-bit reverse bits algorithm: 5188// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5189// n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA); 5190// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5191// n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC); 5192// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5193// n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0); 5194// Step 4: byte reverse (Suppose n = [B0,B1,B2,B3,B4,B5,B6,B7]): 5195// Apply the same byte reverse algorithm mentioned above for the fast 32-bit 5196// reverse to both the high 32 bit and low 32 bit of the 64 bit value. And 5197// then OR them together to get the final result. 5198def MaskValues64 { 5199 dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32)); 5200 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32)); 5201 dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32)); 5202 dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32)); 5203 dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32)); 5204 dag Hi4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi4, sub_32)); 5205} 5206 5207def DWMaskValues { 5208 dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555); 5209 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA); 5210 dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333); 5211 dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC); 5212 dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F); 5213 dag Hi4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi4, 32, 31), 0xF0F0), 0xF0F0); 5214} 5215 5216def DWSwapInByte { 5217 dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1), 5218 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1)); 5219 dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2), 5220 (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2)); 5221 dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4), 5222 (AND8 (RLDICR Swap2, 4, 59), DWMaskValues.Hi4)); 5223} 5224 5225// Intra-byte swap is done, now start inter-byte swap. 5226def DWBytes4567 { 5227 dag Word = (i32 (EXTRACT_SUBREG DWSwapInByte.Swap4, sub_32)); 5228} 5229 5230def DWBytes7456 { 5231 dag Word = (RLWINM DWBytes4567.Word, 24, 0, 31); 5232} 5233 5234def DWBytes7656 { 5235 dag Word = (RLWIMI DWBytes7456.Word, DWBytes4567.Word, 8, 8, 15); 5236} 5237 5238// B7 B6 B5 B4 in the right order 5239def DWBytes7654 { 5240 dag Word = (RLWIMI DWBytes7656.Word, DWBytes4567.Word, 8, 24, 31); 5241 dag DWord = 5242 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5243} 5244 5245def DWBytes0123 { 5246 dag Word = (i32 (EXTRACT_SUBREG (RLDICL DWSwapInByte.Swap4, 32, 32), sub_32)); 5247} 5248 5249def DWBytes3012 { 5250 dag Word = (RLWINM DWBytes0123.Word, 24, 0, 31); 5251} 5252 5253def DWBytes3212 { 5254 dag Word = (RLWIMI DWBytes3012.Word, DWBytes0123.Word, 8, 8, 15); 5255} 5256 5257// B3 B2 B1 B0 in the right order 5258def DWBytes3210 { 5259 dag Word = (RLWIMI DWBytes3212.Word, DWBytes0123.Word, 8, 24, 31); 5260 dag DWord = 5261 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5262} 5263 5264// These instructions store a hash computed from the value of the link register 5265// and the value of the stack pointer. 5266let mayStore = 1 in { 5267def HASHST : XForm_XD6_RA5_RB5<31, 722, (outs), 5268 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5269 "hashst $RB, $addr", IIC_IntGeneral, []>; 5270def HASHSTP : XForm_XD6_RA5_RB5<31, 658, (outs), 5271 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5272 "hashstp $RB, $addr", IIC_IntGeneral, []>; 5273} 5274 5275// These instructions check a hash computed from the value of the link register 5276// and the value of the stack pointer. The hasSideEffects flag is needed as the 5277// instruction may TRAP if the hash does not match the hash stored at the 5278// specified address. 5279let mayLoad = 1, hasSideEffects = 1 in { 5280def HASHCHK : XForm_XD6_RA5_RB5<31, 754, (outs), 5281 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5282 "hashchk $RB, $addr", IIC_IntGeneral, []>; 5283def HASHCHKP : XForm_XD6_RA5_RB5<31, 690, (outs), 5284 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5285 "hashchkp $RB, $addr", IIC_IntGeneral, []>; 5286} 5287 5288let Defs = [CR7], Itinerary = IIC_LdStSync in 5289def CFENCE : PPCPostRAExpPseudo<(outs), (ins gprc:$cr), "#CFENCE", []>; 5290 5291// Now both high word and low word are reversed, next 5292// swap the high word and low word. 5293def : Pat<(i64 (bitreverse i64:$A)), 5294 (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>; 5295 5296def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A), 5297 (RLWINM (STWCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5298def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 4), 5299 (RLWINM (STWCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5300def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A), 5301 (RLWINM (STBCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5302def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 1), 5303 (RLWINM (STBCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5304 5305def : Pat<(int_ppc_fcfid f64:$A), 5306 (XSCVSXDDP $A)>; 5307def : Pat<(int_ppc_fcfud f64:$A), 5308 (XSCVUXDDP $A)>; 5309def : Pat<(int_ppc_fctid f64:$A), 5310 (FCTID $A)>; 5311def : Pat<(int_ppc_fctidz f64:$A), 5312 (XSCVDPSXDS $A)>; 5313def : Pat<(int_ppc_fctiw f64:$A), 5314 (FCTIW $A)>; 5315def : Pat<(int_ppc_fctiwz f64:$A), 5316 (XSCVDPSXWS $A)>; 5317def : Pat<(int_ppc_fctudz f64:$A), 5318 (XSCVDPUXDS $A)>; 5319def : Pat<(int_ppc_fctuwz f64:$A), 5320 (XSCVDPUXWS $A)>; 5321 5322def : Pat<(int_ppc_mfmsr), (MFMSR)>; 5323def : Pat<(int_ppc_mftbu), (MFTB 269)>; 5324def : Pat<(i32 (int_ppc_mfspr timm:$SPR)), 5325 (MFSPR $SPR)>; 5326def : Pat<(int_ppc_mtspr timm:$SPR, gprc:$RT), 5327 (MTSPR $SPR, $RT)>; 5328def : Pat<(int_ppc_mtmsr gprc:$RS), 5329 (MTMSR $RS, 0)>; 5330 5331let Predicates = [IsISA2_07] in { 5332 def : Pat<(int_ppc_sthcx ForceXForm:$dst, gprc:$A), 5333 (RLWINM (STHCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5334 def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 2), 5335 (RLWINM (STHCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5336} 5337def : Pat<(int_ppc_dcbtstt ForceXForm:$dst), 5338 (DCBTST 16, ForceXForm:$dst)>; 5339def : Pat<(int_ppc_dcbtt ForceXForm:$dst), 5340 (DCBT 16, ForceXForm:$dst)>; 5341 5342def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT), 5343 (STFIWX f64:$XT, ForceXForm:$dst)>; 5344