1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22 let OperandType = "OPERAND_IMMEDIATE"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29 let OperandType = "OPERAND_IMMEDIATE"; 30} 31def s17imm64 : Operand<i64> { 32 // This operand type is used for addis/lis to allow the assembler parser 33 // to accept immediates in the range -65536..65535 for compatibility with 34 // the GNU assembler. The operand is treated as 16-bit otherwise. 35 let PrintMethod = "printS16ImmOperand"; 36 let EncoderMethod = "getImm16Encoding"; 37 let ParserMatchClass = PPCS17ImmAsmOperand; 38 let DecoderMethod = "decodeSImmOperand<16>"; 39 let OperandType = "OPERAND_IMMEDIATE"; 40} 41def tocentry : Operand<iPTR> { 42 let MIOperandInfo = (ops i64imm:$imm); 43} 44def tlsreg : Operand<i64> { 45 let EncoderMethod = "getTLSRegEncoding"; 46 let ParserMatchClass = PPCTLSRegOperand; 47} 48def tlsgd : Operand<i64> {} 49def tlscall : Operand<i64> { 50 let PrintMethod = "printTLSCall"; 51 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 52 let EncoderMethod = "getTLSCallEncoding"; 53} 54 55//===----------------------------------------------------------------------===// 56// 64-bit transformation functions. 57// 58 59def SHL64 : SDNodeXForm<imm, [{ 60 // Transformation function: 63 - imm 61 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 62}]>; 63 64def SRL64 : SDNodeXForm<imm, [{ 65 // Transformation function: 64 - imm 66 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 67 : getI32Imm(0, SDLoc(N)); 68}]>; 69 70 71//===----------------------------------------------------------------------===// 72// Calls. 73// 74 75let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 76let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 77 let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in 78 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 79 [(PPCretglue)]>, Requires<[In64BitMode]>; 80 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 81 let isPredicable = 1 in 82 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 83 []>, 84 Requires<[In64BitMode]>; 85 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond), 86 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 87 []>, 88 Requires<[In64BitMode]>; 89 90 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI), 91 "bcctr 12, $BI, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI), 94 "bcctr 4, $BI, 0", IIC_BrB, []>, 95 Requires<[In64BitMode]>; 96 } 97} 98 99let Defs = [LR8] in 100 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 101 PPC970_Unit_BRU; 102 103let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 104 let Defs = [CTR8], Uses = [CTR8] in { 105 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD), 106 "bdz $BD">; 107 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD), 108 "bdnz $BD">; 109 } 110 111 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 112 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 113 "bdzlr", IIC_BrB, []>; 114 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 115 "bdnzlr", IIC_BrB, []>; 116 } 117} 118 119 120 121let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in { 122 // Convenient aliases for call instructions 123 let Uses = [RM] in { 124 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$LI), 125 "bl $LI", IIC_BrB, []>; // See Pat patterns below. 126 127 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$LI), 128 "bl $LI", IIC_BrB, []>; 129 130 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), 131 "bla $LI", IIC_BrB, [(PPCcall (i64 imm:$LI))]>; 132 } 133 let Uses = [RM], isCodeGenOnly = 1 in { 134 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 135 (outs), (ins calltarget:$LI), 136 "bl $LI\n\tnop", IIC_BrB, []>; 137 138 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 139 (outs), (ins tlscall:$LI), 140 "bl $LI\n\tnop", IIC_BrB, []>; 141 142 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 143 (outs), (ins abscalltarget:$LI), 144 "bla $LI\n\tnop", IIC_BrB, 145 [(PPCcall_nop (i64 imm:$LI))]>; 146 let Predicates = [PCRelativeMemops] in { 147 // BL8_NOTOC means that the caller does not use the TOC pointer and if 148 // it does use R2 then it is just a caller saved register. Therefore it is 149 // safe to emit only the bl and not the nop for this instruction. The 150 // linker will not try to restore R2 after the call. 151 def BL8_NOTOC : IForm<18, 0, 1, (outs), 152 (ins calltarget:$LI), 153 "bl $LI", IIC_BrB, []>; 154 def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs), 155 (ins tlscall:$LI), 156 "bl $LI", IIC_BrB, []>; 157 } 158 } 159 let Uses = [CTR8, RM] in { 160 let isPredicable = 1 in 161 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 162 "bctrl", IIC_BrB, [(PPCbctrl)]>, 163 Requires<[In64BitMode]>; 164 165 let isCodeGenOnly = 1 in { 166 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond), 167 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 168 []>, 169 Requires<[In64BitMode]>; 170 171 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI), 172 "bcctrl 12, $BI, 0", IIC_BrB, []>, 173 Requires<[In64BitMode]>; 174 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI), 175 "bcctrl 4, $BI, 0", IIC_BrB, []>, 176 Requires<[In64BitMode]>; 177 } 178 } 179} 180 181let isCall = 1, PPC970_Unit = 7, Defs = [LR8, RM], hasSideEffects = 0, 182 isCodeGenOnly = 1, Uses = [RM] in { 183 // Convenient aliases for call instructions 184 def BL8_RM : IForm<18, 0, 1, (outs), (ins calltarget:$LI), 185 "bl $LI", IIC_BrB, []>; // See Pat patterns below. 186 187 def BLA8_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), 188 "bla $LI", IIC_BrB, [(PPCcall_rm (i64 imm:$LI))]>; 189 def BL8_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, 190 (outs), (ins calltarget:$LI), 191 "bl $LI\n\tnop", IIC_BrB, []>; 192 193 def BLA8_NOP_RM : IForm_and_DForm_4_zero<18, 1, 1, 24, 194 (outs), (ins abscalltarget:$LI), 195 "bla $LI\n\tnop", IIC_BrB, 196 [(PPCcall_nop_rm (i64 imm:$LI))]>; 197 let Predicates = [PCRelativeMemops] in { 198 // BL8_NOTOC means that the caller does not use the TOC pointer and if 199 // it does use R2 then it is just a caller saved register. Therefore it is 200 // safe to emit only the bl and not the nop for this instruction. The 201 // linker will not try to restore R2 after the call. 202 def BL8_NOTOC_RM : IForm<18, 0, 1, (outs), 203 (ins calltarget:$LI), 204 "bl $LI", IIC_BrB, []>; 205 } 206 let Uses = [CTR8, RM] in { 207 let isPredicable = 1 in 208 def BCTRL8_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 209 "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, 210 Requires<[In64BitMode]>; 211 } 212} 213 214let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 215 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 216 def BCTRL8_LDinto_toc : 217 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 218 (ins (memrix $D, $RA):$src), 219 "bctrl\n\tld 2, $src", IIC_BrB, 220 [(PPCbctrl_load_toc iaddrX4:$src)]>, 221 Requires<[In64BitMode]>; 222} 223 224let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 225 Defs = [LR8, X2, RM], Uses = [CTR8, RM], RST = 2 in { 226 def BCTRL8_LDinto_toc_RM : 227 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 228 (ins (memrix $D, $RA):$src), 229 "bctrl\n\tld 2, $src", IIC_BrB, 230 [(PPCbctrl_load_toc_rm iaddrX4:$src)]>, 231 Requires<[In64BitMode]>; 232} 233 234} // Interpretation64Bit 235 236// FIXME: Duplicating this for the asm parser should be unnecessary, but the 237// previous definition must be marked as CodeGen only to prevent decoding 238// conflicts. 239let Interpretation64Bit = 1, isAsmParserOnly = 1, hasSideEffects = 0 in 240let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 241def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$LI), 242 "bl $LI", IIC_BrB, []>; 243 244// Calls 245def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 246 (BL8 tglobaladdr:$dst)>; 247def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 248 (BL8_NOP tglobaladdr:$dst)>; 249 250def : Pat<(PPCcall (i64 texternalsym:$dst)), 251 (BL8 texternalsym:$dst)>; 252def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 253 (BL8_NOP texternalsym:$dst)>; 254 255def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)), 256 (BL8_NOTOC tglobaladdr:$dst)>; 257def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)), 258 (BL8_NOTOC texternalsym:$dst)>; 259 260def : Pat<(PPCcall_rm (i64 tglobaladdr:$dst)), 261 (BL8_RM tglobaladdr:$dst)>; 262def : Pat<(PPCcall_nop_rm (i64 tglobaladdr:$dst)), 263 (BL8_NOP_RM tglobaladdr:$dst)>; 264 265def : Pat<(PPCcall_rm (i64 texternalsym:$dst)), 266 (BL8_RM texternalsym:$dst)>; 267def : Pat<(PPCcall_nop_rm (i64 texternalsym:$dst)), 268 (BL8_NOP_RM texternalsym:$dst)>; 269 270def : Pat<(PPCcall_notoc_rm (i64 tglobaladdr:$dst)), 271 (BL8_NOTOC_RM tglobaladdr:$dst)>; 272def : Pat<(PPCcall_notoc_rm (i64 texternalsym:$dst)), 273 (BL8_NOTOC_RM texternalsym:$dst)>; 274 275// Calls for AIX 276def : Pat<(PPCcall (i64 mcsym:$dst)), 277 (BL8 mcsym:$dst)>; 278def : Pat<(PPCcall_nop (i64 mcsym:$dst)), 279 (BL8_NOP mcsym:$dst)>; 280 281def : Pat<(PPCcall_rm (i64 mcsym:$dst)), 282 (BL8_RM mcsym:$dst)>; 283def : Pat<(PPCcall_nop_rm (i64 mcsym:$dst)), 284 (BL8_NOP_RM mcsym:$dst)>; 285 286// Atomic operations 287// FIXME: some of these might be used with constant operands. This will result 288// in constant materialization instructions that may be redundant. We currently 289// clean this up in PPCMIPeephole with calls to 290// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 291// in the first place. 292let Defs = [CR0] in { 293 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 294 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 295 [(set i64:$dst, (atomic_load_add_i64 ForceXForm:$ptr, i64:$incr))]>; 296 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 297 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 298 [(set i64:$dst, (atomic_load_sub_i64 ForceXForm:$ptr, i64:$incr))]>; 299 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 300 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 301 [(set i64:$dst, (atomic_load_or_i64 ForceXForm:$ptr, i64:$incr))]>; 302 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 303 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 304 [(set i64:$dst, (atomic_load_xor_i64 ForceXForm:$ptr, i64:$incr))]>; 305 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 306 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 307 [(set i64:$dst, (atomic_load_and_i64 ForceXForm:$ptr, i64:$incr))]>; 308 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 309 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 310 [(set i64:$dst, (atomic_load_nand_i64 ForceXForm:$ptr, i64:$incr))]>; 311 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 312 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 313 [(set i64:$dst, (atomic_load_min_i64 ForceXForm:$ptr, i64:$incr))]>; 314 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 315 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 316 [(set i64:$dst, (atomic_load_max_i64 ForceXForm:$ptr, i64:$incr))]>; 317 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 318 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 319 [(set i64:$dst, (atomic_load_umin_i64 ForceXForm:$ptr, i64:$incr))]>; 320 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 321 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 322 [(set i64:$dst, (atomic_load_umax_i64 ForceXForm:$ptr, i64:$incr))]>; 323 324 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 325 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 326 [(set i64:$dst, (atomic_cmp_swap_i64 ForceXForm:$ptr, i64:$old, i64:$new))]>; 327 328 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 329 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 330 [(set i64:$dst, (atomic_swap_i64 ForceXForm:$ptr, i64:$new))]>; 331} 332 333// Instructions to support atomic operations 334let mayLoad = 1, hasSideEffects = 0 in { 335def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 336 "ldarx $RST, $addr", IIC_LdStLDARX, []>; 337// TODO: Add scheduling info. 338let hasNoSchedulingInfo = 1 in 339def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr), 340 "lqarx $RST, $addr", IIC_LdStLQARX, []>, isPPC64; 341 342// Instruction to support lock versions of atomics 343// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 344def LDARXL : XForm_1<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 345 "ldarx $RST, $addr, 1", IIC_LdStLDARX, []>, isRecordForm; 346// TODO: Add scheduling info. 347let hasNoSchedulingInfo = 1 in 348// FIXME: We have to seek a way to remove isRecordForm since 349// LQARXL is not really altering CR0. 350def LQARXL : XForm_1<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr), 351 "lqarx $RST, $addr, 1", IIC_LdStLQARX, []>, 352 isPPC64, isRecordForm; 353 354let hasExtraDefRegAllocReq = 1 in 355def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$RST), (ins g8rc:$RA, u5imm:$RB), 356 "ldat $RST, $RA, $RB", IIC_LdStLoad>, isPPC64, 357 Requires<[IsISA3_0]>; 358} 359 360let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 361def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), 362 "stdcx. $RST, $addr", IIC_LdStSTDCX, []>, isRecordForm; 363// TODO: Add scheduling info. 364let hasNoSchedulingInfo = 1 in 365def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RST, (memrr $RA, $RB):$addr), 366 "stqcx. $RST, $addr", IIC_LdStSTQCX, []>, 367 isPPC64, isRecordForm; 368} 369 370def SPLIT_QUADWORD : PPCCustomInserterPseudo<(outs g8rc:$lo, g8rc:$hi), 371 (ins g8prc:$src), 372 "#SPLIT_QUADWORD", []>; 373class AtomicRMW128<string asmstr> 374 : PPCPostRAExpPseudo<(outs g8prc:$RTp, g8prc:$scratch), 375 (ins memrr:$ptr, g8rc:$incr_lo, g8rc:$incr_hi), 376 asmstr, []>; 377// We have to keep values in MI's uses during LL/SC looping as they are, 378// so set both $RTp and $scratch earlyclobber. 379let mayStore = 1, mayLoad = 1, 380 Defs = [CR0], 381 Constraints = "@earlyclobber $scratch,@earlyclobber $RTp" in { 382// Atomic pseudo instructions expanded post-ra. 383def ATOMIC_SWAP_I128 : AtomicRMW128<"#ATOMIC_SWAP_I128">; 384def ATOMIC_LOAD_ADD_I128 : AtomicRMW128<"#ATOMIC_LOAD_ADD_I128">; 385def ATOMIC_LOAD_SUB_I128 : AtomicRMW128<"#ATOMIC_LOAD_SUB_I128">; 386def ATOMIC_LOAD_AND_I128 : AtomicRMW128<"#ATOMIC_LOAD_AND_I128">; 387def ATOMIC_LOAD_XOR_I128 : AtomicRMW128<"#ATOMIC_LOAD_XOR_I128">; 388def ATOMIC_LOAD_OR_I128 : AtomicRMW128<"#ATOMIC_LOAD_OR_I128">; 389def ATOMIC_LOAD_NAND_I128 : AtomicRMW128<"#ATOMIC_LOAD_NAND_I128">; 390 391def ATOMIC_CMP_SWAP_I128 : PPCPostRAExpPseudo< 392 (outs g8prc:$RTp, g8prc:$scratch), 393 (ins memrr:$ptr, g8rc:$cmp_lo, g8rc:$cmp_hi, 394 g8rc:$new_lo, g8rc:$new_hi), 395 "#ATOMIC_CMP_SWAP_I128", []>; 396} 397 398class PatAtomicRMWI128<SDPatternOperator OpNode, AtomicRMW128 Inst> : 399 Pat<(OpNode ForceXForm:$ptr, 400 i64:$incr_lo, 401 i64:$incr_hi), 402 (SPLIT_QUADWORD (Inst memrr:$ptr, 403 g8rc:$incr_lo, 404 g8rc:$incr_hi))>; 405 406def : PatAtomicRMWI128<int_ppc_atomicrmw_add_i128, ATOMIC_LOAD_ADD_I128>; 407def : PatAtomicRMWI128<int_ppc_atomicrmw_sub_i128, ATOMIC_LOAD_SUB_I128>; 408def : PatAtomicRMWI128<int_ppc_atomicrmw_xor_i128, ATOMIC_LOAD_XOR_I128>; 409def : PatAtomicRMWI128<int_ppc_atomicrmw_and_i128, ATOMIC_LOAD_AND_I128>; 410def : PatAtomicRMWI128<int_ppc_atomicrmw_nand_i128, ATOMIC_LOAD_NAND_I128>; 411def : PatAtomicRMWI128<int_ppc_atomicrmw_or_i128, ATOMIC_LOAD_OR_I128>; 412def : PatAtomicRMWI128<int_ppc_atomicrmw_xchg_i128, ATOMIC_SWAP_I128>; 413def : Pat<(int_ppc_cmpxchg_i128 ForceXForm:$ptr, 414 i64:$cmp_lo, 415 i64:$cmp_hi, 416 i64:$new_lo, 417 i64:$new_hi), 418 (SPLIT_QUADWORD (ATOMIC_CMP_SWAP_I128 419 memrr:$ptr, 420 g8rc:$cmp_lo, 421 g8rc:$cmp_hi, 422 g8rc:$new_lo, 423 g8rc:$new_hi))>; 424 425let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 426def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$RST, g8rc:$RA, u5imm:$RB), 427 "stdat $RST, $RA, $RB", IIC_LdStStore>, isPPC64, 428 Requires<[IsISA3_0]>; 429 430let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 431let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 432def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 433 (ins calltarget:$dst, i32imm:$offset), 434 "#TC_RETURNd8 $dst $offset", 435 []>; 436 437let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 438def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 439 "#TC_RETURNa8 $func $offset", 440 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 441 442let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 443def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 444 "#TC_RETURNr8 $dst $offset", 445 []>; 446 447let hasSideEffects = 0 in { 448let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 449 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 450def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 451 []>, 452 Requires<[In64BitMode]>; 453 454let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 455 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 456def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$LI), 457 "b $LI", IIC_BrB, 458 []>; 459 460let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 461 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 462def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$LI), 463 "ba $LI", IIC_BrB, 464 []>; 465} 466} // Interpretation64Bit 467 468def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 469 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 470 471def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 472 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 473 474def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 475 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 476 477 478// 64-bit CR instructions 479let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 480let hasSideEffects = 0 in { 481// mtocrf's input needs to be prepared by shifting by an amount dependent 482// on the cr register selected. Thus, post-ra anti-dep breaking must not 483// later change that register assignment. 484let hasExtraDefRegAllocReq = 1 in { 485def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$RST), 486 "mtocrf $FXM, $RST", IIC_BrMCRX>, 487 PPC970_DGroup_First, PPC970_Unit_CRU; 488 489// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 490// is dependent on the cr fields being set. 491def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$RST), 492 "mtcrf $FXM, $RST", IIC_BrMCRX>, 493 PPC970_MicroCode, PPC970_Unit_CRU; 494} // hasExtraDefRegAllocReq = 1 495 496// mfocrf's input needs to be prepared by shifting by an amount dependent 497// on the cr register selected. Thus, post-ra anti-dep breaking must not 498// later change that register assignment. 499let hasExtraSrcRegAllocReq = 1 in { 500def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$RST), (ins crbitm:$FXM), 501 "mfocrf $RST, $FXM", IIC_SprMFCRF>, 502 PPC970_DGroup_First, PPC970_Unit_CRU; 503 504// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 505// is dependent on the cr fields being copied. 506def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$RT), (ins), 507 "mfcr $RT", IIC_SprMFCR>, 508 PPC970_MicroCode, PPC970_Unit_CRU; 509} // hasExtraSrcRegAllocReq = 1 510} // hasSideEffects = 0 511 512// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 513// is not. 514let hasSideEffects = 1 in { 515 let Defs = [CTR8] in 516 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 517 "#EH_SJLJ_SETJMP64", 518 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 519 Requires<[In64BitMode]>; 520} 521 522let hasSideEffects = 1, isBarrier = 1 in { 523 let isTerminator = 1 in 524 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 525 "#EH_SJLJ_LONGJMP64", 526 [(PPCeh_sjlj_longjmp addr:$buf)]>, 527 Requires<[In64BitMode]>; 528} 529 530def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RST), (ins i32imm:$SPR), 531 "mfspr $RST, $SPR", IIC_SprMFSPR>; 532def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RST), 533 "mtspr $SPR, $RST", IIC_SprMTSPR>; 534 535 536//===----------------------------------------------------------------------===// 537// 64-bit SPR manipulation instrs. 538 539let Uses = [CTR8] in { 540def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$RST), (ins), 541 "mfctr $RST", IIC_SprMFSPR>, 542 PPC970_DGroup_First, PPC970_Unit_FXU; 543} 544let Pattern = [(PPCmtctr i64:$RST)], Defs = [CTR8] in { 545def MTCTR8 : XFXForm_1_ext<31, 467, 9, (outs), (ins g8rc:$RST), 546 "mtctr $RST", IIC_SprMTSPR>, 547 PPC970_DGroup_First, PPC970_Unit_FXU; 548} 549// MTCTR[8|]loop must be inside a loop-preheader, duplicating 550// the loop-preheader block will break this assumption. 551let hasSideEffects = 1, isNotDuplicable = 1, Defs = [CTR8] in { 552let Pattern = [(int_set_loop_iterations i64:$RST)] in 553def MTCTR8loop : XFXForm_1_ext<31, 467, 9, (outs), (ins g8rc:$RST), 554 "mtctr $RST", IIC_SprMTSPR>, 555 PPC970_DGroup_First, PPC970_Unit_FXU; 556} 557 558let hasSideEffects = 1, hasNoSchedulingInfo = 1, isNotDuplicable = 1, Uses = [CTR8], Defs = [CTR8] in 559def DecreaseCTR8loop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i64imm:$stride), 560 "#DecreaseCTR8loop", [(set i1:$rT, (int_loop_decrement (i64 imm:$stride)))]>; 561 562let Pattern = [(set i64:$RST, readcyclecounter)] in 563def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$RST), (ins), 564 "mfspr $RST, 268", IIC_SprMFTB>, 565 PPC970_DGroup_First, PPC970_Unit_FXU; 566// Note that encoding mftb using mfspr is now the preferred form, 567// and has been since at least ISA v2.03. The mftb instruction has 568// now been phased out. Using mfspr, however, is known not to work on 569// the POWER3. 570 571let Defs = [X1], Uses = [X1] in 572def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 573 [(set i64:$result, 574 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 575def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 576 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 577// Probed alloca to support stack clash protection. 578let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in { 579def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result), 580 (ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64", 581 [(set i64:$result, 582 (PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>; 583def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs 584 g8rc:$fp, g8rc:$actual_negsize), 585 (ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>; 586def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 : PPCEmitTimePseudo<(outs 587 g8rc:$fp, g8rc:$actual_negsize), 588 (ins g8rc:$negsize, memri:$fpsi), 589 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", []>, 590 RegConstraint<"$actual_negsize = $negsize">; 591def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp), 592 (ins i64imm:$stacksize), 593 "#PROBED_STACKALLOC_64", []>; 594} 595 596let hasSideEffects = 0 in { 597let Defs = [LR8] in { 598def MTLR8 : XFXForm_1_ext<31, 467, 8, (outs), (ins g8rc:$RST), 599 "mtlr $RST", IIC_SprMTSPR>, 600 PPC970_DGroup_First, PPC970_Unit_FXU; 601} 602let Uses = [LR8] in { 603def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$RST), (ins), 604 "mflr $RST", IIC_SprMFSPR>, 605 PPC970_DGroup_First, PPC970_Unit_FXU; 606} 607} // Interpretation64Bit 608} 609 610//===----------------------------------------------------------------------===// 611// Fixed point instructions. 612// 613 614let PPC970_Unit = 1 in { // FXU Operations. 615let Interpretation64Bit = 1 in { 616let hasSideEffects = 0 in { 617let isCodeGenOnly = 1 in { 618 619let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 620def LI8 : DForm_2_r0<14, (outs g8rc:$RST), (ins s16imm64:$D), 621 "li $RST, $D", IIC_IntSimple, 622 [(set i64:$RST, imm64SExt16:$D)]>, SExt32To64; 623def LIS8 : DForm_2_r0<15, (outs g8rc:$RST), (ins s17imm64:$D), 624 "lis $RST, $D", IIC_IntSimple, 625 [(set i64:$RST, imm16ShiftedSExt:$D)]>, SExt32To64; 626} 627 628// Logical ops. 629let isCommutable = 1 in { 630defm NAND8: XForm_6r<31, 476, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 631 "nand", "$RA, $RST, $RB", IIC_IntSimple, 632 [(set i64:$RA, (not (and i64:$RST, i64:$RB)))]>; 633defm AND8 : XForm_6r<31, 28, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 634 "and", "$RA, $RST, $RB", IIC_IntSimple, 635 [(set i64:$RA, (and i64:$RST, i64:$RB))]>; 636} // isCommutable 637defm ANDC8: XForm_6r<31, 60, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 638 "andc", "$RA, $RST, $RB", IIC_IntSimple, 639 [(set i64:$RA, (and i64:$RST, (not i64:$RB)))]>; 640let isCommutable = 1 in { 641defm OR8 : XForm_6r<31, 444, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 642 "or", "$RA, $RST, $RB", IIC_IntSimple, 643 [(set i64:$RA, (or i64:$RST, i64:$RB))]>; 644defm NOR8 : XForm_6r<31, 124, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 645 "nor", "$RA, $RST, $RB", IIC_IntSimple, 646 [(set i64:$RA, (not (or i64:$RST, i64:$RB)))]>; 647} // isCommutable 648defm ORC8 : XForm_6r<31, 412, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 649 "orc", "$RA, $RST, $RB", IIC_IntSimple, 650 [(set i64:$RA, (or i64:$RST, (not i64:$RB)))]>; 651let isCommutable = 1 in { 652defm EQV8 : XForm_6r<31, 284, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 653 "eqv", "$RA, $RST, $RB", IIC_IntSimple, 654 [(set i64:$RA, (not (xor i64:$RST, i64:$RB)))]>; 655defm XOR8 : XForm_6r<31, 316, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 656 "xor", "$RA, $RST, $RB", IIC_IntSimple, 657 [(set i64:$RA, (xor i64:$RST, i64:$RB))]>; 658} // let isCommutable = 1 659 660// Logical ops with immediate. 661let Defs = [CR0] in { 662def ANDI8_rec : DForm_4<28, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), 663 "andi. $RA, $RST, $D", IIC_IntGeneral, 664 [(set i64:$RA, (and i64:$RST, immZExt16:$D))]>, 665 isRecordForm, SExt32To64, ZExt32To64; 666def ANDIS8_rec : DForm_4<29, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), 667 "andis. $RA, $RST, $D", IIC_IntGeneral, 668 [(set i64:$RA, (and i64:$RST, imm16ShiftedZExt:$D))]>, 669 isRecordForm, ZExt32To64; 670} 671def ORI8 : DForm_4<24, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), 672 "ori $RA, $RST, $D", IIC_IntSimple, 673 [(set i64:$RA, (or i64:$RST, immZExt16:$D))]>; 674def ORIS8 : DForm_4<25, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), 675 "oris $RA, $RST, $D", IIC_IntSimple, 676 [(set i64:$RA, (or i64:$RST, imm16ShiftedZExt:$D))]>; 677def XORI8 : DForm_4<26, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), 678 "xori $RA, $RST, $D", IIC_IntSimple, 679 [(set i64:$RA, (xor i64:$RST, immZExt16:$D))]>; 680def XORIS8 : DForm_4<27, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), 681 "xoris $RA, $RST, $D", IIC_IntSimple, 682 [(set i64:$RA, (xor i64:$RST, imm16ShiftedZExt:$D))]>; 683 684let isCommutable = 1 in 685defm ADD8 : XOForm_1rx<31, 266, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 686 "add", "$RT, $RA, $RB", IIC_IntSimple, 687 [(set i64:$RT, (add i64:$RA, i64:$RB))]>; 688// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 689// initial-exec thread-local storage model. We need to forbid r0 here - 690// while it works for add just fine, the linker can relax this to local-exec 691// addi, which won't work for r0. 692def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc_nox0:$RA, tlsreg:$RB), 693 "add $RT, $RA, $RB", IIC_IntSimple, 694 [(set i64:$RT, (add i64:$RA, tglobaltlsaddr:$RB))]>; 695let mayLoad = 1 in { 696def LBZXTLS : XForm_1<31, 87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 697 "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>; 698def LHZXTLS : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 699 "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>; 700def LHAXTLS : XForm_1<31, 343, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 701 "lhax $RST, $RA, $RB", IIC_LdStLoad, []>; 702def LWZXTLS : XForm_1<31, 23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 703 "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>; 704def LWAXTLS : XForm_1<31, 341, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 705 "lwax $RST, $RA, $RB", IIC_LdStLoad, []>; 706def LDXTLS : XForm_1<31, 21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 707 "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64; 708def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 709 "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>; 710def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 711 "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>; 712def LHAXTLS_32 : XForm_1<31, 343, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 713 "lhax $RST, $RA, $RB", IIC_LdStLoad, []>; 714def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 715 "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>; 716def LWAXTLS_32 : XForm_1<31, 341, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 717 "lwax $RST, $RA, $RB", IIC_LdStLoad, []>; 718 719} 720let mayLoad = 1, Predicates = [HasFPU] in { 721def LFSXTLS : XForm_25<31, 535, (outs f4rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 722 "lfsx $RST, $RA, $RB", IIC_LdStLFD, []>; 723def LFDXTLS : XForm_25<31, 599, (outs f8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 724 "lfdx $RST, $RA, $RB", IIC_LdStLFD, []>; 725} 726 727let mayStore = 1 in { 728def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 729 "stbx $RST, $RA, $RB", IIC_LdStStore, []>, 730 PPC970_DGroup_Cracked; 731def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 732 "sthx $RST, $RA, $RB", IIC_LdStStore, []>, 733 PPC970_DGroup_Cracked; 734def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 735 "stwx $RST, $RA, $RB", IIC_LdStStore, []>, 736 PPC970_DGroup_Cracked; 737def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 738 "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64, 739 PPC970_DGroup_Cracked; 740def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 741 "stbx $RST, $RA, $RB", IIC_LdStStore, []>, 742 PPC970_DGroup_Cracked; 743def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 744 "sthx $RST, $RA, $RB", IIC_LdStStore, []>, 745 PPC970_DGroup_Cracked; 746def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 747 "stwx $RST, $RA, $RB", IIC_LdStStore, []>, 748 PPC970_DGroup_Cracked; 749 750} 751let mayStore = 1, Predicates = [HasFPU] in { 752def STFSXTLS : XForm_8<31, 663, (outs), (ins f4rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 753 "stfsx $RST, $RA, $RB", IIC_LdStSTFD, []>, 754 PPC970_DGroup_Cracked; 755def STFDXTLS : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 756 "stfdx $RST, $RA, $RB", IIC_LdStSTFD, []>, 757 PPC970_DGroup_Cracked; 758} 759 760let isCommutable = 1 in 761defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 762 "addc", "$RT, $RA, $RB", IIC_IntGeneral, 763 [(set i64:$RT, (addc i64:$RA, i64:$RB))]>, 764 PPC970_DGroup_Cracked; 765 766let Defs = [CARRY] in 767def ADDIC8 : DForm_2<12, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D), 768 "addic $RST, $RA, $D", IIC_IntGeneral, 769 [(set i64:$RST, (addc i64:$RA, imm64SExt16:$D))]>; 770def ADDI8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D), 771 "addi $RST, $RA, $D", IIC_IntSimple, 772 [(set i64:$RST, (add i64:$RA, imm64SExt16:$D))]>; 773def ADDIS8 : DForm_2<15, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s17imm64:$D), 774 "addis $RST, $RA, $D", IIC_IntSimple, 775 [(set i64:$RST, (add i64:$RA, imm16ShiftedSExt:$D))]>; 776 777def LA8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D), 778 "la $RST, $D($RA)", IIC_IntGeneral, 779 [(set i64:$RST, (add i64:$RA, 780 (PPClo tglobaladdr:$D, 0)))]>, MemriOp; 781 782let Defs = [CARRY] in { 783def SUBFIC8: DForm_2< 8, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D), 784 "subfic $RST, $RA, $D", IIC_IntGeneral, 785 [(set i64:$RST, (subc imm64SExt16:$D, i64:$RA))]>; 786} 787defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 788 "subfc", "$RT, $RA, $RB", IIC_IntGeneral, 789 [(set i64:$RT, (subc i64:$RB, i64:$RA))]>, 790 PPC970_DGroup_Cracked; 791defm SUBF8 : XOForm_1rx<31, 40, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 792 "subf", "$RT, $RA, $RB", IIC_IntGeneral, 793 [(set i64:$RT, (sub i64:$RB, i64:$RA))]>; 794defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$RT), (ins g8rc:$RA), 795 "neg", "$RT, $RA", IIC_IntSimple, 796 [(set i64:$RT, (ineg i64:$RA))]>; 797let Uses = [CARRY] in { 798let isCommutable = 1 in 799defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 800 "adde", "$RT, $RA, $RB", IIC_IntGeneral, 801 [(set i64:$RT, (adde i64:$RA, i64:$RB))]>; 802defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$RT), (ins g8rc:$RA), 803 "addme", "$RT, $RA", IIC_IntGeneral, 804 [(set i64:$RT, (adde i64:$RA, -1))]>; 805defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$RT), (ins g8rc:$RA), 806 "addze", "$RT, $RA", IIC_IntGeneral, 807 [(set i64:$RT, (adde i64:$RA, 0))]>; 808defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 809 "subfe", "$RT, $RA, $RB", IIC_IntGeneral, 810 [(set i64:$RT, (sube i64:$RB, i64:$RA))]>; 811defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$RT), (ins g8rc:$RA), 812 "subfme", "$RT, $RA", IIC_IntGeneral, 813 [(set i64:$RT, (sube -1, i64:$RA))]>; 814defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$RT), (ins g8rc:$RA), 815 "subfze", "$RT, $RA", IIC_IntGeneral, 816 [(set i64:$RT, (sube 0, i64:$RA))]>; 817} 818} // isCodeGenOnly 819 820// FIXME: Duplicating this for the asm parser should be unnecessary, but the 821// previous definition must be marked as CodeGen only to prevent decoding 822// conflicts. 823let isAsmParserOnly = 1 in { 824def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc:$RA, tlsreg:$RB), 825 "add $RT, $RA, $RB", IIC_IntSimple, []>; 826 827let mayLoad = 1 in { 828def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 829 "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>; 830def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 831 "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>; 832def LHAXTLS_ : XForm_1<31, 343, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 833 "lhax $RST, $RA, $RB", IIC_LdStLoad, []>; 834def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 835 "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>; 836def LWAXTLS_ : XForm_1<31, 341, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 837 "lwax $RST, $RA, $RB", IIC_LdStLoad, []>; 838def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 839 "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64; 840} 841 842let mayLoad = 1, Predicates = [HasFPU] in { 843def LFSXTLS_ : XForm_25<31, 535, (outs f4rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 844 "lfsx $RST, $RA, $RB", IIC_LdStLFD, []>; 845def LFDXTLS_ : XForm_25<31, 599, (outs f8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 846 "lfdx $RST, $RA, $RB", IIC_LdStLFD, []>; 847} 848 849let mayStore = 1 in { 850def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 851 "stbx $RST, $RA, $RB", IIC_LdStStore, []>, 852 PPC970_DGroup_Cracked; 853def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 854 "sthx $RST, $RA, $RB", IIC_LdStStore, []>, 855 PPC970_DGroup_Cracked; 856def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 857 "stwx $RST, $RA, $RB", IIC_LdStStore, []>, 858 PPC970_DGroup_Cracked; 859def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 860 "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64, 861 PPC970_DGroup_Cracked; 862} 863 864let mayStore = 1, Predicates = [HasFPU] in { 865def STFSXTLS_ : XForm_8<31, 663, (outs), (ins f4rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 866 "stfsx $RST, $RA, $RB", IIC_LdStSTFD, []>, 867 PPC970_DGroup_Cracked; 868def STFDXTLS_ : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 869 "stfdx $RST, $RA, $RB", IIC_LdStSTFD, []>, 870 PPC970_DGroup_Cracked; 871} 872} 873 874let isCommutable = 1 in { 875defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 876 "mulhd", "$RT, $RA, $RB", IIC_IntMulHW, 877 [(set i64:$RT, (mulhs i64:$RA, i64:$RB))]>; 878defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 879 "mulhdu", "$RT, $RA, $RB", IIC_IntMulHWU, 880 [(set i64:$RT, (mulhu i64:$RA, i64:$RB))]>; 881} // isCommutable 882} 883} // Interpretation64Bit 884 885let isCompare = 1, hasSideEffects = 0 in { 886 def CMPD : XForm_16_ext<31, 0, (outs crrc:$BF), (ins g8rc:$RA, g8rc:$RB), 887 "cmpd $BF, $RA, $RB", IIC_IntCompare>, isPPC64; 888 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$BF), (ins g8rc:$RA, g8rc:$RB), 889 "cmpld $BF, $RA, $RB", IIC_IntCompare>, isPPC64; 890 def CMPDI : DForm_5_ext<11, (outs crrc:$BF), (ins g8rc:$RA, s16imm64:$D), 891 "cmpdi $BF, $RA, $D", IIC_IntCompare>, isPPC64; 892 def CMPLDI : DForm_6_ext<10, (outs crrc:$BF), (ins g8rc:$RA, u16imm64:$D), 893 "cmpldi $BF, $RA, $D", 894 IIC_IntCompare>, isPPC64; 895 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 896 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 897 (ins u1imm:$L, g8rc:$RA, g8rc:$RB), 898 "cmprb $BF, $L, $RA, $RB", IIC_IntCompare, []>, 899 Requires<[IsISA3_0]>; 900 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crrc:$BF), 901 (ins g8rc:$RA, g8rc:$RB), "cmpeqb $BF, $RA, $RB", 902 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 903} 904 905let hasSideEffects = 0 in { 906defm SLD : XForm_6r<31, 27, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB), 907 "sld", "$RA, $RST, $RB", IIC_IntRotateD, 908 [(set i64:$RA, (PPCshl i64:$RST, i32:$RB))]>, isPPC64; 909defm SRD : XForm_6r<31, 539, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB), 910 "srd", "$RA, $RST, $RB", IIC_IntRotateD, 911 [(set i64:$RA, (PPCsrl i64:$RST, i32:$RB))]>, isPPC64; 912defm SRAD : XForm_6rc<31, 794, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB), 913 "srad", "$RA, $RST, $RB", IIC_IntRotateD, 914 [(set i64:$RA, (PPCsra i64:$RST, i32:$RB))]>, isPPC64; 915 916let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 917defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$RA), (ins g8rc:$RST), 918 "cntlzw", "$RA, $RST", IIC_IntGeneral, []>, 919 ZExt32To64, SExt32To64; 920defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$RA), (ins g8rc:$RST), 921 "cnttzw", "$RA, $RST", IIC_IntGeneral, []>, 922 Requires<[IsISA3_0]>, ZExt32To64, SExt32To64; 923 924defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$RA), (ins g8rc:$RST), 925 "extsb", "$RA, $RST", IIC_IntSimple, 926 [(set i64:$RA, (sext_inreg i64:$RST, i8))]>, SExt32To64; 927defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$RA), (ins g8rc:$RST), 928 "extsh", "$RA, $RST", IIC_IntSimple, 929 [(set i64:$RA, (sext_inreg i64:$RST, i16))]>, SExt32To64; 930 931defm SLW8 : XForm_6r<31, 24, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 932 "slw", "$RA, $RST, $RB", IIC_IntGeneral, []>, ZExt32To64; 933defm SRW8 : XForm_6r<31, 536, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 934 "srw", "$RA, $RST, $RB", IIC_IntGeneral, []>, ZExt32To64; 935 936defm SRAW8 : XForm_6rc<31, 792, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 937 "sraw", "$RA, $RST, $RB", IIC_IntShift, 938 []>, SExt32To64; 939 940defm SRAWI8 : XForm_10rc<31, 824, (outs g8rc:$RA), (ins g8rc:$RST, u5imm:$RB), 941 "srawi", "$RA, $RST, $RB", IIC_IntShift, []>, SExt32To64; 942 943} // Interpretation64Bit 944 945// For fast-isel: 946let isCodeGenOnly = 1 in { 947def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$RA), (ins gprc:$RST), 948 "extsb $RA, $RST", IIC_IntSimple, []>, isPPC64, 949 SExt32To64; 950def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$RA), (ins gprc:$RST), 951 "extsh $RA, $RST", IIC_IntSimple, []>, isPPC64, 952 SExt32To64; 953} // isCodeGenOnly for fast-isel 954 955defm EXTSW : XForm_11r<31, 986, (outs g8rc:$RA), (ins g8rc:$RST), 956 "extsw", "$RA, $RST", IIC_IntSimple, 957 [(set i64:$RA, (sext_inreg i64:$RST, i32))]>, isPPC64, 958 SExt32To64; 959let Interpretation64Bit = 1, isCodeGenOnly = 1 in 960defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$RA), (ins gprc:$RST), 961 "extsw", "$RA, $RST", IIC_IntSimple, 962 [(set i64:$RA, (sext i32:$RST))]>, isPPC64, 963 SExt32To64; 964let isCodeGenOnly = 1 in 965def EXTSW_32 : XForm_11<31, 986, (outs gprc:$RA), (ins gprc:$RST), 966 "extsw $RA, $RST", IIC_IntSimple, 967 []>, isPPC64; 968 969defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH), 970 "sradi", "$RA, $RS, $SH", IIC_IntRotateDI, 971 [(set i64:$RA, (sra i64:$RS, (i32 imm:$SH)))]>, isPPC64; 972 973let Interpretation64Bit = 1, isCodeGenOnly = 1 in 974defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$RA), 975 (ins gprc:$RS, u6imm:$SH), 976 "extswsli", "$RA, $RS, $SH", IIC_IntRotateDI, 977 [(set i64:$RA, 978 (PPCextswsli i32:$RS, (i32 imm:$SH)))]>, 979 isPPC64, Requires<[IsISA3_0]>; 980 981defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH), 982 "extswsli", "$RA, $RS, $SH", IIC_IntRotateDI, 983 []>, isPPC64, Requires<[IsISA3_0]>; 984 985// For fast-isel: 986let isCodeGenOnly = 1, Defs = [CARRY] in 987def SRADI_32 : XSForm_1<31, 413, (outs gprc:$RA), (ins gprc:$RS, u6imm:$SH), 988 "sradi $RA, $RS, $SH", IIC_IntRotateDI, []>, isPPC64; 989 990defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$RA), (ins g8rc:$RST), 991 "cntlzd", "$RA, $RST", IIC_IntGeneral, 992 [(set i64:$RA, (ctlz i64:$RST))]>, 993 ZExt32To64, SExt32To64; 994defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$RA), (ins g8rc:$RST), 995 "cnttzd", "$RA, $RST", IIC_IntGeneral, 996 [(set i64:$RA, (cttz i64:$RST))]>, Requires<[IsISA3_0]>, 997 ZExt32To64, SExt32To64; 998def POPCNTD : XForm_11<31, 506, (outs g8rc:$RA), (ins g8rc:$RST), 999 "popcntd $RA, $RST", IIC_IntGeneral, 1000 [(set i64:$RA, (ctpop i64:$RST))]>, 1001 ZExt32To64, SExt32To64; 1002def BPERMD : XForm_6<31, 252, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1003 "bpermd $RA, $RST, $RB", IIC_IntGeneral, 1004 [(set i64:$RA, (int_ppc_bpermd g8rc:$RST, g8rc:$RB))]>, 1005 isPPC64, Requires<[HasBPERMD]>; 1006 1007let isCodeGenOnly = 1, isCommutable = 1 in 1008def CMPB8 : XForm_6<31, 508, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1009 "cmpb $RA, $RST, $RB", IIC_IntGeneral, 1010 [(set i64:$RA, (PPCcmpb i64:$RST, i64:$RB))]>; 1011 1012// popcntw also does a population count on the high 32 bits (storing the 1013// results in the high 32-bits of the output). We'll ignore that here (which is 1014// safe because we never separately use the high part of the 64-bit registers). 1015def POPCNTW : XForm_11<31, 378, (outs gprc:$RA), (ins gprc:$RST), 1016 "popcntw $RA, $RST", IIC_IntGeneral, 1017 [(set i32:$RA, (ctpop i32:$RST))]>; 1018 1019let isCodeGenOnly = 1 in { 1020def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$RA), (ins g8rc:$RST), 1021 "popcntb $RA, $RST", IIC_IntGeneral, 1022 [(set i64:$RA, (int_ppc_popcntb i64:$RST))]>; 1023 1024def CDTBCD8 : XForm_11<31, 282, (outs g8rc:$RA), (ins g8rc:$RST), 1025 "cdtbcd $RA, $RST", IIC_IntGeneral, 1026 [(set i64:$RA, (int_ppc_cdtbcdd i64:$RST))]>; 1027def CBCDTD8 : XForm_11<31, 314, (outs g8rc:$RA), (ins g8rc:$RST), 1028 "cbcdtd $RA, $RST", IIC_IntGeneral, 1029 [(set i64:$RA, (int_ppc_cbcdtdd i64:$RST))]>; 1030def ADDG6S8 : XOForm_1<31, 74, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 1031 "addg6s $RT, $RA, $RB", IIC_IntGeneral, 1032 [(set i64:$RT, (int_ppc_addg6sd i64:$RA, i64:$RB))]>; 1033} 1034 1035defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 1036 "divd", "$RT, $RA, $RB", IIC_IntDivD, 1037 [(set i64:$RT, (sdiv i64:$RA, i64:$RB))]>, isPPC64; 1038defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 1039 "divdu", "$RT, $RA, $RB", IIC_IntDivD, 1040 [(set i64:$RT, (udiv i64:$RA, i64:$RB))]>, isPPC64; 1041defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 1042 "divde", "$RT, $RA, $RB", IIC_IntDivD, 1043 [(set i64:$RT, (int_ppc_divde g8rc:$RA, g8rc:$RB))]>, 1044 isPPC64, Requires<[HasExtDiv]>; 1045 1046let Predicates = [IsISA3_0] in { 1047def MADDHD : VAForm_1a<48, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 1048 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 1049def MADDHDU : VAForm_1a<49, 1050 (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 1051 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 1052def MADDLD : VAForm_1a<51, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 1053 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 1054 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 1055 isPPC64; 1056let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1057 def MADDLD8 : VAForm_1a<51, 1058 (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 1059 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 1060 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 1061 isPPC64; 1062 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 1063 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64, SExt32To64; 1064} 1065def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 1066 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 1067def MODSD : XForm_8<31, 777, (outs g8rc:$RST), (ins g8rc:$RA, g8rc:$RB), 1068 "modsd $RST, $RA, $RB", IIC_IntDivW, 1069 [(set i64:$RST, (srem i64:$RA, i64:$RB))]>; 1070def MODUD : XForm_8<31, 265, (outs g8rc:$RST), (ins g8rc:$RA, g8rc:$RB), 1071 "modud $RST, $RA, $RB", IIC_IntDivW, 1072 [(set i64:$RST, (urem i64:$RA, i64:$RB))]>; 1073} 1074 1075defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 1076 "divdeu", "$RT, $RA, $RB", IIC_IntDivD, 1077 [(set i64:$RT, (int_ppc_divdeu g8rc:$RA, g8rc:$RB))]>, 1078 isPPC64, Requires<[HasExtDiv]>; 1079let isCommutable = 1 in 1080defm MULLD : XOForm_1rx<31, 233, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 1081 "mulld", "$RT, $RA, $RB", IIC_IntMulHD, 1082 [(set i64:$RT, (mul i64:$RA, i64:$RB))]>, isPPC64; 1083let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1084def MULLI8 : DForm_2<7, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D), 1085 "mulli $RST, $RA, $D", IIC_IntMulLI, 1086 [(set i64:$RST, (mul i64:$RA, imm64SExt16:$D))]>; 1087} 1088 1089let hasSideEffects = 1 in { 1090def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L), 1091 "darn $RT, $L", IIC_LdStLD>, isPPC64; 1092} 1093 1094let hasSideEffects = 0 in { 1095defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$RA), 1096 (ins g8rc:$RAi, g8rc:$RS, u6imm:$SH, u6imm:$MBE), 1097 "rldimi", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI, 1098 []>, isPPC64, RegConstraint<"$RAi = $RA">, 1099 NoEncode<"$RAi">; 1100 1101// Rotate instructions. 1102defm RLDCL : MDSForm_1r<30, 8, 1103 (outs g8rc:$RA), (ins g8rc:$RS, gprc:$RB, u6imm:$MBE), 1104 "rldcl", "$RA, $RS, $RB, $MBE", IIC_IntRotateD, 1105 []>, isPPC64; 1106defm RLDCR : MDSForm_1r<30, 9, 1107 (outs g8rc:$RA), (ins g8rc:$RS, gprc:$RB, u6imm:$MBE), 1108 "rldcr", "$RA, $RS, $RB, $MBE", IIC_IntRotateD, 1109 []>, isPPC64; 1110defm RLDICL : MDForm_1r<30, 0, 1111 (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE), 1112 "rldicl", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI, 1113 []>, isPPC64; 1114// For fast-isel: 1115let isCodeGenOnly = 1 in 1116def RLDICL_32_64 : MDForm_1<30, 0, 1117 (outs g8rc:$RA), 1118 (ins gprc:$RS, u6imm:$SH, u6imm:$MBE), 1119 "rldicl $RA, $RS, $SH, $MBE", IIC_IntRotateDI, 1120 []>, isPPC64; 1121// End fast-isel. 1122let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1123defm RLDICL_32 : MDForm_1r<30, 0, 1124 (outs gprc:$RA), 1125 (ins gprc:$RS, u6imm:$SH, u6imm:$MBE), 1126 "rldicl", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI, 1127 []>, isPPC64; 1128defm RLDICR : MDForm_1r<30, 1, 1129 (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE), 1130 "rldicr", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI, 1131 []>, isPPC64; 1132let isCodeGenOnly = 1 in 1133def RLDICR_32 : MDForm_1<30, 1, 1134 (outs gprc:$RA), (ins gprc:$RS, u6imm:$SH, u6imm:$MBE), 1135 "rldicr $RA, $RS, $SH, $MBE", IIC_IntRotateDI, 1136 []>, isPPC64; 1137defm RLDIC : MDForm_1r<30, 2, 1138 (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE), 1139 "rldic", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI, 1140 []>, isPPC64; 1141 1142let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1143defm RLWINM8 : MForm_2r<21, (outs g8rc:$RA), 1144 (ins g8rc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1145 "rlwinm", "$RA, $RS, $SH, $MB, $ME", IIC_IntGeneral, 1146 []>; 1147 1148defm RLWNM8 : MForm_1r<23, (outs g8rc:$RA), 1149 (ins g8rc:$RS, g8rc:$RB, u5imm:$MB, u5imm:$ME), 1150 "rlwnm", "$RA, $RS, $RB, $MB, $ME", IIC_IntGeneral, 1151 []>; 1152 1153// RLWIMI can be commuted if the rotate amount is zero. 1154let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1155defm RLWIMI8 : MForm_2r<20, (outs g8rc:$RA), 1156 (ins g8rc:$RAi, g8rc:$RS, u5imm:$SH, u5imm:$MB, 1157 u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME", 1158 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 1159 RegConstraint<"$RAi = $RA">, NoEncode<"$RAi">; 1160 1161let isSelect = 1 in 1162def ISEL8 : AForm_4<31, 15, 1163 (outs g8rc:$RT), (ins g8rc_nox0:$RA, g8rc:$RB, crbitrc:$COND), 1164 "isel $RT, $RA, $RB, $COND", IIC_IntISEL, 1165 []>; 1166} // Interpretation64Bit 1167} // hasSideEffects = 0 1168} // End FXU Operations. 1169 1170def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>; 1171def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>; 1172 1173def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1174def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1175 1176def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1177def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1178 1179def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 1180 1181def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1182def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1183def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1184def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1185 1186def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 1187def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 1188def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 1189def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 1190def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 1191def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 1192 1193def : InstAlias<"isellt $rT, $rA, $rB", 1194 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>; 1195def : InstAlias<"iselgt $rT, $rA, $rB", 1196 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>; 1197def : InstAlias<"iseleq $rT, $rA, $rB", 1198 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>; 1199 1200def : InstAlias<"nop", (ORI8 X0, X0, 0)>; 1201def : InstAlias<"xnop", (XORI8 X0, X0, 0)>; 1202 1203def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>; 1204def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>; 1205 1206def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>; 1207def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>; 1208 1209//Disable this alias on AIX for now because as does not support them. 1210let Predicates = [ModernAs] in { 1211 1212def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>; 1213def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>; 1214 1215def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>; 1216def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>; 1217 1218def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>; 1219def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>; 1220 1221def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>; 1222def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>; 1223 1224def : InstAlias<"mtuamr $Rx", (MTSPR8 13, g8rc:$Rx)>; 1225def : InstAlias<"mfuamr $Rx", (MFSPR8 g8rc:$Rx, 13)>; 1226 1227def : InstAlias<"mtdscr $Rx", (MTSPR8 17, g8rc:$Rx)>; 1228def : InstAlias<"mfdscr $Rx", (MFSPR8 g8rc:$Rx, 17)>; 1229 1230def : InstAlias<"mtdsisr $Rx", (MTSPR8 18, g8rc:$Rx)>; 1231def : InstAlias<"mfdsisr $Rx", (MFSPR8 g8rc:$Rx, 18)>; 1232 1233def : InstAlias<"mtdar $Rx", (MTSPR8 19, g8rc:$Rx)>; 1234def : InstAlias<"mfdar $Rx", (MFSPR8 g8rc:$Rx, 19)>; 1235 1236def : InstAlias<"mtdec $Rx", (MTSPR8 22, g8rc:$Rx)>; 1237def : InstAlias<"mfdec $Rx", (MFSPR8 g8rc:$Rx, 22)>; 1238 1239def : InstAlias<"mtsdr1 $Rx", (MTSPR8 25, g8rc:$Rx)>; 1240def : InstAlias<"mfsdr1 $Rx", (MFSPR8 g8rc:$Rx, 25)>; 1241 1242def : InstAlias<"mtsrr0 $Rx", (MTSPR8 26, g8rc:$Rx)>; 1243def : InstAlias<"mfsrr0 $Rx", (MFSPR8 g8rc:$Rx, 26)>; 1244 1245def : InstAlias<"mtsrr1 $Rx", (MTSPR8 27, g8rc:$Rx)>; 1246def : InstAlias<"mfsrr1 $Rx", (MFSPR8 g8rc:$Rx, 27)>; 1247 1248def : InstAlias<"mtcfar $Rx", (MTSPR8 28, g8rc:$Rx)>; 1249def : InstAlias<"mfcfar $Rx", (MFSPR8 g8rc:$Rx, 28)>; 1250 1251def : InstAlias<"mtamr $Rx", (MTSPR8 29, g8rc:$Rx)>; 1252def : InstAlias<"mfamr $Rx", (MFSPR8 g8rc:$Rx, 29)>; 1253 1254foreach SPRG = 0-3 in { 1255 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1256 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1257 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1258 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1259} 1260 1261def : InstAlias<"mfasr $RT", (MFSPR8 g8rc:$RT, 280)>; 1262def : InstAlias<"mtasr $RT", (MTSPR8 280, g8rc:$RT)>; 1263 1264def : InstAlias<"mttbl $Rx", (MTSPR8 284, g8rc:$Rx)>; 1265def : InstAlias<"mttbu $Rx", (MTSPR8 285, g8rc:$Rx)>; 1266 1267def : InstAlias<"mfpvr $RT", (MFSPR8 g8rc:$RT, 287)>; 1268 1269def : InstAlias<"mfspefscr $Rx", (MFSPR8 g8rc:$Rx, 512)>; 1270def : InstAlias<"mtspefscr $Rx", (MTSPR8 512, g8rc:$Rx)>; 1271 1272} 1273 1274//===----------------------------------------------------------------------===// 1275// Load/Store instructions. 1276// 1277 1278 1279// Sign extending loads. 1280let PPC970_Unit = 2 in { 1281let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1282def LHA8: DForm_1<42, (outs g8rc:$RST), (ins (memri $D, $RA):$addr), 1283 "lha $RST, $addr", IIC_LdStLHA, 1284 [(set i64:$RST, (sextloadi16 DForm:$addr))]>, 1285 PPC970_DGroup_Cracked, SExt32To64; 1286def LWA : DSForm_1<58, 2, (outs g8rc:$RST), (ins (memrix $D, $RA):$addr), 1287 "lwa $RST, $addr", IIC_LdStLWA, 1288 [(set i64:$RST, 1289 (sextloadi32 DSForm:$addr))]>, isPPC64, 1290 PPC970_DGroup_Cracked, SExt32To64; 1291let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1292def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1293 "lhax $RST, $addr", IIC_LdStLHA, 1294 [(set i64:$RST, (sextloadi16 XForm:$addr))]>, 1295 PPC970_DGroup_Cracked, SExt32To64; 1296def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1297 "lwax $RST, $addr", IIC_LdStLHA, 1298 [(set i64:$RST, (sextloadi32 XForm:$addr))]>, isPPC64, 1299 PPC970_DGroup_Cracked, SExt32To64; 1300// For fast-isel: 1301let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { 1302def LWA_32 : DSForm_1<58, 2, (outs gprc:$RST), (ins (memrix $D, $RA):$addr), 1303 "lwa $RST, $addr", IIC_LdStLWA, []>, isPPC64, 1304 PPC970_DGroup_Cracked, SExt32To64; 1305def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1306 "lwax $RST, $addr", IIC_LdStLHA, []>, isPPC64, 1307 PPC970_DGroup_Cracked, SExt32To64; 1308} // end fast-isel isCodeGenOnly 1309 1310// Update forms. 1311let mayLoad = 1, hasSideEffects = 0 in { 1312let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1313def LHAU8 : DForm_1<43, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1314 (ins (memri $D, $RA):$addr), 1315 "lhau $RST, $addr", IIC_LdStLHAU, 1316 []>, RegConstraint<"$addr.reg = $ea_result">, 1317 NoEncode<"$ea_result">; 1318// NO LWAU! 1319 1320let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1321def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1322 (ins (memrr $RA, $RB):$addr), 1323 "lhaux $RST, $addr", IIC_LdStLHAUX, 1324 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1325 NoEncode<"$ea_result">; 1326def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1327 (ins (memrr $RA, $RB):$addr), 1328 "lwaux $RST, $addr", IIC_LdStLHAUX, 1329 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1330 NoEncode<"$ea_result">, isPPC64; 1331} 1332} 1333 1334let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1335// Zero extending loads. 1336let PPC970_Unit = 2 in { 1337def LBZ8 : DForm_1<34, (outs g8rc:$RST), (ins (memri $D, $RA):$addr), 1338 "lbz $RST, $addr", IIC_LdStLoad, 1339 [(set i64:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64, 1340 SExt32To64; 1341def LHZ8 : DForm_1<40, (outs g8rc:$RST), (ins (memri $D, $RA):$addr), 1342 "lhz $RST, $addr", IIC_LdStLoad, 1343 [(set i64:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64, 1344 SExt32To64; 1345def LWZ8 : DForm_1<32, (outs g8rc:$RST), (ins (memri $D, $RA):$addr), 1346 "lwz $RST, $addr", IIC_LdStLoad, 1347 [(set i64:$RST, (zextloadi32 DForm:$addr))]>, isPPC64, 1348 ZExt32To64; 1349 1350def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1351 "lbzx $RST, $addr", IIC_LdStLoad, 1352 [(set i64:$RST, (zextloadi8 XForm:$addr))]>, ZExt32To64, 1353 SExt32To64; 1354def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1355 "lhzx $RST, $addr", IIC_LdStLoad, 1356 [(set i64:$RST, (zextloadi16 XForm:$addr))]>, 1357 ZExt32To64, SExt32To64; 1358def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1359 "lwzx $RST, $addr", IIC_LdStLoad, 1360 [(set i64:$RST, (zextloadi32 XForm:$addr))]>, 1361 ZExt32To64; 1362 1363 1364// Update forms. 1365let mayLoad = 1, hasSideEffects = 0 in { 1366def LBZU8 : DForm_1<35, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1367 (ins (memri $D, $RA):$addr), 1368 "lbzu $RST, $addr", IIC_LdStLoadUpd, 1369 []>, RegConstraint<"$addr.reg = $ea_result">, 1370 NoEncode<"$ea_result">; 1371def LHZU8 : DForm_1<41, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1372 (ins (memri $D, $RA):$addr), 1373 "lhzu $RST, $addr", IIC_LdStLoadUpd, 1374 []>, RegConstraint<"$addr.reg = $ea_result">, 1375 NoEncode<"$ea_result">; 1376def LWZU8 : DForm_1<33, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1377 (ins (memri $D, $RA):$addr), 1378 "lwzu $RST, $addr", IIC_LdStLoadUpd, 1379 []>, RegConstraint<"$addr.reg = $ea_result">, 1380 NoEncode<"$ea_result">; 1381 1382def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1383 (ins (memrr $RA, $RB):$addr), 1384 "lbzux $RST, $addr", IIC_LdStLoadUpdX, 1385 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1386 NoEncode<"$ea_result">; 1387def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1388 (ins (memrr $RA, $RB):$addr), 1389 "lhzux $RST, $addr", IIC_LdStLoadUpdX, 1390 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1391 NoEncode<"$ea_result">; 1392def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1393 (ins (memrr $RA, $RB):$addr), 1394 "lwzux $RST, $addr", IIC_LdStLoadUpdX, 1395 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1396 NoEncode<"$ea_result">; 1397} 1398} 1399} // Interpretation64Bit 1400 1401 1402// Full 8-byte loads. 1403let PPC970_Unit = 2 in { 1404def LD : DSForm_1<58, 0, (outs g8rc:$RST), (ins (memrix $D, $RA):$addr), 1405 "ld $RST, $addr", IIC_LdStLD, 1406 [(set i64:$RST, (load DSForm:$addr))]>, isPPC64; 1407// The following four definitions are selected for small code model only. 1408// Otherwise, we need to create two instructions to form a 32-bit offset, 1409// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1410def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1411 "#LDtoc", 1412 [(set i64:$rD, 1413 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1414def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1415 "#LDtocJTI", 1416 [(set i64:$rD, 1417 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1418def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1419 "#LDtocCPT", 1420 [(set i64:$rD, 1421 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1422def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1423 "#LDtocCPT", 1424 [(set i64:$rD, 1425 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1426 1427def LDX : XForm_1_memOp<31, 21, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1428 "ldx $RST, $addr", IIC_LdStLD, 1429 [(set i64:$RST, (load XForm:$addr))]>, isPPC64; 1430 1431let Predicates = [IsISA2_06] in { 1432def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1433 "ldbrx $RST, $addr", IIC_LdStLoad, 1434 [(set i64:$RST, (PPClbrx ForceXForm:$addr, i64))]>, isPPC64; 1435} 1436 1437let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1438def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1439 "lhbrx $RST, $addr", IIC_LdStLoad, []>, ZExt32To64; 1440def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1441 "lwbrx $RST, $addr", IIC_LdStLoad, []>, ZExt32To64; 1442} 1443 1444let mayLoad = 1, hasSideEffects = 0 in { 1445def LDU : DSForm_1<58, 1, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1446 (ins (memrix $D, $RA):$addr), 1447 "ldu $RST, $addr", IIC_LdStLDU, 1448 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1449 NoEncode<"$ea_result">; 1450 1451def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1452 (ins (memrr $RA, $RB):$addr), 1453 "ldux $RST, $addr", IIC_LdStLDUX, 1454 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1455 NoEncode<"$ea_result">, isPPC64; 1456} 1457 1458let mayLoad = 1, hasNoSchedulingInfo = 1 in { 1459// Full 16-byte load. 1460// Early clobber $RTp to avoid assigned to the same register as RA. 1461// TODO: Add scheduling info. 1462def LQ : DQForm_RTp5_RA17_MEM<56, 0, 1463 (outs g8prc:$RTp), 1464 (ins (memrix16 $DQ, $RA):$addr), 1465 "lq $RTp, $addr", IIC_LdStLQ, 1466 []>, 1467 RegConstraint<"@earlyclobber $RTp">, 1468 isPPC64; 1469// We don't really have LQX in the ISA, make a pseudo one so that we can 1470// handle x-form during isel. Make it pre-ra may expose 1471// oppotunities to some opts(CSE, LICM and etc.) for the result of adding 1472// RA and RB. 1473def LQX_PSEUDO : PPCCustomInserterPseudo<(outs g8prc:$RTp), 1474 (ins memrr:$src), "#LQX_PSEUDO", []>; 1475 1476def RESTORE_QUADWORD : PPCEmitTimePseudo<(outs g8prc:$RTp), (ins memrix:$src), 1477 "#RESTORE_QUADWORD", []>; 1478} 1479 1480} 1481 1482def : Pat<(int_ppc_atomic_load_i128 iaddrX16:$src), 1483 (SPLIT_QUADWORD (LQ memrix16:$src))>; 1484 1485def : Pat<(int_ppc_atomic_load_i128 ForceXForm:$src), 1486 (SPLIT_QUADWORD (LQX_PSEUDO memrr:$src))>; 1487 1488// Support for medium and large code model. 1489let hasSideEffects = 0 in { 1490let isReMaterializable = 1 in { 1491def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1492 "#ADDIStocHA8", []>, isPPC64; 1493def ADDItocL8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1494 "#ADDItocL8", []>, isPPC64; 1495} 1496 1497// Local Data Transform 1498def ADDItoc8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1499 "#ADDItoc8", 1500 []>, isPPC64; 1501let mayLoad = 1 in 1502def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1503 "#LDtocL", []>, isPPC64; 1504} 1505 1506// Support for thread-local storage. 1507def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1508 "#ADDISgotTprelHA", 1509 [(set i64:$rD, 1510 (PPCaddisGotTprelHA i64:$reg, 1511 tglobaltlsaddr:$disp))]>, 1512 isPPC64; 1513def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1514 "#LDgotTprelL", 1515 [(set i64:$rD, 1516 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1517 isPPC64; 1518 1519let Defs = [CR7], Itinerary = IIC_LdStSync in 1520def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1521 1522def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1523 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1524def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1525 "#ADDIStlsgdHA", 1526 [(set i64:$rD, 1527 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1528 isPPC64; 1529def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1530 "#ADDItlsgdL", 1531 [(set i64:$rD, 1532 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1533 isPPC64; 1534 1535class GETtlsADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1536 asmstr, 1537 [(set i64:$rD, 1538 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1539 isPPC64; 1540class GETtlsldADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1541 asmstr, 1542 [(set i64:$rD, 1543 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1544 isPPC64; 1545 1546let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1 in { 1547// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1548// explicitly defined when this op is created, so not mentioned here. 1549// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1550// correct because the branch select pass is relying on it. 1551let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1552def GETtlsADDR : GETtlsADDRPseudo <"#GETtlsADDR">; 1553let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1554def GETtlsADDRPCREL : GETtlsADDRPseudo <"#GETtlsADDRPCREL">; 1555 1556// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1557// explicitly defined when this op is created, so not mentioned here. 1558let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1559def GETtlsldADDR : GETtlsldADDRPseudo <"#GETtlsldADDR">; 1560let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1561def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">; 1562 1563// On AIX, the call to __tls_get_addr needs two inputs in X3/X4 for the 1564// offset and region handle respectively. The call is not followed by a nop 1565// so we don't need to mark it with a size of 8 bytes. Finally, the assembly 1566// manual mentions this exact set of registers as the clobbered set, others 1567// are guaranteed not to be clobbered. 1568let Defs = [X0,X4,X5,X11,LR8,CR0] in { 1569def GETtlsADDR64AIX : 1570 PPCEmitTimePseudo<(outs g8rc:$rD),(ins g8rc:$offset, g8rc:$handle), 1571 "GETtlsADDR64AIX", 1572 [(set i64:$rD, 1573 (PPCgetTlsAddr i64:$offset, i64:$handle))]>, isPPC64; 1574// On AIX, the call to .__tls_get_mod needs one input in X3 for the module handle. 1575def GETtlsMOD64AIX : 1576 PPCEmitTimePseudo<(outs g8rc:$rD),(ins g8rc:$handle), 1577 "GETtlsMOD64AIX", 1578 [(set i64:$rD, 1579 (PPCgetTlsMod i64:$handle))]>, isPPC64; 1580} 1581} 1582 1583// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1584// are true defines while the rest of the Defs are clobbers. 1585let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1586 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1587 in 1588def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1589 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1590 "#ADDItlsgdLADDR", 1591 [(set i64:$rD, 1592 (PPCaddiTlsgdLAddr i64:$reg, 1593 tglobaltlsaddr:$disp, 1594 tglobaltlsaddr:$sym))]>, 1595 isPPC64; 1596def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1597 "#ADDIStlsldHA", 1598 [(set i64:$rD, 1599 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1600 isPPC64; 1601def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1602 "#ADDItlsldL", 1603 [(set i64:$rD, 1604 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1605 isPPC64; 1606// This pseudo is expanded to two copies to put the variable offset in R4 and 1607// the region handle in R3 and GETtlsADDR64AIX. 1608def TLSGDAIX8 : 1609 PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$offset, g8rc:$handle), 1610 "#TLSGDAIX8", 1611 [(set i64:$rD, 1612 (PPCTlsgdAIX i64:$offset, i64:$handle))]>; 1613// This pseudo is expanded to the call to GETtlsMOD64AIX. 1614def TLSLDAIX8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$handle), 1615 "#TLSLDAIX8", [(set i64:$rD, (PPCTlsldAIX i64:$handle))]>; 1616// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1617// are true defines, while the rest of the Defs are clobbers. 1618let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1619 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1620 in 1621def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1622 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1623 "#ADDItlsldLADDR", 1624 [(set i64:$rD, 1625 (PPCaddiTlsldLAddr i64:$reg, 1626 tglobaltlsaddr:$disp, 1627 tglobaltlsaddr:$sym))]>, 1628 isPPC64; 1629def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1630 "#ADDISdtprelHA", 1631 [(set i64:$rD, 1632 (PPCaddisDtprelHA i64:$reg, 1633 tglobaltlsaddr:$disp))]>, 1634 isPPC64; 1635def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1636 "#ADDIdtprelL", 1637 [(set i64:$rD, 1638 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1639 isPPC64; 1640def PADDIdtprel : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1641 "#PADDIdtprel", 1642 [(set i64:$rD, 1643 (PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>, 1644 isPPC64; 1645 1646let PPC970_Unit = 2 in { 1647let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1648// Truncating stores. 1649def STB8 : DForm_1<38, (outs), (ins g8rc:$RST, (memri $D, $RA):$addr), 1650 "stb $RST, $addr", IIC_LdStStore, 1651 [(truncstorei8 i64:$RST, DForm:$addr)]>; 1652def STH8 : DForm_1<44, (outs), (ins g8rc:$RST, (memri $D, $RA):$addr), 1653 "sth $RST, $addr", IIC_LdStStore, 1654 [(truncstorei16 i64:$RST, DForm:$addr)]>; 1655def STW8 : DForm_1<36, (outs), (ins g8rc:$RST, (memri $D, $RA):$addr), 1656 "stw $RST, $addr", IIC_LdStStore, 1657 [(truncstorei32 i64:$RST, DForm:$addr)]>; 1658def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1659 "stbx $RST, $addr", IIC_LdStStore, 1660 [(truncstorei8 i64:$RST, XForm:$addr)]>, 1661 PPC970_DGroup_Cracked; 1662def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1663 "sthx $RST, $addr", IIC_LdStStore, 1664 [(truncstorei16 i64:$RST, XForm:$addr)]>, 1665 PPC970_DGroup_Cracked; 1666def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1667 "stwx $RST, $addr", IIC_LdStStore, 1668 [(truncstorei32 i64:$RST, XForm:$addr)]>, 1669 PPC970_DGroup_Cracked; 1670} // Interpretation64Bit 1671 1672// Normal 8-byte stores. 1673def STD : DSForm_1<62, 0, (outs), (ins g8rc:$RST, (memrix $D, $RA):$addr), 1674 "std $RST, $addr", IIC_LdStSTD, 1675 [(store i64:$RST, DSForm:$addr)]>, isPPC64; 1676def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1677 "stdx $RST, $addr", IIC_LdStSTD, 1678 [(store i64:$RST, XForm:$addr)]>, isPPC64, 1679 PPC970_DGroup_Cracked; 1680 1681let Predicates = [IsISA2_06] in { 1682def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1683 "stdbrx $RST, $addr", IIC_LdStStore, 1684 [(PPCstbrx i64:$RST, ForceXForm:$addr, i64)]>, isPPC64, 1685 PPC970_DGroup_Cracked; 1686} 1687 1688let mayStore = 1, hasNoSchedulingInfo = 1 in { 1689// Normal 16-byte stores. 1690// TODO: Add scheduling info. 1691def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RST, (memrix $D, $RA):$addr), 1692 "stq $RST, $addr", IIC_LdStSTQ, 1693 []>, isPPC64; 1694 1695def STQX_PSEUDO : PPCCustomInserterPseudo<(outs), 1696 (ins g8prc:$RSp, memrr:$dst), 1697 "#STQX_PSEUDO", []>; 1698 1699def SPILL_QUADWORD : PPCEmitTimePseudo<(outs), (ins g8prc:$RSp, memrix:$dst), 1700 "#SPILL_QUADWORD", []>; 1701} 1702 1703} 1704 1705def BUILD_QUADWORD : PPCPostRAExpPseudo< 1706 (outs g8prc:$RTp), 1707 (ins g8rc:$lo, g8rc:$hi), 1708 "#BUILD_QUADWORD", []>; 1709 1710def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, DSForm:$dst), 1711 (STQ (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrix:$dst)>; 1712 1713def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, ForceXForm:$dst), 1714 (STQX_PSEUDO (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrr:$dst)>; 1715 1716// Stores with Update (pre-inc). 1717let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1718let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1719def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), 1720 "stbu $RST, $addr", IIC_LdStSTU, []>, 1721 RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">; 1722def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), 1723 "sthu $RST, $addr", IIC_LdStSTU, []>, 1724 RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">; 1725def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), 1726 "stwu $RST, $addr", IIC_LdStSTU, []>, 1727 RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">; 1728 1729def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1730 (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1731 "stbux $RST, $addr", IIC_LdStSTUX, []>, 1732 RegConstraint<"$addr.ptrreg = $ea_res">, 1733 NoEncode<"$ea_res">, 1734 PPC970_DGroup_Cracked; 1735def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1736 (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1737 "sthux $RST, $addr", IIC_LdStSTUX, []>, 1738 RegConstraint<"$addr.ptrreg = $ea_res">, 1739 NoEncode<"$ea_res">, 1740 PPC970_DGroup_Cracked; 1741def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1742 (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1743 "stwux $RST, $addr", IIC_LdStSTUX, []>, 1744 RegConstraint<"$addr.ptrreg = $ea_res">, 1745 NoEncode<"$ea_res">, 1746 PPC970_DGroup_Cracked; 1747} // Interpretation64Bit 1748 1749def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1750 (ins g8rc:$RST, (memrix $D, $RA):$addr), 1751 "stdu $RST, $addr", IIC_LdStSTU, []>, 1752 RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">, 1753 isPPC64; 1754 1755def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1756 (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1757 "stdux $RST, $addr", IIC_LdStSTUX, []>, 1758 RegConstraint<"$addr.ptrreg = $ea_res">, 1759 NoEncode<"$ea_res">, 1760 PPC970_DGroup_Cracked, isPPC64; 1761} 1762 1763// Patterns to match the pre-inc stores. We can't put the patterns on 1764// the instruction definitions directly as ISel wants the address base 1765// and offset to be separate operands, not a single complex operand. 1766def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1767 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1768def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1769 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1770def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1771 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1772def : Pat<(DSFormPreStore i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1773 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1774 1775def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1776 (STBUX8 $rS, $ptrreg, $ptroff)>; 1777def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1778 (STHUX8 $rS, $ptrreg, $ptroff)>; 1779def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1780 (STWUX8 $rS, $ptrreg, $ptroff)>; 1781def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1782 (STDUX $rS, $ptrreg, $ptroff)>; 1783 1784 1785//===----------------------------------------------------------------------===// 1786// Floating point instructions. 1787// 1788 1789 1790let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1, 1791 Uses = [RM] in { // FPU Operations. 1792defm FCFID : XForm_26r<63, 846, (outs f8rc:$RST), (ins f8rc:$RB), 1793 "fcfid", "$RST, $RB", IIC_FPGeneral, 1794 [(set f64:$RST, (PPCany_fcfid f64:$RB))]>, isPPC64; 1795defm FCTID : XForm_26r<63, 814, (outs f8rc:$RST), (ins f8rc:$RB), 1796 "fctid", "$RST, $RB", IIC_FPGeneral, 1797 []>, isPPC64; 1798defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$RST), (ins f8rc:$RB), 1799 "fctidu", "$RST, $RB", IIC_FPGeneral, 1800 []>, isPPC64; 1801defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$RST), (ins f8rc:$RB), 1802 "fctidz", "$RST, $RB", IIC_FPGeneral, 1803 [(set f64:$RST, (PPCany_fctidz f64:$RB))]>, isPPC64; 1804 1805defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$RST), (ins f8rc:$RB), 1806 "fcfidu", "$RST, $RB", IIC_FPGeneral, 1807 [(set f64:$RST, (PPCany_fcfidu f64:$RB))]>, isPPC64; 1808defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$RST), (ins f8rc:$RB), 1809 "fcfids", "$RST, $RB", IIC_FPGeneral, 1810 [(set f32:$RST, (PPCany_fcfids f64:$RB))]>, isPPC64; 1811defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$RST), (ins f8rc:$RB), 1812 "fcfidus", "$RST, $RB", IIC_FPGeneral, 1813 [(set f32:$RST, (PPCany_fcfidus f64:$RB))]>, isPPC64; 1814defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$RST), (ins f8rc:$RB), 1815 "fctiduz", "$RST, $RB", IIC_FPGeneral, 1816 [(set f64:$RST, (PPCany_fctiduz f64:$RB))]>, isPPC64; 1817defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$RST), (ins f8rc:$RB), 1818 "fctiwuz", "$RST, $RB", IIC_FPGeneral, 1819 [(set f64:$RST, (PPCany_fctiwuz f64:$RB))]>, isPPC64; 1820} 1821 1822// These instructions store a hash computed from the value of the link register 1823// and the value of the stack pointer. 1824let mayStore = 1, Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1825def HASHST8 : XForm_XD6_RA5_RB5<31, 722, (outs), 1826 (ins g8rc:$RB, (memrihash $D, $RA):$addr), 1827 "hashst $RB, $addr", IIC_IntGeneral, []>; 1828def HASHSTP8 : XForm_XD6_RA5_RB5<31, 658, (outs), 1829 (ins g8rc:$RB, (memrihash $D, $RA):$addr), 1830 "hashstp $RB, $addr", IIC_IntGeneral, []>; 1831} 1832 1833// These instructions check a hash computed from the value of the link register 1834// and the value of the stack pointer. The hasSideEffects flag is needed as the 1835// instruction may TRAP if the hash does not match the hash stored at the 1836// specified address. 1837let mayLoad = 1, hasSideEffects = 1, 1838 Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1839def HASHCHK8 : XForm_XD6_RA5_RB5<31, 754, (outs), 1840 (ins g8rc:$RB, (memrihash $D, $RA):$addr), 1841 "hashchk $RB, $addr", IIC_IntGeneral, []>; 1842def HASHCHKP8 : XForm_XD6_RA5_RB5<31, 690, (outs), 1843 (ins g8rc:$RB, (memrihash $D, $RA):$addr), 1844 "hashchkp $RB, $addr", IIC_IntGeneral, []>; 1845} 1846 1847let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in 1848def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$RT), 1849 (ins g8rc:$RA, g8rc:$RB, u2imm:$CY), 1850 "addex $RT, $RA, $RB, $CY", IIC_IntGeneral, 1851 [(set i64:$RT, (int_ppc_addex i64:$RA, i64:$RB, 1852 timm:$CY))]>; 1853 1854//===----------------------------------------------------------------------===// 1855// Instruction Patterns 1856// 1857 1858// Extensions and truncates to/from 32-bit regs. 1859def : Pat<(i64 (zext i32:$in)), 1860 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1861 0, 32)>; 1862def : Pat<(i64 (anyext i32:$in)), 1863 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1864def : Pat<(i32 (trunc i64:$in)), 1865 (EXTRACT_SUBREG $in, sub_32)>; 1866 1867// Implement the 'not' operation with the NOR instruction. 1868// (we could use the default xori pattern, but nor has lower latency on some 1869// cores (such as the A2)). 1870def i64not : OutPatFrag<(ops node:$in), 1871 (NOR8 $in, $in)>; 1872def : Pat<(not i64:$in), 1873 (i64not $in)>; 1874 1875// Extending loads with i64 targets. 1876def : Pat<(zextloadi1 DForm:$src), 1877 (LBZ8 DForm:$src)>; 1878def : Pat<(zextloadi1 XForm:$src), 1879 (LBZX8 XForm:$src)>; 1880def : Pat<(extloadi1 DForm:$src), 1881 (LBZ8 DForm:$src)>; 1882def : Pat<(extloadi1 XForm:$src), 1883 (LBZX8 XForm:$src)>; 1884def : Pat<(extloadi8 DForm:$src), 1885 (LBZ8 DForm:$src)>; 1886def : Pat<(extloadi8 XForm:$src), 1887 (LBZX8 XForm:$src)>; 1888def : Pat<(extloadi16 DForm:$src), 1889 (LHZ8 DForm:$src)>; 1890def : Pat<(extloadi16 XForm:$src), 1891 (LHZX8 XForm:$src)>; 1892def : Pat<(extloadi32 DForm:$src), 1893 (LWZ8 DForm:$src)>; 1894def : Pat<(extloadi32 XForm:$src), 1895 (LWZX8 XForm:$src)>; 1896 1897// Standard shifts. These are represented separately from the real shifts above 1898// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1899// amounts. 1900def : Pat<(sra i64:$rS, i32:$rB), 1901 (SRAD $rS, $rB)>; 1902def : Pat<(srl i64:$rS, i32:$rB), 1903 (SRD $rS, $rB)>; 1904def : Pat<(shl i64:$rS, i32:$rB), 1905 (SLD $rS, $rB)>; 1906 1907// SUBFIC 1908def : Pat<(sub imm64SExt16:$imm, i64:$in), 1909 (SUBFIC8 $in, imm:$imm)>; 1910 1911// SHL/SRL 1912def : Pat<(shl i64:$in, (i32 imm:$imm)), 1913 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1914def : Pat<(srl i64:$in, (i32 imm:$imm)), 1915 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1916 1917// ROTL 1918def : Pat<(rotl i64:$in, i32:$sh), 1919 (RLDCL $in, $sh, 0)>; 1920def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1921 (RLDICL $in, imm:$imm, 0)>; 1922 1923// Hi and Lo for Darwin Global Addresses. 1924def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1925def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1926def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1927def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1928def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1929def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1930def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1931def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1932def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1933 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1934def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1935 (ADDI8 $in, tglobaltlsaddr:$g)>; 1936def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1937 (ADDIS8 $in, tglobaladdr:$g)>; 1938def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1939 (ADDIS8 $in, tconstpool:$g)>; 1940def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1941 (ADDIS8 $in, tjumptable:$g)>; 1942def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1943 (ADDIS8 $in, tblockaddress:$g)>; 1944 1945// AIX 64-bit small code model TLS access. 1946// This is used for global dynamic accesses when loading the region handle and 1947// variable offset, and also for local-exec accesses to load the offset of a 1948// TLS variable from the TOC, prior to adding it to r13. 1949def : Pat<(i64 (PPCtoc_entry tglobaltlsaddr:$disp, i64:$reg)), 1950 (i64 (LDtoc tglobaltlsaddr:$disp, i64:$reg))>; 1951 1952// The following pattern matches 64-bit local- and initial-exec TLS accesses on AIX. 1953// PPCaddTls is used in local- and initial-exec accesses in order to: 1954// - Get the address of a variable (adding the variable offset to the thread 1955// pointer in r13). 1956// - Create an opportunity to optimize the user of the loaded address. 1957def : Pat<(PPCaddTls i64:$in, i64:$addr), 1958 (ADD8TLS $in, $addr)>; 1959 1960// 64-bits atomic loads and stores 1961def : Pat<(atomic_load_64 DSForm:$src), (LD memrix:$src)>; 1962def : Pat<(atomic_load_64 XForm:$src), (LDX memrr:$src)>; 1963 1964def : Pat<(atomic_store_64 i64:$val, DSForm:$ptr), (STD g8rc:$val, memrix:$ptr)>; 1965def : Pat<(atomic_store_64 i64:$val, XForm:$ptr), (STDX g8rc:$val, memrr:$ptr)>; 1966 1967let Predicates = [IsISA3_0, In64BitMode] in { 1968def : Pat<(i64 (int_ppc_cmpeqb g8rc:$a, g8rc:$b)), 1969 (i64 (SETB8 (CMPEQB $a, $b)))>; 1970def : Pat<(i64 (int_ppc_setb g8rc:$a, g8rc:$b)), 1971 (i64 (SETB8 (CMPD $a, $b)))>; 1972def : Pat<(i64 (int_ppc_maddhd g8rc:$a, g8rc:$b, g8rc:$c)), 1973 (i64 (MADDHD $a, $b, $c))>; 1974def : Pat<(i64 (int_ppc_maddhdu g8rc:$a, g8rc:$b, g8rc:$c)), 1975 (i64 (MADDHDU $a, $b, $c))>; 1976def : Pat<(i64 (int_ppc_maddld g8rc:$a, g8rc:$b, g8rc:$c)), 1977 (i64 (MADDLD8 $a, $b, $c))>; 1978} 1979 1980let Predicates = [In64BitMode] in { 1981def : Pat<(i64 (int_ppc_mulhd g8rc:$a, g8rc:$b)), 1982 (i64 (MULHD $a, $b))>; 1983def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)), 1984 (i64 (MULHDU $a, $b))>; 1985def : Pat<(int_ppc_load8r ForceXForm:$ptr), 1986 (LDBRX ForceXForm:$ptr)>; 1987def : Pat<(int_ppc_store8r g8rc:$a, ForceXForm:$ptr), 1988 (STDBRX g8rc:$a, ForceXForm:$ptr)>; 1989} 1990 1991def : Pat<(i64 (int_ppc_cmpb g8rc:$a, g8rc:$b)), 1992 (i64 (CMPB8 $a, $b))>; 1993 1994let Predicates = [IsISA3_0] in { 1995// DARN (deliver random number) 1996// L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random 1997def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>; 1998def : Pat<(int_ppc_darn), (DARN 1)>; 1999def : Pat<(int_ppc_darnraw), (DARN 2)>; 2000 2001class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 2002 InstrItinClass itin, list<dag> pattern> 2003 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$RA, ty:$RB, u1imm:$L), 2004 !strconcat(opc, " $RA, $RB"), itin, pattern>{ 2005 let L = 1; 2006} 2007 2008class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 2009 InstrItinClass itin, list<dag> pattern> 2010 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$RA, ty:$RB, u1imm:$L), 2011 !strconcat(opc, " $RA, $RB, $L"), itin, pattern>; 2012 2013let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 2014def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 2015def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; 2016} 2017 2018// SLB Invalidate Entry Global 2019def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RST, gprc:$RB), 2020 "slbieg $RST, $RB", IIC_SprSLBIEG, []>; 2021// SLB Synchronize 2022def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 2023 2024} // IsISA3_0 2025 2026def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A), 2027 (RLWINM (STDCX g8rc:$A, ForceXForm:$dst), 31, 31, 31)>; 2028def : Pat<(PPCStoreCond ForceXForm:$dst, g8rc:$A, 8), 2029 (RLWINM (STDCX g8rc:$A, ForceXForm:$dst), 31, 31, 31)>; 2030 2031def : Pat<(i64 (int_ppc_mfspr timm:$SPR)), 2032 (MFSPR8 $SPR)>; 2033def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT), 2034 (MTSPR8 $SPR, $RT)>; 2035