1//===--- P10InstrResources.td - P10 Scheduling Definitions -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// Automatically generated file, do not edit! 9// 10// This file defines instruction data for SchedModel of the POWER10 processor. 11// 12//===----------------------------------------------------------------------===// 13// 22 Cycles Binary Floating Point operations, 2 input operands 14def : InstRW<[P10W_BF_22C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 15 (instrs 16 FDIVS, 17 XSDIVSP 18)>; 19 20// 2-way crack instructions 21// 22 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 22def : InstRW<[P10W_BF_22C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 23 (instrs 24 FDIVS_rec 25)>; 26 27// 24 Cycles Binary Floating Point operations, 2 input operands 28def : InstRW<[P10W_BF_24C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 29 (instrs 30 XVDIVSP 31)>; 32 33// 26 Cycles Binary Floating Point operations, 1 input operands 34def : InstRW<[P10W_BF_26C, P10W_DISP_ANY, P10BF_Read], 35 (instrs 36 FSQRTS, 37 XSSQRTSP 38)>; 39 40// 2-way crack instructions 41// 26 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 42def : InstRW<[P10W_BF_26C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 43 (instrs 44 FSQRTS_rec 45)>; 46 47// 27 Cycles Binary Floating Point operations, 1 input operands 48def : InstRW<[P10W_BF_27C, P10W_DISP_ANY, P10BF_Read], 49 (instrs 50 XVSQRTSP 51)>; 52 53// 27 Cycles Binary Floating Point operations, 2 input operands 54def : InstRW<[P10W_BF_27C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 55 (instrs 56 FDIV, 57 XSDIVDP, 58 XVDIVDP 59)>; 60 61// 2-way crack instructions 62// 27 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 63def : InstRW<[P10W_BF_27C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 64 (instrs 65 FDIV_rec 66)>; 67 68// 36 Cycles Binary Floating Point operations, 1 input operands 69def : InstRW<[P10W_BF_36C, P10W_DISP_ANY, P10BF_Read], 70 (instrs 71 FSQRT, 72 XSSQRTDP, 73 XVSQRTDP 74)>; 75 76// 2-way crack instructions 77// 36 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 78def : InstRW<[P10W_BF_36C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 79 (instrs 80 FSQRT_rec 81)>; 82 83// 7 Cycles Binary Floating Point operations, 1 input operands 84def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read], 85 (instrs 86 FCFID, 87 FCFIDS, 88 FCFIDU, 89 FCFIDUS, 90 FCTID, 91 FCTIDU, 92 FCTIDUZ, 93 FCTIDZ, 94 FCTIW, 95 FCTIWU, 96 FCTIWUZ, 97 FCTIWZ, 98 FRE, 99 FRES, 100 FRIMD, FRIMS, 101 FRIND, FRINS, 102 FRIPD, FRIPS, 103 FRIZD, FRIZS, 104 FRSP, 105 FRSQRTE, 106 FRSQRTES, 107 VCFSX, VCFSX_0, 108 VCFUX, VCFUX_0, 109 VCTSXS, VCTSXS_0, 110 VCTUXS, VCTUXS_0, 111 VLOGEFP, 112 VREFP, 113 VRFIM, 114 VRFIN, 115 VRFIP, 116 VRFIZ, 117 VRSQRTEFP, 118 XSCVDPHP, 119 XSCVDPSP, 120 XSCVDPSPN, 121 XSCVDPSXDS, XSCVDPSXDSs, 122 XSCVDPSXWS, XSCVDPSXWSs, 123 XSCVDPUXDS, XSCVDPUXDSs, 124 XSCVDPUXWS, XSCVDPUXWSs, 125 XSCVSPDP, 126 XSCVSXDDP, 127 XSCVSXDSP, 128 XSCVUXDDP, 129 XSCVUXDSP, 130 XSRDPI, 131 XSRDPIC, 132 XSRDPIM, 133 XSRDPIP, 134 XSRDPIZ, 135 XSREDP, 136 XSRESP, 137 XSRSP, 138 XSRSQRTEDP, 139 XSRSQRTESP, 140 XVCVDPSP, 141 XVCVDPSXDS, 142 XVCVDPSXWS, 143 XVCVDPUXDS, 144 XVCVDPUXWS, 145 XVCVSPBF16, 146 XVCVSPDP, 147 XVCVSPHP, 148 XVCVSPSXDS, 149 XVCVSPSXWS, 150 XVCVSPUXDS, 151 XVCVSPUXWS, 152 XVCVSXDDP, 153 XVCVSXDSP, 154 XVCVSXWDP, 155 XVCVSXWSP, 156 XVCVUXDDP, 157 XVCVUXDSP, 158 XVCVUXWDP, 159 XVCVUXWSP, 160 XVRDPI, 161 XVRDPIC, 162 XVRDPIM, 163 XVRDPIP, 164 XVRDPIZ, 165 XVREDP, 166 XVRESP, 167 XVRSPI, 168 XVRSPIC, 169 XVRSPIM, 170 XVRSPIP, 171 XVRSPIZ, 172 XVRSQRTEDP, 173 XVRSQRTESP 174)>; 175 176// 7 Cycles Binary Floating Point operations, 2 input operands 177def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 178 (instrs 179 FADD, 180 FADDS, 181 FMUL, 182 FMULS, 183 FSUB, 184 FSUBS, 185 VADDFP, 186 VSUBFP, 187 XSADDDP, 188 XSADDSP, 189 XSMULDP, 190 XSMULSP, 191 XSSUBDP, 192 XSSUBSP, 193 XVADDDP, 194 XVADDSP, 195 XVMULDP, 196 XVMULSP, 197 XVSUBDP, 198 XVSUBSP 199)>; 200 201// 7 Cycles Binary Floating Point operations, 3 input operands 202def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read, P10BF_Read, P10BF_Read], 203 (instrs 204 FMADD, 205 FMADDS, 206 FMSUB, 207 FMSUBS, 208 FNMADD, 209 FNMADDS, 210 FNMSUB, 211 FNMSUBS, 212 FSELD, FSELS, 213 VMADDFP, 214 VNMSUBFP, 215 XSMADDADP, 216 XSMADDASP, 217 XSMADDMDP, 218 XSMADDMSP, 219 XSMSUBADP, 220 XSMSUBASP, 221 XSMSUBMDP, 222 XSMSUBMSP, 223 XSNMADDADP, 224 XSNMADDASP, 225 XSNMADDMDP, 226 XSNMADDMSP, 227 XSNMSUBADP, 228 XSNMSUBASP, 229 XSNMSUBMDP, 230 XSNMSUBMSP, 231 XVMADDADP, 232 XVMADDASP, 233 XVMADDMDP, 234 XVMADDMSP, 235 XVMSUBADP, 236 XVMSUBASP, 237 XVMSUBMDP, 238 XVMSUBMSP, 239 XVNMADDADP, 240 XVNMADDASP, 241 XVNMADDMDP, 242 XVNMADDMSP, 243 XVNMSUBADP, 244 XVNMSUBASP, 245 XVNMSUBMDP, 246 XVNMSUBMSP 247)>; 248 249// 2-way crack instructions 250// 7 Cycles Binary Floating Point operations, and 7 Cycles Binary Floating Point operations, 1 input operands 251def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_BF_7C, P10W_DISP_ANY, P10BF_Read], 252 (instrs 253 VEXPTEFP 254)>; 255 256// 2-way crack instructions 257// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 258def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 259 (instrs 260 FADD_rec, 261 FADDS_rec, 262 FMUL_rec, 263 FMULS_rec, 264 FSUB_rec, 265 FSUBS_rec 266)>; 267 268// 2-way crack instructions 269// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 270def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 271 (instrs 272 FCFID_rec, 273 FCFIDS_rec, 274 FCFIDU_rec, 275 FCFIDUS_rec, 276 FCTID_rec, 277 FCTIDU_rec, 278 FCTIDUZ_rec, 279 FCTIDZ_rec, 280 FCTIW_rec, 281 FCTIWU_rec, 282 FCTIWUZ_rec, 283 FCTIWZ_rec, 284 FRE_rec, 285 FRES_rec, 286 FRIMD_rec, FRIMS_rec, 287 FRIND_rec, FRINS_rec, 288 FRIPD_rec, FRIPS_rec, 289 FRIZD_rec, FRIZS_rec, 290 FRSP_rec, 291 FRSQRTE_rec, 292 FRSQRTES_rec 293)>; 294 295// 2-way crack instructions 296// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 3 input operands 297def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 298 (instrs 299 FMADD_rec, 300 FMADDS_rec, 301 FMSUB_rec, 302 FMSUBS_rec, 303 FNMADD_rec, 304 FNMADDS_rec, 305 FNMSUB_rec, 306 FNMSUBS_rec, 307 FSELD_rec, FSELS_rec 308)>; 309 310// 2 Cycles Branch operations, 1 input operands 311def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read], 312 (instrs 313 B, BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCCLRL, CTRL_DEP, TAILB, TAILB8, 314 BA, TAILBA, TAILBA8, 315 BCCTR, BCCTR8, BCCTR8n, BCCTRn, gBCCTR, 316 BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, gBCCTRL, 317 BCLR, BCLRn, BDNZLR, BDNZLR8, BDNZLRm, BDNZLRp, BDZLR, BDZLR8, BDZLRm, BDZLRp, gBCLR, 318 BCLRL, BCLRLn, BDNZLRL, BDNZLRLm, BDNZLRLp, BDZLRL, BDZLRLm, BDZLRLp, gBCLRL, 319 BL, BL8, BL8_NOP, BL8_NOP_RM, BL8_NOP_TLS, BL8_NOTOC, BL8_NOTOC_RM, BL8_NOTOC_TLS, BL8_RM, BL8_TLS, BL8_TLS_, BLR, BLR8, BLRL, BL_NOP, BL_NOP_RM, BL_RM, BL_TLS, 320 BLA, BLA8, BLA8_NOP, BLA8_NOP_RM, BLA8_RM, BLA_RM 321)>; 322 323// 2 Cycles Branch operations, 2 input operands 324def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read, P10BR_Read], 325 (instrs 326 BC, BCTR, BCTR8, BCTRL, BCTRL8, BCTRL8_LDinto_toc, BCTRL8_LDinto_toc_RM, BCTRL8_RM, BCTRL_LWZinto_toc, BCTRL_LWZinto_toc_RM, BCTRL_RM, BCn, BDNZ, BDNZ8, BDNZm, BDNZp, BDZ, BDZ8, BDZm, BDZp, TAILBCTR, TAILBCTR8, gBC, gBCat, 327 BDNZA, BDNZAm, BDNZAp, BDZA, BDZAm, BDZAp, gBCA, gBCAat, 328 BCL, BCLalways, BCLn, BDNZL, BDNZLm, BDNZLp, BDZL, BDZLm, BDZLp, gBCL, gBCLat, 329 BDNZLA, BDNZLAm, BDNZLAp, BDZLA, BDZLAm, BDZLAp, gBCLA, gBCLAat 330)>; 331 332// 7 Cycles Crypto operations, 1 input operands 333def : InstRW<[P10W_CY_7C, P10W_DISP_ANY, P10CY_Read], 334 (instrs 335 VGNB, 336 VSBOX 337)>; 338 339// 7 Cycles Crypto operations, 2 input operands 340def : InstRW<[P10W_CY_7C, P10W_DISP_ANY, P10CY_Read, P10CY_Read], 341 (instrs 342 CFUGED, 343 CNTLZDM, 344 CNTTZDM, 345 PDEPD, 346 PEXTD, 347 VCFUGED, 348 VCIPHER, 349 VCIPHERLAST, 350 VCLZDM, 351 VCTZDM, 352 VNCIPHER, 353 VNCIPHERLAST, 354 VPDEPD, 355 VPEXTD, 356 VPMSUMB, 357 VPMSUMD, 358 VPMSUMH, 359 VPMSUMW 360)>; 361 362// 13 Cycles Decimal Floating Point operations, 1 input operands 363def : InstRW<[P10W_DF_13C, P10W_DISP_ANY, P10DF_Read], 364 (instrs 365 XSCVDPQP, 366 XSCVQPDP, 367 XSCVQPDPO, 368 XSCVQPSDZ, 369 XSCVQPSQZ, 370 XSCVQPSWZ, 371 XSCVQPUDZ, 372 XSCVQPUQZ, 373 XSCVQPUWZ, 374 XSCVSDQP, 375 XSCVSQQP, 376 XSCVUDQP, 377 XSCVUQQP, 378 XSRQPI, 379 XSRQPIX, 380 XSRQPXP 381)>; 382 383// 13 Cycles Decimal Floating Point operations, 2 input operands 384def : InstRW<[P10W_DF_13C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 385 (instrs 386 BCDSR_rec, 387 XSADDQP, 388 XSADDQPO, 389 XSSUBQP, 390 XSSUBQPO 391)>; 392 393// 2-way crack instructions 394// 13 Cycles Decimal Floating Point operations, and 3 Cycles Store operations, 1 input operands 395def : InstRW<[P10W_DF_13C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY], 396 (instrs 397 HASHST, HASHST8, 398 HASHSTP, HASHSTP8 399)>; 400 401// 24 Cycles Decimal Floating Point operations, 1 input operands 402def : InstRW<[P10W_DF_24C, P10W_DISP_ANY, P10DF_Read], 403 (instrs 404 BCDCTSQ_rec 405)>; 406 407// 25 Cycles Decimal Floating Point operations, 2 input operands 408def : InstRW<[P10W_DF_25C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 409 (instrs 410 XSMULQP, 411 XSMULQPO 412)>; 413 414// 25 Cycles Decimal Floating Point operations, 3 input operands 415def : InstRW<[P10W_DF_25C, P10W_DISP_ANY, P10DF_Read, P10DF_Read, P10DF_Read], 416 (instrs 417 XSMADDQP, 418 XSMADDQPO, 419 XSMSUBQP, 420 XSMSUBQPO, 421 XSNMADDQP, 422 XSNMADDQPO, 423 XSNMSUBQP, 424 XSNMSUBQPO 425)>; 426 427// 38 Cycles Decimal Floating Point operations, 1 input operands 428def : InstRW<[P10W_DF_38C, P10W_DISP_ANY, P10DF_Read], 429 (instrs 430 BCDCFSQ_rec 431)>; 432 433// 59 Cycles Decimal Floating Point operations, 2 input operands 434def : InstRW<[P10W_DF_59C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 435 (instrs 436 XSDIVQP, 437 XSDIVQPO 438)>; 439 440// 61 Cycles Decimal Floating Point operations, 2 input operands 441def : InstRW<[P10W_DF_61C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 442 (instrs 443 VDIVESQ, 444 VDIVEUQ, 445 VDIVSQ, 446 VDIVUQ 447)>; 448 449// 68 Cycles Decimal Floating Point operations, 2 input operands 450def : InstRW<[P10W_DF_68C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 451 (instrs 452 VMODSQ, 453 VMODUQ 454)>; 455 456// 77 Cycles Decimal Floating Point operations, 1 input operands 457def : InstRW<[P10W_DF_77C, P10W_DISP_ANY, P10DF_Read], 458 (instrs 459 XSSQRTQP, 460 XSSQRTQPO 461)>; 462 463// 20 Cycles Scalar Fixed-Point Divide operations, 2 input operands 464def : InstRW<[P10W_DV_20C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 465 (instrs 466 DIVW, 467 DIVWO, 468 DIVWU, 469 DIVWUO, 470 MODSW 471)>; 472 473// 2-way crack instructions 474// 20 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 475def : InstRW<[P10W_DV_20C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 476 (instrs 477 DIVW_rec, 478 DIVWO_rec, 479 DIVWU_rec, 480 DIVWUO_rec 481)>; 482 483// 25 Cycles Scalar Fixed-Point Divide operations, 2 input operands 484def : InstRW<[P10W_DV_25C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 485 (instrs 486 DIVD, 487 DIVDO, 488 DIVDU, 489 DIVDUO, 490 DIVWE, 491 DIVWEO, 492 DIVWEU, 493 DIVWEUO 494)>; 495 496// 2-way crack instructions 497// 25 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 498def : InstRW<[P10W_DV_25C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 499 (instrs 500 DIVD_rec, 501 DIVDO_rec, 502 DIVDU_rec, 503 DIVDUO_rec, 504 DIVWE_rec, 505 DIVWEO_rec, 506 DIVWEU_rec, 507 DIVWEUO_rec 508)>; 509 510// 27 Cycles Scalar Fixed-Point Divide operations, 2 input operands 511def : InstRW<[P10W_DV_27C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 512 (instrs 513 MODSD, 514 MODUD, 515 MODUW 516)>; 517 518// 41 Cycles Scalar Fixed-Point Divide operations, 2 input operands 519def : InstRW<[P10W_DV_41C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 520 (instrs 521 DIVDE, 522 DIVDEO, 523 DIVDEU, 524 DIVDEUO 525)>; 526 527// 2-way crack instructions 528// 41 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 529def : InstRW<[P10W_DV_41C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 530 (instrs 531 DIVDE_rec, 532 DIVDEO_rec, 533 DIVDEU_rec, 534 DIVDEUO_rec 535)>; 536 537// 43 Cycles Scalar Fixed-Point Divide operations, 2 input operands 538def : InstRW<[P10W_DV_43C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 539 (instrs 540 VDIVSD, 541 VDIVUD 542)>; 543 544// 47 Cycles Scalar Fixed-Point Divide operations, 2 input operands 545def : InstRW<[P10W_DV_47C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 546 (instrs 547 VMODSD, 548 VMODUD 549)>; 550 551// 54 Cycles Scalar Fixed-Point Divide operations, 2 input operands 552def : InstRW<[P10W_DV_54C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 553 (instrs 554 VDIVSW, 555 VDIVUW 556)>; 557 558// 60 Cycles Scalar Fixed-Point Divide operations, 2 input operands 559def : InstRW<[P10W_DV_60C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 560 (instrs 561 VMODSW, 562 VMODUW 563)>; 564 565// 75 Cycles Scalar Fixed-Point Divide operations, 2 input operands 566def : InstRW<[P10W_DV_75C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 567 (instrs 568 VDIVESD, 569 VDIVEUD 570)>; 571 572// 83 Cycles Scalar Fixed-Point Divide operations, 2 input operands 573def : InstRW<[P10W_DV_83C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 574 (instrs 575 VDIVESW, 576 VDIVEUW 577)>; 578 579// 5 Cycles Fixed-Point and BCD operations, 1 input operands 580def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read], 581 (instrs 582 BCDCFN_rec, 583 BCDCFZ_rec, 584 BCDCTN_rec, 585 BCDCTZ_rec, 586 BCDSETSGN_rec, 587 VMUL10CUQ, 588 VMUL10UQ, 589 XSTSTDCQP, 590 XSXSIGQP, 591 XXGENPCVBM 592)>; 593 594// 5 Cycles Fixed-Point and BCD operations, 2 input operands 595def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read, P10DX_Read], 596 (instrs 597 BCDADD_rec, 598 BCDCPSGN_rec, 599 BCDS_rec, 600 BCDSUB_rec, 601 BCDTRUNC_rec, 602 BCDUS_rec, 603 BCDUTRUNC_rec, 604 VADDCUQ, 605 VADDUQM, 606 VMUL10ECUQ, 607 VMUL10EUQ, 608 VSUBCUQ, 609 VSUBUQM, 610 XSCMPEQQP, 611 XSCMPEXPQP, 612 XSCMPGEQP, 613 XSCMPGTQP, 614 XSCMPOQP, 615 XSCMPUQP, 616 XSMAXCQP, 617 XSMINCQP 618)>; 619 620// 5 Cycles Fixed-Point and BCD operations, 3 input operands 621def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read, P10DX_Read, P10DX_Read], 622 (instrs 623 VADDECUQ, 624 VADDEUQM, 625 VSUBECUQ, 626 VSUBEUQM 627)>; 628 629// 4 Cycles ALU2 operations, 0 input operands 630def : InstRW<[P10W_F2_4C, P10W_DISP_ANY], 631 (instrs 632 MTVSRBMI 633)>; 634 635// 4 Cycles ALU2 operations, 1 input operands 636def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read], 637 (instrs 638 CBCDTD, CBCDTD8, 639 CDTBCD, CDTBCD8, 640 CNTLZD, 641 CNTLZD_rec, 642 CNTLZW, CNTLZW8, 643 CNTLZW8_rec, CNTLZW_rec, 644 CNTTZD, 645 CNTTZD_rec, 646 CNTTZW, CNTTZW8, 647 CNTTZW8_rec, CNTTZW_rec, 648 EXTSWSLI_32_64_rec, EXTSWSLI_rec, 649 FTSQRT, 650 MTVSRBM, 651 MTVSRDM, 652 MTVSRHM, 653 MTVSRQM, 654 MTVSRWM, 655 POPCNTB, POPCNTB8, 656 POPCNTD, 657 POPCNTW, 658 RLDIC_rec, 659 RLDICL_32_rec, RLDICL_rec, 660 RLDICR_rec, 661 RLWINM8_rec, RLWINM_rec, 662 VCLZB, 663 VCLZD, 664 VCLZH, 665 VCLZW, 666 VCNTMBB, 667 VCNTMBD, 668 VCNTMBH, 669 VCNTMBW, 670 VCTZB, 671 VCTZD, 672 VCTZH, 673 VCTZW, 674 VEXPANDBM, 675 VEXPANDDM, 676 VEXPANDHM, 677 VEXPANDQM, 678 VEXPANDWM, 679 VEXTRACTBM, 680 VEXTRACTDM, 681 VEXTRACTHM, 682 VEXTRACTQM, 683 VEXTRACTWM, 684 VPOPCNTB, 685 VPOPCNTD, 686 VPOPCNTH, 687 VPOPCNTW, 688 VPRTYBD, 689 VPRTYBW, 690 VSHASIGMAD, 691 VSHASIGMAW, 692 XSCVHPDP, 693 XSCVSPDPN, 694 XSTSQRTDP, 695 XSTSTDCDP, 696 XSTSTDCSP, 697 XVCVHPSP, 698 XVTLSBB, 699 XVTSQRTDP, 700 XVTSQRTSP, 701 XVTSTDCDP, 702 XVTSTDCSP 703)>; 704 705// 4 Cycles ALU2 operations, 2 input operands 706def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read], 707 (instrs 708 CMPEQB, 709 CMPRB, CMPRB8, 710 FCMPOD, FCMPOS, 711 FCMPUD, FCMPUS, 712 FTDIV, 713 RLDCL_rec, 714 RLDCR_rec, 715 RLDIMI_rec, 716 RLWIMI8_rec, RLWIMI_rec, 717 RLWNM8_rec, RLWNM_rec, 718 SLD_rec, 719 SLW8_rec, SLW_rec, 720 SRD_rec, 721 SRW8_rec, SRW_rec, 722 TDI, 723 TWI, 724 VABSDUB, 725 VABSDUH, 726 VABSDUW, 727 VADDCUW, 728 VADDSBS, 729 VADDSHS, 730 VADDSWS, 731 VADDUBS, 732 VADDUHS, 733 VADDUWS, 734 VAVGSB, 735 VAVGSH, 736 VAVGSW, 737 VAVGUB, 738 VAVGUH, 739 VAVGUW, 740 VCMPBFP, 741 VCMPBFP_rec, 742 VCMPEQFP, 743 VCMPEQFP_rec, 744 VCMPEQUB_rec, 745 VCMPEQUD_rec, 746 VCMPEQUH_rec, 747 VCMPEQUQ, 748 VCMPEQUQ_rec, 749 VCMPEQUW_rec, 750 VCMPGEFP, 751 VCMPGEFP_rec, 752 VCMPGTFP, 753 VCMPGTFP_rec, 754 VCMPGTSB_rec, 755 VCMPGTSD_rec, 756 VCMPGTSH_rec, 757 VCMPGTSQ, 758 VCMPGTSQ_rec, 759 VCMPGTSW_rec, 760 VCMPGTUB_rec, 761 VCMPGTUD_rec, 762 VCMPGTUH_rec, 763 VCMPGTUQ, 764 VCMPGTUQ_rec, 765 VCMPGTUW_rec, 766 VCMPNEB_rec, 767 VCMPNEH_rec, 768 VCMPNEW_rec, 769 VCMPNEZB_rec, 770 VCMPNEZH_rec, 771 VCMPNEZW_rec, 772 VCMPSQ, 773 VCMPUQ, 774 VMAXFP, 775 VMINFP, 776 VSUBCUW, 777 VSUBSBS, 778 VSUBSHS, 779 VSUBSWS, 780 VSUBUBS, 781 VSUBUHS, 782 VSUBUWS, 783 XSCMPEQDP, 784 XSCMPEXPDP, 785 XSCMPGEDP, 786 XSCMPGTDP, 787 XSCMPODP, 788 XSCMPUDP, 789 XSMAXCDP, 790 XSMAXDP, 791 XSMAXJDP, 792 XSMINCDP, 793 XSMINDP, 794 XSMINJDP, 795 XSTDIVDP, 796 XVCMPEQDP, 797 XVCMPEQDP_rec, 798 XVCMPEQSP, 799 XVCMPEQSP_rec, 800 XVCMPGEDP, 801 XVCMPGEDP_rec, 802 XVCMPGESP, 803 XVCMPGESP_rec, 804 XVCMPGTDP, 805 XVCMPGTDP_rec, 806 XVCMPGTSP, 807 XVCMPGTSP_rec, 808 XVMAXDP, 809 XVMAXSP, 810 XVMINDP, 811 XVMINSP, 812 XVTDIVDP, 813 XVTDIVSP 814)>; 815 816// 4 Cycles ALU2 operations, 3 input operands 817def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read], 818 (instrs 819 TD, 820 TRAP, TW 821)>; 822 823// Single crack instructions 824// 4 Cycles ALU2 operations, 1 input operands 825def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read], 826 (instrs 827 SRADI_rec, 828 SRAWI_rec, 829 SRAWI8_rec 830)>; 831 832// Single crack instructions 833// 4 Cycles ALU2 operations, 2 input operands 834def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read, P10F2_Read], 835 (instrs 836 SRAD_rec, 837 SRAW_rec, 838 SRAW8_rec 839)>; 840 841// 2-way crack instructions 842// 4 Cycles ALU2 operations, and 4 Cycles Permute operations, 2 input operands 843def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 844 (instrs 845 VRLQ, 846 VRLQNM, 847 VSLQ, 848 VSRAQ, 849 VSRQ 850)>; 851 852// 2-way crack instructions 853// 4 Cycles ALU2 operations, and 4 Cycles Permute operations, 3 input operands 854def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 855 (instrs 856 VRLQMI 857)>; 858 859// 2-way crack instructions 860// 4 Cycles ALU2 operations, and 4 Cycles ALU2 operations, 0 input operands 861def : InstRW<[P10W_F2_4C, P10W_DISP_PAIR, P10W_F2_4C], 862 (instrs 863 MFCR, MFCR8 864)>; 865 866// 2 Cycles ALU operations, 1 input operands 867def : InstRW<[P10W_FX_2C, P10W_DISP_ANY, P10FX_Read], 868 (instrs 869 MTCTR, MTCTR8, MTCTR8loop, MTCTRloop, 870 MTLR, MTLR8 871)>; 872 873// 3 Cycles ALU operations, 0 input operands 874def : InstRW<[P10W_FX_3C, P10W_DISP_ANY], 875 (instrs 876 DSS, DSSALL, 877 MCRXRX, 878 MFCTR, MFCTR8, 879 MFLR, MFLR8, 880 WAIT, WAITP10 881)>; 882 883// 3 Cycles ALU operations, 1 input operands 884def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read], 885 (instrs 886 ADDI, ADDI8, ADDIdtprelL32, ADDItlsldLADDR32, ADDItocL, ADDItocL8, LI, LI8, 887 ADDIC, ADDIC8, 888 ADDIS, ADDIS8, ADDISdtprelHA32, ADDIStocHA, ADDIStocHA8, LIS, LIS8, 889 ADDME, ADDME8, 890 ADDME8O, ADDMEO, 891 ADDZE, ADDZE8, 892 ADDZE8O, ADDZEO, 893 ANDI8_rec, ANDI_rec, 894 ANDIS8_rec, ANDIS_rec, 895 CMPDI, CMPWI, 896 CMPLDI, CMPLWI, 897 EXTSB, EXTSB8, EXTSB8_32_64, 898 EXTSB8_rec, EXTSB_rec, 899 EXTSH, EXTSH8, EXTSH8_32_64, 900 EXTSH8_rec, EXTSH_rec, 901 EXTSW, EXTSW_32, EXTSW_32_64, 902 EXTSW_32_64_rec, EXTSW_rec, 903 EXTSWSLI, EXTSWSLI_32_64, 904 FABSD, FABSS, 905 FMR, 906 FNABSD, FNABSS, 907 FNEGD, FNEGS, 908 MCRF, 909 MFOCRF, MFOCRF8, 910 MFVRD, MFVSRD, 911 MFVRWZ, MFVSRWZ, 912 MTOCRF, MTOCRF8, 913 MTVRD, MTVSRD, 914 MTVRWA, MTVSRWA, 915 MTVRWZ, MTVSRWZ, 916 NEG, NEG8, 917 NEG8_rec, NEG_rec, 918 NEG8O, NEGO, 919 NOP, NOP_GT_PWR6, NOP_GT_PWR7, ORI, ORI8, 920 ORIS, ORIS8, 921 RLDIC, 922 RLDICL, RLDICL_32, RLDICL_32_64, 923 RLDICR, RLDICR_32, 924 RLWINM, RLWINM8, 925 SETB, SETB8, 926 SETBC, SETBC8, 927 SETBCR, SETBCR8, 928 SETNBC, SETNBC8, 929 SETNBCR, SETNBCR8, 930 SRADI, SRADI_32, 931 SRAWI, SRAWI8, 932 SUBFIC, SUBFIC8, 933 SUBFME, SUBFME8, 934 SUBFME8O, SUBFMEO, 935 SUBFZE, SUBFZE8, 936 SUBFZE8O, SUBFZEO, 937 VEXTSB2D, VEXTSB2Ds, 938 VEXTSB2W, VEXTSB2Ws, 939 VEXTSD2Q, 940 VEXTSH2D, VEXTSH2Ds, 941 VEXTSH2W, VEXTSH2Ws, 942 VEXTSW2D, VEXTSW2Ds, 943 VNEGD, 944 VNEGW, 945 XORI, XORI8, 946 XORIS, XORIS8, 947 XSABSDP, 948 XSABSQP, 949 XSNABSDP, XSNABSDPs, 950 XSNABSQP, 951 XSNEGDP, 952 XSNEGQP, 953 XSXEXPDP, 954 XSXEXPQP, 955 XSXSIGDP, 956 XVABSDP, 957 XVABSSP, 958 XVNABSDP, 959 XVNABSSP, 960 XVNEGDP, 961 XVNEGSP, 962 XVXEXPDP, 963 XVXEXPSP, 964 XVXSIGDP, 965 XVXSIGSP 966)>; 967 968// 3 Cycles ALU operations, 2 input operands 969def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 970 (instrs 971 ADD4, ADD4TLS, ADD8, ADD8TLS, ADD8TLS_, 972 ADD4_rec, ADD8_rec, 973 ADDE, ADDE8, 974 ADDE8O, ADDEO, 975 ADDEX, ADDEX8, 976 ADD4O, ADD8O, 977 AND, AND8, 978 AND8_rec, AND_rec, 979 ANDC, ANDC8, 980 ANDC8_rec, ANDC_rec, 981 CMPD, CMPW, 982 CMPB, CMPB8, 983 CMPLD, CMPLW, 984 CRAND, 985 CRANDC, 986 CR6SET, CREQV, CRSET, 987 CRNAND, 988 CRNOR, 989 CROR, 990 CRORC, 991 CR6UNSET, CRUNSET, CRXOR, 992 DST, DST64, DSTT, DSTT64, 993 DSTST, DSTST64, DSTSTT, DSTSTT64, 994 EQV, EQV8, 995 EQV8_rec, EQV_rec, 996 FCPSGND, FCPSGNS, 997 NAND, NAND8, 998 NAND8_rec, NAND_rec, 999 NOR, NOR8, 1000 NOR8_rec, NOR_rec, 1001 COPY, OR, OR8, 1002 OR8_rec, OR_rec, 1003 ORC, ORC8, 1004 ORC8_rec, ORC_rec, 1005 RLDCL, 1006 RLDCR, 1007 RLDIMI, 1008 RLWIMI, RLWIMI8, 1009 RLWNM, RLWNM8, 1010 SLD, 1011 SLW, SLW8, 1012 SRAD, 1013 SRAW, SRAW8, 1014 SRD, 1015 SRW, SRW8, 1016 SUBF, SUBF8, 1017 SUBF8_rec, SUBF_rec, 1018 SUBFE, SUBFE8, 1019 SUBFE8O, SUBFEO, 1020 SUBF8O, SUBFO, 1021 VADDUBM, 1022 VADDUDM, 1023 VADDUHM, 1024 VADDUWM, 1025 VAND, 1026 VANDC, 1027 VCMPEQUB, 1028 VCMPEQUD, 1029 VCMPEQUH, 1030 VCMPEQUW, 1031 VCMPGTSB, 1032 VCMPGTSD, 1033 VCMPGTSH, 1034 VCMPGTSW, 1035 VCMPGTUB, 1036 VCMPGTUD, 1037 VCMPGTUH, 1038 VCMPGTUW, 1039 VCMPNEB, 1040 VCMPNEH, 1041 VCMPNEW, 1042 VCMPNEZB, 1043 VCMPNEZH, 1044 VCMPNEZW, 1045 VEQV, 1046 VMAXSB, 1047 VMAXSD, 1048 VMAXSH, 1049 VMAXSW, 1050 VMAXUB, 1051 VMAXUD, 1052 VMAXUH, 1053 VMAXUW, 1054 VMINSB, 1055 VMINSD, 1056 VMINSH, 1057 VMINSW, 1058 VMINUB, 1059 VMINUD, 1060 VMINUH, 1061 VMINUW, 1062 VMRGEW, 1063 VMRGOW, 1064 VNAND, 1065 VNOR, 1066 VOR, 1067 VORC, 1068 VRLB, 1069 VRLD, 1070 VRLDNM, 1071 VRLH, 1072 VRLW, 1073 VRLWNM, 1074 VSLB, 1075 VSLD, 1076 VSLH, 1077 VSLW, 1078 VSRAB, 1079 VSRAD, 1080 VSRAH, 1081 VSRAW, 1082 VSRB, 1083 VSRD, 1084 VSRH, 1085 VSRW, 1086 VSUBUBM, 1087 VSUBUDM, 1088 VSUBUHM, 1089 VSUBUWM, 1090 VXOR, V_SET0, V_SET0B, V_SET0H, 1091 XOR, XOR8, 1092 XOR8_rec, XOR_rec, 1093 XSCPSGNDP, 1094 XSCPSGNQP, 1095 XSIEXPDP, 1096 XSIEXPQP, 1097 XVCPSGNDP, 1098 XVCPSGNSP, 1099 XVIEXPDP, 1100 XVIEXPSP, 1101 XXLAND, 1102 XXLANDC, 1103 XXLEQV, XXLEQVOnes, 1104 XXLNAND, 1105 XXLNOR, 1106 XXLOR, XXLORf, 1107 XXLORC, 1108 XXLXOR, XXLXORdpz, XXLXORspz, XXLXORz 1109)>; 1110 1111// 3 Cycles ALU operations, 3 input operands 1112def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read], 1113 (instrs 1114 ISEL, ISEL8, 1115 VRLDMI, 1116 VRLWMI, 1117 VSEL, 1118 XXSEL 1119)>; 1120 1121// Single crack instructions 1122// 3 Cycles ALU operations, 0 input operands 1123def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1124 (instrs 1125 MFFS, 1126 MFFS_rec, 1127 MFFSCDRNI, 1128 MFFSCRNI, 1129 MFFSL, 1130 MFVSCR, 1131 MTFSB0 1132)>; 1133 1134// Single crack instructions 1135// 3 Cycles ALU operations, 1 input operands 1136def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10FX_Read], 1137 (instrs 1138 ADDIC_rec, 1139 ADDME8_rec, ADDME_rec, 1140 ADDME8O_rec, ADDMEO_rec, 1141 ADDZE8_rec, ADDZE_rec, 1142 ADDZE8O_rec, ADDZEO_rec, 1143 MCRFS, 1144 MFFSCDRN, 1145 MFFSCRN, 1146 MTVSCR, 1147 NEG8O_rec, NEGO_rec, 1148 SUBFME8_rec, SUBFME_rec, 1149 SUBFME8O_rec, SUBFMEO_rec, 1150 SUBFZE8_rec, SUBFZE_rec, 1151 SUBFZE8O_rec, SUBFZEO_rec 1152)>; 1153 1154// Single crack instructions 1155// 3 Cycles ALU operations, 2 input operands 1156def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1157 (instrs 1158 ADDE8_rec, ADDE_rec, 1159 ADDE8O_rec, ADDEO_rec, 1160 ADD4O_rec, ADD8O_rec, 1161 SUBFE8_rec, SUBFE_rec, 1162 SUBFE8O_rec, SUBFEO_rec, 1163 SUBF8O_rec, SUBFO_rec 1164)>; 1165 1166// 2-way crack instructions 1167// 3 Cycles ALU operations, and 4 Cycles ALU2 operations, 2 input operands 1168def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_F2_4C, P10W_DISP_ANY], 1169 (instrs 1170 ADDG6S, ADDG6S8 1171)>; 1172 1173// 2-way crack instructions 1174// 3 Cycles ALU operations, and 3 Cycles ALU operations, 0 input operands 1175def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1176 (instrs 1177 HRFID, 1178 MFFSCE, 1179 MTFSB1, 1180 MTFSFI, MTFSFIb, 1181 MTFSFI_rec, 1182 RFEBB, 1183 RFID, 1184 SC, 1185 STOP 1186)>; 1187 1188// 2-way crack instructions 1189// 3 Cycles ALU operations, and 3 Cycles ALU operations, 1 input operands 1190def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read], 1191 (instrs 1192 FABSD_rec, FABSS_rec, 1193 FMR_rec, 1194 FNABSD_rec, FNABSS_rec, 1195 FNEGD_rec, FNEGS_rec, 1196 MTFSF, MTFSFb, 1197 MTFSF_rec 1198)>; 1199 1200// 2-way crack instructions 1201// 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands 1202def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1203 (instrs 1204 ADDC, ADDC8, 1205 ADDC8_rec, ADDC_rec, 1206 ADDC8O, ADDCO, 1207 FCPSGND_rec, FCPSGNS_rec, 1208 SUBFC, SUBFC8, 1209 SUBFC8_rec, SUBFC_rec, 1210 SUBFC8O, SUBFCO 1211)>; 1212 1213// 4-way crack instructions 1214// 3 Cycles ALU operations, 3 Cycles ALU operations, 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands 1215def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1216 (instrs 1217 ADDC8O_rec, ADDCO_rec, 1218 SUBFC8O_rec, SUBFCO_rec 1219)>; 1220 1221// 2-way crack instructions 1222// 3 Cycles ALU operations, and 4 Cycles Permute operations, 1 input operands 1223def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 1224 (instrs 1225 VSTRIBL_rec, 1226 VSTRIBR_rec, 1227 VSTRIHL_rec, 1228 VSTRIHR_rec 1229)>; 1230 1231// 2-way crack instructions 1232// 3 Cycles ALU operations, and 3 Cycles ALU operations, 1 input operands 1233def : InstRW<[P10W_FX_3C, P10W_DISP_PAIR, P10W_FX_3C, P10FX_Read], 1234 (instrs 1235 MTCRF, MTCRF8 1236)>; 1237 1238// 6 Cycles Load operations, 0 input operands 1239def : InstRW<[P10W_LD_6C, P10W_DISP_ANY], 1240 (instrs 1241 LBZ, LBZ8, 1242 LD, LDtoc, LDtocBA, LDtocCPT, LDtocJTI, LDtocL, SPILLTOVSR_LD, 1243 DFLOADf32, DFLOADf64, LFD, 1244 LHA, LHA8, 1245 LHZ, LHZ8, 1246 LWA, LWA_32, 1247 LWZ, LWZ8, LWZtoc, LWZtocL, 1248 LXSD, 1249 LXV 1250)>; 1251 1252// 6 Cycles Load operations, 1 input operands 1253def : InstRW<[P10W_LD_6C, P10W_DISP_ANY, P10LD_Read], 1254 (instrs 1255 LXVL, 1256 LXVLL 1257)>; 1258 1259// 6 Cycles Load operations, 2 input operands 1260def : InstRW<[P10W_LD_6C, P10W_DISP_ANY, P10LD_Read, P10LD_Read], 1261 (instrs 1262 DCBT, 1263 DCBTST, 1264 ICBT, 1265 LBZX, LBZX8, LBZXTLS, LBZXTLS_, LBZXTLS_32, 1266 LDBRX, 1267 LDX, LDXTLS, LDXTLS_, SPILLTOVSR_LDX, 1268 LFDX, LFDXTLS, LFDXTLS_, XFLOADf32, XFLOADf64, 1269 LFIWAX, LIWAX, 1270 LFIWZX, LIWZX, 1271 LHAX, LHAX8, LHAXTLS, LHAXTLS_, LHAXTLS_32, 1272 LHBRX, LHBRX8, 1273 LHZX, LHZX8, LHZXTLS, LHZXTLS_, LHZXTLS_32, 1274 LVEBX, 1275 LVEHX, 1276 LVEWX, 1277 LVX, 1278 LVXL, 1279 LWAX, LWAXTLS, LWAXTLS_, LWAXTLS_32, LWAX_32, 1280 LWBRX, LWBRX8, 1281 LWZX, LWZX8, LWZXTLS, LWZXTLS_, LWZXTLS_32, 1282 LXSDX, 1283 LXSIBZX, 1284 LXSIHZX, 1285 LXSIWAX, 1286 LXSIWZX, 1287 LXVB16X, 1288 LXVD2X, 1289 LXVDSX, 1290 LXVH8X, 1291 LXVRBX, 1292 LXVRDX, 1293 LXVRHX, 1294 LXVRWX, 1295 LXVW4X, 1296 LXVWSX, 1297 LXVX 1298)>; 1299 1300// 2-way crack instructions 1301// 6 Cycles Load operations, and 13 Cycles Decimal Floating Point operations, 1 input operands 1302def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DF_13C, P10W_DISP_ANY], 1303 (instrs 1304 HASHCHK, HASHCHK8, 1305 HASHCHKP, HASHCHKP8 1306)>; 1307 1308// Single crack instructions 1309// 6 Cycles Load operations, 0 input operands 1310def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY], 1311 (instrs 1312 DARN, 1313 SLBIA 1314)>; 1315 1316// Single crack instructions 1317// 6 Cycles Load operations, 1 input operands 1318def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY, P10LD_Read], 1319 (instrs 1320 MTSPR, MTSPR8, MTSR, MTUDSCR, MTVRSAVE, MTVRSAVEv, 1321 SLBFEE_rec, 1322 SLBIE, 1323 SLBMFEE, 1324 SLBMFEV 1325)>; 1326 1327// Single crack instructions 1328// 6 Cycles Load operations, 2 input operands 1329def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY, P10LD_Read, P10LD_Read], 1330 (instrs 1331 LBARX, LBARXL, 1332 LBZCIX, 1333 LDARX, LDARXL, 1334 LDCIX, 1335 LHARX, LHARXL, 1336 LHZCIX, 1337 LWARX, LWARXL, 1338 LWZCIX 1339)>; 1340 1341// Expand instructions 1342// 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load operations, 0 input operands 1343def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY], 1344 (instrs 1345 LMW 1346)>; 1347 1348// Expand instructions 1349// 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load operations, 1 input operands 1350def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10LD_Read], 1351 (instrs 1352 LSWI 1353)>; 1354 1355// 2-way crack instructions 1356// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1357def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_SX_3C, P10W_DISP_ANY], 1358 (instrs 1359 LBZU, LBZU8, 1360 LDU, 1361 LFDU, 1362 LHAU, LHAU8, 1363 LHZU, LHZU8, 1364 LWZU, LWZU8 1365)>; 1366 1367// 2-way crack instructions 1368// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 2 input operands 1369def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_SX_3C, P10W_DISP_ANY], 1370 (instrs 1371 LBZUX, LBZUX8, 1372 LDUX, 1373 LFDUX, 1374 LHAUX, LHAUX8, 1375 LHZUX, LHZUX8, 1376 LWAUX, 1377 LWZUX, LWZUX8 1378)>; 1379 1380// 6 Cycles Load operations, 0 input operands 1381def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR], 1382 (instrs 1383 PLBZ, PLBZ8, PLBZ8pc, PLBZpc, 1384 PLD, PLDpc, 1385 PLFD, PLFDpc, 1386 PLFS, PLFSpc, 1387 PLHA, PLHA8, PLHA8pc, PLHApc, 1388 PLHZ, PLHZ8, PLHZ8pc, PLHZpc, 1389 PLWA, PLWA8, PLWA8pc, PLWApc, 1390 PLWZ, PLWZ8, PLWZ8pc, PLWZpc, 1391 PLXSD, PLXSDpc, 1392 PLXSSP, PLXSSPpc, 1393 PLXV, PLXVpc, 1394 PLXVP, PLXVPpc 1395)>; 1396 1397// 2-way crack instructions 1398// 6 Cycles Load operations, and 4 Cycles ALU2 operations, 0 input operands 1399def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C], 1400 (instrs 1401 LFS, 1402 LXSSP 1403)>; 1404 1405// 2-way crack instructions 1406// 6 Cycles Load operations, and 4 Cycles ALU2 operations, 2 input operands 1407def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C], 1408 (instrs 1409 LFSX, LFSXTLS, LFSXTLS_, 1410 LXSSPX 1411)>; 1412 1413// 4-way crack instructions 1414// 6 Cycles Load operations, 4 Cycles ALU2 operations, 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 0 input operands 1415def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C, P10W_SX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY], 1416 (instrs 1417 LFSU 1418)>; 1419 1420// 4-way crack instructions 1421// 6 Cycles Load operations, 4 Cycles ALU2 operations, 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 2 input operands 1422def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C, P10W_SX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY], 1423 (instrs 1424 LFSUX 1425)>; 1426 1427// 2-way crack instructions 1428// 6 Cycles Load operations, and 6 Cycles Load operations, 1 input operands 1429def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read], 1430 (instrs 1431 TLBIEL 1432)>; 1433 1434// 2-way crack instructions 1435// 6 Cycles Load operations, and 6 Cycles Load operations, 2 input operands 1436def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read, P10LD_Read], 1437 (instrs 1438 SLBMTE 1439)>; 1440 1441// 2-way crack instructions 1442// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1443def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_SX_3C], 1444 (instrs 1445 LXVP 1446)>; 1447 1448// 2-way crack instructions 1449// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 2 input operands 1450def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_SX_3C], 1451 (instrs 1452 LXVPX 1453)>; 1454 1455// Single crack instructions 1456// 13 Cycles Unknown operations, 1 input operands 1457def : InstRW<[P10W_MFL_13C, P10W_DISP_EVEN, P10W_DISP_ANY], 1458 (instrs 1459 MFSPR, MFSPR8, MFSR, MFTB8, MFUDSCR, MFVRSAVE, MFVRSAVEv 1460)>; 1461 1462// 10 Cycles SIMD Matrix Multiply Engine operations, 0 input operands 1463def : InstRW<[P10W_MM_10C, P10W_DISP_ANY], 1464 (instrs 1465 XXSETACCZ 1466)>; 1467 1468// 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands 1469def : InstRW<[P10W_MM_10C, P10W_DISP_ANY, P10MM_Read, P10MM_Read], 1470 (instrs 1471 XVBF16GER2, 1472 XVF16GER2, 1473 XVF32GER, 1474 XVF64GER, 1475 XVI16GER2, 1476 XVI16GER2S, 1477 XVI4GER8, 1478 XVI8GER4 1479)>; 1480 1481// 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands 1482def : InstRW<[P10W_MM_10C, P10W_DISP_ANY, P10MM_Read, P10MM_Read, P10MM_Read], 1483 (instrs 1484 XVBF16GER2NN, 1485 XVBF16GER2NP, 1486 XVBF16GER2PN, 1487 XVBF16GER2PP, 1488 XVF16GER2NN, 1489 XVF16GER2NP, 1490 XVF16GER2PN, 1491 XVF16GER2PP, 1492 XVF32GERNN, 1493 XVF32GERNP, 1494 XVF32GERPN, 1495 XVF32GERPP, 1496 XVF64GERNN, 1497 XVF64GERNP, 1498 XVF64GERPN, 1499 XVF64GERPP, 1500 XVI16GER2PP, 1501 XVI16GER2SPP, 1502 XVI4GER8PP, 1503 XVI8GER4PP, 1504 XVI8GER4SPP 1505)>; 1506 1507// 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands 1508def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10MM_Read, P10MM_Read], 1509 (instrs 1510 PMXVBF16GER2, 1511 PMXVF16GER2, 1512 PMXVF32GER, 1513 PMXVF64GER, 1514 PMXVI16GER2, 1515 PMXVI16GER2S, 1516 PMXVI4GER8, 1517 PMXVI8GER4 1518)>; 1519 1520// 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands 1521def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10MM_Read, P10MM_Read, P10MM_Read], 1522 (instrs 1523 PMXVBF16GER2NN, 1524 PMXVBF16GER2NP, 1525 PMXVBF16GER2PN, 1526 PMXVBF16GER2PP, 1527 PMXVF16GER2NN, 1528 PMXVF16GER2NP, 1529 PMXVF16GER2PN, 1530 PMXVF16GER2PP, 1531 PMXVF32GERNN, 1532 PMXVF32GERNP, 1533 PMXVF32GERPN, 1534 PMXVF32GERPP, 1535 PMXVF64GERNN, 1536 PMXVF64GERNP, 1537 PMXVF64GERPN, 1538 PMXVF64GERPP, 1539 PMXVI16GER2PP, 1540 PMXVI16GER2SPP, 1541 PMXVI4GER8PP, 1542 PMXVI8GER4PP, 1543 PMXVI8GER4SPP 1544)>; 1545 1546// 2-way crack instructions 1547// 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands 1548def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C], 1549 (instrs 1550 XXMTACC 1551)>; 1552 1553// 4-way crack instructions 1554// 10 Cycles SIMD Matrix Multiply Engine operations, 3 Cycles ALU operations, 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands 1555def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C, P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C], 1556 (instrs 1557 XXMFACC 1558)>; 1559 1560// 5 Cycles GPR Multiply operations, 1 input operands 1561def : InstRW<[P10W_MU_5C, P10W_DISP_ANY, P10MU_Read], 1562 (instrs 1563 MULLI, MULLI8 1564)>; 1565 1566// 5 Cycles GPR Multiply operations, 2 input operands 1567def : InstRW<[P10W_MU_5C, P10W_DISP_ANY, P10MU_Read, P10MU_Read], 1568 (instrs 1569 MULHD, 1570 MULHDU, 1571 MULHW, 1572 MULHWU, 1573 MULLD, 1574 MULLDO, 1575 MULLW, 1576 MULLWO, 1577 VMULHSD, 1578 VMULHUD, 1579 VMULLD 1580)>; 1581 1582// 5 Cycles GPR Multiply operations, 3 input operands 1583def : InstRW<[P10W_MU_5C, P10W_DISP_ANY, P10MU_Read, P10MU_Read, P10MU_Read], 1584 (instrs 1585 MADDHD, 1586 MADDHDU, 1587 MADDLD, MADDLD8 1588)>; 1589 1590// 2-way crack instructions 1591// 5 Cycles GPR Multiply operations, and 3 Cycles ALU operations, 2 input operands 1592def : InstRW<[P10W_MU_5C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1593 (instrs 1594 MULHD_rec, 1595 MULHDU_rec, 1596 MULHW_rec, 1597 MULHWU_rec, 1598 MULLD_rec, 1599 MULLDO_rec, 1600 MULLW_rec, 1601 MULLWO_rec 1602)>; 1603 1604// 4 Cycles Permute operations, 0 input operands 1605def : InstRW<[P10W_PM_4C, P10W_DISP_ANY], 1606 (instrs 1607 LXVKQ, 1608 VSPLTISB, 1609 VSPLTISH, 1610 VSPLTISW, V_SETALLONES, V_SETALLONESB, V_SETALLONESH, 1611 XXSPLTIB 1612)>; 1613 1614// 4 Cycles Permute operations, 1 input operands 1615def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read], 1616 (instrs 1617 BRD, 1618 BRH, BRH8, 1619 BRW, BRW8, 1620 MFVSRLD, 1621 MTVSRWS, 1622 VCLZLSBB, 1623 VCTZLSBB, 1624 VEXTRACTD, 1625 VEXTRACTUB, 1626 VEXTRACTUH, 1627 VEXTRACTUW, 1628 VGBBD, 1629 VINSERTD, 1630 VINSERTW, 1631 VPRTYBQ, 1632 VSPLTB, VSPLTBs, 1633 VSPLTH, VSPLTHs, 1634 VSPLTW, 1635 VSTRIBL, 1636 VSTRIBR, 1637 VSTRIHL, 1638 VSTRIHR, 1639 VUPKHPX, 1640 VUPKHSB, 1641 VUPKHSH, 1642 VUPKHSW, 1643 VUPKLPX, 1644 VUPKLSB, 1645 VUPKLSH, 1646 VUPKLSW, 1647 XVCVBF16SPN, 1648 XXBRD, 1649 XXBRH, 1650 XXBRQ, 1651 XXBRW, 1652 XXEXTRACTUW, 1653 XXGENPCVDM, 1654 XXGENPCVHM, 1655 XXGENPCVWM, 1656 XXSPLTW, XXSPLTWs 1657)>; 1658 1659// 4 Cycles Permute operations, 2 input operands 1660def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read, P10PM_Read], 1661 (instrs 1662 BPERMD, 1663 LVSL, 1664 LVSR, 1665 MTVSRDD, 1666 VBPERMD, 1667 VBPERMQ, 1668 VCLRLB, 1669 VCLRRB, 1670 VEXTUBLX, 1671 VEXTUBRX, 1672 VEXTUHLX, 1673 VEXTUHRX, 1674 VEXTUWLX, 1675 VEXTUWRX, 1676 VINSD, 1677 VINSERTB, 1678 VINSERTH, 1679 VINSW, 1680 VMRGHB, 1681 VMRGHH, 1682 VMRGHW, 1683 VMRGLB, 1684 VMRGLH, 1685 VMRGLW, 1686 VPKPX, 1687 VPKSDSS, 1688 VPKSDUS, 1689 VPKSHSS, 1690 VPKSHUS, 1691 VPKSWSS, 1692 VPKSWUS, 1693 VPKUDUM, 1694 VPKUDUS, 1695 VPKUHUM, 1696 VPKUHUS, 1697 VPKUWUM, 1698 VPKUWUS, 1699 VSL, 1700 VSLDBI, 1701 VSLDOI, 1702 VSLO, 1703 VSLV, 1704 VSR, 1705 VSRDBI, 1706 VSRO, 1707 VSRV, 1708 XXINSERTW, 1709 XXMRGHW, 1710 XXMRGLW, 1711 XXPERMDI, XXPERMDIs, 1712 XXSLDWI, XXSLDWIs 1713)>; 1714 1715// 4 Cycles Permute operations, 3 input operands 1716def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read, P10PM_Read, P10PM_Read], 1717 (instrs 1718 VEXTDDVLX, 1719 VEXTDDVRX, 1720 VEXTDUBVLX, 1721 VEXTDUBVRX, 1722 VEXTDUHVLX, 1723 VEXTDUHVRX, 1724 VEXTDUWVLX, 1725 VEXTDUWVRX, 1726 VINSBLX, 1727 VINSBRX, 1728 VINSBVLX, 1729 VINSBVRX, 1730 VINSDLX, 1731 VINSDRX, 1732 VINSHLX, 1733 VINSHRX, 1734 VINSHVLX, 1735 VINSHVRX, 1736 VINSWLX, 1737 VINSWRX, 1738 VINSWVLX, 1739 VINSWVRX, 1740 VPERM, 1741 VPERMR, 1742 VPERMXOR, 1743 XXPERM, 1744 XXPERMR 1745)>; 1746 1747// 2-way crack instructions 1748// 4 Cycles Permute operations, and 7 Cycles VMX Multiply operations, 2 input operands 1749def : InstRW<[P10W_PM_4C, P10W_DISP_EVEN, P10W_vMU_7C, P10W_DISP_ANY], 1750 (instrs 1751 VSUMSWS 1752)>; 1753 1754// 4 Cycles Permute operations, 0 input operands 1755def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR], 1756 (instrs 1757 XXSPLTIDP, 1758 XXSPLTIW 1759)>; 1760 1761// 4 Cycles Permute operations, 1 input operands 1762def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR, P10PM_Read], 1763 (instrs 1764 XXSPLTI32DX 1765)>; 1766 1767// 4 Cycles Permute operations, 3 input operands 1768def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR, P10PM_Read, P10PM_Read, P10PM_Read], 1769 (instrs 1770 XXBLENDVB, 1771 XXBLENDVD, 1772 XXBLENDVH, 1773 XXBLENDVW, 1774 XXEVAL, 1775 XXPERMX 1776)>; 1777 1778// 3 Cycles Store operations, 1 input operands 1779def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read], 1780 (instrs 1781 PSTXVP, PSTXVPpc, 1782 STB, STB8, 1783 STBU, STBU8, 1784 SPILLTOVSR_ST, STD, 1785 STDU, 1786 DFSTOREf32, DFSTOREf64, STFD, 1787 STFDU, 1788 STFS, 1789 STFSU, 1790 STH, STH8, 1791 STHU, STHU8, 1792 STW, STW8, 1793 STWU, STWU8, 1794 STXSD, 1795 STXSSP, 1796 STXV 1797)>; 1798 1799// 3 Cycles Store operations, 2 input operands 1800def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1801 (instrs 1802 CP_COPY, CP_COPY8, 1803 DCBF, 1804 DCBST, 1805 DCBZ, 1806 ICBI, 1807 STXVL, 1808 STXVLL 1809)>; 1810 1811// 3 Cycles Store operations, 3 input operands 1812def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read], 1813 (instrs 1814 STBUX, STBUX8, 1815 STBX, STBX8, STBXTLS, STBXTLS_, STBXTLS_32, 1816 STDBRX, 1817 STDUX, 1818 SPILLTOVSR_STX, STDX, STDXTLS, STDXTLS_, 1819 STFDUX, 1820 STFDX, STFDXTLS, STFDXTLS_, 1821 STFIWX, STIWX, 1822 STFSUX, 1823 STFSX, STFSXTLS, STFSXTLS_, 1824 STHBRX, 1825 STHUX, STHUX8, 1826 STHX, STHX8, STHXTLS, STHXTLS_, STHXTLS_32, 1827 STVEBX, 1828 STVEHX, 1829 STVEWX, 1830 STVX, 1831 STVXL, 1832 STWBRX, 1833 STWUX, STWUX8, 1834 STWX, STWX8, STWXTLS, STWXTLS_, STWXTLS_32, 1835 STXSDX, 1836 STXSIBX, STXSIBXv, 1837 STXSIHX, STXSIHXv, 1838 STXSIWX, 1839 STXSSPX, 1840 STXVB16X, 1841 STXVD2X, 1842 STXVH8X, 1843 STXVRBX, 1844 STXVRDX, 1845 STXVRHX, 1846 STXVRWX, 1847 STXVW4X, 1848 STXVX 1849)>; 1850 1851// Single crack instructions 1852// 3 Cycles Store operations, 0 input operands 1853def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1854 (instrs 1855 EnforceIEIO, 1856 MSGSYNC, 1857 SLBSYNC, 1858 TLBSYNC 1859)>; 1860 1861// Single crack instructions 1862// 3 Cycles Store operations, 2 input operands 1863def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1864 (instrs 1865 CP_PASTE8_rec, CP_PASTE_rec, 1866 SLBIEG, 1867 TLBIE 1868)>; 1869 1870// Single crack instructions 1871// 3 Cycles Store operations, 3 input operands 1872def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read], 1873 (instrs 1874 STBCIX, 1875 STBCX, 1876 STDCIX, 1877 STDCX, 1878 STHCIX, 1879 STHCX, 1880 STWCIX, 1881 STWCX 1882)>; 1883 1884// 2-way crack instructions 1885// 3 Cycles Store operations, and 3 Cycles ALU operations, 0 input operands 1886def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1887 (instrs 1888 ISYNC, 1889 SYNCP10, 1890 SYNC 1891)>; 1892 1893// Expand instructions 1894// 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, 3 Cycles ALU operations, 6 Cycles Load operations, and 3 Cycles Store operations, 1 input operands 1895def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY], 1896 (instrs 1897 LDAT, 1898 LWAT 1899)>; 1900 1901// 4-way crack instructions 1902// 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, and 3 Cycles Store operations, 2 input operands 1903def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY], 1904 (instrs 1905 STDAT, 1906 STWAT 1907)>; 1908 1909// Expand instructions 1910// 3 Cycles Store operations, 3 Cycles Store operations, 3 Cycles Store operations, and 3 Cycles Store operations, 1 input operands 1911def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10ST_Read], 1912 (instrs 1913 STMW 1914)>; 1915 1916// Expand instructions 1917// 3 Cycles Store operations, 3 Cycles Store operations, 3 Cycles Store operations, and 3 Cycles Store operations, 2 input operands 1918def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1919 (instrs 1920 STSWI 1921)>; 1922 1923// 3 Cycles Store operations, 1 input operands 1924def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10ST_Read], 1925 (instrs 1926 PSTB, PSTB8, PSTB8pc, PSTBpc, 1927 PSTD, PSTDpc, 1928 PSTFD, PSTFDpc, 1929 PSTFS, PSTFSpc, 1930 PSTH, PSTH8, PSTH8pc, PSTHpc, 1931 PSTW, PSTW8, PSTW8pc, PSTWpc, 1932 PSTXSD, PSTXSDpc, 1933 PSTXSSP, PSTXSSPpc, 1934 PSTXV, PSTXVpc 1935)>; 1936 1937// 2-way crack instructions 1938// 3 Cycles Store operations, and 3 Cycles Store operations, 1 input operands 1939def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10W_ST_3C, P10ST_Read], 1940 (instrs 1941 STXVP 1942)>; 1943 1944// 2-way crack instructions 1945// 3 Cycles Store operations, and 3 Cycles Store operations, 3 input operands 1946def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10W_ST_3C, P10ST_Read, P10ST_Read, P10ST_Read], 1947 (instrs 1948 STXVPX 1949)>; 1950 1951// FIXME - Miss scheduling information from datasheet 1952// Temporary set it as 1 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1953def : InstRW<[P10W_SX, P10W_DISP_ANY], 1954 (instrs 1955 ATTN, 1956 CP_ABORT, 1957 CRNOT, 1958 DCBA, 1959 DCBI, 1960 DCBZL, 1961 DCCCI, 1962 ICBLC, 1963 ICBLQ, 1964 ICBTLS, 1965 ICCCI, 1966 LA, LA8, 1967 MFDCR, 1968 MFPMR, 1969 MFSRIN, 1970 MSYNC, 1971 MTDCR, 1972 MTPMR, 1973 MTSRIN, 1974 NAP, 1975 TLBIA, 1976 TLBLD, 1977 TLBLI, 1978 TLBRE2, 1979 TLBSX2, 1980 TLBSX2D, 1981 TLBWE2 1982)>; 1983 1984// Single crack instructions 1985// 3 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1986def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1987 (instrs 1988 CLRBHRB, 1989 MFBHRBE, 1990 MFMSR, 1991 MFTB 1992)>; 1993 1994// Single crack instructions 1995// 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 1996def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10SX_Read], 1997 (instrs 1998 MTMSR, 1999 MTMSRD 2000)>; 2001 2002// 2-way crack instructions 2003// 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 0 input operands 2004def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 2005 (instrs 2006 ADDPCIS 2007)>; 2008 2009// 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 2010def : InstRW<[P10W_SX_3C, P10W_DISP_PAIR, P10SX_Read], 2011 (instrs 2012 PADDI, PADDI8, PADDI8pc, PADDIpc, PLI, PLI8 2013)>; 2014 2015// 7 Cycles VMX Multiply operations, 2 input operands 2016def : InstRW<[P10W_vMU_7C, P10W_DISP_ANY, P10vMU_Read, P10vMU_Read], 2017 (instrs 2018 VMULESB, 2019 VMULESD, 2020 VMULESH, 2021 VMULESW, 2022 VMULEUB, 2023 VMULEUD, 2024 VMULEUH, 2025 VMULEUW, 2026 VMULHSW, 2027 VMULHUW, 2028 VMULOSB, 2029 VMULOSD, 2030 VMULOSH, 2031 VMULOSW, 2032 VMULOUB, 2033 VMULOUD, 2034 VMULOUH, 2035 VMULOUW, 2036 VMULUWM, 2037 VSUM2SWS, 2038 VSUM4SBS, 2039 VSUM4SHS, 2040 VSUM4UBS 2041)>; 2042 2043// 7 Cycles VMX Multiply operations, 3 input operands 2044def : InstRW<[P10W_vMU_7C, P10W_DISP_ANY, P10vMU_Read, P10vMU_Read, P10vMU_Read], 2045 (instrs 2046 VMHADDSHS, 2047 VMHRADDSHS, 2048 VMLADDUHM, 2049 VMSUMCUD, 2050 VMSUMMBM, 2051 VMSUMSHM, 2052 VMSUMSHS, 2053 VMSUMUBM, 2054 VMSUMUDM, 2055 VMSUMUHM, 2056 VMSUMUHS 2057)>; 2058 2059