1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/PPCMCExpr.h" 11 #include "MCTargetDesc/PPCMCTargetDesc.h" 12 #include "PPCTargetStreamer.h" 13 #include "llvm/ADT/STLExtras.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Twine.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCParser/MCAsmLexer.h" 21 #include "llvm/MC/MCParser/MCAsmParser.h" 22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 23 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/MC/MCStreamer.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/MC/MCSymbolELF.h" 28 #include "llvm/Support/SourceMgr.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include "llvm/Support/raw_ostream.h" 31 32 using namespace llvm; 33 34 static const MCPhysReg RRegs[32] = { 35 PPC::R0, PPC::R1, PPC::R2, PPC::R3, 36 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 37 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 38 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 39 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 40 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 41 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 42 PPC::R28, PPC::R29, PPC::R30, PPC::R31 43 }; 44 static const MCPhysReg RRegsNoR0[32] = { 45 PPC::ZERO, 46 PPC::R1, PPC::R2, PPC::R3, 47 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 48 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 49 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 50 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 51 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 52 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 53 PPC::R28, PPC::R29, PPC::R30, PPC::R31 54 }; 55 static const MCPhysReg XRegs[32] = { 56 PPC::X0, PPC::X1, PPC::X2, PPC::X3, 57 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 58 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 59 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 60 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 61 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 62 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 63 PPC::X28, PPC::X29, PPC::X30, PPC::X31 64 }; 65 static const MCPhysReg XRegsNoX0[32] = { 66 PPC::ZERO8, 67 PPC::X1, PPC::X2, PPC::X3, 68 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 69 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 70 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 71 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 72 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 73 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 74 PPC::X28, PPC::X29, PPC::X30, PPC::X31 75 }; 76 static const MCPhysReg FRegs[32] = { 77 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 78 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 79 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 80 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 81 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 82 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 83 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 84 PPC::F28, PPC::F29, PPC::F30, PPC::F31 85 }; 86 static const MCPhysReg VFRegs[32] = { 87 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3, 88 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7, 89 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, 90 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, 91 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, 92 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, 93 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27, 94 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31 95 }; 96 static const MCPhysReg VRegs[32] = { 97 PPC::V0, PPC::V1, PPC::V2, PPC::V3, 98 PPC::V4, PPC::V5, PPC::V6, PPC::V7, 99 PPC::V8, PPC::V9, PPC::V10, PPC::V11, 100 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 101 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 102 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 103 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 104 PPC::V28, PPC::V29, PPC::V30, PPC::V31 105 }; 106 static const MCPhysReg VSRegs[64] = { 107 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, 108 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, 109 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, 110 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, 111 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, 112 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, 113 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, 114 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, 115 116 PPC::V0, PPC::V1, PPC::V2, PPC::V3, 117 PPC::V4, PPC::V5, PPC::V6, PPC::V7, 118 PPC::V8, PPC::V9, PPC::V10, PPC::V11, 119 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 120 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 121 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 122 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 123 PPC::V28, PPC::V29, PPC::V30, PPC::V31 124 }; 125 static const MCPhysReg VSFRegs[64] = { 126 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 127 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 128 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 129 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 130 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 131 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 132 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 133 PPC::F28, PPC::F29, PPC::F30, PPC::F31, 134 135 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3, 136 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7, 137 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, 138 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, 139 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, 140 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, 141 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27, 142 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31 143 }; 144 static const MCPhysReg VSSRegs[64] = { 145 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 146 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 147 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 148 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 149 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 150 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 151 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 152 PPC::F28, PPC::F29, PPC::F30, PPC::F31, 153 154 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3, 155 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7, 156 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, 157 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, 158 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, 159 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, 160 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27, 161 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31 162 }; 163 static unsigned QFRegs[32] = { 164 PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3, 165 PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7, 166 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, 167 PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15, 168 PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19, 169 PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23, 170 PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27, 171 PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31 172 }; 173 static const MCPhysReg CRBITRegs[32] = { 174 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, 175 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, 176 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 177 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 178 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 179 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, 180 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, 181 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN 182 }; 183 static const MCPhysReg CRRegs[8] = { 184 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, 185 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7 186 }; 187 188 // Evaluate an expression containing condition register 189 // or condition register field symbols. Returns positive 190 // value on success, or -1 on error. 191 static int64_t 192 EvaluateCRExpr(const MCExpr *E) { 193 switch (E->getKind()) { 194 case MCExpr::Target: 195 return -1; 196 197 case MCExpr::Constant: { 198 int64_t Res = cast<MCConstantExpr>(E)->getValue(); 199 return Res < 0 ? -1 : Res; 200 } 201 202 case MCExpr::SymbolRef: { 203 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 204 StringRef Name = SRE->getSymbol().getName(); 205 206 if (Name == "lt") return 0; 207 if (Name == "gt") return 1; 208 if (Name == "eq") return 2; 209 if (Name == "so") return 3; 210 if (Name == "un") return 3; 211 212 if (Name == "cr0") return 0; 213 if (Name == "cr1") return 1; 214 if (Name == "cr2") return 2; 215 if (Name == "cr3") return 3; 216 if (Name == "cr4") return 4; 217 if (Name == "cr5") return 5; 218 if (Name == "cr6") return 6; 219 if (Name == "cr7") return 7; 220 221 return -1; 222 } 223 224 case MCExpr::Unary: 225 return -1; 226 227 case MCExpr::Binary: { 228 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 229 int64_t LHSVal = EvaluateCRExpr(BE->getLHS()); 230 int64_t RHSVal = EvaluateCRExpr(BE->getRHS()); 231 int64_t Res; 232 233 if (LHSVal < 0 || RHSVal < 0) 234 return -1; 235 236 switch (BE->getOpcode()) { 237 default: return -1; 238 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break; 239 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break; 240 } 241 242 return Res < 0 ? -1 : Res; 243 } 244 } 245 246 llvm_unreachable("Invalid expression kind!"); 247 } 248 249 namespace { 250 251 struct PPCOperand; 252 253 class PPCAsmParser : public MCTargetAsmParser { 254 bool IsPPC64; 255 bool IsDarwin; 256 257 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); } 258 259 bool isPPC64() const { return IsPPC64; } 260 bool isDarwin() const { return IsDarwin; } 261 262 bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal); 263 264 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 265 266 const MCExpr *ExtractModifierFromExpr(const MCExpr *E, 267 PPCMCExpr::VariantKind &Variant); 268 const MCExpr *FixupVariantKind(const MCExpr *E); 269 bool ParseExpression(const MCExpr *&EVal); 270 bool ParseDarwinExpression(const MCExpr *&EVal); 271 272 bool ParseOperand(OperandVector &Operands); 273 274 bool ParseDirectiveWord(unsigned Size, AsmToken ID); 275 bool ParseDirectiveTC(unsigned Size, AsmToken ID); 276 bool ParseDirectiveMachine(SMLoc L); 277 bool ParseDarwinDirectiveMachine(SMLoc L); 278 bool ParseDirectiveAbiVersion(SMLoc L); 279 bool ParseDirectiveLocalEntry(SMLoc L); 280 281 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 282 OperandVector &Operands, MCStreamer &Out, 283 uint64_t &ErrorInfo, 284 bool MatchingInlineAsm) override; 285 286 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops); 287 288 /// @name Auto-generated Match Functions 289 /// { 290 291 #define GET_ASSEMBLER_HEADER 292 #include "PPCGenAsmMatcher.inc" 293 294 /// } 295 296 297 public: 298 PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &, 299 const MCInstrInfo &MII, const MCTargetOptions &Options) 300 : MCTargetAsmParser(Options, STI, MII) { 301 // Check for 64-bit vs. 32-bit pointer mode. 302 const Triple &TheTriple = STI.getTargetTriple(); 303 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 || 304 TheTriple.getArch() == Triple::ppc64le); 305 IsDarwin = TheTriple.isMacOSX(); 306 // Initialize the set of available features. 307 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 308 } 309 310 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 311 SMLoc NameLoc, OperandVector &Operands) override; 312 313 bool ParseDirective(AsmToken DirectiveID) override; 314 315 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 316 unsigned Kind) override; 317 318 const MCExpr *applyModifierToExpr(const MCExpr *E, 319 MCSymbolRefExpr::VariantKind, 320 MCContext &Ctx) override; 321 }; 322 323 /// PPCOperand - Instances of this class represent a parsed PowerPC machine 324 /// instruction. 325 struct PPCOperand : public MCParsedAsmOperand { 326 enum KindTy { 327 Token, 328 Immediate, 329 ContextImmediate, 330 Expression, 331 TLSRegister 332 } Kind; 333 334 SMLoc StartLoc, EndLoc; 335 bool IsPPC64; 336 337 struct TokOp { 338 const char *Data; 339 unsigned Length; 340 }; 341 342 struct ImmOp { 343 int64_t Val; 344 }; 345 346 struct ExprOp { 347 const MCExpr *Val; 348 int64_t CRVal; // Cached result of EvaluateCRExpr(Val) 349 }; 350 351 struct TLSRegOp { 352 const MCSymbolRefExpr *Sym; 353 }; 354 355 union { 356 struct TokOp Tok; 357 struct ImmOp Imm; 358 struct ExprOp Expr; 359 struct TLSRegOp TLSReg; 360 }; 361 362 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 363 public: 364 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() { 365 Kind = o.Kind; 366 StartLoc = o.StartLoc; 367 EndLoc = o.EndLoc; 368 IsPPC64 = o.IsPPC64; 369 switch (Kind) { 370 case Token: 371 Tok = o.Tok; 372 break; 373 case Immediate: 374 case ContextImmediate: 375 Imm = o.Imm; 376 break; 377 case Expression: 378 Expr = o.Expr; 379 break; 380 case TLSRegister: 381 TLSReg = o.TLSReg; 382 break; 383 } 384 } 385 386 // Disable use of sized deallocation due to overallocation of PPCOperand 387 // objects in CreateTokenWithStringCopy. 388 void operator delete(void *p) { ::operator delete(p); } 389 390 /// getStartLoc - Get the location of the first token of this operand. 391 SMLoc getStartLoc() const override { return StartLoc; } 392 393 /// getEndLoc - Get the location of the last token of this operand. 394 SMLoc getEndLoc() const override { return EndLoc; } 395 396 /// getLocRange - Get the range between the first and last token of this 397 /// operand. 398 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 399 400 /// isPPC64 - True if this operand is for an instruction in 64-bit mode. 401 bool isPPC64() const { return IsPPC64; } 402 403 int64_t getImm() const { 404 assert(Kind == Immediate && "Invalid access!"); 405 return Imm.Val; 406 } 407 int64_t getImmS16Context() const { 408 assert((Kind == Immediate || Kind == ContextImmediate) && 409 "Invalid access!"); 410 if (Kind == Immediate) 411 return Imm.Val; 412 return static_cast<int16_t>(Imm.Val); 413 } 414 int64_t getImmU16Context() const { 415 assert((Kind == Immediate || Kind == ContextImmediate) && 416 "Invalid access!"); 417 return Imm.Val; 418 } 419 420 const MCExpr *getExpr() const { 421 assert(Kind == Expression && "Invalid access!"); 422 return Expr.Val; 423 } 424 425 int64_t getExprCRVal() const { 426 assert(Kind == Expression && "Invalid access!"); 427 return Expr.CRVal; 428 } 429 430 const MCExpr *getTLSReg() const { 431 assert(Kind == TLSRegister && "Invalid access!"); 432 return TLSReg.Sym; 433 } 434 435 unsigned getReg() const override { 436 assert(isRegNumber() && "Invalid access!"); 437 return (unsigned) Imm.Val; 438 } 439 440 unsigned getVSReg() const { 441 assert(isVSRegNumber() && "Invalid access!"); 442 return (unsigned) Imm.Val; 443 } 444 445 unsigned getCCReg() const { 446 assert(isCCRegNumber() && "Invalid access!"); 447 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 448 } 449 450 unsigned getCRBit() const { 451 assert(isCRBitNumber() && "Invalid access!"); 452 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 453 } 454 455 unsigned getCRBitMask() const { 456 assert(isCRBitMask() && "Invalid access!"); 457 return 7 - countTrailingZeros<uint64_t>(Imm.Val); 458 } 459 460 bool isToken() const override { return Kind == Token; } 461 bool isImm() const override { 462 return Kind == Immediate || Kind == Expression; 463 } 464 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } 465 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } 466 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } 467 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } 468 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } 469 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } 470 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } 471 bool isU6ImmX2() const { return Kind == Immediate && 472 isUInt<6>(getImm()) && 473 (getImm() & 1) == 0; } 474 bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); } 475 bool isU7ImmX4() const { return Kind == Immediate && 476 isUInt<7>(getImm()) && 477 (getImm() & 3) == 0; } 478 bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); } 479 bool isU8ImmX8() const { return Kind == Immediate && 480 isUInt<8>(getImm()) && 481 (getImm() & 7) == 0; } 482 483 bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); } 484 bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); } 485 bool isU16Imm() const { 486 switch (Kind) { 487 case Expression: 488 return true; 489 case Immediate: 490 case ContextImmediate: 491 return isUInt<16>(getImmU16Context()); 492 default: 493 return false; 494 } 495 } 496 bool isS16Imm() const { 497 switch (Kind) { 498 case Expression: 499 return true; 500 case Immediate: 501 case ContextImmediate: 502 return isInt<16>(getImmS16Context()); 503 default: 504 return false; 505 } 506 } 507 bool isS16ImmX4() const { return Kind == Expression || 508 (Kind == Immediate && isInt<16>(getImm()) && 509 (getImm() & 3) == 0); } 510 bool isS16ImmX16() const { return Kind == Expression || 511 (Kind == Immediate && isInt<16>(getImm()) && 512 (getImm() & 15) == 0); } 513 bool isS17Imm() const { 514 switch (Kind) { 515 case Expression: 516 return true; 517 case Immediate: 518 case ContextImmediate: 519 return isInt<17>(getImmS16Context()); 520 default: 521 return false; 522 } 523 } 524 bool isTLSReg() const { return Kind == TLSRegister; } 525 bool isDirectBr() const { 526 if (Kind == Expression) 527 return true; 528 if (Kind != Immediate) 529 return false; 530 // Operand must be 64-bit aligned, signed 27-bit immediate. 531 if ((getImm() & 3) != 0) 532 return false; 533 if (isInt<26>(getImm())) 534 return true; 535 if (!IsPPC64) { 536 // In 32-bit mode, large 32-bit quantities wrap around. 537 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm()))) 538 return true; 539 } 540 return false; 541 } 542 bool isCondBr() const { return Kind == Expression || 543 (Kind == Immediate && isInt<16>(getImm()) && 544 (getImm() & 3) == 0); } 545 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } 546 bool isVSRegNumber() const { 547 return Kind == Immediate && isUInt<6>(getImm()); 548 } 549 bool isCCRegNumber() const { return (Kind == Expression 550 && isUInt<3>(getExprCRVal())) || 551 (Kind == Immediate 552 && isUInt<3>(getImm())); } 553 bool isCRBitNumber() const { return (Kind == Expression 554 && isUInt<5>(getExprCRVal())) || 555 (Kind == Immediate 556 && isUInt<5>(getImm())); } 557 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) && 558 isPowerOf2_32(getImm()); } 559 bool isATBitsAsHint() const { return false; } 560 bool isMem() const override { return false; } 561 bool isReg() const override { return false; } 562 563 void addRegOperands(MCInst &Inst, unsigned N) const { 564 llvm_unreachable("addRegOperands"); 565 } 566 567 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { 568 assert(N == 1 && "Invalid number of operands!"); 569 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 570 } 571 572 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { 573 assert(N == 1 && "Invalid number of operands!"); 574 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); 575 } 576 577 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { 578 assert(N == 1 && "Invalid number of operands!"); 579 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); 580 } 581 582 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { 583 assert(N == 1 && "Invalid number of operands!"); 584 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); 585 } 586 587 void addRegGxRCOperands(MCInst &Inst, unsigned N) const { 588 if (isPPC64()) 589 addRegG8RCOperands(Inst, N); 590 else 591 addRegGPRCOperands(Inst, N); 592 } 593 594 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const { 595 if (isPPC64()) 596 addRegG8RCNoX0Operands(Inst, N); 597 else 598 addRegGPRCNoR0Operands(Inst, N); 599 } 600 601 void addRegF4RCOperands(MCInst &Inst, unsigned N) const { 602 assert(N == 1 && "Invalid number of operands!"); 603 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 604 } 605 606 void addRegF8RCOperands(MCInst &Inst, unsigned N) const { 607 assert(N == 1 && "Invalid number of operands!"); 608 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 609 } 610 611 void addRegVFRCOperands(MCInst &Inst, unsigned N) const { 612 assert(N == 1 && "Invalid number of operands!"); 613 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); 614 } 615 616 void addRegVRRCOperands(MCInst &Inst, unsigned N) const { 617 assert(N == 1 && "Invalid number of operands!"); 618 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); 619 } 620 621 void addRegVSRCOperands(MCInst &Inst, unsigned N) const { 622 assert(N == 1 && "Invalid number of operands!"); 623 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); 624 } 625 626 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const { 627 assert(N == 1 && "Invalid number of operands!"); 628 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); 629 } 630 631 void addRegVSSRCOperands(MCInst &Inst, unsigned N) const { 632 assert(N == 1 && "Invalid number of operands!"); 633 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); 634 } 635 636 void addRegQFRCOperands(MCInst &Inst, unsigned N) const { 637 assert(N == 1 && "Invalid number of operands!"); 638 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()])); 639 } 640 641 void addRegQSRCOperands(MCInst &Inst, unsigned N) const { 642 assert(N == 1 && "Invalid number of operands!"); 643 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()])); 644 } 645 646 void addRegQBRCOperands(MCInst &Inst, unsigned N) const { 647 assert(N == 1 && "Invalid number of operands!"); 648 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()])); 649 } 650 651 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const { 652 assert(N == 1 && "Invalid number of operands!"); 653 Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()])); 654 } 655 656 void addRegCRRCOperands(MCInst &Inst, unsigned N) const { 657 assert(N == 1 && "Invalid number of operands!"); 658 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()])); 659 } 660 661 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const { 662 assert(N == 1 && "Invalid number of operands!"); 663 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()])); 664 } 665 666 void addImmOperands(MCInst &Inst, unsigned N) const { 667 assert(N == 1 && "Invalid number of operands!"); 668 if (Kind == Immediate) 669 Inst.addOperand(MCOperand::createImm(getImm())); 670 else 671 Inst.addOperand(MCOperand::createExpr(getExpr())); 672 } 673 674 void addS16ImmOperands(MCInst &Inst, unsigned N) const { 675 assert(N == 1 && "Invalid number of operands!"); 676 switch (Kind) { 677 case Immediate: 678 Inst.addOperand(MCOperand::createImm(getImm())); 679 break; 680 case ContextImmediate: 681 Inst.addOperand(MCOperand::createImm(getImmS16Context())); 682 break; 683 default: 684 Inst.addOperand(MCOperand::createExpr(getExpr())); 685 break; 686 } 687 } 688 689 void addU16ImmOperands(MCInst &Inst, unsigned N) const { 690 assert(N == 1 && "Invalid number of operands!"); 691 switch (Kind) { 692 case Immediate: 693 Inst.addOperand(MCOperand::createImm(getImm())); 694 break; 695 case ContextImmediate: 696 Inst.addOperand(MCOperand::createImm(getImmU16Context())); 697 break; 698 default: 699 Inst.addOperand(MCOperand::createExpr(getExpr())); 700 break; 701 } 702 } 703 704 void addBranchTargetOperands(MCInst &Inst, unsigned N) const { 705 assert(N == 1 && "Invalid number of operands!"); 706 if (Kind == Immediate) 707 Inst.addOperand(MCOperand::createImm(getImm() / 4)); 708 else 709 Inst.addOperand(MCOperand::createExpr(getExpr())); 710 } 711 712 void addTLSRegOperands(MCInst &Inst, unsigned N) const { 713 assert(N == 1 && "Invalid number of operands!"); 714 Inst.addOperand(MCOperand::createExpr(getTLSReg())); 715 } 716 717 StringRef getToken() const { 718 assert(Kind == Token && "Invalid access!"); 719 return StringRef(Tok.Data, Tok.Length); 720 } 721 722 void print(raw_ostream &OS) const override; 723 724 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S, 725 bool IsPPC64) { 726 auto Op = make_unique<PPCOperand>(Token); 727 Op->Tok.Data = Str.data(); 728 Op->Tok.Length = Str.size(); 729 Op->StartLoc = S; 730 Op->EndLoc = S; 731 Op->IsPPC64 = IsPPC64; 732 return Op; 733 } 734 735 static std::unique_ptr<PPCOperand> 736 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) { 737 // Allocate extra memory for the string and copy it. 738 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default 739 // deleter which will destroy them by simply using "delete", not correctly 740 // calling operator delete on this extra memory after calling the dtor 741 // explicitly. 742 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size()); 743 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token)); 744 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1); 745 Op->Tok.Length = Str.size(); 746 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size()); 747 Op->StartLoc = S; 748 Op->EndLoc = S; 749 Op->IsPPC64 = IsPPC64; 750 return Op; 751 } 752 753 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E, 754 bool IsPPC64) { 755 auto Op = make_unique<PPCOperand>(Immediate); 756 Op->Imm.Val = Val; 757 Op->StartLoc = S; 758 Op->EndLoc = E; 759 Op->IsPPC64 = IsPPC64; 760 return Op; 761 } 762 763 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S, 764 SMLoc E, bool IsPPC64) { 765 auto Op = make_unique<PPCOperand>(Expression); 766 Op->Expr.Val = Val; 767 Op->Expr.CRVal = EvaluateCRExpr(Val); 768 Op->StartLoc = S; 769 Op->EndLoc = E; 770 Op->IsPPC64 = IsPPC64; 771 return Op; 772 } 773 774 static std::unique_ptr<PPCOperand> 775 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) { 776 auto Op = make_unique<PPCOperand>(TLSRegister); 777 Op->TLSReg.Sym = Sym; 778 Op->StartLoc = S; 779 Op->EndLoc = E; 780 Op->IsPPC64 = IsPPC64; 781 return Op; 782 } 783 784 static std::unique_ptr<PPCOperand> 785 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) { 786 auto Op = make_unique<PPCOperand>(ContextImmediate); 787 Op->Imm.Val = Val; 788 Op->StartLoc = S; 789 Op->EndLoc = E; 790 Op->IsPPC64 = IsPPC64; 791 return Op; 792 } 793 794 static std::unique_ptr<PPCOperand> 795 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) { 796 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val)) 797 return CreateImm(CE->getValue(), S, E, IsPPC64); 798 799 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val)) 800 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS) 801 return CreateTLSReg(SRE, S, E, IsPPC64); 802 803 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) { 804 int64_t Res; 805 if (TE->evaluateAsConstant(Res)) 806 return CreateContextImm(Res, S, E, IsPPC64); 807 } 808 809 return CreateExpr(Val, S, E, IsPPC64); 810 } 811 }; 812 813 } // end anonymous namespace. 814 815 void PPCOperand::print(raw_ostream &OS) const { 816 switch (Kind) { 817 case Token: 818 OS << "'" << getToken() << "'"; 819 break; 820 case Immediate: 821 case ContextImmediate: 822 OS << getImm(); 823 break; 824 case Expression: 825 OS << *getExpr(); 826 break; 827 case TLSRegister: 828 OS << *getTLSReg(); 829 break; 830 } 831 } 832 833 static void 834 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) { 835 if (Op.isImm()) { 836 Inst.addOperand(MCOperand::createImm(-Op.getImm())); 837 return; 838 } 839 const MCExpr *Expr = Op.getExpr(); 840 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) { 841 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) { 842 Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr())); 843 return; 844 } 845 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) { 846 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) { 847 const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(), 848 BinExpr->getLHS(), Ctx); 849 Inst.addOperand(MCOperand::createExpr(NE)); 850 return; 851 } 852 } 853 Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx))); 854 } 855 856 void PPCAsmParser::ProcessInstruction(MCInst &Inst, 857 const OperandVector &Operands) { 858 int Opcode = Inst.getOpcode(); 859 switch (Opcode) { 860 case PPC::DCBTx: 861 case PPC::DCBTT: 862 case PPC::DCBTSTx: 863 case PPC::DCBTSTT: { 864 MCInst TmpInst; 865 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? 866 PPC::DCBT : PPC::DCBTST); 867 TmpInst.addOperand(MCOperand::createImm( 868 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16)); 869 TmpInst.addOperand(Inst.getOperand(0)); 870 TmpInst.addOperand(Inst.getOperand(1)); 871 Inst = TmpInst; 872 break; 873 } 874 case PPC::DCBTCT: 875 case PPC::DCBTDS: { 876 MCInst TmpInst; 877 TmpInst.setOpcode(PPC::DCBT); 878 TmpInst.addOperand(Inst.getOperand(2)); 879 TmpInst.addOperand(Inst.getOperand(0)); 880 TmpInst.addOperand(Inst.getOperand(1)); 881 Inst = TmpInst; 882 break; 883 } 884 case PPC::DCBTSTCT: 885 case PPC::DCBTSTDS: { 886 MCInst TmpInst; 887 TmpInst.setOpcode(PPC::DCBTST); 888 TmpInst.addOperand(Inst.getOperand(2)); 889 TmpInst.addOperand(Inst.getOperand(0)); 890 TmpInst.addOperand(Inst.getOperand(1)); 891 Inst = TmpInst; 892 break; 893 } 894 case PPC::DCBFx: 895 case PPC::DCBFL: 896 case PPC::DCBFLP: { 897 int L = 0; 898 if (Opcode == PPC::DCBFL) 899 L = 1; 900 else if (Opcode == PPC::DCBFLP) 901 L = 3; 902 903 MCInst TmpInst; 904 TmpInst.setOpcode(PPC::DCBF); 905 TmpInst.addOperand(MCOperand::createImm(L)); 906 TmpInst.addOperand(Inst.getOperand(0)); 907 TmpInst.addOperand(Inst.getOperand(1)); 908 Inst = TmpInst; 909 break; 910 } 911 case PPC::LAx: { 912 MCInst TmpInst; 913 TmpInst.setOpcode(PPC::LA); 914 TmpInst.addOperand(Inst.getOperand(0)); 915 TmpInst.addOperand(Inst.getOperand(2)); 916 TmpInst.addOperand(Inst.getOperand(1)); 917 Inst = TmpInst; 918 break; 919 } 920 case PPC::SUBI: { 921 MCInst TmpInst; 922 TmpInst.setOpcode(PPC::ADDI); 923 TmpInst.addOperand(Inst.getOperand(0)); 924 TmpInst.addOperand(Inst.getOperand(1)); 925 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 926 Inst = TmpInst; 927 break; 928 } 929 case PPC::SUBIS: { 930 MCInst TmpInst; 931 TmpInst.setOpcode(PPC::ADDIS); 932 TmpInst.addOperand(Inst.getOperand(0)); 933 TmpInst.addOperand(Inst.getOperand(1)); 934 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 935 Inst = TmpInst; 936 break; 937 } 938 case PPC::SUBIC: { 939 MCInst TmpInst; 940 TmpInst.setOpcode(PPC::ADDIC); 941 TmpInst.addOperand(Inst.getOperand(0)); 942 TmpInst.addOperand(Inst.getOperand(1)); 943 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 944 Inst = TmpInst; 945 break; 946 } 947 case PPC::SUBICo: { 948 MCInst TmpInst; 949 TmpInst.setOpcode(PPC::ADDICo); 950 TmpInst.addOperand(Inst.getOperand(0)); 951 TmpInst.addOperand(Inst.getOperand(1)); 952 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 953 Inst = TmpInst; 954 break; 955 } 956 case PPC::EXTLWI: 957 case PPC::EXTLWIo: { 958 MCInst TmpInst; 959 int64_t N = Inst.getOperand(2).getImm(); 960 int64_t B = Inst.getOperand(3).getImm(); 961 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo); 962 TmpInst.addOperand(Inst.getOperand(0)); 963 TmpInst.addOperand(Inst.getOperand(1)); 964 TmpInst.addOperand(MCOperand::createImm(B)); 965 TmpInst.addOperand(MCOperand::createImm(0)); 966 TmpInst.addOperand(MCOperand::createImm(N - 1)); 967 Inst = TmpInst; 968 break; 969 } 970 case PPC::EXTRWI: 971 case PPC::EXTRWIo: { 972 MCInst TmpInst; 973 int64_t N = Inst.getOperand(2).getImm(); 974 int64_t B = Inst.getOperand(3).getImm(); 975 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo); 976 TmpInst.addOperand(Inst.getOperand(0)); 977 TmpInst.addOperand(Inst.getOperand(1)); 978 TmpInst.addOperand(MCOperand::createImm(B + N)); 979 TmpInst.addOperand(MCOperand::createImm(32 - N)); 980 TmpInst.addOperand(MCOperand::createImm(31)); 981 Inst = TmpInst; 982 break; 983 } 984 case PPC::INSLWI: 985 case PPC::INSLWIo: { 986 MCInst TmpInst; 987 int64_t N = Inst.getOperand(2).getImm(); 988 int64_t B = Inst.getOperand(3).getImm(); 989 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo); 990 TmpInst.addOperand(Inst.getOperand(0)); 991 TmpInst.addOperand(Inst.getOperand(0)); 992 TmpInst.addOperand(Inst.getOperand(1)); 993 TmpInst.addOperand(MCOperand::createImm(32 - B)); 994 TmpInst.addOperand(MCOperand::createImm(B)); 995 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 996 Inst = TmpInst; 997 break; 998 } 999 case PPC::INSRWI: 1000 case PPC::INSRWIo: { 1001 MCInst TmpInst; 1002 int64_t N = Inst.getOperand(2).getImm(); 1003 int64_t B = Inst.getOperand(3).getImm(); 1004 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo); 1005 TmpInst.addOperand(Inst.getOperand(0)); 1006 TmpInst.addOperand(Inst.getOperand(0)); 1007 TmpInst.addOperand(Inst.getOperand(1)); 1008 TmpInst.addOperand(MCOperand::createImm(32 - (B + N))); 1009 TmpInst.addOperand(MCOperand::createImm(B)); 1010 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 1011 Inst = TmpInst; 1012 break; 1013 } 1014 case PPC::ROTRWI: 1015 case PPC::ROTRWIo: { 1016 MCInst TmpInst; 1017 int64_t N = Inst.getOperand(2).getImm(); 1018 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo); 1019 TmpInst.addOperand(Inst.getOperand(0)); 1020 TmpInst.addOperand(Inst.getOperand(1)); 1021 TmpInst.addOperand(MCOperand::createImm(32 - N)); 1022 TmpInst.addOperand(MCOperand::createImm(0)); 1023 TmpInst.addOperand(MCOperand::createImm(31)); 1024 Inst = TmpInst; 1025 break; 1026 } 1027 case PPC::SLWI: 1028 case PPC::SLWIo: { 1029 MCInst TmpInst; 1030 int64_t N = Inst.getOperand(2).getImm(); 1031 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo); 1032 TmpInst.addOperand(Inst.getOperand(0)); 1033 TmpInst.addOperand(Inst.getOperand(1)); 1034 TmpInst.addOperand(MCOperand::createImm(N)); 1035 TmpInst.addOperand(MCOperand::createImm(0)); 1036 TmpInst.addOperand(MCOperand::createImm(31 - N)); 1037 Inst = TmpInst; 1038 break; 1039 } 1040 case PPC::SRWI: 1041 case PPC::SRWIo: { 1042 MCInst TmpInst; 1043 int64_t N = Inst.getOperand(2).getImm(); 1044 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo); 1045 TmpInst.addOperand(Inst.getOperand(0)); 1046 TmpInst.addOperand(Inst.getOperand(1)); 1047 TmpInst.addOperand(MCOperand::createImm(32 - N)); 1048 TmpInst.addOperand(MCOperand::createImm(N)); 1049 TmpInst.addOperand(MCOperand::createImm(31)); 1050 Inst = TmpInst; 1051 break; 1052 } 1053 case PPC::CLRRWI: 1054 case PPC::CLRRWIo: { 1055 MCInst TmpInst; 1056 int64_t N = Inst.getOperand(2).getImm(); 1057 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo); 1058 TmpInst.addOperand(Inst.getOperand(0)); 1059 TmpInst.addOperand(Inst.getOperand(1)); 1060 TmpInst.addOperand(MCOperand::createImm(0)); 1061 TmpInst.addOperand(MCOperand::createImm(0)); 1062 TmpInst.addOperand(MCOperand::createImm(31 - N)); 1063 Inst = TmpInst; 1064 break; 1065 } 1066 case PPC::CLRLSLWI: 1067 case PPC::CLRLSLWIo: { 1068 MCInst TmpInst; 1069 int64_t B = Inst.getOperand(2).getImm(); 1070 int64_t N = Inst.getOperand(3).getImm(); 1071 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo); 1072 TmpInst.addOperand(Inst.getOperand(0)); 1073 TmpInst.addOperand(Inst.getOperand(1)); 1074 TmpInst.addOperand(MCOperand::createImm(N)); 1075 TmpInst.addOperand(MCOperand::createImm(B - N)); 1076 TmpInst.addOperand(MCOperand::createImm(31 - N)); 1077 Inst = TmpInst; 1078 break; 1079 } 1080 case PPC::EXTLDI: 1081 case PPC::EXTLDIo: { 1082 MCInst TmpInst; 1083 int64_t N = Inst.getOperand(2).getImm(); 1084 int64_t B = Inst.getOperand(3).getImm(); 1085 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo); 1086 TmpInst.addOperand(Inst.getOperand(0)); 1087 TmpInst.addOperand(Inst.getOperand(1)); 1088 TmpInst.addOperand(MCOperand::createImm(B)); 1089 TmpInst.addOperand(MCOperand::createImm(N - 1)); 1090 Inst = TmpInst; 1091 break; 1092 } 1093 case PPC::EXTRDI: 1094 case PPC::EXTRDIo: { 1095 MCInst TmpInst; 1096 int64_t N = Inst.getOperand(2).getImm(); 1097 int64_t B = Inst.getOperand(3).getImm(); 1098 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo); 1099 TmpInst.addOperand(Inst.getOperand(0)); 1100 TmpInst.addOperand(Inst.getOperand(1)); 1101 TmpInst.addOperand(MCOperand::createImm(B + N)); 1102 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1103 Inst = TmpInst; 1104 break; 1105 } 1106 case PPC::INSRDI: 1107 case PPC::INSRDIo: { 1108 MCInst TmpInst; 1109 int64_t N = Inst.getOperand(2).getImm(); 1110 int64_t B = Inst.getOperand(3).getImm(); 1111 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo); 1112 TmpInst.addOperand(Inst.getOperand(0)); 1113 TmpInst.addOperand(Inst.getOperand(0)); 1114 TmpInst.addOperand(Inst.getOperand(1)); 1115 TmpInst.addOperand(MCOperand::createImm(64 - (B + N))); 1116 TmpInst.addOperand(MCOperand::createImm(B)); 1117 Inst = TmpInst; 1118 break; 1119 } 1120 case PPC::ROTRDI: 1121 case PPC::ROTRDIo: { 1122 MCInst TmpInst; 1123 int64_t N = Inst.getOperand(2).getImm(); 1124 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo); 1125 TmpInst.addOperand(Inst.getOperand(0)); 1126 TmpInst.addOperand(Inst.getOperand(1)); 1127 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1128 TmpInst.addOperand(MCOperand::createImm(0)); 1129 Inst = TmpInst; 1130 break; 1131 } 1132 case PPC::SLDI: 1133 case PPC::SLDIo: { 1134 MCInst TmpInst; 1135 int64_t N = Inst.getOperand(2).getImm(); 1136 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo); 1137 TmpInst.addOperand(Inst.getOperand(0)); 1138 TmpInst.addOperand(Inst.getOperand(1)); 1139 TmpInst.addOperand(MCOperand::createImm(N)); 1140 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1141 Inst = TmpInst; 1142 break; 1143 } 1144 case PPC::SUBPCIS: { 1145 MCInst TmpInst; 1146 int64_t N = Inst.getOperand(1).getImm(); 1147 TmpInst.setOpcode(PPC::ADDPCIS); 1148 TmpInst.addOperand(Inst.getOperand(0)); 1149 TmpInst.addOperand(MCOperand::createImm(-N)); 1150 Inst = TmpInst; 1151 break; 1152 } 1153 case PPC::SRDI: 1154 case PPC::SRDIo: { 1155 MCInst TmpInst; 1156 int64_t N = Inst.getOperand(2).getImm(); 1157 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo); 1158 TmpInst.addOperand(Inst.getOperand(0)); 1159 TmpInst.addOperand(Inst.getOperand(1)); 1160 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1161 TmpInst.addOperand(MCOperand::createImm(N)); 1162 Inst = TmpInst; 1163 break; 1164 } 1165 case PPC::CLRRDI: 1166 case PPC::CLRRDIo: { 1167 MCInst TmpInst; 1168 int64_t N = Inst.getOperand(2).getImm(); 1169 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo); 1170 TmpInst.addOperand(Inst.getOperand(0)); 1171 TmpInst.addOperand(Inst.getOperand(1)); 1172 TmpInst.addOperand(MCOperand::createImm(0)); 1173 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1174 Inst = TmpInst; 1175 break; 1176 } 1177 case PPC::CLRLSLDI: 1178 case PPC::CLRLSLDIo: { 1179 MCInst TmpInst; 1180 int64_t B = Inst.getOperand(2).getImm(); 1181 int64_t N = Inst.getOperand(3).getImm(); 1182 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo); 1183 TmpInst.addOperand(Inst.getOperand(0)); 1184 TmpInst.addOperand(Inst.getOperand(1)); 1185 TmpInst.addOperand(MCOperand::createImm(N)); 1186 TmpInst.addOperand(MCOperand::createImm(B - N)); 1187 Inst = TmpInst; 1188 break; 1189 } 1190 case PPC::RLWINMbm: 1191 case PPC::RLWINMobm: { 1192 unsigned MB, ME; 1193 int64_t BM = Inst.getOperand(3).getImm(); 1194 if (!isRunOfOnes(BM, MB, ME)) 1195 break; 1196 1197 MCInst TmpInst; 1198 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo); 1199 TmpInst.addOperand(Inst.getOperand(0)); 1200 TmpInst.addOperand(Inst.getOperand(1)); 1201 TmpInst.addOperand(Inst.getOperand(2)); 1202 TmpInst.addOperand(MCOperand::createImm(MB)); 1203 TmpInst.addOperand(MCOperand::createImm(ME)); 1204 Inst = TmpInst; 1205 break; 1206 } 1207 case PPC::RLWIMIbm: 1208 case PPC::RLWIMIobm: { 1209 unsigned MB, ME; 1210 int64_t BM = Inst.getOperand(3).getImm(); 1211 if (!isRunOfOnes(BM, MB, ME)) 1212 break; 1213 1214 MCInst TmpInst; 1215 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo); 1216 TmpInst.addOperand(Inst.getOperand(0)); 1217 TmpInst.addOperand(Inst.getOperand(0)); // The tied operand. 1218 TmpInst.addOperand(Inst.getOperand(1)); 1219 TmpInst.addOperand(Inst.getOperand(2)); 1220 TmpInst.addOperand(MCOperand::createImm(MB)); 1221 TmpInst.addOperand(MCOperand::createImm(ME)); 1222 Inst = TmpInst; 1223 break; 1224 } 1225 case PPC::RLWNMbm: 1226 case PPC::RLWNMobm: { 1227 unsigned MB, ME; 1228 int64_t BM = Inst.getOperand(3).getImm(); 1229 if (!isRunOfOnes(BM, MB, ME)) 1230 break; 1231 1232 MCInst TmpInst; 1233 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo); 1234 TmpInst.addOperand(Inst.getOperand(0)); 1235 TmpInst.addOperand(Inst.getOperand(1)); 1236 TmpInst.addOperand(Inst.getOperand(2)); 1237 TmpInst.addOperand(MCOperand::createImm(MB)); 1238 TmpInst.addOperand(MCOperand::createImm(ME)); 1239 Inst = TmpInst; 1240 break; 1241 } 1242 case PPC::MFTB: { 1243 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) { 1244 assert(Inst.getNumOperands() == 2 && "Expecting two operands"); 1245 Inst.setOpcode(PPC::MFSPR); 1246 } 1247 break; 1248 } 1249 case PPC::CP_COPYx: 1250 case PPC::CP_COPY_FIRST: { 1251 MCInst TmpInst; 1252 TmpInst.setOpcode(PPC::CP_COPY); 1253 TmpInst.addOperand(Inst.getOperand(0)); 1254 TmpInst.addOperand(Inst.getOperand(1)); 1255 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1)); 1256 1257 Inst = TmpInst; 1258 break; 1259 } 1260 case PPC::CP_PASTEx : 1261 case PPC::CP_PASTE_LAST: { 1262 MCInst TmpInst; 1263 TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ? 1264 PPC::CP_PASTE : PPC::CP_PASTEo); 1265 TmpInst.addOperand(Inst.getOperand(0)); 1266 TmpInst.addOperand(Inst.getOperand(1)); 1267 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1)); 1268 1269 Inst = TmpInst; 1270 break; 1271 } 1272 } 1273 } 1274 1275 static std::string PPCMnemonicSpellCheck(StringRef S, uint64_t FBS, 1276 unsigned VariantID = 0); 1277 1278 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 1279 OperandVector &Operands, 1280 MCStreamer &Out, uint64_t &ErrorInfo, 1281 bool MatchingInlineAsm) { 1282 MCInst Inst; 1283 1284 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { 1285 case Match_Success: 1286 // Post-process instructions (typically extended mnemonics) 1287 ProcessInstruction(Inst, Operands); 1288 Inst.setLoc(IDLoc); 1289 Out.EmitInstruction(Inst, getSTI()); 1290 return false; 1291 case Match_MissingFeature: 1292 return Error(IDLoc, "instruction use requires an option to be enabled"); 1293 case Match_MnemonicFail: { 1294 uint64_t FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); 1295 std::string Suggestion = PPCMnemonicSpellCheck( 1296 ((PPCOperand &)*Operands[0]).getToken(), FBS); 1297 return Error(IDLoc, "invalid instruction" + Suggestion, 1298 ((PPCOperand &)*Operands[0]).getLocRange()); 1299 } 1300 case Match_InvalidOperand: { 1301 SMLoc ErrorLoc = IDLoc; 1302 if (ErrorInfo != ~0ULL) { 1303 if (ErrorInfo >= Operands.size()) 1304 return Error(IDLoc, "too few operands for instruction"); 1305 1306 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc(); 1307 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 1308 } 1309 1310 return Error(ErrorLoc, "invalid operand for instruction"); 1311 } 1312 } 1313 1314 llvm_unreachable("Implement any new match types added!"); 1315 } 1316 1317 bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) { 1318 if (getParser().getTok().is(AsmToken::Identifier)) { 1319 StringRef Name = getParser().getTok().getString(); 1320 if (Name.equals_lower("lr")) { 1321 RegNo = isPPC64()? PPC::LR8 : PPC::LR; 1322 IntVal = 8; 1323 } else if (Name.equals_lower("ctr")) { 1324 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR; 1325 IntVal = 9; 1326 } else if (Name.equals_lower("vrsave")) { 1327 RegNo = PPC::VRSAVE; 1328 IntVal = 256; 1329 } else if (Name.startswith_lower("r") && 1330 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1331 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal]; 1332 } else if (Name.startswith_lower("f") && 1333 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1334 RegNo = FRegs[IntVal]; 1335 } else if (Name.startswith_lower("vs") && 1336 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) { 1337 RegNo = VSRegs[IntVal]; 1338 } else if (Name.startswith_lower("v") && 1339 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1340 RegNo = VRegs[IntVal]; 1341 } else if (Name.startswith_lower("q") && 1342 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1343 RegNo = QFRegs[IntVal]; 1344 } else if (Name.startswith_lower("cr") && 1345 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { 1346 RegNo = CRRegs[IntVal]; 1347 } else 1348 return true; 1349 getParser().Lex(); 1350 return false; 1351 } 1352 return true; 1353 } 1354 1355 bool PPCAsmParser:: 1356 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 1357 const AsmToken &Tok = getParser().getTok(); 1358 StartLoc = Tok.getLoc(); 1359 EndLoc = Tok.getEndLoc(); 1360 RegNo = 0; 1361 int64_t IntVal; 1362 if (MatchRegisterName(RegNo, IntVal)) 1363 return TokError("invalid register name"); 1364 return false; 1365 } 1366 1367 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan 1368 /// the expression and check for VK_PPC_LO/HI/HA 1369 /// symbol variants. If all symbols with modifier use the same 1370 /// variant, return the corresponding PPCMCExpr::VariantKind, 1371 /// and a modified expression using the default symbol variant. 1372 /// Otherwise, return NULL. 1373 const MCExpr *PPCAsmParser:: 1374 ExtractModifierFromExpr(const MCExpr *E, 1375 PPCMCExpr::VariantKind &Variant) { 1376 MCContext &Context = getParser().getContext(); 1377 Variant = PPCMCExpr::VK_PPC_None; 1378 1379 switch (E->getKind()) { 1380 case MCExpr::Target: 1381 case MCExpr::Constant: 1382 return nullptr; 1383 1384 case MCExpr::SymbolRef: { 1385 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1386 1387 switch (SRE->getKind()) { 1388 case MCSymbolRefExpr::VK_PPC_LO: 1389 Variant = PPCMCExpr::VK_PPC_LO; 1390 break; 1391 case MCSymbolRefExpr::VK_PPC_HI: 1392 Variant = PPCMCExpr::VK_PPC_HI; 1393 break; 1394 case MCSymbolRefExpr::VK_PPC_HA: 1395 Variant = PPCMCExpr::VK_PPC_HA; 1396 break; 1397 case MCSymbolRefExpr::VK_PPC_HIGHER: 1398 Variant = PPCMCExpr::VK_PPC_HIGHER; 1399 break; 1400 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1401 Variant = PPCMCExpr::VK_PPC_HIGHERA; 1402 break; 1403 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1404 Variant = PPCMCExpr::VK_PPC_HIGHEST; 1405 break; 1406 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1407 Variant = PPCMCExpr::VK_PPC_HIGHESTA; 1408 break; 1409 default: 1410 return nullptr; 1411 } 1412 1413 return MCSymbolRefExpr::create(&SRE->getSymbol(), Context); 1414 } 1415 1416 case MCExpr::Unary: { 1417 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1418 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant); 1419 if (!Sub) 1420 return nullptr; 1421 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1422 } 1423 1424 case MCExpr::Binary: { 1425 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1426 PPCMCExpr::VariantKind LHSVariant, RHSVariant; 1427 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant); 1428 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant); 1429 1430 if (!LHS && !RHS) 1431 return nullptr; 1432 1433 if (!LHS) LHS = BE->getLHS(); 1434 if (!RHS) RHS = BE->getRHS(); 1435 1436 if (LHSVariant == PPCMCExpr::VK_PPC_None) 1437 Variant = RHSVariant; 1438 else if (RHSVariant == PPCMCExpr::VK_PPC_None) 1439 Variant = LHSVariant; 1440 else if (LHSVariant == RHSVariant) 1441 Variant = LHSVariant; 1442 else 1443 return nullptr; 1444 1445 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1446 } 1447 } 1448 1449 llvm_unreachable("Invalid expression kind!"); 1450 } 1451 1452 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace 1453 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having 1454 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT. 1455 /// FIXME: This is a hack. 1456 const MCExpr *PPCAsmParser:: 1457 FixupVariantKind(const MCExpr *E) { 1458 MCContext &Context = getParser().getContext(); 1459 1460 switch (E->getKind()) { 1461 case MCExpr::Target: 1462 case MCExpr::Constant: 1463 return E; 1464 1465 case MCExpr::SymbolRef: { 1466 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1467 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; 1468 1469 switch (SRE->getKind()) { 1470 case MCSymbolRefExpr::VK_TLSGD: 1471 Variant = MCSymbolRefExpr::VK_PPC_TLSGD; 1472 break; 1473 case MCSymbolRefExpr::VK_TLSLD: 1474 Variant = MCSymbolRefExpr::VK_PPC_TLSLD; 1475 break; 1476 default: 1477 return E; 1478 } 1479 return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context); 1480 } 1481 1482 case MCExpr::Unary: { 1483 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1484 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr()); 1485 if (Sub == UE->getSubExpr()) 1486 return E; 1487 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1488 } 1489 1490 case MCExpr::Binary: { 1491 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1492 const MCExpr *LHS = FixupVariantKind(BE->getLHS()); 1493 const MCExpr *RHS = FixupVariantKind(BE->getRHS()); 1494 if (LHS == BE->getLHS() && RHS == BE->getRHS()) 1495 return E; 1496 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1497 } 1498 } 1499 1500 llvm_unreachable("Invalid expression kind!"); 1501 } 1502 1503 /// ParseExpression. This differs from the default "parseExpression" in that 1504 /// it handles modifiers. 1505 bool PPCAsmParser:: 1506 ParseExpression(const MCExpr *&EVal) { 1507 1508 if (isDarwin()) 1509 return ParseDarwinExpression(EVal); 1510 1511 // (ELF Platforms) 1512 // Handle \code @l/@ha \endcode 1513 if (getParser().parseExpression(EVal)) 1514 return true; 1515 1516 EVal = FixupVariantKind(EVal); 1517 1518 PPCMCExpr::VariantKind Variant; 1519 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant); 1520 if (E) 1521 EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext()); 1522 1523 return false; 1524 } 1525 1526 /// ParseDarwinExpression. (MachO Platforms) 1527 /// This differs from the default "parseExpression" in that it handles detection 1528 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present, 1529 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO 1530 /// syntax form so it is done here. TODO: Determine if there is merit in 1531 /// arranging for this to be done at a higher level. 1532 bool PPCAsmParser:: 1533 ParseDarwinExpression(const MCExpr *&EVal) { 1534 MCAsmParser &Parser = getParser(); 1535 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None; 1536 switch (getLexer().getKind()) { 1537 default: 1538 break; 1539 case AsmToken::Identifier: 1540 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus 1541 // something starting with any other char should be part of the 1542 // asm syntax. If handwritten asm includes an identifier like lo16, 1543 // then all bets are off - but no-one would do that, right? 1544 StringRef poss = Parser.getTok().getString(); 1545 if (poss.equals_lower("lo16")) { 1546 Variant = PPCMCExpr::VK_PPC_LO; 1547 } else if (poss.equals_lower("hi16")) { 1548 Variant = PPCMCExpr::VK_PPC_HI; 1549 } else if (poss.equals_lower("ha16")) { 1550 Variant = PPCMCExpr::VK_PPC_HA; 1551 } 1552 if (Variant != PPCMCExpr::VK_PPC_None) { 1553 Parser.Lex(); // Eat the xx16 1554 if (getLexer().isNot(AsmToken::LParen)) 1555 return Error(Parser.getTok().getLoc(), "expected '('"); 1556 Parser.Lex(); // Eat the '(' 1557 } 1558 break; 1559 } 1560 1561 if (getParser().parseExpression(EVal)) 1562 return true; 1563 1564 if (Variant != PPCMCExpr::VK_PPC_None) { 1565 if (getLexer().isNot(AsmToken::RParen)) 1566 return Error(Parser.getTok().getLoc(), "expected ')'"); 1567 Parser.Lex(); // Eat the ')' 1568 EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext()); 1569 } 1570 return false; 1571 } 1572 1573 /// ParseOperand 1574 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and 1575 /// rNN for MachO. 1576 bool PPCAsmParser::ParseOperand(OperandVector &Operands) { 1577 MCAsmParser &Parser = getParser(); 1578 SMLoc S = Parser.getTok().getLoc(); 1579 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1580 const MCExpr *EVal; 1581 1582 // Attempt to parse the next token as an immediate 1583 switch (getLexer().getKind()) { 1584 // Special handling for register names. These are interpreted 1585 // as immediates corresponding to the register number. 1586 case AsmToken::Percent: 1587 Parser.Lex(); // Eat the '%'. 1588 unsigned RegNo; 1589 int64_t IntVal; 1590 if (MatchRegisterName(RegNo, IntVal)) 1591 return Error(S, "invalid register name"); 1592 1593 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1594 return false; 1595 1596 case AsmToken::Identifier: 1597 case AsmToken::LParen: 1598 case AsmToken::Plus: 1599 case AsmToken::Minus: 1600 case AsmToken::Integer: 1601 case AsmToken::Dot: 1602 case AsmToken::Dollar: 1603 case AsmToken::Exclaim: 1604 case AsmToken::Tilde: 1605 // Note that non-register-name identifiers from the compiler will begin 1606 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include 1607 // identifiers like r31foo - so we fall through in the event that parsing 1608 // a register name fails. 1609 if (isDarwin()) { 1610 unsigned RegNo; 1611 int64_t IntVal; 1612 if (!MatchRegisterName(RegNo, IntVal)) { 1613 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1614 return false; 1615 } 1616 } 1617 // All other expressions 1618 1619 if (!ParseExpression(EVal)) 1620 break; 1621 // Fall-through 1622 LLVM_FALLTHROUGH; 1623 default: 1624 return Error(S, "unknown operand"); 1625 } 1626 1627 // Push the parsed operand into the list of operands 1628 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64())); 1629 1630 // Check whether this is a TLS call expression 1631 bool TLSCall = false; 1632 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal)) 1633 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr"; 1634 1635 if (TLSCall && getLexer().is(AsmToken::LParen)) { 1636 const MCExpr *TLSSym; 1637 1638 Parser.Lex(); // Eat the '('. 1639 S = Parser.getTok().getLoc(); 1640 if (ParseExpression(TLSSym)) 1641 return Error(S, "invalid TLS call expression"); 1642 if (getLexer().isNot(AsmToken::RParen)) 1643 return Error(Parser.getTok().getLoc(), "missing ')'"); 1644 E = Parser.getTok().getLoc(); 1645 Parser.Lex(); // Eat the ')'. 1646 1647 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64())); 1648 } 1649 1650 // Otherwise, check for D-form memory operands 1651 if (!TLSCall && getLexer().is(AsmToken::LParen)) { 1652 Parser.Lex(); // Eat the '('. 1653 S = Parser.getTok().getLoc(); 1654 1655 int64_t IntVal; 1656 switch (getLexer().getKind()) { 1657 case AsmToken::Percent: 1658 Parser.Lex(); // Eat the '%'. 1659 unsigned RegNo; 1660 if (MatchRegisterName(RegNo, IntVal)) 1661 return Error(S, "invalid register name"); 1662 break; 1663 1664 case AsmToken::Integer: 1665 if (isDarwin()) 1666 return Error(S, "unexpected integer value"); 1667 else if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 || 1668 IntVal > 31) 1669 return Error(S, "invalid register number"); 1670 break; 1671 case AsmToken::Identifier: 1672 if (isDarwin()) { 1673 unsigned RegNo; 1674 if (!MatchRegisterName(RegNo, IntVal)) { 1675 break; 1676 } 1677 } 1678 LLVM_FALLTHROUGH; 1679 1680 default: 1681 return Error(S, "invalid memory operand"); 1682 } 1683 1684 E = Parser.getTok().getLoc(); 1685 if (parseToken(AsmToken::RParen, "missing ')'")) 1686 return true; 1687 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1688 } 1689 1690 return false; 1691 } 1692 1693 /// Parse an instruction mnemonic followed by its operands. 1694 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 1695 SMLoc NameLoc, OperandVector &Operands) { 1696 // The first operand is the token for the instruction name. 1697 // If the next character is a '+' or '-', we need to add it to the 1698 // instruction name, to match what TableGen is doing. 1699 std::string NewOpcode; 1700 if (parseOptionalToken(AsmToken::Plus)) { 1701 NewOpcode = Name; 1702 NewOpcode += '+'; 1703 Name = NewOpcode; 1704 } 1705 if (parseOptionalToken(AsmToken::Minus)) { 1706 NewOpcode = Name; 1707 NewOpcode += '-'; 1708 Name = NewOpcode; 1709 } 1710 // If the instruction ends in a '.', we need to create a separate 1711 // token for it, to match what TableGen is doing. 1712 size_t Dot = Name.find('.'); 1713 StringRef Mnemonic = Name.slice(0, Dot); 1714 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1715 Operands.push_back( 1716 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64())); 1717 else 1718 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64())); 1719 if (Dot != StringRef::npos) { 1720 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot); 1721 StringRef DotStr = Name.slice(Dot, StringRef::npos); 1722 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1723 Operands.push_back( 1724 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64())); 1725 else 1726 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64())); 1727 } 1728 1729 // If there are no more operands then finish 1730 if (parseOptionalToken(AsmToken::EndOfStatement)) 1731 return false; 1732 1733 // Parse the first operand 1734 if (ParseOperand(Operands)) 1735 return true; 1736 1737 while (!parseOptionalToken(AsmToken::EndOfStatement)) { 1738 if (parseToken(AsmToken::Comma) || ParseOperand(Operands)) 1739 return true; 1740 } 1741 1742 // We'll now deal with an unfortunate special case: the syntax for the dcbt 1743 // and dcbtst instructions differs for server vs. embedded cores. 1744 // The syntax for dcbt is: 1745 // dcbt ra, rb, th [server] 1746 // dcbt th, ra, rb [embedded] 1747 // where th can be omitted when it is 0. dcbtst is the same. We take the 1748 // server form to be the default, so swap the operands if we're parsing for 1749 // an embedded core (they'll be swapped again upon printing). 1750 if (getSTI().getFeatureBits()[PPC::FeatureBookE] && 1751 Operands.size() == 4 && 1752 (Name == "dcbt" || Name == "dcbtst")) { 1753 std::swap(Operands[1], Operands[3]); 1754 std::swap(Operands[2], Operands[1]); 1755 } 1756 1757 return false; 1758 } 1759 1760 /// ParseDirective parses the PPC specific directives 1761 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) { 1762 StringRef IDVal = DirectiveID.getIdentifier(); 1763 if (isDarwin()) { 1764 if (IDVal == ".machine") 1765 ParseDarwinDirectiveMachine(DirectiveID.getLoc()); 1766 else 1767 return true; 1768 } else if (IDVal == ".word") 1769 ParseDirectiveWord(2, DirectiveID); 1770 else if (IDVal == ".llong") 1771 ParseDirectiveWord(8, DirectiveID); 1772 else if (IDVal == ".tc") 1773 ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID); 1774 else if (IDVal == ".machine") 1775 ParseDirectiveMachine(DirectiveID.getLoc()); 1776 else if (IDVal == ".abiversion") 1777 ParseDirectiveAbiVersion(DirectiveID.getLoc()); 1778 else if (IDVal == ".localentry") 1779 ParseDirectiveLocalEntry(DirectiveID.getLoc()); 1780 else 1781 return true; 1782 return false; 1783 } 1784 1785 /// ParseDirectiveWord 1786 /// ::= .word [ expression (, expression)* ] 1787 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) { 1788 auto parseOp = [&]() -> bool { 1789 const MCExpr *Value; 1790 SMLoc ExprLoc = getParser().getTok().getLoc(); 1791 if (getParser().parseExpression(Value)) 1792 return true; 1793 if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) { 1794 assert(Size <= 8 && "Invalid size"); 1795 uint64_t IntValue = MCE->getValue(); 1796 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue)) 1797 return Error(ExprLoc, "literal value out of range for '" + 1798 ID.getIdentifier() + "' directive"); 1799 getStreamer().EmitIntValue(IntValue, Size); 1800 } else 1801 getStreamer().EmitValue(Value, Size, ExprLoc); 1802 return false; 1803 }; 1804 1805 if (parseMany(parseOp)) 1806 return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive"); 1807 return false; 1808 } 1809 1810 /// ParseDirectiveTC 1811 /// ::= .tc [ symbol (, expression)* ] 1812 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) { 1813 MCAsmParser &Parser = getParser(); 1814 // Skip TC symbol, which is only used with XCOFF. 1815 while (getLexer().isNot(AsmToken::EndOfStatement) 1816 && getLexer().isNot(AsmToken::Comma)) 1817 Parser.Lex(); 1818 if (parseToken(AsmToken::Comma)) 1819 return addErrorSuffix(" in '.tc' directive"); 1820 1821 // Align to word size. 1822 getParser().getStreamer().EmitValueToAlignment(Size); 1823 1824 // Emit expressions. 1825 return ParseDirectiveWord(Size, ID); 1826 } 1827 1828 /// ParseDirectiveMachine (ELF platforms) 1829 /// ::= .machine [ cpu | "push" | "pop" ] 1830 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) { 1831 MCAsmParser &Parser = getParser(); 1832 if (Parser.getTok().isNot(AsmToken::Identifier) && 1833 Parser.getTok().isNot(AsmToken::String)) 1834 return Error(L, "unexpected token in '.machine' directive"); 1835 1836 StringRef CPU = Parser.getTok().getIdentifier(); 1837 1838 // FIXME: Right now, the parser always allows any available 1839 // instruction, so the .machine directive is not useful. 1840 // Implement ".machine any" (by doing nothing) for the benefit 1841 // of existing assembler code. Likewise, we can then implement 1842 // ".machine push" and ".machine pop" as no-op. 1843 if (CPU != "any" && CPU != "push" && CPU != "pop") 1844 return TokError("unrecognized machine type"); 1845 1846 Parser.Lex(); 1847 1848 if (parseToken(AsmToken::EndOfStatement)) 1849 return addErrorSuffix(" in '.machine' directive"); 1850 1851 PPCTargetStreamer &TStreamer = 1852 *static_cast<PPCTargetStreamer *>( 1853 getParser().getStreamer().getTargetStreamer()); 1854 TStreamer.emitMachine(CPU); 1855 1856 return false; 1857 } 1858 1859 /// ParseDarwinDirectiveMachine (Mach-o platforms) 1860 /// ::= .machine cpu-identifier 1861 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) { 1862 MCAsmParser &Parser = getParser(); 1863 if (Parser.getTok().isNot(AsmToken::Identifier) && 1864 Parser.getTok().isNot(AsmToken::String)) 1865 return Error(L, "unexpected token in directive"); 1866 1867 StringRef CPU = Parser.getTok().getIdentifier(); 1868 Parser.Lex(); 1869 1870 // FIXME: this is only the 'default' set of cpu variants. 1871 // However we don't act on this information at present, this is simply 1872 // allowing parsing to proceed with minimal sanity checking. 1873 if (check(CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64", L, 1874 "unrecognized cpu type") || 1875 check(isPPC64() && (CPU == "ppc7400" || CPU == "ppc"), L, 1876 "wrong cpu type specified for 64bit") || 1877 check(!isPPC64() && CPU == "ppc64", L, 1878 "wrong cpu type specified for 32bit") || 1879 parseToken(AsmToken::EndOfStatement)) 1880 return addErrorSuffix(" in '.machine' directive"); 1881 return false; 1882 } 1883 1884 /// ParseDirectiveAbiVersion 1885 /// ::= .abiversion constant-expression 1886 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) { 1887 int64_t AbiVersion; 1888 if (check(getParser().parseAbsoluteExpression(AbiVersion), L, 1889 "expected constant expression") || 1890 parseToken(AsmToken::EndOfStatement)) 1891 return addErrorSuffix(" in '.abiversion' directive"); 1892 1893 PPCTargetStreamer &TStreamer = 1894 *static_cast<PPCTargetStreamer *>( 1895 getParser().getStreamer().getTargetStreamer()); 1896 TStreamer.emitAbiVersion(AbiVersion); 1897 1898 return false; 1899 } 1900 1901 /// ParseDirectiveLocalEntry 1902 /// ::= .localentry symbol, expression 1903 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) { 1904 StringRef Name; 1905 if (getParser().parseIdentifier(Name)) 1906 return Error(L, "expected identifier in '.localentry' directive"); 1907 1908 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name)); 1909 const MCExpr *Expr; 1910 1911 if (parseToken(AsmToken::Comma) || 1912 check(getParser().parseExpression(Expr), L, "expected expression") || 1913 parseToken(AsmToken::EndOfStatement)) 1914 return addErrorSuffix(" in '.localentry' directive"); 1915 1916 PPCTargetStreamer &TStreamer = 1917 *static_cast<PPCTargetStreamer *>( 1918 getParser().getStreamer().getTargetStreamer()); 1919 TStreamer.emitLocalEntry(Sym, Expr); 1920 1921 return false; 1922 } 1923 1924 1925 1926 /// Force static initialization. 1927 extern "C" void LLVMInitializePowerPCAsmParser() { 1928 RegisterMCAsmParser<PPCAsmParser> A(getThePPC32Target()); 1929 RegisterMCAsmParser<PPCAsmParser> B(getThePPC64Target()); 1930 RegisterMCAsmParser<PPCAsmParser> C(getThePPC64LETarget()); 1931 } 1932 1933 #define GET_REGISTER_MATCHER 1934 #define GET_MATCHER_IMPLEMENTATION 1935 #define GET_MNEMONIC_SPELL_CHECKER 1936 #include "PPCGenAsmMatcher.inc" 1937 1938 // Define this matcher function after the auto-generated include so we 1939 // have the match class enum definitions. 1940 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, 1941 unsigned Kind) { 1942 // If the kind is a token for a literal immediate, check if our asm 1943 // operand matches. This is for InstAliases which have a fixed-value 1944 // immediate in the syntax. 1945 int64_t ImmVal; 1946 switch (Kind) { 1947 case MCK_0: ImmVal = 0; break; 1948 case MCK_1: ImmVal = 1; break; 1949 case MCK_2: ImmVal = 2; break; 1950 case MCK_3: ImmVal = 3; break; 1951 case MCK_4: ImmVal = 4; break; 1952 case MCK_5: ImmVal = 5; break; 1953 case MCK_6: ImmVal = 6; break; 1954 case MCK_7: ImmVal = 7; break; 1955 default: return Match_InvalidOperand; 1956 } 1957 1958 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp); 1959 if (Op.isImm() && Op.getImm() == ImmVal) 1960 return Match_Success; 1961 1962 return Match_InvalidOperand; 1963 } 1964 1965 const MCExpr * 1966 PPCAsmParser::applyModifierToExpr(const MCExpr *E, 1967 MCSymbolRefExpr::VariantKind Variant, 1968 MCContext &Ctx) { 1969 switch (Variant) { 1970 case MCSymbolRefExpr::VK_PPC_LO: 1971 return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx); 1972 case MCSymbolRefExpr::VK_PPC_HI: 1973 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx); 1974 case MCSymbolRefExpr::VK_PPC_HA: 1975 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx); 1976 case MCSymbolRefExpr::VK_PPC_HIGHER: 1977 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx); 1978 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1979 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx); 1980 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1981 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx); 1982 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1983 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx); 1984 default: 1985 return nullptr; 1986 } 1987 } 1988