xref: /llvm-project/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (revision dda8e784f616390e03c132203685a58dcefea5d7) 
1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCTargetAsmParser.h"
29 #include "llvm/Support/SourceMgr.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
32 
33 using namespace llvm;
34 
35 namespace {
36 
37 static unsigned RRegs[32] = {
38   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
39   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
40   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
41   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
42   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
43   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
44   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
45   PPC::R28, PPC::R29, PPC::R30, PPC::R31
46 };
47 static unsigned RRegsNoR0[32] = {
48   PPC::ZERO,
49             PPC::R1,  PPC::R2,  PPC::R3,
50   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
51   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
52   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
53   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
54   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
55   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
56   PPC::R28, PPC::R29, PPC::R30, PPC::R31
57 };
58 static unsigned XRegs[32] = {
59   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
60   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
61   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
62   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
63   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
64   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
65   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
66   PPC::X28, PPC::X29, PPC::X30, PPC::X31
67 };
68 static unsigned XRegsNoX0[32] = {
69   PPC::ZERO8,
70             PPC::X1,  PPC::X2,  PPC::X3,
71   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
72   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
73   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
74   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
75   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
76   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
77   PPC::X28, PPC::X29, PPC::X30, PPC::X31
78 };
79 static unsigned FRegs[32] = {
80   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
81   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
82   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
83   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
84   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
85   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
86   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
87   PPC::F28, PPC::F29, PPC::F30, PPC::F31
88 };
89 static unsigned VRegs[32] = {
90   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
91   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
92   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
93   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
94   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
95   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
96   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
97   PPC::V28, PPC::V29, PPC::V30, PPC::V31
98 };
99 static unsigned VSRegs[64] = {
100   PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
101   PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
102   PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
103   PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
104   PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
105   PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
106   PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
107   PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
108 
109   PPC::VSH0,  PPC::VSH1,  PPC::VSH2,  PPC::VSH3,
110   PPC::VSH4,  PPC::VSH5,  PPC::VSH6,  PPC::VSH7,
111   PPC::VSH8,  PPC::VSH9,  PPC::VSH10, PPC::VSH11,
112   PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
113   PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
114   PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
115   PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
116   PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
117 };
118 static unsigned VSFRegs[64] = {
119   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
120   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
121   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
122   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
123   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
124   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
125   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
126   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
127 
128   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
129   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
130   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
131   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
132   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
133   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
134   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
135   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
136 };
137 static unsigned CRBITRegs[32] = {
138   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
139   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
140   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
141   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
142   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
143   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
144   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
145   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
146 };
147 static unsigned CRRegs[8] = {
148   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
149   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
150 };
151 
152 // Evaluate an expression containing condition register
153 // or condition register field symbols.  Returns positive
154 // value on success, or -1 on error.
155 static int64_t
156 EvaluateCRExpr(const MCExpr *E) {
157   switch (E->getKind()) {
158   case MCExpr::Target:
159     return -1;
160 
161   case MCExpr::Constant: {
162     int64_t Res = cast<MCConstantExpr>(E)->getValue();
163     return Res < 0 ? -1 : Res;
164   }
165 
166   case MCExpr::SymbolRef: {
167     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
168     StringRef Name = SRE->getSymbol().getName();
169 
170     if (Name == "lt") return 0;
171     if (Name == "gt") return 1;
172     if (Name == "eq") return 2;
173     if (Name == "so") return 3;
174     if (Name == "un") return 3;
175 
176     if (Name == "cr0") return 0;
177     if (Name == "cr1") return 1;
178     if (Name == "cr2") return 2;
179     if (Name == "cr3") return 3;
180     if (Name == "cr4") return 4;
181     if (Name == "cr5") return 5;
182     if (Name == "cr6") return 6;
183     if (Name == "cr7") return 7;
184 
185     return -1;
186   }
187 
188   case MCExpr::Unary:
189     return -1;
190 
191   case MCExpr::Binary: {
192     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
193     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
194     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
195     int64_t Res;
196 
197     if (LHSVal < 0 || RHSVal < 0)
198       return -1;
199 
200     switch (BE->getOpcode()) {
201     default: return -1;
202     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
203     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
204     }
205 
206     return Res < 0 ? -1 : Res;
207   }
208   }
209 
210   llvm_unreachable("Invalid expression kind!");
211 }
212 
213 struct PPCOperand;
214 
215 class PPCAsmParser : public MCTargetAsmParser {
216   MCSubtargetInfo &STI;
217   MCAsmParser &Parser;
218   const MCInstrInfo &MII;
219   bool IsPPC64;
220   bool IsDarwin;
221 
222   MCAsmParser &getParser() const { return Parser; }
223   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
224 
225   void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
226   bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
227 
228   bool isPPC64() const { return IsPPC64; }
229   bool isDarwin() const { return IsDarwin; }
230 
231   bool MatchRegisterName(const AsmToken &Tok,
232                          unsigned &RegNo, int64_t &IntVal);
233 
234   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
235 
236   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
237                                         PPCMCExpr::VariantKind &Variant);
238   const MCExpr *FixupVariantKind(const MCExpr *E);
239   bool ParseExpression(const MCExpr *&EVal);
240   bool ParseDarwinExpression(const MCExpr *&EVal);
241 
242   bool ParseOperand(OperandVector &Operands);
243 
244   bool ParseDirectiveWord(unsigned Size, SMLoc L);
245   bool ParseDirectiveTC(unsigned Size, SMLoc L);
246   bool ParseDirectiveMachine(SMLoc L);
247   bool ParseDarwinDirectiveMachine(SMLoc L);
248   bool ParseDirectiveAbiVersion(SMLoc L);
249   bool ParseDirectiveLocalEntry(SMLoc L);
250 
251   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
252                                OperandVector &Operands, MCStreamer &Out,
253                                unsigned &ErrorInfo,
254                                bool MatchingInlineAsm) override;
255 
256   void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
257 
258   /// @name Auto-generated Match Functions
259   /// {
260 
261 #define GET_ASSEMBLER_HEADER
262 #include "PPCGenAsmMatcher.inc"
263 
264   /// }
265 
266 
267 public:
268   PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
269                const MCInstrInfo &_MII,
270                const MCTargetOptions &Options)
271       : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) {
272     // Check for 64-bit vs. 32-bit pointer mode.
273     Triple TheTriple(STI.getTargetTriple());
274     IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
275                TheTriple.getArch() == Triple::ppc64le);
276     IsDarwin = TheTriple.isMacOSX();
277     // Initialize the set of available features.
278     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
279   }
280 
281   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
282                         SMLoc NameLoc, OperandVector &Operands) override;
283 
284   bool ParseDirective(AsmToken DirectiveID) override;
285 
286   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
287                                       unsigned Kind) override;
288 
289   const MCExpr *applyModifierToExpr(const MCExpr *E,
290                                     MCSymbolRefExpr::VariantKind,
291                                     MCContext &Ctx) override;
292 };
293 
294 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
295 /// instruction.
296 struct PPCOperand : public MCParsedAsmOperand {
297   enum KindTy {
298     Token,
299     Immediate,
300     Expression,
301     TLSRegister
302   } Kind;
303 
304   SMLoc StartLoc, EndLoc;
305   bool IsPPC64;
306 
307   struct TokOp {
308     const char *Data;
309     unsigned Length;
310   };
311 
312   struct ImmOp {
313     int64_t Val;
314   };
315 
316   struct ExprOp {
317     const MCExpr *Val;
318     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
319   };
320 
321   struct TLSRegOp {
322     const MCSymbolRefExpr *Sym;
323   };
324 
325   union {
326     struct TokOp Tok;
327     struct ImmOp Imm;
328     struct ExprOp Expr;
329     struct TLSRegOp TLSReg;
330   };
331 
332   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
333 public:
334   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
335     Kind = o.Kind;
336     StartLoc = o.StartLoc;
337     EndLoc = o.EndLoc;
338     IsPPC64 = o.IsPPC64;
339     switch (Kind) {
340     case Token:
341       Tok = o.Tok;
342       break;
343     case Immediate:
344       Imm = o.Imm;
345       break;
346     case Expression:
347       Expr = o.Expr;
348       break;
349     case TLSRegister:
350       TLSReg = o.TLSReg;
351       break;
352     }
353   }
354 
355   /// getStartLoc - Get the location of the first token of this operand.
356   SMLoc getStartLoc() const override { return StartLoc; }
357 
358   /// getEndLoc - Get the location of the last token of this operand.
359   SMLoc getEndLoc() const override { return EndLoc; }
360 
361   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
362   bool isPPC64() const { return IsPPC64; }
363 
364   int64_t getImm() const {
365     assert(Kind == Immediate && "Invalid access!");
366     return Imm.Val;
367   }
368 
369   const MCExpr *getExpr() const {
370     assert(Kind == Expression && "Invalid access!");
371     return Expr.Val;
372   }
373 
374   int64_t getExprCRVal() const {
375     assert(Kind == Expression && "Invalid access!");
376     return Expr.CRVal;
377   }
378 
379   const MCExpr *getTLSReg() const {
380     assert(Kind == TLSRegister && "Invalid access!");
381     return TLSReg.Sym;
382   }
383 
384   unsigned getReg() const override {
385     assert(isRegNumber() && "Invalid access!");
386     return (unsigned) Imm.Val;
387   }
388 
389   unsigned getVSReg() const {
390     assert(isVSRegNumber() && "Invalid access!");
391     return (unsigned) Imm.Val;
392   }
393 
394   unsigned getCCReg() const {
395     assert(isCCRegNumber() && "Invalid access!");
396     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
397   }
398 
399   unsigned getCRBit() const {
400     assert(isCRBitNumber() && "Invalid access!");
401     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
402   }
403 
404   unsigned getCRBitMask() const {
405     assert(isCRBitMask() && "Invalid access!");
406     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
407   }
408 
409   bool isToken() const override { return Kind == Token; }
410   bool isImm() const override { return Kind == Immediate || Kind == Expression; }
411   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
412   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
413   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
414   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
415   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
416   bool isU16Imm() const { return Kind == Expression ||
417                                  (Kind == Immediate && isUInt<16>(getImm())); }
418   bool isS16Imm() const { return Kind == Expression ||
419                                  (Kind == Immediate && isInt<16>(getImm())); }
420   bool isS16ImmX4() const { return Kind == Expression ||
421                                    (Kind == Immediate && isInt<16>(getImm()) &&
422                                     (getImm() & 3) == 0); }
423   bool isS17Imm() const { return Kind == Expression ||
424                                  (Kind == Immediate && isInt<17>(getImm())); }
425   bool isTLSReg() const { return Kind == TLSRegister; }
426   bool isDirectBr() const { return Kind == Expression ||
427                                    (Kind == Immediate && isInt<26>(getImm()) &&
428                                     (getImm() & 3) == 0); }
429   bool isCondBr() const { return Kind == Expression ||
430                                  (Kind == Immediate && isInt<16>(getImm()) &&
431                                   (getImm() & 3) == 0); }
432   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
433   bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
434   bool isCCRegNumber() const { return (Kind == Expression
435                                        && isUInt<3>(getExprCRVal())) ||
436                                       (Kind == Immediate
437                                        && isUInt<3>(getImm())); }
438   bool isCRBitNumber() const { return (Kind == Expression
439                                        && isUInt<5>(getExprCRVal())) ||
440                                       (Kind == Immediate
441                                        && isUInt<5>(getImm())); }
442   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
443                                     isPowerOf2_32(getImm()); }
444   bool isMem() const override { return false; }
445   bool isReg() const override { return false; }
446 
447   void addRegOperands(MCInst &Inst, unsigned N) const {
448     llvm_unreachable("addRegOperands");
449   }
450 
451   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
452     assert(N == 1 && "Invalid number of operands!");
453     Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
454   }
455 
456   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
457     assert(N == 1 && "Invalid number of operands!");
458     Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
459   }
460 
461   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
462     assert(N == 1 && "Invalid number of operands!");
463     Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
464   }
465 
466   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
467     assert(N == 1 && "Invalid number of operands!");
468     Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
469   }
470 
471   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
472     if (isPPC64())
473       addRegG8RCOperands(Inst, N);
474     else
475       addRegGPRCOperands(Inst, N);
476   }
477 
478   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
479     if (isPPC64())
480       addRegG8RCNoX0Operands(Inst, N);
481     else
482       addRegGPRCNoR0Operands(Inst, N);
483   }
484 
485   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
486     assert(N == 1 && "Invalid number of operands!");
487     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
488   }
489 
490   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
491     assert(N == 1 && "Invalid number of operands!");
492     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
493   }
494 
495   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
496     assert(N == 1 && "Invalid number of operands!");
497     Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
498   }
499 
500   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
501     assert(N == 1 && "Invalid number of operands!");
502     Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
503   }
504 
505   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
506     assert(N == 1 && "Invalid number of operands!");
507     Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
508   }
509 
510   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
511     assert(N == 1 && "Invalid number of operands!");
512     Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
513   }
514 
515   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
516     assert(N == 1 && "Invalid number of operands!");
517     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
518   }
519 
520   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
521     assert(N == 1 && "Invalid number of operands!");
522     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
523   }
524 
525   void addImmOperands(MCInst &Inst, unsigned N) const {
526     assert(N == 1 && "Invalid number of operands!");
527     if (Kind == Immediate)
528       Inst.addOperand(MCOperand::CreateImm(getImm()));
529     else
530       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
531   }
532 
533   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
534     assert(N == 1 && "Invalid number of operands!");
535     if (Kind == Immediate)
536       Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
537     else
538       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
539   }
540 
541   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
542     assert(N == 1 && "Invalid number of operands!");
543     Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
544   }
545 
546   StringRef getToken() const {
547     assert(Kind == Token && "Invalid access!");
548     return StringRef(Tok.Data, Tok.Length);
549   }
550 
551   void print(raw_ostream &OS) const override;
552 
553   static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
554                                                  bool IsPPC64) {
555     auto Op = make_unique<PPCOperand>(Token);
556     Op->Tok.Data = Str.data();
557     Op->Tok.Length = Str.size();
558     Op->StartLoc = S;
559     Op->EndLoc = S;
560     Op->IsPPC64 = IsPPC64;
561     return Op;
562   }
563 
564   static std::unique_ptr<PPCOperand>
565   CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
566     // Allocate extra memory for the string and copy it.
567     // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
568     // deleter which will destroy them by simply using "delete", not correctly
569     // calling operator delete on this extra memory after calling the dtor
570     // explicitly.
571     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
572     std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
573     Op->Tok.Data = (const char *)(Op.get() + 1);
574     Op->Tok.Length = Str.size();
575     std::memcpy((void *)Op->Tok.Data, Str.data(), Str.size());
576     Op->StartLoc = S;
577     Op->EndLoc = S;
578     Op->IsPPC64 = IsPPC64;
579     return Op;
580   }
581 
582   static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
583                                                bool IsPPC64) {
584     auto Op = make_unique<PPCOperand>(Immediate);
585     Op->Imm.Val = Val;
586     Op->StartLoc = S;
587     Op->EndLoc = E;
588     Op->IsPPC64 = IsPPC64;
589     return Op;
590   }
591 
592   static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
593                                                 SMLoc E, bool IsPPC64) {
594     auto Op = make_unique<PPCOperand>(Expression);
595     Op->Expr.Val = Val;
596     Op->Expr.CRVal = EvaluateCRExpr(Val);
597     Op->StartLoc = S;
598     Op->EndLoc = E;
599     Op->IsPPC64 = IsPPC64;
600     return Op;
601   }
602 
603   static std::unique_ptr<PPCOperand>
604   CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
605     auto Op = make_unique<PPCOperand>(TLSRegister);
606     Op->TLSReg.Sym = Sym;
607     Op->StartLoc = S;
608     Op->EndLoc = E;
609     Op->IsPPC64 = IsPPC64;
610     return Op;
611   }
612 
613   static std::unique_ptr<PPCOperand>
614   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
615     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
616       return CreateImm(CE->getValue(), S, E, IsPPC64);
617 
618     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
619       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
620         return CreateTLSReg(SRE, S, E, IsPPC64);
621 
622     return CreateExpr(Val, S, E, IsPPC64);
623   }
624 };
625 
626 } // end anonymous namespace.
627 
628 void PPCOperand::print(raw_ostream &OS) const {
629   switch (Kind) {
630   case Token:
631     OS << "'" << getToken() << "'";
632     break;
633   case Immediate:
634     OS << getImm();
635     break;
636   case Expression:
637     getExpr()->print(OS);
638     break;
639   case TLSRegister:
640     getTLSReg()->print(OS);
641     break;
642   }
643 }
644 
645 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
646                                       const OperandVector &Operands) {
647   int Opcode = Inst.getOpcode();
648   switch (Opcode) {
649   case PPC::LAx: {
650     MCInst TmpInst;
651     TmpInst.setOpcode(PPC::LA);
652     TmpInst.addOperand(Inst.getOperand(0));
653     TmpInst.addOperand(Inst.getOperand(2));
654     TmpInst.addOperand(Inst.getOperand(1));
655     Inst = TmpInst;
656     break;
657   }
658   case PPC::SUBI: {
659     MCInst TmpInst;
660     int64_t N = Inst.getOperand(2).getImm();
661     TmpInst.setOpcode(PPC::ADDI);
662     TmpInst.addOperand(Inst.getOperand(0));
663     TmpInst.addOperand(Inst.getOperand(1));
664     TmpInst.addOperand(MCOperand::CreateImm(-N));
665     Inst = TmpInst;
666     break;
667   }
668   case PPC::SUBIS: {
669     MCInst TmpInst;
670     int64_t N = Inst.getOperand(2).getImm();
671     TmpInst.setOpcode(PPC::ADDIS);
672     TmpInst.addOperand(Inst.getOperand(0));
673     TmpInst.addOperand(Inst.getOperand(1));
674     TmpInst.addOperand(MCOperand::CreateImm(-N));
675     Inst = TmpInst;
676     break;
677   }
678   case PPC::SUBIC: {
679     MCInst TmpInst;
680     int64_t N = Inst.getOperand(2).getImm();
681     TmpInst.setOpcode(PPC::ADDIC);
682     TmpInst.addOperand(Inst.getOperand(0));
683     TmpInst.addOperand(Inst.getOperand(1));
684     TmpInst.addOperand(MCOperand::CreateImm(-N));
685     Inst = TmpInst;
686     break;
687   }
688   case PPC::SUBICo: {
689     MCInst TmpInst;
690     int64_t N = Inst.getOperand(2).getImm();
691     TmpInst.setOpcode(PPC::ADDICo);
692     TmpInst.addOperand(Inst.getOperand(0));
693     TmpInst.addOperand(Inst.getOperand(1));
694     TmpInst.addOperand(MCOperand::CreateImm(-N));
695     Inst = TmpInst;
696     break;
697   }
698   case PPC::EXTLWI:
699   case PPC::EXTLWIo: {
700     MCInst TmpInst;
701     int64_t N = Inst.getOperand(2).getImm();
702     int64_t B = Inst.getOperand(3).getImm();
703     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
704     TmpInst.addOperand(Inst.getOperand(0));
705     TmpInst.addOperand(Inst.getOperand(1));
706     TmpInst.addOperand(MCOperand::CreateImm(B));
707     TmpInst.addOperand(MCOperand::CreateImm(0));
708     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
709     Inst = TmpInst;
710     break;
711   }
712   case PPC::EXTRWI:
713   case PPC::EXTRWIo: {
714     MCInst TmpInst;
715     int64_t N = Inst.getOperand(2).getImm();
716     int64_t B = Inst.getOperand(3).getImm();
717     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
718     TmpInst.addOperand(Inst.getOperand(0));
719     TmpInst.addOperand(Inst.getOperand(1));
720     TmpInst.addOperand(MCOperand::CreateImm(B + N));
721     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
722     TmpInst.addOperand(MCOperand::CreateImm(31));
723     Inst = TmpInst;
724     break;
725   }
726   case PPC::INSLWI:
727   case PPC::INSLWIo: {
728     MCInst TmpInst;
729     int64_t N = Inst.getOperand(2).getImm();
730     int64_t B = Inst.getOperand(3).getImm();
731     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
732     TmpInst.addOperand(Inst.getOperand(0));
733     TmpInst.addOperand(Inst.getOperand(0));
734     TmpInst.addOperand(Inst.getOperand(1));
735     TmpInst.addOperand(MCOperand::CreateImm(32 - B));
736     TmpInst.addOperand(MCOperand::CreateImm(B));
737     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
738     Inst = TmpInst;
739     break;
740   }
741   case PPC::INSRWI:
742   case PPC::INSRWIo: {
743     MCInst TmpInst;
744     int64_t N = Inst.getOperand(2).getImm();
745     int64_t B = Inst.getOperand(3).getImm();
746     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
747     TmpInst.addOperand(Inst.getOperand(0));
748     TmpInst.addOperand(Inst.getOperand(0));
749     TmpInst.addOperand(Inst.getOperand(1));
750     TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
751     TmpInst.addOperand(MCOperand::CreateImm(B));
752     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
753     Inst = TmpInst;
754     break;
755   }
756   case PPC::ROTRWI:
757   case PPC::ROTRWIo: {
758     MCInst TmpInst;
759     int64_t N = Inst.getOperand(2).getImm();
760     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
761     TmpInst.addOperand(Inst.getOperand(0));
762     TmpInst.addOperand(Inst.getOperand(1));
763     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
764     TmpInst.addOperand(MCOperand::CreateImm(0));
765     TmpInst.addOperand(MCOperand::CreateImm(31));
766     Inst = TmpInst;
767     break;
768   }
769   case PPC::SLWI:
770   case PPC::SLWIo: {
771     MCInst TmpInst;
772     int64_t N = Inst.getOperand(2).getImm();
773     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
774     TmpInst.addOperand(Inst.getOperand(0));
775     TmpInst.addOperand(Inst.getOperand(1));
776     TmpInst.addOperand(MCOperand::CreateImm(N));
777     TmpInst.addOperand(MCOperand::CreateImm(0));
778     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
779     Inst = TmpInst;
780     break;
781   }
782   case PPC::SRWI:
783   case PPC::SRWIo: {
784     MCInst TmpInst;
785     int64_t N = Inst.getOperand(2).getImm();
786     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
787     TmpInst.addOperand(Inst.getOperand(0));
788     TmpInst.addOperand(Inst.getOperand(1));
789     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
790     TmpInst.addOperand(MCOperand::CreateImm(N));
791     TmpInst.addOperand(MCOperand::CreateImm(31));
792     Inst = TmpInst;
793     break;
794   }
795   case PPC::CLRRWI:
796   case PPC::CLRRWIo: {
797     MCInst TmpInst;
798     int64_t N = Inst.getOperand(2).getImm();
799     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
800     TmpInst.addOperand(Inst.getOperand(0));
801     TmpInst.addOperand(Inst.getOperand(1));
802     TmpInst.addOperand(MCOperand::CreateImm(0));
803     TmpInst.addOperand(MCOperand::CreateImm(0));
804     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
805     Inst = TmpInst;
806     break;
807   }
808   case PPC::CLRLSLWI:
809   case PPC::CLRLSLWIo: {
810     MCInst TmpInst;
811     int64_t B = Inst.getOperand(2).getImm();
812     int64_t N = Inst.getOperand(3).getImm();
813     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
814     TmpInst.addOperand(Inst.getOperand(0));
815     TmpInst.addOperand(Inst.getOperand(1));
816     TmpInst.addOperand(MCOperand::CreateImm(N));
817     TmpInst.addOperand(MCOperand::CreateImm(B - N));
818     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
819     Inst = TmpInst;
820     break;
821   }
822   case PPC::EXTLDI:
823   case PPC::EXTLDIo: {
824     MCInst TmpInst;
825     int64_t N = Inst.getOperand(2).getImm();
826     int64_t B = Inst.getOperand(3).getImm();
827     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
828     TmpInst.addOperand(Inst.getOperand(0));
829     TmpInst.addOperand(Inst.getOperand(1));
830     TmpInst.addOperand(MCOperand::CreateImm(B));
831     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
832     Inst = TmpInst;
833     break;
834   }
835   case PPC::EXTRDI:
836   case PPC::EXTRDIo: {
837     MCInst TmpInst;
838     int64_t N = Inst.getOperand(2).getImm();
839     int64_t B = Inst.getOperand(3).getImm();
840     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
841     TmpInst.addOperand(Inst.getOperand(0));
842     TmpInst.addOperand(Inst.getOperand(1));
843     TmpInst.addOperand(MCOperand::CreateImm(B + N));
844     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
845     Inst = TmpInst;
846     break;
847   }
848   case PPC::INSRDI:
849   case PPC::INSRDIo: {
850     MCInst TmpInst;
851     int64_t N = Inst.getOperand(2).getImm();
852     int64_t B = Inst.getOperand(3).getImm();
853     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
854     TmpInst.addOperand(Inst.getOperand(0));
855     TmpInst.addOperand(Inst.getOperand(0));
856     TmpInst.addOperand(Inst.getOperand(1));
857     TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
858     TmpInst.addOperand(MCOperand::CreateImm(B));
859     Inst = TmpInst;
860     break;
861   }
862   case PPC::ROTRDI:
863   case PPC::ROTRDIo: {
864     MCInst TmpInst;
865     int64_t N = Inst.getOperand(2).getImm();
866     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
867     TmpInst.addOperand(Inst.getOperand(0));
868     TmpInst.addOperand(Inst.getOperand(1));
869     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
870     TmpInst.addOperand(MCOperand::CreateImm(0));
871     Inst = TmpInst;
872     break;
873   }
874   case PPC::SLDI:
875   case PPC::SLDIo: {
876     MCInst TmpInst;
877     int64_t N = Inst.getOperand(2).getImm();
878     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
879     TmpInst.addOperand(Inst.getOperand(0));
880     TmpInst.addOperand(Inst.getOperand(1));
881     TmpInst.addOperand(MCOperand::CreateImm(N));
882     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
883     Inst = TmpInst;
884     break;
885   }
886   case PPC::SRDI:
887   case PPC::SRDIo: {
888     MCInst TmpInst;
889     int64_t N = Inst.getOperand(2).getImm();
890     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
891     TmpInst.addOperand(Inst.getOperand(0));
892     TmpInst.addOperand(Inst.getOperand(1));
893     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
894     TmpInst.addOperand(MCOperand::CreateImm(N));
895     Inst = TmpInst;
896     break;
897   }
898   case PPC::CLRRDI:
899   case PPC::CLRRDIo: {
900     MCInst TmpInst;
901     int64_t N = Inst.getOperand(2).getImm();
902     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
903     TmpInst.addOperand(Inst.getOperand(0));
904     TmpInst.addOperand(Inst.getOperand(1));
905     TmpInst.addOperand(MCOperand::CreateImm(0));
906     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
907     Inst = TmpInst;
908     break;
909   }
910   case PPC::CLRLSLDI:
911   case PPC::CLRLSLDIo: {
912     MCInst TmpInst;
913     int64_t B = Inst.getOperand(2).getImm();
914     int64_t N = Inst.getOperand(3).getImm();
915     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
916     TmpInst.addOperand(Inst.getOperand(0));
917     TmpInst.addOperand(Inst.getOperand(1));
918     TmpInst.addOperand(MCOperand::CreateImm(N));
919     TmpInst.addOperand(MCOperand::CreateImm(B - N));
920     Inst = TmpInst;
921     break;
922   }
923   }
924 }
925 
926 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
927                                            OperandVector &Operands,
928                                            MCStreamer &Out, unsigned &ErrorInfo,
929                                            bool MatchingInlineAsm) {
930   MCInst Inst;
931 
932   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
933   default: break;
934   case Match_Success:
935     // Post-process instructions (typically extended mnemonics)
936     ProcessInstruction(Inst, Operands);
937     Inst.setLoc(IDLoc);
938     Out.EmitInstruction(Inst, STI);
939     return false;
940   case Match_MissingFeature:
941     return Error(IDLoc, "instruction use requires an option to be enabled");
942   case Match_MnemonicFail:
943       return Error(IDLoc, "unrecognized instruction mnemonic");
944   case Match_InvalidOperand: {
945     SMLoc ErrorLoc = IDLoc;
946     if (ErrorInfo != ~0U) {
947       if (ErrorInfo >= Operands.size())
948         return Error(IDLoc, "too few operands for instruction");
949 
950       ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
951       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
952     }
953 
954     return Error(ErrorLoc, "invalid operand for instruction");
955   }
956   }
957 
958   llvm_unreachable("Implement any new match types added!");
959 }
960 
961 bool PPCAsmParser::
962 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
963   if (Tok.is(AsmToken::Identifier)) {
964     StringRef Name = Tok.getString();
965 
966     if (Name.equals_lower("lr")) {
967       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
968       IntVal = 8;
969       return false;
970     } else if (Name.equals_lower("ctr")) {
971       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
972       IntVal = 9;
973       return false;
974     } else if (Name.equals_lower("vrsave")) {
975       RegNo = PPC::VRSAVE;
976       IntVal = 256;
977       return false;
978     } else if (Name.startswith_lower("r") &&
979                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
980       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
981       return false;
982     } else if (Name.startswith_lower("f") &&
983                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
984       RegNo = FRegs[IntVal];
985       return false;
986     } else if (Name.startswith_lower("v") &&
987                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
988       RegNo = VRegs[IntVal];
989       return false;
990     } else if (Name.startswith_lower("cr") &&
991                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
992       RegNo = CRRegs[IntVal];
993       return false;
994     }
995   }
996 
997   return true;
998 }
999 
1000 bool PPCAsmParser::
1001 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1002   const AsmToken &Tok = Parser.getTok();
1003   StartLoc = Tok.getLoc();
1004   EndLoc = Tok.getEndLoc();
1005   RegNo = 0;
1006   int64_t IntVal;
1007 
1008   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1009     Parser.Lex(); // Eat identifier token.
1010     return false;
1011   }
1012 
1013   return Error(StartLoc, "invalid register name");
1014 }
1015 
1016 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1017 /// the expression and check for VK_PPC_LO/HI/HA
1018 /// symbol variants.  If all symbols with modifier use the same
1019 /// variant, return the corresponding PPCMCExpr::VariantKind,
1020 /// and a modified expression using the default symbol variant.
1021 /// Otherwise, return NULL.
1022 const MCExpr *PPCAsmParser::
1023 ExtractModifierFromExpr(const MCExpr *E,
1024                         PPCMCExpr::VariantKind &Variant) {
1025   MCContext &Context = getParser().getContext();
1026   Variant = PPCMCExpr::VK_PPC_None;
1027 
1028   switch (E->getKind()) {
1029   case MCExpr::Target:
1030   case MCExpr::Constant:
1031     return nullptr;
1032 
1033   case MCExpr::SymbolRef: {
1034     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1035 
1036     switch (SRE->getKind()) {
1037     case MCSymbolRefExpr::VK_PPC_LO:
1038       Variant = PPCMCExpr::VK_PPC_LO;
1039       break;
1040     case MCSymbolRefExpr::VK_PPC_HI:
1041       Variant = PPCMCExpr::VK_PPC_HI;
1042       break;
1043     case MCSymbolRefExpr::VK_PPC_HA:
1044       Variant = PPCMCExpr::VK_PPC_HA;
1045       break;
1046     case MCSymbolRefExpr::VK_PPC_HIGHER:
1047       Variant = PPCMCExpr::VK_PPC_HIGHER;
1048       break;
1049     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1050       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1051       break;
1052     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1053       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1054       break;
1055     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1056       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1057       break;
1058     default:
1059       return nullptr;
1060     }
1061 
1062     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1063   }
1064 
1065   case MCExpr::Unary: {
1066     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1067     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1068     if (!Sub)
1069       return nullptr;
1070     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1071   }
1072 
1073   case MCExpr::Binary: {
1074     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1075     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1076     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1077     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1078 
1079     if (!LHS && !RHS)
1080       return nullptr;
1081 
1082     if (!LHS) LHS = BE->getLHS();
1083     if (!RHS) RHS = BE->getRHS();
1084 
1085     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1086       Variant = RHSVariant;
1087     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1088       Variant = LHSVariant;
1089     else if (LHSVariant == RHSVariant)
1090       Variant = LHSVariant;
1091     else
1092       return nullptr;
1093 
1094     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1095   }
1096   }
1097 
1098   llvm_unreachable("Invalid expression kind!");
1099 }
1100 
1101 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1102 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1103 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1104 /// FIXME: This is a hack.
1105 const MCExpr *PPCAsmParser::
1106 FixupVariantKind(const MCExpr *E) {
1107   MCContext &Context = getParser().getContext();
1108 
1109   switch (E->getKind()) {
1110   case MCExpr::Target:
1111   case MCExpr::Constant:
1112     return E;
1113 
1114   case MCExpr::SymbolRef: {
1115     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1116     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1117 
1118     switch (SRE->getKind()) {
1119     case MCSymbolRefExpr::VK_TLSGD:
1120       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1121       break;
1122     case MCSymbolRefExpr::VK_TLSLD:
1123       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1124       break;
1125     default:
1126       return E;
1127     }
1128     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1129   }
1130 
1131   case MCExpr::Unary: {
1132     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1133     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1134     if (Sub == UE->getSubExpr())
1135       return E;
1136     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1137   }
1138 
1139   case MCExpr::Binary: {
1140     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1141     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1142     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1143     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1144       return E;
1145     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1146   }
1147   }
1148 
1149   llvm_unreachable("Invalid expression kind!");
1150 }
1151 
1152 /// ParseExpression.  This differs from the default "parseExpression" in that
1153 /// it handles modifiers.
1154 bool PPCAsmParser::
1155 ParseExpression(const MCExpr *&EVal) {
1156 
1157   if (isDarwin())
1158     return ParseDarwinExpression(EVal);
1159 
1160   // (ELF Platforms)
1161   // Handle \code @l/@ha \endcode
1162   if (getParser().parseExpression(EVal))
1163     return true;
1164 
1165   EVal = FixupVariantKind(EVal);
1166 
1167   PPCMCExpr::VariantKind Variant;
1168   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1169   if (E)
1170     EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1171 
1172   return false;
1173 }
1174 
1175 /// ParseDarwinExpression.  (MachO Platforms)
1176 /// This differs from the default "parseExpression" in that it handles detection
1177 /// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1178 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1179 /// syntax form so it is done here.  TODO: Determine if there is merit in arranging
1180 /// for this to be done at a higher level.
1181 bool PPCAsmParser::
1182 ParseDarwinExpression(const MCExpr *&EVal) {
1183   PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1184   switch (getLexer().getKind()) {
1185   default:
1186     break;
1187   case AsmToken::Identifier:
1188     // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1189     // something starting with any other char should be part of the
1190     // asm syntax.  If handwritten asm includes an identifier like lo16,
1191     // then all bets are off - but no-one would do that, right?
1192     StringRef poss = Parser.getTok().getString();
1193     if (poss.equals_lower("lo16")) {
1194       Variant = PPCMCExpr::VK_PPC_LO;
1195     } else if (poss.equals_lower("hi16")) {
1196       Variant = PPCMCExpr::VK_PPC_HI;
1197     } else if (poss.equals_lower("ha16")) {
1198       Variant = PPCMCExpr::VK_PPC_HA;
1199     }
1200     if (Variant != PPCMCExpr::VK_PPC_None) {
1201       Parser.Lex(); // Eat the xx16
1202       if (getLexer().isNot(AsmToken::LParen))
1203         return Error(Parser.getTok().getLoc(), "expected '('");
1204       Parser.Lex(); // Eat the '('
1205     }
1206     break;
1207   }
1208 
1209   if (getParser().parseExpression(EVal))
1210     return true;
1211 
1212   if (Variant != PPCMCExpr::VK_PPC_None) {
1213     if (getLexer().isNot(AsmToken::RParen))
1214       return Error(Parser.getTok().getLoc(), "expected ')'");
1215     Parser.Lex(); // Eat the ')'
1216     EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1217   }
1218   return false;
1219 }
1220 
1221 /// ParseOperand
1222 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1223 /// rNN for MachO.
1224 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1225   SMLoc S = Parser.getTok().getLoc();
1226   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1227   const MCExpr *EVal;
1228 
1229   // Attempt to parse the next token as an immediate
1230   switch (getLexer().getKind()) {
1231   // Special handling for register names.  These are interpreted
1232   // as immediates corresponding to the register number.
1233   case AsmToken::Percent:
1234     Parser.Lex(); // Eat the '%'.
1235     unsigned RegNo;
1236     int64_t IntVal;
1237     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1238       Parser.Lex(); // Eat the identifier token.
1239       Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1240       return false;
1241     }
1242     return Error(S, "invalid register name");
1243 
1244   case AsmToken::Identifier:
1245     // Note that non-register-name identifiers from the compiler will begin
1246     // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1247     // identifiers like r31foo - so we fall through in the event that parsing
1248     // a register name fails.
1249     if (isDarwin()) {
1250       unsigned RegNo;
1251       int64_t IntVal;
1252       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1253         Parser.Lex(); // Eat the identifier token.
1254         Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1255         return false;
1256       }
1257     }
1258   // Fall-through to process non-register-name identifiers as expression.
1259   // All other expressions
1260   case AsmToken::LParen:
1261   case AsmToken::Plus:
1262   case AsmToken::Minus:
1263   case AsmToken::Integer:
1264   case AsmToken::Dot:
1265   case AsmToken::Dollar:
1266   case AsmToken::Exclaim:
1267   case AsmToken::Tilde:
1268     if (!ParseExpression(EVal))
1269       break;
1270     /* fall through */
1271   default:
1272     return Error(S, "unknown operand");
1273   }
1274 
1275   // Push the parsed operand into the list of operands
1276   Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1277 
1278   // Check whether this is a TLS call expression
1279   bool TLSCall = false;
1280   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1281     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1282 
1283   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1284     const MCExpr *TLSSym;
1285 
1286     Parser.Lex(); // Eat the '('.
1287     S = Parser.getTok().getLoc();
1288     if (ParseExpression(TLSSym))
1289       return Error(S, "invalid TLS call expression");
1290     if (getLexer().isNot(AsmToken::RParen))
1291       return Error(Parser.getTok().getLoc(), "missing ')'");
1292     E = Parser.getTok().getLoc();
1293     Parser.Lex(); // Eat the ')'.
1294 
1295     Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1296   }
1297 
1298   // Otherwise, check for D-form memory operands
1299   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1300     Parser.Lex(); // Eat the '('.
1301     S = Parser.getTok().getLoc();
1302 
1303     int64_t IntVal;
1304     switch (getLexer().getKind()) {
1305     case AsmToken::Percent:
1306       Parser.Lex(); // Eat the '%'.
1307       unsigned RegNo;
1308       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1309         return Error(S, "invalid register name");
1310       Parser.Lex(); // Eat the identifier token.
1311       break;
1312 
1313     case AsmToken::Integer:
1314       if (!isDarwin()) {
1315         if (getParser().parseAbsoluteExpression(IntVal) ||
1316           IntVal < 0 || IntVal > 31)
1317         return Error(S, "invalid register number");
1318       } else {
1319         return Error(S, "unexpected integer value");
1320       }
1321       break;
1322 
1323    case AsmToken::Identifier:
1324     if (isDarwin()) {
1325       unsigned RegNo;
1326       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1327         Parser.Lex(); // Eat the identifier token.
1328         break;
1329       }
1330     }
1331     // Fall-through..
1332 
1333     default:
1334       return Error(S, "invalid memory operand");
1335     }
1336 
1337     if (getLexer().isNot(AsmToken::RParen))
1338       return Error(Parser.getTok().getLoc(), "missing ')'");
1339     E = Parser.getTok().getLoc();
1340     Parser.Lex(); // Eat the ')'.
1341 
1342     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1343   }
1344 
1345   return false;
1346 }
1347 
1348 /// Parse an instruction mnemonic followed by its operands.
1349 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1350                                     SMLoc NameLoc, OperandVector &Operands) {
1351   // The first operand is the token for the instruction name.
1352   // If the next character is a '+' or '-', we need to add it to the
1353   // instruction name, to match what TableGen is doing.
1354   std::string NewOpcode;
1355   if (getLexer().is(AsmToken::Plus)) {
1356     getLexer().Lex();
1357     NewOpcode = Name;
1358     NewOpcode += '+';
1359     Name = NewOpcode;
1360   }
1361   if (getLexer().is(AsmToken::Minus)) {
1362     getLexer().Lex();
1363     NewOpcode = Name;
1364     NewOpcode += '-';
1365     Name = NewOpcode;
1366   }
1367   // If the instruction ends in a '.', we need to create a separate
1368   // token for it, to match what TableGen is doing.
1369   size_t Dot = Name.find('.');
1370   StringRef Mnemonic = Name.slice(0, Dot);
1371   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1372     Operands.push_back(
1373         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1374   else
1375     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1376   if (Dot != StringRef::npos) {
1377     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1378     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1379     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1380       Operands.push_back(
1381           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1382     else
1383       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1384   }
1385 
1386   // If there are no more operands then finish
1387   if (getLexer().is(AsmToken::EndOfStatement))
1388     return false;
1389 
1390   // Parse the first operand
1391   if (ParseOperand(Operands))
1392     return true;
1393 
1394   while (getLexer().isNot(AsmToken::EndOfStatement) &&
1395          getLexer().is(AsmToken::Comma)) {
1396     // Consume the comma token
1397     getLexer().Lex();
1398 
1399     // Parse the next operand
1400     if (ParseOperand(Operands))
1401       return true;
1402   }
1403 
1404   return false;
1405 }
1406 
1407 /// ParseDirective parses the PPC specific directives
1408 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1409   StringRef IDVal = DirectiveID.getIdentifier();
1410   if (!isDarwin()) {
1411     if (IDVal == ".word")
1412       return ParseDirectiveWord(2, DirectiveID.getLoc());
1413     if (IDVal == ".llong")
1414       return ParseDirectiveWord(8, DirectiveID.getLoc());
1415     if (IDVal == ".tc")
1416       return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1417     if (IDVal == ".machine")
1418       return ParseDirectiveMachine(DirectiveID.getLoc());
1419     if (IDVal == ".abiversion")
1420       return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1421     if (IDVal == ".localentry")
1422       return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1423   } else {
1424     if (IDVal == ".machine")
1425       return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1426   }
1427   return true;
1428 }
1429 
1430 /// ParseDirectiveWord
1431 ///  ::= .word [ expression (, expression)* ]
1432 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1433   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1434     for (;;) {
1435       const MCExpr *Value;
1436       if (getParser().parseExpression(Value))
1437         return false;
1438 
1439       getParser().getStreamer().EmitValue(Value, Size);
1440 
1441       if (getLexer().is(AsmToken::EndOfStatement))
1442         break;
1443 
1444       if (getLexer().isNot(AsmToken::Comma))
1445         return Error(L, "unexpected token in directive");
1446       Parser.Lex();
1447     }
1448   }
1449 
1450   Parser.Lex();
1451   return false;
1452 }
1453 
1454 /// ParseDirectiveTC
1455 ///  ::= .tc [ symbol (, expression)* ]
1456 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1457   // Skip TC symbol, which is only used with XCOFF.
1458   while (getLexer().isNot(AsmToken::EndOfStatement)
1459          && getLexer().isNot(AsmToken::Comma))
1460     Parser.Lex();
1461   if (getLexer().isNot(AsmToken::Comma)) {
1462     Error(L, "unexpected token in directive");
1463     return false;
1464   }
1465   Parser.Lex();
1466 
1467   // Align to word size.
1468   getParser().getStreamer().EmitValueToAlignment(Size);
1469 
1470   // Emit expressions.
1471   return ParseDirectiveWord(Size, L);
1472 }
1473 
1474 /// ParseDirectiveMachine (ELF platforms)
1475 ///  ::= .machine [ cpu | "push" | "pop" ]
1476 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1477   if (getLexer().isNot(AsmToken::Identifier) &&
1478       getLexer().isNot(AsmToken::String)) {
1479     Error(L, "unexpected token in directive");
1480     return false;
1481   }
1482 
1483   StringRef CPU = Parser.getTok().getIdentifier();
1484   Parser.Lex();
1485 
1486   // FIXME: Right now, the parser always allows any available
1487   // instruction, so the .machine directive is not useful.
1488   // Implement ".machine any" (by doing nothing) for the benefit
1489   // of existing assembler code.  Likewise, we can then implement
1490   // ".machine push" and ".machine pop" as no-op.
1491   if (CPU != "any" && CPU != "push" && CPU != "pop") {
1492     Error(L, "unrecognized machine type");
1493     return false;
1494   }
1495 
1496   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1497     Error(L, "unexpected token in directive");
1498     return false;
1499   }
1500   PPCTargetStreamer &TStreamer =
1501       *static_cast<PPCTargetStreamer *>(
1502            getParser().getStreamer().getTargetStreamer());
1503   TStreamer.emitMachine(CPU);
1504 
1505   return false;
1506 }
1507 
1508 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1509 ///  ::= .machine cpu-identifier
1510 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1511   if (getLexer().isNot(AsmToken::Identifier) &&
1512       getLexer().isNot(AsmToken::String)) {
1513     Error(L, "unexpected token in directive");
1514     return false;
1515   }
1516 
1517   StringRef CPU = Parser.getTok().getIdentifier();
1518   Parser.Lex();
1519 
1520   // FIXME: this is only the 'default' set of cpu variants.
1521   // However we don't act on this information at present, this is simply
1522   // allowing parsing to proceed with minimal sanity checking.
1523   if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1524     Error(L, "unrecognized cpu type");
1525     return false;
1526   }
1527 
1528   if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1529     Error(L, "wrong cpu type specified for 64bit");
1530     return false;
1531   }
1532   if (!isPPC64() && CPU == "ppc64") {
1533     Error(L, "wrong cpu type specified for 32bit");
1534     return false;
1535   }
1536 
1537   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1538     Error(L, "unexpected token in directive");
1539     return false;
1540   }
1541 
1542   return false;
1543 }
1544 
1545 /// ParseDirectiveAbiVersion
1546 ///  ::= .abiversion constant-expression
1547 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1548   int64_t AbiVersion;
1549   if (getParser().parseAbsoluteExpression(AbiVersion)){
1550     Error(L, "expected constant expression");
1551     return false;
1552   }
1553   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1554     Error(L, "unexpected token in directive");
1555     return false;
1556   }
1557 
1558   PPCTargetStreamer &TStreamer =
1559       *static_cast<PPCTargetStreamer *>(
1560            getParser().getStreamer().getTargetStreamer());
1561   TStreamer.emitAbiVersion(AbiVersion);
1562 
1563   return false;
1564 }
1565 
1566 /// ParseDirectiveLocalEntry
1567 ///  ::= .localentry symbol, expression
1568 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1569   StringRef Name;
1570   if (getParser().parseIdentifier(Name)) {
1571     Error(L, "expected identifier in directive");
1572     return false;
1573   }
1574   MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
1575 
1576   if (getLexer().isNot(AsmToken::Comma)) {
1577     Error(L, "unexpected token in directive");
1578     return false;
1579   }
1580   Lex();
1581 
1582   const MCExpr *Expr;
1583   if (getParser().parseExpression(Expr)) {
1584     Error(L, "expected expression");
1585     return false;
1586   }
1587 
1588   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1589     Error(L, "unexpected token in directive");
1590     return false;
1591   }
1592 
1593   PPCTargetStreamer &TStreamer =
1594       *static_cast<PPCTargetStreamer *>(
1595            getParser().getStreamer().getTargetStreamer());
1596   TStreamer.emitLocalEntry(Sym, Expr);
1597 
1598   return false;
1599 }
1600 
1601 
1602 
1603 /// Force static initialization.
1604 extern "C" void LLVMInitializePowerPCAsmParser() {
1605   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1606   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1607   RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1608 }
1609 
1610 #define GET_REGISTER_MATCHER
1611 #define GET_MATCHER_IMPLEMENTATION
1612 #include "PPCGenAsmMatcher.inc"
1613 
1614 // Define this matcher function after the auto-generated include so we
1615 // have the match class enum definitions.
1616 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1617                                                   unsigned Kind) {
1618   // If the kind is a token for a literal immediate, check if our asm
1619   // operand matches. This is for InstAliases which have a fixed-value
1620   // immediate in the syntax.
1621   int64_t ImmVal;
1622   switch (Kind) {
1623     case MCK_0: ImmVal = 0; break;
1624     case MCK_1: ImmVal = 1; break;
1625     case MCK_2: ImmVal = 2; break;
1626     case MCK_3: ImmVal = 3; break;
1627     case MCK_4: ImmVal = 4; break;
1628     case MCK_5: ImmVal = 5; break;
1629     case MCK_6: ImmVal = 6; break;
1630     case MCK_7: ImmVal = 7; break;
1631     default: return Match_InvalidOperand;
1632   }
1633 
1634   PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1635   if (Op.isImm() && Op.getImm() == ImmVal)
1636     return Match_Success;
1637 
1638   return Match_InvalidOperand;
1639 }
1640 
1641 const MCExpr *
1642 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1643                                   MCSymbolRefExpr::VariantKind Variant,
1644                                   MCContext &Ctx) {
1645   switch (Variant) {
1646   case MCSymbolRefExpr::VK_PPC_LO:
1647     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1648   case MCSymbolRefExpr::VK_PPC_HI:
1649     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1650   case MCSymbolRefExpr::VK_PPC_HA:
1651     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1652   case MCSymbolRefExpr::VK_PPC_HIGHER:
1653     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1654   case MCSymbolRefExpr::VK_PPC_HIGHERA:
1655     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1656   case MCSymbolRefExpr::VK_PPC_HIGHEST:
1657     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1658   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1659     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1660   default:
1661     return nullptr;
1662   }
1663 }
1664