1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCExpr.h" 10 #include "MCTargetDesc/PPCMCTargetDesc.h" 11 #include "PPCTargetStreamer.h" 12 #include "TargetInfo/PowerPCTargetInfo.h" 13 #include "llvm/ADT/STLExtras.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Twine.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCParser/MCAsmLexer.h" 21 #include "llvm/MC/MCParser/MCAsmParser.h" 22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 23 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 24 #include "llvm/MC/MCStreamer.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/MC/MCSymbolELF.h" 27 #include "llvm/Support/SourceMgr.h" 28 #include "llvm/Support/TargetRegistry.h" 29 #include "llvm/Support/raw_ostream.h" 30 31 using namespace llvm; 32 33 DEFINE_PPC_REGCLASSES; 34 35 // Evaluate an expression containing condition register 36 // or condition register field symbols. Returns positive 37 // value on success, or -1 on error. 38 static int64_t 39 EvaluateCRExpr(const MCExpr *E) { 40 switch (E->getKind()) { 41 case MCExpr::Target: 42 return -1; 43 44 case MCExpr::Constant: { 45 int64_t Res = cast<MCConstantExpr>(E)->getValue(); 46 return Res < 0 ? -1 : Res; 47 } 48 49 case MCExpr::SymbolRef: { 50 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 51 StringRef Name = SRE->getSymbol().getName(); 52 53 if (Name == "lt") return 0; 54 if (Name == "gt") return 1; 55 if (Name == "eq") return 2; 56 if (Name == "so") return 3; 57 if (Name == "un") return 3; 58 59 if (Name == "cr0") return 0; 60 if (Name == "cr1") return 1; 61 if (Name == "cr2") return 2; 62 if (Name == "cr3") return 3; 63 if (Name == "cr4") return 4; 64 if (Name == "cr5") return 5; 65 if (Name == "cr6") return 6; 66 if (Name == "cr7") return 7; 67 68 return -1; 69 } 70 71 case MCExpr::Unary: 72 return -1; 73 74 case MCExpr::Binary: { 75 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 76 int64_t LHSVal = EvaluateCRExpr(BE->getLHS()); 77 int64_t RHSVal = EvaluateCRExpr(BE->getRHS()); 78 int64_t Res; 79 80 if (LHSVal < 0 || RHSVal < 0) 81 return -1; 82 83 switch (BE->getOpcode()) { 84 default: return -1; 85 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break; 86 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break; 87 } 88 89 return Res < 0 ? -1 : Res; 90 } 91 } 92 93 llvm_unreachable("Invalid expression kind!"); 94 } 95 96 namespace { 97 98 struct PPCOperand; 99 100 class PPCAsmParser : public MCTargetAsmParser { 101 bool IsPPC64; 102 bool IsDarwin; 103 104 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); } 105 106 bool isPPC64() const { return IsPPC64; } 107 bool isDarwin() const { return IsDarwin; } 108 109 bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal); 110 111 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 112 OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, 113 SMLoc &EndLoc) override; 114 115 const MCExpr *ExtractModifierFromExpr(const MCExpr *E, 116 PPCMCExpr::VariantKind &Variant); 117 const MCExpr *FixupVariantKind(const MCExpr *E); 118 bool ParseExpression(const MCExpr *&EVal); 119 bool ParseDarwinExpression(const MCExpr *&EVal); 120 121 bool ParseOperand(OperandVector &Operands); 122 123 bool ParseDirectiveWord(unsigned Size, AsmToken ID); 124 bool ParseDirectiveTC(unsigned Size, AsmToken ID); 125 bool ParseDirectiveMachine(SMLoc L); 126 bool ParseDarwinDirectiveMachine(SMLoc L); 127 bool ParseDirectiveAbiVersion(SMLoc L); 128 bool ParseDirectiveLocalEntry(SMLoc L); 129 130 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 131 OperandVector &Operands, MCStreamer &Out, 132 uint64_t &ErrorInfo, 133 bool MatchingInlineAsm) override; 134 135 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops); 136 137 /// @name Auto-generated Match Functions 138 /// { 139 140 #define GET_ASSEMBLER_HEADER 141 #include "PPCGenAsmMatcher.inc" 142 143 /// } 144 145 146 public: 147 PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &, 148 const MCInstrInfo &MII, const MCTargetOptions &Options) 149 : MCTargetAsmParser(Options, STI, MII) { 150 // Check for 64-bit vs. 32-bit pointer mode. 151 const Triple &TheTriple = STI.getTargetTriple(); 152 IsPPC64 = TheTriple.isPPC64(); 153 IsDarwin = TheTriple.isMacOSX(); 154 // Initialize the set of available features. 155 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 156 } 157 158 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 159 SMLoc NameLoc, OperandVector &Operands) override; 160 161 bool ParseDirective(AsmToken DirectiveID) override; 162 163 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 164 unsigned Kind) override; 165 166 const MCExpr *applyModifierToExpr(const MCExpr *E, 167 MCSymbolRefExpr::VariantKind, 168 MCContext &Ctx) override; 169 }; 170 171 /// PPCOperand - Instances of this class represent a parsed PowerPC machine 172 /// instruction. 173 struct PPCOperand : public MCParsedAsmOperand { 174 enum KindTy { 175 Token, 176 Immediate, 177 ContextImmediate, 178 Expression, 179 TLSRegister 180 } Kind; 181 182 SMLoc StartLoc, EndLoc; 183 bool IsPPC64; 184 185 struct TokOp { 186 const char *Data; 187 unsigned Length; 188 }; 189 190 struct ImmOp { 191 int64_t Val; 192 }; 193 194 struct ExprOp { 195 const MCExpr *Val; 196 int64_t CRVal; // Cached result of EvaluateCRExpr(Val) 197 }; 198 199 struct TLSRegOp { 200 const MCSymbolRefExpr *Sym; 201 }; 202 203 union { 204 struct TokOp Tok; 205 struct ImmOp Imm; 206 struct ExprOp Expr; 207 struct TLSRegOp TLSReg; 208 }; 209 210 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 211 public: 212 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() { 213 Kind = o.Kind; 214 StartLoc = o.StartLoc; 215 EndLoc = o.EndLoc; 216 IsPPC64 = o.IsPPC64; 217 switch (Kind) { 218 case Token: 219 Tok = o.Tok; 220 break; 221 case Immediate: 222 case ContextImmediate: 223 Imm = o.Imm; 224 break; 225 case Expression: 226 Expr = o.Expr; 227 break; 228 case TLSRegister: 229 TLSReg = o.TLSReg; 230 break; 231 } 232 } 233 234 // Disable use of sized deallocation due to overallocation of PPCOperand 235 // objects in CreateTokenWithStringCopy. 236 void operator delete(void *p) { ::operator delete(p); } 237 238 /// getStartLoc - Get the location of the first token of this operand. 239 SMLoc getStartLoc() const override { return StartLoc; } 240 241 /// getEndLoc - Get the location of the last token of this operand. 242 SMLoc getEndLoc() const override { return EndLoc; } 243 244 /// getLocRange - Get the range between the first and last token of this 245 /// operand. 246 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 247 248 /// isPPC64 - True if this operand is for an instruction in 64-bit mode. 249 bool isPPC64() const { return IsPPC64; } 250 251 int64_t getImm() const { 252 assert(Kind == Immediate && "Invalid access!"); 253 return Imm.Val; 254 } 255 int64_t getImmS16Context() const { 256 assert((Kind == Immediate || Kind == ContextImmediate) && 257 "Invalid access!"); 258 if (Kind == Immediate) 259 return Imm.Val; 260 return static_cast<int16_t>(Imm.Val); 261 } 262 int64_t getImmU16Context() const { 263 assert((Kind == Immediate || Kind == ContextImmediate) && 264 "Invalid access!"); 265 return Imm.Val; 266 } 267 268 const MCExpr *getExpr() const { 269 assert(Kind == Expression && "Invalid access!"); 270 return Expr.Val; 271 } 272 273 int64_t getExprCRVal() const { 274 assert(Kind == Expression && "Invalid access!"); 275 return Expr.CRVal; 276 } 277 278 const MCExpr *getTLSReg() const { 279 assert(Kind == TLSRegister && "Invalid access!"); 280 return TLSReg.Sym; 281 } 282 283 unsigned getReg() const override { 284 assert(isRegNumber() && "Invalid access!"); 285 return (unsigned) Imm.Val; 286 } 287 288 unsigned getVSReg() const { 289 assert(isVSRegNumber() && "Invalid access!"); 290 return (unsigned) Imm.Val; 291 } 292 293 unsigned getCCReg() const { 294 assert(isCCRegNumber() && "Invalid access!"); 295 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 296 } 297 298 unsigned getCRBit() const { 299 assert(isCRBitNumber() && "Invalid access!"); 300 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 301 } 302 303 unsigned getCRBitMask() const { 304 assert(isCRBitMask() && "Invalid access!"); 305 return 7 - countTrailingZeros<uint64_t>(Imm.Val); 306 } 307 308 bool isToken() const override { return Kind == Token; } 309 bool isImm() const override { 310 return Kind == Immediate || Kind == Expression; 311 } 312 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } 313 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } 314 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } 315 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } 316 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } 317 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } 318 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } 319 bool isU6ImmX2() const { return Kind == Immediate && 320 isUInt<6>(getImm()) && 321 (getImm() & 1) == 0; } 322 bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); } 323 bool isU7ImmX4() const { return Kind == Immediate && 324 isUInt<7>(getImm()) && 325 (getImm() & 3) == 0; } 326 bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); } 327 bool isU8ImmX8() const { return Kind == Immediate && 328 isUInt<8>(getImm()) && 329 (getImm() & 7) == 0; } 330 331 bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); } 332 bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); } 333 bool isU16Imm() const { 334 switch (Kind) { 335 case Expression: 336 return true; 337 case Immediate: 338 case ContextImmediate: 339 return isUInt<16>(getImmU16Context()); 340 default: 341 return false; 342 } 343 } 344 bool isS16Imm() const { 345 switch (Kind) { 346 case Expression: 347 return true; 348 case Immediate: 349 case ContextImmediate: 350 return isInt<16>(getImmS16Context()); 351 default: 352 return false; 353 } 354 } 355 bool isS16ImmX4() const { return Kind == Expression || 356 (Kind == Immediate && isInt<16>(getImm()) && 357 (getImm() & 3) == 0); } 358 bool isS16ImmX16() const { return Kind == Expression || 359 (Kind == Immediate && isInt<16>(getImm()) && 360 (getImm() & 15) == 0); } 361 bool isS34ImmX16() const { 362 return Kind == Expression || 363 (Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0); 364 } 365 bool isS34Imm() const { 366 // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit 367 // ContextImmediate is needed. 368 return Kind == Expression || (Kind == Immediate && isInt<34>(getImm())); 369 } 370 371 bool isS17Imm() const { 372 switch (Kind) { 373 case Expression: 374 return true; 375 case Immediate: 376 case ContextImmediate: 377 return isInt<17>(getImmS16Context()); 378 default: 379 return false; 380 } 381 } 382 bool isTLSReg() const { return Kind == TLSRegister; } 383 bool isDirectBr() const { 384 if (Kind == Expression) 385 return true; 386 if (Kind != Immediate) 387 return false; 388 // Operand must be 64-bit aligned, signed 27-bit immediate. 389 if ((getImm() & 3) != 0) 390 return false; 391 if (isInt<26>(getImm())) 392 return true; 393 if (!IsPPC64) { 394 // In 32-bit mode, large 32-bit quantities wrap around. 395 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm()))) 396 return true; 397 } 398 return false; 399 } 400 bool isCondBr() const { return Kind == Expression || 401 (Kind == Immediate && isInt<16>(getImm()) && 402 (getImm() & 3) == 0); } 403 bool isImmZero() const { return Kind == Immediate && getImm() == 0; } 404 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } 405 bool isVSRegNumber() const { 406 return Kind == Immediate && isUInt<6>(getImm()); 407 } 408 bool isCCRegNumber() const { return (Kind == Expression 409 && isUInt<3>(getExprCRVal())) || 410 (Kind == Immediate 411 && isUInt<3>(getImm())); } 412 bool isCRBitNumber() const { return (Kind == Expression 413 && isUInt<5>(getExprCRVal())) || 414 (Kind == Immediate 415 && isUInt<5>(getImm())); } 416 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) && 417 isPowerOf2_32(getImm()); } 418 bool isATBitsAsHint() const { return false; } 419 bool isMem() const override { return false; } 420 bool isReg() const override { return false; } 421 422 void addRegOperands(MCInst &Inst, unsigned N) const { 423 llvm_unreachable("addRegOperands"); 424 } 425 426 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { 427 assert(N == 1 && "Invalid number of operands!"); 428 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 429 } 430 431 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { 432 assert(N == 1 && "Invalid number of operands!"); 433 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); 434 } 435 436 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { 437 assert(N == 1 && "Invalid number of operands!"); 438 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); 439 } 440 441 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { 442 assert(N == 1 && "Invalid number of operands!"); 443 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); 444 } 445 446 void addRegGxRCOperands(MCInst &Inst, unsigned N) const { 447 if (isPPC64()) 448 addRegG8RCOperands(Inst, N); 449 else 450 addRegGPRCOperands(Inst, N); 451 } 452 453 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const { 454 if (isPPC64()) 455 addRegG8RCNoX0Operands(Inst, N); 456 else 457 addRegGPRCNoR0Operands(Inst, N); 458 } 459 460 void addRegF4RCOperands(MCInst &Inst, unsigned N) const { 461 assert(N == 1 && "Invalid number of operands!"); 462 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 463 } 464 465 void addRegF8RCOperands(MCInst &Inst, unsigned N) const { 466 assert(N == 1 && "Invalid number of operands!"); 467 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 468 } 469 470 void addRegVFRCOperands(MCInst &Inst, unsigned N) const { 471 assert(N == 1 && "Invalid number of operands!"); 472 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); 473 } 474 475 void addRegVRRCOperands(MCInst &Inst, unsigned N) const { 476 assert(N == 1 && "Invalid number of operands!"); 477 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); 478 } 479 480 void addRegVSRCOperands(MCInst &Inst, unsigned N) const { 481 assert(N == 1 && "Invalid number of operands!"); 482 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); 483 } 484 485 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const { 486 assert(N == 1 && "Invalid number of operands!"); 487 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); 488 } 489 490 void addRegVSSRCOperands(MCInst &Inst, unsigned N) const { 491 assert(N == 1 && "Invalid number of operands!"); 492 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); 493 } 494 495 void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const { 496 assert(N == 1 && "Invalid number of operands!"); 497 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 498 } 499 500 void addRegSPERCOperands(MCInst &Inst, unsigned N) const { 501 assert(N == 1 && "Invalid number of operands!"); 502 Inst.addOperand(MCOperand::createReg(SPERegs[getReg()])); 503 } 504 505 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const { 506 assert(N == 1 && "Invalid number of operands!"); 507 Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()])); 508 } 509 510 void addRegCRRCOperands(MCInst &Inst, unsigned N) const { 511 assert(N == 1 && "Invalid number of operands!"); 512 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()])); 513 } 514 515 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const { 516 assert(N == 1 && "Invalid number of operands!"); 517 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()])); 518 } 519 520 void addImmOperands(MCInst &Inst, unsigned N) const { 521 assert(N == 1 && "Invalid number of operands!"); 522 if (Kind == Immediate) 523 Inst.addOperand(MCOperand::createImm(getImm())); 524 else 525 Inst.addOperand(MCOperand::createExpr(getExpr())); 526 } 527 528 void addS16ImmOperands(MCInst &Inst, unsigned N) const { 529 assert(N == 1 && "Invalid number of operands!"); 530 switch (Kind) { 531 case Immediate: 532 Inst.addOperand(MCOperand::createImm(getImm())); 533 break; 534 case ContextImmediate: 535 Inst.addOperand(MCOperand::createImm(getImmS16Context())); 536 break; 537 default: 538 Inst.addOperand(MCOperand::createExpr(getExpr())); 539 break; 540 } 541 } 542 543 void addU16ImmOperands(MCInst &Inst, unsigned N) const { 544 assert(N == 1 && "Invalid number of operands!"); 545 switch (Kind) { 546 case Immediate: 547 Inst.addOperand(MCOperand::createImm(getImm())); 548 break; 549 case ContextImmediate: 550 Inst.addOperand(MCOperand::createImm(getImmU16Context())); 551 break; 552 default: 553 Inst.addOperand(MCOperand::createExpr(getExpr())); 554 break; 555 } 556 } 557 558 void addBranchTargetOperands(MCInst &Inst, unsigned N) const { 559 assert(N == 1 && "Invalid number of operands!"); 560 if (Kind == Immediate) 561 Inst.addOperand(MCOperand::createImm(getImm() / 4)); 562 else 563 Inst.addOperand(MCOperand::createExpr(getExpr())); 564 } 565 566 void addTLSRegOperands(MCInst &Inst, unsigned N) const { 567 assert(N == 1 && "Invalid number of operands!"); 568 Inst.addOperand(MCOperand::createExpr(getTLSReg())); 569 } 570 571 StringRef getToken() const { 572 assert(Kind == Token && "Invalid access!"); 573 return StringRef(Tok.Data, Tok.Length); 574 } 575 576 void print(raw_ostream &OS) const override; 577 578 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S, 579 bool IsPPC64) { 580 auto Op = std::make_unique<PPCOperand>(Token); 581 Op->Tok.Data = Str.data(); 582 Op->Tok.Length = Str.size(); 583 Op->StartLoc = S; 584 Op->EndLoc = S; 585 Op->IsPPC64 = IsPPC64; 586 return Op; 587 } 588 589 static std::unique_ptr<PPCOperand> 590 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) { 591 // Allocate extra memory for the string and copy it. 592 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default 593 // deleter which will destroy them by simply using "delete", not correctly 594 // calling operator delete on this extra memory after calling the dtor 595 // explicitly. 596 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size()); 597 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token)); 598 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1); 599 Op->Tok.Length = Str.size(); 600 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size()); 601 Op->StartLoc = S; 602 Op->EndLoc = S; 603 Op->IsPPC64 = IsPPC64; 604 return Op; 605 } 606 607 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E, 608 bool IsPPC64) { 609 auto Op = std::make_unique<PPCOperand>(Immediate); 610 Op->Imm.Val = Val; 611 Op->StartLoc = S; 612 Op->EndLoc = E; 613 Op->IsPPC64 = IsPPC64; 614 return Op; 615 } 616 617 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S, 618 SMLoc E, bool IsPPC64) { 619 auto Op = std::make_unique<PPCOperand>(Expression); 620 Op->Expr.Val = Val; 621 Op->Expr.CRVal = EvaluateCRExpr(Val); 622 Op->StartLoc = S; 623 Op->EndLoc = E; 624 Op->IsPPC64 = IsPPC64; 625 return Op; 626 } 627 628 static std::unique_ptr<PPCOperand> 629 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) { 630 auto Op = std::make_unique<PPCOperand>(TLSRegister); 631 Op->TLSReg.Sym = Sym; 632 Op->StartLoc = S; 633 Op->EndLoc = E; 634 Op->IsPPC64 = IsPPC64; 635 return Op; 636 } 637 638 static std::unique_ptr<PPCOperand> 639 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) { 640 auto Op = std::make_unique<PPCOperand>(ContextImmediate); 641 Op->Imm.Val = Val; 642 Op->StartLoc = S; 643 Op->EndLoc = E; 644 Op->IsPPC64 = IsPPC64; 645 return Op; 646 } 647 648 static std::unique_ptr<PPCOperand> 649 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) { 650 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val)) 651 return CreateImm(CE->getValue(), S, E, IsPPC64); 652 653 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val)) 654 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS) 655 return CreateTLSReg(SRE, S, E, IsPPC64); 656 657 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) { 658 int64_t Res; 659 if (TE->evaluateAsConstant(Res)) 660 return CreateContextImm(Res, S, E, IsPPC64); 661 } 662 663 return CreateExpr(Val, S, E, IsPPC64); 664 } 665 }; 666 667 } // end anonymous namespace. 668 669 void PPCOperand::print(raw_ostream &OS) const { 670 switch (Kind) { 671 case Token: 672 OS << "'" << getToken() << "'"; 673 break; 674 case Immediate: 675 case ContextImmediate: 676 OS << getImm(); 677 break; 678 case Expression: 679 OS << *getExpr(); 680 break; 681 case TLSRegister: 682 OS << *getTLSReg(); 683 break; 684 } 685 } 686 687 static void 688 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) { 689 if (Op.isImm()) { 690 Inst.addOperand(MCOperand::createImm(-Op.getImm())); 691 return; 692 } 693 const MCExpr *Expr = Op.getExpr(); 694 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) { 695 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) { 696 Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr())); 697 return; 698 } 699 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) { 700 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) { 701 const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(), 702 BinExpr->getLHS(), Ctx); 703 Inst.addOperand(MCOperand::createExpr(NE)); 704 return; 705 } 706 } 707 Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx))); 708 } 709 710 void PPCAsmParser::ProcessInstruction(MCInst &Inst, 711 const OperandVector &Operands) { 712 int Opcode = Inst.getOpcode(); 713 switch (Opcode) { 714 case PPC::DCBTx: 715 case PPC::DCBTT: 716 case PPC::DCBTSTx: 717 case PPC::DCBTSTT: { 718 MCInst TmpInst; 719 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? 720 PPC::DCBT : PPC::DCBTST); 721 TmpInst.addOperand(MCOperand::createImm( 722 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16)); 723 TmpInst.addOperand(Inst.getOperand(0)); 724 TmpInst.addOperand(Inst.getOperand(1)); 725 Inst = TmpInst; 726 break; 727 } 728 case PPC::DCBTCT: 729 case PPC::DCBTDS: { 730 MCInst TmpInst; 731 TmpInst.setOpcode(PPC::DCBT); 732 TmpInst.addOperand(Inst.getOperand(2)); 733 TmpInst.addOperand(Inst.getOperand(0)); 734 TmpInst.addOperand(Inst.getOperand(1)); 735 Inst = TmpInst; 736 break; 737 } 738 case PPC::DCBTSTCT: 739 case PPC::DCBTSTDS: { 740 MCInst TmpInst; 741 TmpInst.setOpcode(PPC::DCBTST); 742 TmpInst.addOperand(Inst.getOperand(2)); 743 TmpInst.addOperand(Inst.getOperand(0)); 744 TmpInst.addOperand(Inst.getOperand(1)); 745 Inst = TmpInst; 746 break; 747 } 748 case PPC::DCBFx: 749 case PPC::DCBFL: 750 case PPC::DCBFLP: { 751 int L = 0; 752 if (Opcode == PPC::DCBFL) 753 L = 1; 754 else if (Opcode == PPC::DCBFLP) 755 L = 3; 756 757 MCInst TmpInst; 758 TmpInst.setOpcode(PPC::DCBF); 759 TmpInst.addOperand(MCOperand::createImm(L)); 760 TmpInst.addOperand(Inst.getOperand(0)); 761 TmpInst.addOperand(Inst.getOperand(1)); 762 Inst = TmpInst; 763 break; 764 } 765 case PPC::LAx: { 766 MCInst TmpInst; 767 TmpInst.setOpcode(PPC::LA); 768 TmpInst.addOperand(Inst.getOperand(0)); 769 TmpInst.addOperand(Inst.getOperand(2)); 770 TmpInst.addOperand(Inst.getOperand(1)); 771 Inst = TmpInst; 772 break; 773 } 774 case PPC::SUBI: { 775 MCInst TmpInst; 776 TmpInst.setOpcode(PPC::ADDI); 777 TmpInst.addOperand(Inst.getOperand(0)); 778 TmpInst.addOperand(Inst.getOperand(1)); 779 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 780 Inst = TmpInst; 781 break; 782 } 783 case PPC::SUBIS: { 784 MCInst TmpInst; 785 TmpInst.setOpcode(PPC::ADDIS); 786 TmpInst.addOperand(Inst.getOperand(0)); 787 TmpInst.addOperand(Inst.getOperand(1)); 788 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 789 Inst = TmpInst; 790 break; 791 } 792 case PPC::SUBIC: { 793 MCInst TmpInst; 794 TmpInst.setOpcode(PPC::ADDIC); 795 TmpInst.addOperand(Inst.getOperand(0)); 796 TmpInst.addOperand(Inst.getOperand(1)); 797 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 798 Inst = TmpInst; 799 break; 800 } 801 case PPC::SUBIC_rec: { 802 MCInst TmpInst; 803 TmpInst.setOpcode(PPC::ADDIC_rec); 804 TmpInst.addOperand(Inst.getOperand(0)); 805 TmpInst.addOperand(Inst.getOperand(1)); 806 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 807 Inst = TmpInst; 808 break; 809 } 810 case PPC::EXTLWI: 811 case PPC::EXTLWI_rec: { 812 MCInst TmpInst; 813 int64_t N = Inst.getOperand(2).getImm(); 814 int64_t B = Inst.getOperand(3).getImm(); 815 TmpInst.setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec); 816 TmpInst.addOperand(Inst.getOperand(0)); 817 TmpInst.addOperand(Inst.getOperand(1)); 818 TmpInst.addOperand(MCOperand::createImm(B)); 819 TmpInst.addOperand(MCOperand::createImm(0)); 820 TmpInst.addOperand(MCOperand::createImm(N - 1)); 821 Inst = TmpInst; 822 break; 823 } 824 case PPC::EXTRWI: 825 case PPC::EXTRWI_rec: { 826 MCInst TmpInst; 827 int64_t N = Inst.getOperand(2).getImm(); 828 int64_t B = Inst.getOperand(3).getImm(); 829 TmpInst.setOpcode(Opcode == PPC::EXTRWI ? PPC::RLWINM : PPC::RLWINM_rec); 830 TmpInst.addOperand(Inst.getOperand(0)); 831 TmpInst.addOperand(Inst.getOperand(1)); 832 TmpInst.addOperand(MCOperand::createImm(B + N)); 833 TmpInst.addOperand(MCOperand::createImm(32 - N)); 834 TmpInst.addOperand(MCOperand::createImm(31)); 835 Inst = TmpInst; 836 break; 837 } 838 case PPC::INSLWI: 839 case PPC::INSLWI_rec: { 840 MCInst TmpInst; 841 int64_t N = Inst.getOperand(2).getImm(); 842 int64_t B = Inst.getOperand(3).getImm(); 843 TmpInst.setOpcode(Opcode == PPC::INSLWI ? PPC::RLWIMI : PPC::RLWIMI_rec); 844 TmpInst.addOperand(Inst.getOperand(0)); 845 TmpInst.addOperand(Inst.getOperand(0)); 846 TmpInst.addOperand(Inst.getOperand(1)); 847 TmpInst.addOperand(MCOperand::createImm(32 - B)); 848 TmpInst.addOperand(MCOperand::createImm(B)); 849 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 850 Inst = TmpInst; 851 break; 852 } 853 case PPC::INSRWI: 854 case PPC::INSRWI_rec: { 855 MCInst TmpInst; 856 int64_t N = Inst.getOperand(2).getImm(); 857 int64_t B = Inst.getOperand(3).getImm(); 858 TmpInst.setOpcode(Opcode == PPC::INSRWI ? PPC::RLWIMI : PPC::RLWIMI_rec); 859 TmpInst.addOperand(Inst.getOperand(0)); 860 TmpInst.addOperand(Inst.getOperand(0)); 861 TmpInst.addOperand(Inst.getOperand(1)); 862 TmpInst.addOperand(MCOperand::createImm(32 - (B + N))); 863 TmpInst.addOperand(MCOperand::createImm(B)); 864 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 865 Inst = TmpInst; 866 break; 867 } 868 case PPC::ROTRWI: 869 case PPC::ROTRWI_rec: { 870 MCInst TmpInst; 871 int64_t N = Inst.getOperand(2).getImm(); 872 TmpInst.setOpcode(Opcode == PPC::ROTRWI ? PPC::RLWINM : PPC::RLWINM_rec); 873 TmpInst.addOperand(Inst.getOperand(0)); 874 TmpInst.addOperand(Inst.getOperand(1)); 875 TmpInst.addOperand(MCOperand::createImm(32 - N)); 876 TmpInst.addOperand(MCOperand::createImm(0)); 877 TmpInst.addOperand(MCOperand::createImm(31)); 878 Inst = TmpInst; 879 break; 880 } 881 case PPC::SLWI: 882 case PPC::SLWI_rec: { 883 MCInst TmpInst; 884 int64_t N = Inst.getOperand(2).getImm(); 885 TmpInst.setOpcode(Opcode == PPC::SLWI ? PPC::RLWINM : PPC::RLWINM_rec); 886 TmpInst.addOperand(Inst.getOperand(0)); 887 TmpInst.addOperand(Inst.getOperand(1)); 888 TmpInst.addOperand(MCOperand::createImm(N)); 889 TmpInst.addOperand(MCOperand::createImm(0)); 890 TmpInst.addOperand(MCOperand::createImm(31 - N)); 891 Inst = TmpInst; 892 break; 893 } 894 case PPC::SRWI: 895 case PPC::SRWI_rec: { 896 MCInst TmpInst; 897 int64_t N = Inst.getOperand(2).getImm(); 898 TmpInst.setOpcode(Opcode == PPC::SRWI ? PPC::RLWINM : PPC::RLWINM_rec); 899 TmpInst.addOperand(Inst.getOperand(0)); 900 TmpInst.addOperand(Inst.getOperand(1)); 901 TmpInst.addOperand(MCOperand::createImm(32 - N)); 902 TmpInst.addOperand(MCOperand::createImm(N)); 903 TmpInst.addOperand(MCOperand::createImm(31)); 904 Inst = TmpInst; 905 break; 906 } 907 case PPC::CLRRWI: 908 case PPC::CLRRWI_rec: { 909 MCInst TmpInst; 910 int64_t N = Inst.getOperand(2).getImm(); 911 TmpInst.setOpcode(Opcode == PPC::CLRRWI ? PPC::RLWINM : PPC::RLWINM_rec); 912 TmpInst.addOperand(Inst.getOperand(0)); 913 TmpInst.addOperand(Inst.getOperand(1)); 914 TmpInst.addOperand(MCOperand::createImm(0)); 915 TmpInst.addOperand(MCOperand::createImm(0)); 916 TmpInst.addOperand(MCOperand::createImm(31 - N)); 917 Inst = TmpInst; 918 break; 919 } 920 case PPC::CLRLSLWI: 921 case PPC::CLRLSLWI_rec: { 922 MCInst TmpInst; 923 int64_t B = Inst.getOperand(2).getImm(); 924 int64_t N = Inst.getOperand(3).getImm(); 925 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI ? PPC::RLWINM : PPC::RLWINM_rec); 926 TmpInst.addOperand(Inst.getOperand(0)); 927 TmpInst.addOperand(Inst.getOperand(1)); 928 TmpInst.addOperand(MCOperand::createImm(N)); 929 TmpInst.addOperand(MCOperand::createImm(B - N)); 930 TmpInst.addOperand(MCOperand::createImm(31 - N)); 931 Inst = TmpInst; 932 break; 933 } 934 case PPC::EXTLDI: 935 case PPC::EXTLDI_rec: { 936 MCInst TmpInst; 937 int64_t N = Inst.getOperand(2).getImm(); 938 int64_t B = Inst.getOperand(3).getImm(); 939 TmpInst.setOpcode(Opcode == PPC::EXTLDI ? PPC::RLDICR : PPC::RLDICR_rec); 940 TmpInst.addOperand(Inst.getOperand(0)); 941 TmpInst.addOperand(Inst.getOperand(1)); 942 TmpInst.addOperand(MCOperand::createImm(B)); 943 TmpInst.addOperand(MCOperand::createImm(N - 1)); 944 Inst = TmpInst; 945 break; 946 } 947 case PPC::EXTRDI: 948 case PPC::EXTRDI_rec: { 949 MCInst TmpInst; 950 int64_t N = Inst.getOperand(2).getImm(); 951 int64_t B = Inst.getOperand(3).getImm(); 952 TmpInst.setOpcode(Opcode == PPC::EXTRDI ? PPC::RLDICL : PPC::RLDICL_rec); 953 TmpInst.addOperand(Inst.getOperand(0)); 954 TmpInst.addOperand(Inst.getOperand(1)); 955 TmpInst.addOperand(MCOperand::createImm(B + N)); 956 TmpInst.addOperand(MCOperand::createImm(64 - N)); 957 Inst = TmpInst; 958 break; 959 } 960 case PPC::INSRDI: 961 case PPC::INSRDI_rec: { 962 MCInst TmpInst; 963 int64_t N = Inst.getOperand(2).getImm(); 964 int64_t B = Inst.getOperand(3).getImm(); 965 TmpInst.setOpcode(Opcode == PPC::INSRDI ? PPC::RLDIMI : PPC::RLDIMI_rec); 966 TmpInst.addOperand(Inst.getOperand(0)); 967 TmpInst.addOperand(Inst.getOperand(0)); 968 TmpInst.addOperand(Inst.getOperand(1)); 969 TmpInst.addOperand(MCOperand::createImm(64 - (B + N))); 970 TmpInst.addOperand(MCOperand::createImm(B)); 971 Inst = TmpInst; 972 break; 973 } 974 case PPC::ROTRDI: 975 case PPC::ROTRDI_rec: { 976 MCInst TmpInst; 977 int64_t N = Inst.getOperand(2).getImm(); 978 TmpInst.setOpcode(Opcode == PPC::ROTRDI ? PPC::RLDICL : PPC::RLDICL_rec); 979 TmpInst.addOperand(Inst.getOperand(0)); 980 TmpInst.addOperand(Inst.getOperand(1)); 981 TmpInst.addOperand(MCOperand::createImm(64 - N)); 982 TmpInst.addOperand(MCOperand::createImm(0)); 983 Inst = TmpInst; 984 break; 985 } 986 case PPC::SLDI: 987 case PPC::SLDI_rec: { 988 MCInst TmpInst; 989 int64_t N = Inst.getOperand(2).getImm(); 990 TmpInst.setOpcode(Opcode == PPC::SLDI ? PPC::RLDICR : PPC::RLDICR_rec); 991 TmpInst.addOperand(Inst.getOperand(0)); 992 TmpInst.addOperand(Inst.getOperand(1)); 993 TmpInst.addOperand(MCOperand::createImm(N)); 994 TmpInst.addOperand(MCOperand::createImm(63 - N)); 995 Inst = TmpInst; 996 break; 997 } 998 case PPC::SUBPCIS: { 999 MCInst TmpInst; 1000 int64_t N = Inst.getOperand(1).getImm(); 1001 TmpInst.setOpcode(PPC::ADDPCIS); 1002 TmpInst.addOperand(Inst.getOperand(0)); 1003 TmpInst.addOperand(MCOperand::createImm(-N)); 1004 Inst = TmpInst; 1005 break; 1006 } 1007 case PPC::SRDI: 1008 case PPC::SRDI_rec: { 1009 MCInst TmpInst; 1010 int64_t N = Inst.getOperand(2).getImm(); 1011 TmpInst.setOpcode(Opcode == PPC::SRDI ? PPC::RLDICL : PPC::RLDICL_rec); 1012 TmpInst.addOperand(Inst.getOperand(0)); 1013 TmpInst.addOperand(Inst.getOperand(1)); 1014 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1015 TmpInst.addOperand(MCOperand::createImm(N)); 1016 Inst = TmpInst; 1017 break; 1018 } 1019 case PPC::CLRRDI: 1020 case PPC::CLRRDI_rec: { 1021 MCInst TmpInst; 1022 int64_t N = Inst.getOperand(2).getImm(); 1023 TmpInst.setOpcode(Opcode == PPC::CLRRDI ? PPC::RLDICR : PPC::RLDICR_rec); 1024 TmpInst.addOperand(Inst.getOperand(0)); 1025 TmpInst.addOperand(Inst.getOperand(1)); 1026 TmpInst.addOperand(MCOperand::createImm(0)); 1027 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1028 Inst = TmpInst; 1029 break; 1030 } 1031 case PPC::CLRLSLDI: 1032 case PPC::CLRLSLDI_rec: { 1033 MCInst TmpInst; 1034 int64_t B = Inst.getOperand(2).getImm(); 1035 int64_t N = Inst.getOperand(3).getImm(); 1036 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI ? PPC::RLDIC : PPC::RLDIC_rec); 1037 TmpInst.addOperand(Inst.getOperand(0)); 1038 TmpInst.addOperand(Inst.getOperand(1)); 1039 TmpInst.addOperand(MCOperand::createImm(N)); 1040 TmpInst.addOperand(MCOperand::createImm(B - N)); 1041 Inst = TmpInst; 1042 break; 1043 } 1044 case PPC::RLWINMbm: 1045 case PPC::RLWINMbm_rec: { 1046 unsigned MB, ME; 1047 int64_t BM = Inst.getOperand(3).getImm(); 1048 if (!isRunOfOnes(BM, MB, ME)) 1049 break; 1050 1051 MCInst TmpInst; 1052 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINM_rec); 1053 TmpInst.addOperand(Inst.getOperand(0)); 1054 TmpInst.addOperand(Inst.getOperand(1)); 1055 TmpInst.addOperand(Inst.getOperand(2)); 1056 TmpInst.addOperand(MCOperand::createImm(MB)); 1057 TmpInst.addOperand(MCOperand::createImm(ME)); 1058 Inst = TmpInst; 1059 break; 1060 } 1061 case PPC::RLWIMIbm: 1062 case PPC::RLWIMIbm_rec: { 1063 unsigned MB, ME; 1064 int64_t BM = Inst.getOperand(3).getImm(); 1065 if (!isRunOfOnes(BM, MB, ME)) 1066 break; 1067 1068 MCInst TmpInst; 1069 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMI_rec); 1070 TmpInst.addOperand(Inst.getOperand(0)); 1071 TmpInst.addOperand(Inst.getOperand(0)); // The tied operand. 1072 TmpInst.addOperand(Inst.getOperand(1)); 1073 TmpInst.addOperand(Inst.getOperand(2)); 1074 TmpInst.addOperand(MCOperand::createImm(MB)); 1075 TmpInst.addOperand(MCOperand::createImm(ME)); 1076 Inst = TmpInst; 1077 break; 1078 } 1079 case PPC::RLWNMbm: 1080 case PPC::RLWNMbm_rec: { 1081 unsigned MB, ME; 1082 int64_t BM = Inst.getOperand(3).getImm(); 1083 if (!isRunOfOnes(BM, MB, ME)) 1084 break; 1085 1086 MCInst TmpInst; 1087 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNM_rec); 1088 TmpInst.addOperand(Inst.getOperand(0)); 1089 TmpInst.addOperand(Inst.getOperand(1)); 1090 TmpInst.addOperand(Inst.getOperand(2)); 1091 TmpInst.addOperand(MCOperand::createImm(MB)); 1092 TmpInst.addOperand(MCOperand::createImm(ME)); 1093 Inst = TmpInst; 1094 break; 1095 } 1096 case PPC::MFTB: { 1097 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) { 1098 assert(Inst.getNumOperands() == 2 && "Expecting two operands"); 1099 Inst.setOpcode(PPC::MFSPR); 1100 } 1101 break; 1102 } 1103 case PPC::CP_COPYx: 1104 case PPC::CP_COPY_FIRST: { 1105 MCInst TmpInst; 1106 TmpInst.setOpcode(PPC::CP_COPY); 1107 TmpInst.addOperand(Inst.getOperand(0)); 1108 TmpInst.addOperand(Inst.getOperand(1)); 1109 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1)); 1110 1111 Inst = TmpInst; 1112 break; 1113 } 1114 case PPC::CP_PASTEx : 1115 case PPC::CP_PASTE_LAST: { 1116 MCInst TmpInst; 1117 TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ? PPC::CP_PASTE 1118 : PPC::CP_PASTE_rec); 1119 TmpInst.addOperand(Inst.getOperand(0)); 1120 TmpInst.addOperand(Inst.getOperand(1)); 1121 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1)); 1122 1123 Inst = TmpInst; 1124 break; 1125 } 1126 } 1127 } 1128 1129 static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, 1130 unsigned VariantID = 0); 1131 1132 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 1133 OperandVector &Operands, 1134 MCStreamer &Out, uint64_t &ErrorInfo, 1135 bool MatchingInlineAsm) { 1136 MCInst Inst; 1137 1138 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { 1139 case Match_Success: 1140 // Post-process instructions (typically extended mnemonics) 1141 ProcessInstruction(Inst, Operands); 1142 Inst.setLoc(IDLoc); 1143 Out.emitInstruction(Inst, getSTI()); 1144 return false; 1145 case Match_MissingFeature: 1146 return Error(IDLoc, "instruction use requires an option to be enabled"); 1147 case Match_MnemonicFail: { 1148 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); 1149 std::string Suggestion = PPCMnemonicSpellCheck( 1150 ((PPCOperand &)*Operands[0]).getToken(), FBS); 1151 return Error(IDLoc, "invalid instruction" + Suggestion, 1152 ((PPCOperand &)*Operands[0]).getLocRange()); 1153 } 1154 case Match_InvalidOperand: { 1155 SMLoc ErrorLoc = IDLoc; 1156 if (ErrorInfo != ~0ULL) { 1157 if (ErrorInfo >= Operands.size()) 1158 return Error(IDLoc, "too few operands for instruction"); 1159 1160 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc(); 1161 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 1162 } 1163 1164 return Error(ErrorLoc, "invalid operand for instruction"); 1165 } 1166 } 1167 1168 llvm_unreachable("Implement any new match types added!"); 1169 } 1170 1171 bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) { 1172 if (getParser().getTok().is(AsmToken::Identifier)) { 1173 StringRef Name = getParser().getTok().getString(); 1174 if (Name.equals_lower("lr")) { 1175 RegNo = isPPC64()? PPC::LR8 : PPC::LR; 1176 IntVal = 8; 1177 } else if (Name.equals_lower("ctr")) { 1178 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR; 1179 IntVal = 9; 1180 } else if (Name.equals_lower("vrsave")) { 1181 RegNo = PPC::VRSAVE; 1182 IntVal = 256; 1183 } else if (Name.startswith_lower("r") && 1184 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1185 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal]; 1186 } else if (Name.startswith_lower("f") && 1187 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1188 RegNo = FRegs[IntVal]; 1189 } else if (Name.startswith_lower("vs") && 1190 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) { 1191 RegNo = VSRegs[IntVal]; 1192 } else if (Name.startswith_lower("v") && 1193 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1194 RegNo = VRegs[IntVal]; 1195 } else if (Name.startswith_lower("cr") && 1196 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { 1197 RegNo = CRRegs[IntVal]; 1198 } else 1199 return true; 1200 getParser().Lex(); 1201 return false; 1202 } 1203 return true; 1204 } 1205 1206 bool PPCAsmParser:: 1207 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 1208 if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success) 1209 return TokError("invalid register name"); 1210 return false; 1211 } 1212 1213 OperandMatchResultTy PPCAsmParser::tryParseRegister(unsigned &RegNo, 1214 SMLoc &StartLoc, 1215 SMLoc &EndLoc) { 1216 const AsmToken &Tok = getParser().getTok(); 1217 StartLoc = Tok.getLoc(); 1218 EndLoc = Tok.getEndLoc(); 1219 RegNo = 0; 1220 int64_t IntVal; 1221 if (MatchRegisterName(RegNo, IntVal)) 1222 return MatchOperand_NoMatch; 1223 return MatchOperand_Success; 1224 } 1225 1226 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan 1227 /// the expression and check for VK_PPC_LO/HI/HA 1228 /// symbol variants. If all symbols with modifier use the same 1229 /// variant, return the corresponding PPCMCExpr::VariantKind, 1230 /// and a modified expression using the default symbol variant. 1231 /// Otherwise, return NULL. 1232 const MCExpr *PPCAsmParser:: 1233 ExtractModifierFromExpr(const MCExpr *E, 1234 PPCMCExpr::VariantKind &Variant) { 1235 MCContext &Context = getParser().getContext(); 1236 Variant = PPCMCExpr::VK_PPC_None; 1237 1238 switch (E->getKind()) { 1239 case MCExpr::Target: 1240 case MCExpr::Constant: 1241 return nullptr; 1242 1243 case MCExpr::SymbolRef: { 1244 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1245 1246 switch (SRE->getKind()) { 1247 case MCSymbolRefExpr::VK_PPC_LO: 1248 Variant = PPCMCExpr::VK_PPC_LO; 1249 break; 1250 case MCSymbolRefExpr::VK_PPC_HI: 1251 Variant = PPCMCExpr::VK_PPC_HI; 1252 break; 1253 case MCSymbolRefExpr::VK_PPC_HA: 1254 Variant = PPCMCExpr::VK_PPC_HA; 1255 break; 1256 case MCSymbolRefExpr::VK_PPC_HIGH: 1257 Variant = PPCMCExpr::VK_PPC_HIGH; 1258 break; 1259 case MCSymbolRefExpr::VK_PPC_HIGHA: 1260 Variant = PPCMCExpr::VK_PPC_HIGHA; 1261 break; 1262 case MCSymbolRefExpr::VK_PPC_HIGHER: 1263 Variant = PPCMCExpr::VK_PPC_HIGHER; 1264 break; 1265 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1266 Variant = PPCMCExpr::VK_PPC_HIGHERA; 1267 break; 1268 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1269 Variant = PPCMCExpr::VK_PPC_HIGHEST; 1270 break; 1271 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1272 Variant = PPCMCExpr::VK_PPC_HIGHESTA; 1273 break; 1274 default: 1275 return nullptr; 1276 } 1277 1278 return MCSymbolRefExpr::create(&SRE->getSymbol(), Context); 1279 } 1280 1281 case MCExpr::Unary: { 1282 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1283 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant); 1284 if (!Sub) 1285 return nullptr; 1286 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1287 } 1288 1289 case MCExpr::Binary: { 1290 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1291 PPCMCExpr::VariantKind LHSVariant, RHSVariant; 1292 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant); 1293 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant); 1294 1295 if (!LHS && !RHS) 1296 return nullptr; 1297 1298 if (!LHS) LHS = BE->getLHS(); 1299 if (!RHS) RHS = BE->getRHS(); 1300 1301 if (LHSVariant == PPCMCExpr::VK_PPC_None) 1302 Variant = RHSVariant; 1303 else if (RHSVariant == PPCMCExpr::VK_PPC_None) 1304 Variant = LHSVariant; 1305 else if (LHSVariant == RHSVariant) 1306 Variant = LHSVariant; 1307 else 1308 return nullptr; 1309 1310 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1311 } 1312 } 1313 1314 llvm_unreachable("Invalid expression kind!"); 1315 } 1316 1317 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace 1318 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having 1319 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT. 1320 /// FIXME: This is a hack. 1321 const MCExpr *PPCAsmParser:: 1322 FixupVariantKind(const MCExpr *E) { 1323 MCContext &Context = getParser().getContext(); 1324 1325 switch (E->getKind()) { 1326 case MCExpr::Target: 1327 case MCExpr::Constant: 1328 return E; 1329 1330 case MCExpr::SymbolRef: { 1331 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1332 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; 1333 1334 switch (SRE->getKind()) { 1335 case MCSymbolRefExpr::VK_TLSGD: 1336 Variant = MCSymbolRefExpr::VK_PPC_TLSGD; 1337 break; 1338 case MCSymbolRefExpr::VK_TLSLD: 1339 Variant = MCSymbolRefExpr::VK_PPC_TLSLD; 1340 break; 1341 default: 1342 return E; 1343 } 1344 return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context); 1345 } 1346 1347 case MCExpr::Unary: { 1348 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1349 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr()); 1350 if (Sub == UE->getSubExpr()) 1351 return E; 1352 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1353 } 1354 1355 case MCExpr::Binary: { 1356 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1357 const MCExpr *LHS = FixupVariantKind(BE->getLHS()); 1358 const MCExpr *RHS = FixupVariantKind(BE->getRHS()); 1359 if (LHS == BE->getLHS() && RHS == BE->getRHS()) 1360 return E; 1361 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1362 } 1363 } 1364 1365 llvm_unreachable("Invalid expression kind!"); 1366 } 1367 1368 /// ParseExpression. This differs from the default "parseExpression" in that 1369 /// it handles modifiers. 1370 bool PPCAsmParser:: 1371 ParseExpression(const MCExpr *&EVal) { 1372 1373 if (isDarwin()) 1374 return ParseDarwinExpression(EVal); 1375 1376 // (ELF Platforms) 1377 // Handle \code @l/@ha \endcode 1378 if (getParser().parseExpression(EVal)) 1379 return true; 1380 1381 EVal = FixupVariantKind(EVal); 1382 1383 PPCMCExpr::VariantKind Variant; 1384 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant); 1385 if (E) 1386 EVal = PPCMCExpr::create(Variant, E, getParser().getContext()); 1387 1388 return false; 1389 } 1390 1391 /// ParseDarwinExpression. (MachO Platforms) 1392 /// This differs from the default "parseExpression" in that it handles detection 1393 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present, 1394 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO 1395 /// syntax form so it is done here. TODO: Determine if there is merit in 1396 /// arranging for this to be done at a higher level. 1397 bool PPCAsmParser:: 1398 ParseDarwinExpression(const MCExpr *&EVal) { 1399 MCAsmParser &Parser = getParser(); 1400 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None; 1401 switch (getLexer().getKind()) { 1402 default: 1403 break; 1404 case AsmToken::Identifier: 1405 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus 1406 // something starting with any other char should be part of the 1407 // asm syntax. If handwritten asm includes an identifier like lo16, 1408 // then all bets are off - but no-one would do that, right? 1409 StringRef poss = Parser.getTok().getString(); 1410 if (poss.equals_lower("lo16")) { 1411 Variant = PPCMCExpr::VK_PPC_LO; 1412 } else if (poss.equals_lower("hi16")) { 1413 Variant = PPCMCExpr::VK_PPC_HI; 1414 } else if (poss.equals_lower("ha16")) { 1415 Variant = PPCMCExpr::VK_PPC_HA; 1416 } 1417 if (Variant != PPCMCExpr::VK_PPC_None) { 1418 Parser.Lex(); // Eat the xx16 1419 if (getLexer().isNot(AsmToken::LParen)) 1420 return Error(Parser.getTok().getLoc(), "expected '('"); 1421 Parser.Lex(); // Eat the '(' 1422 } 1423 break; 1424 } 1425 1426 if (getParser().parseExpression(EVal)) 1427 return true; 1428 1429 if (Variant != PPCMCExpr::VK_PPC_None) { 1430 if (getLexer().isNot(AsmToken::RParen)) 1431 return Error(Parser.getTok().getLoc(), "expected ')'"); 1432 Parser.Lex(); // Eat the ')' 1433 EVal = PPCMCExpr::create(Variant, EVal, getParser().getContext()); 1434 } 1435 return false; 1436 } 1437 1438 /// ParseOperand 1439 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and 1440 /// rNN for MachO. 1441 bool PPCAsmParser::ParseOperand(OperandVector &Operands) { 1442 MCAsmParser &Parser = getParser(); 1443 SMLoc S = Parser.getTok().getLoc(); 1444 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1445 const MCExpr *EVal; 1446 1447 // Attempt to parse the next token as an immediate 1448 switch (getLexer().getKind()) { 1449 // Special handling for register names. These are interpreted 1450 // as immediates corresponding to the register number. 1451 case AsmToken::Percent: 1452 Parser.Lex(); // Eat the '%'. 1453 unsigned RegNo; 1454 int64_t IntVal; 1455 if (MatchRegisterName(RegNo, IntVal)) 1456 return Error(S, "invalid register name"); 1457 1458 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1459 return false; 1460 1461 case AsmToken::Identifier: 1462 case AsmToken::LParen: 1463 case AsmToken::Plus: 1464 case AsmToken::Minus: 1465 case AsmToken::Integer: 1466 case AsmToken::Dot: 1467 case AsmToken::Dollar: 1468 case AsmToken::Exclaim: 1469 case AsmToken::Tilde: 1470 // Note that non-register-name identifiers from the compiler will begin 1471 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include 1472 // identifiers like r31foo - so we fall through in the event that parsing 1473 // a register name fails. 1474 if (isDarwin()) { 1475 unsigned RegNo; 1476 int64_t IntVal; 1477 if (!MatchRegisterName(RegNo, IntVal)) { 1478 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1479 return false; 1480 } 1481 } 1482 // All other expressions 1483 1484 if (!ParseExpression(EVal)) 1485 break; 1486 // Fall-through 1487 LLVM_FALLTHROUGH; 1488 default: 1489 return Error(S, "unknown operand"); 1490 } 1491 1492 // Push the parsed operand into the list of operands 1493 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64())); 1494 1495 // Check whether this is a TLS call expression 1496 bool TLSCall = false; 1497 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal)) 1498 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr"; 1499 1500 if (TLSCall && getLexer().is(AsmToken::LParen)) { 1501 const MCExpr *TLSSym; 1502 1503 Parser.Lex(); // Eat the '('. 1504 S = Parser.getTok().getLoc(); 1505 if (ParseExpression(TLSSym)) 1506 return Error(S, "invalid TLS call expression"); 1507 if (getLexer().isNot(AsmToken::RParen)) 1508 return Error(Parser.getTok().getLoc(), "missing ')'"); 1509 E = Parser.getTok().getLoc(); 1510 Parser.Lex(); // Eat the ')'. 1511 1512 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64())); 1513 } 1514 1515 // Otherwise, check for D-form memory operands 1516 if (!TLSCall && getLexer().is(AsmToken::LParen)) { 1517 Parser.Lex(); // Eat the '('. 1518 S = Parser.getTok().getLoc(); 1519 1520 int64_t IntVal; 1521 switch (getLexer().getKind()) { 1522 case AsmToken::Percent: 1523 Parser.Lex(); // Eat the '%'. 1524 unsigned RegNo; 1525 if (MatchRegisterName(RegNo, IntVal)) 1526 return Error(S, "invalid register name"); 1527 break; 1528 1529 case AsmToken::Integer: 1530 if (isDarwin()) 1531 return Error(S, "unexpected integer value"); 1532 else if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 || 1533 IntVal > 31) 1534 return Error(S, "invalid register number"); 1535 break; 1536 case AsmToken::Identifier: 1537 if (isDarwin()) { 1538 unsigned RegNo; 1539 if (!MatchRegisterName(RegNo, IntVal)) { 1540 break; 1541 } 1542 } 1543 LLVM_FALLTHROUGH; 1544 1545 default: 1546 return Error(S, "invalid memory operand"); 1547 } 1548 1549 E = Parser.getTok().getLoc(); 1550 if (parseToken(AsmToken::RParen, "missing ')'")) 1551 return true; 1552 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1553 } 1554 1555 return false; 1556 } 1557 1558 /// Parse an instruction mnemonic followed by its operands. 1559 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 1560 SMLoc NameLoc, OperandVector &Operands) { 1561 // The first operand is the token for the instruction name. 1562 // If the next character is a '+' or '-', we need to add it to the 1563 // instruction name, to match what TableGen is doing. 1564 std::string NewOpcode; 1565 if (parseOptionalToken(AsmToken::Plus)) { 1566 NewOpcode = std::string(Name); 1567 NewOpcode += '+'; 1568 Name = NewOpcode; 1569 } 1570 if (parseOptionalToken(AsmToken::Minus)) { 1571 NewOpcode = std::string(Name); 1572 NewOpcode += '-'; 1573 Name = NewOpcode; 1574 } 1575 // If the instruction ends in a '.', we need to create a separate 1576 // token for it, to match what TableGen is doing. 1577 size_t Dot = Name.find('.'); 1578 StringRef Mnemonic = Name.slice(0, Dot); 1579 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1580 Operands.push_back( 1581 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64())); 1582 else 1583 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64())); 1584 if (Dot != StringRef::npos) { 1585 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot); 1586 StringRef DotStr = Name.slice(Dot, StringRef::npos); 1587 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1588 Operands.push_back( 1589 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64())); 1590 else 1591 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64())); 1592 } 1593 1594 // If there are no more operands then finish 1595 if (parseOptionalToken(AsmToken::EndOfStatement)) 1596 return false; 1597 1598 // Parse the first operand 1599 if (ParseOperand(Operands)) 1600 return true; 1601 1602 while (!parseOptionalToken(AsmToken::EndOfStatement)) { 1603 if (parseToken(AsmToken::Comma) || ParseOperand(Operands)) 1604 return true; 1605 } 1606 1607 // We'll now deal with an unfortunate special case: the syntax for the dcbt 1608 // and dcbtst instructions differs for server vs. embedded cores. 1609 // The syntax for dcbt is: 1610 // dcbt ra, rb, th [server] 1611 // dcbt th, ra, rb [embedded] 1612 // where th can be omitted when it is 0. dcbtst is the same. We take the 1613 // server form to be the default, so swap the operands if we're parsing for 1614 // an embedded core (they'll be swapped again upon printing). 1615 if (getSTI().getFeatureBits()[PPC::FeatureBookE] && 1616 Operands.size() == 4 && 1617 (Name == "dcbt" || Name == "dcbtst")) { 1618 std::swap(Operands[1], Operands[3]); 1619 std::swap(Operands[2], Operands[1]); 1620 } 1621 1622 return false; 1623 } 1624 1625 /// ParseDirective parses the PPC specific directives 1626 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) { 1627 StringRef IDVal = DirectiveID.getIdentifier(); 1628 if (isDarwin()) { 1629 if (IDVal == ".machine") 1630 ParseDarwinDirectiveMachine(DirectiveID.getLoc()); 1631 else 1632 return true; 1633 } else if (IDVal == ".word") 1634 ParseDirectiveWord(2, DirectiveID); 1635 else if (IDVal == ".llong") 1636 ParseDirectiveWord(8, DirectiveID); 1637 else if (IDVal == ".tc") 1638 ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID); 1639 else if (IDVal == ".machine") 1640 ParseDirectiveMachine(DirectiveID.getLoc()); 1641 else if (IDVal == ".abiversion") 1642 ParseDirectiveAbiVersion(DirectiveID.getLoc()); 1643 else if (IDVal == ".localentry") 1644 ParseDirectiveLocalEntry(DirectiveID.getLoc()); 1645 else 1646 return true; 1647 return false; 1648 } 1649 1650 /// ParseDirectiveWord 1651 /// ::= .word [ expression (, expression)* ] 1652 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) { 1653 auto parseOp = [&]() -> bool { 1654 const MCExpr *Value; 1655 SMLoc ExprLoc = getParser().getTok().getLoc(); 1656 if (getParser().parseExpression(Value)) 1657 return true; 1658 if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) { 1659 assert(Size <= 8 && "Invalid size"); 1660 uint64_t IntValue = MCE->getValue(); 1661 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue)) 1662 return Error(ExprLoc, "literal value out of range for '" + 1663 ID.getIdentifier() + "' directive"); 1664 getStreamer().emitIntValue(IntValue, Size); 1665 } else 1666 getStreamer().emitValue(Value, Size, ExprLoc); 1667 return false; 1668 }; 1669 1670 if (parseMany(parseOp)) 1671 return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive"); 1672 return false; 1673 } 1674 1675 /// ParseDirectiveTC 1676 /// ::= .tc [ symbol (, expression)* ] 1677 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) { 1678 MCAsmParser &Parser = getParser(); 1679 // Skip TC symbol, which is only used with XCOFF. 1680 while (getLexer().isNot(AsmToken::EndOfStatement) 1681 && getLexer().isNot(AsmToken::Comma)) 1682 Parser.Lex(); 1683 if (parseToken(AsmToken::Comma)) 1684 return addErrorSuffix(" in '.tc' directive"); 1685 1686 // Align to word size. 1687 getParser().getStreamer().emitValueToAlignment(Size); 1688 1689 // Emit expressions. 1690 return ParseDirectiveWord(Size, ID); 1691 } 1692 1693 /// ParseDirectiveMachine (ELF platforms) 1694 /// ::= .machine [ cpu | "push" | "pop" ] 1695 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) { 1696 MCAsmParser &Parser = getParser(); 1697 if (Parser.getTok().isNot(AsmToken::Identifier) && 1698 Parser.getTok().isNot(AsmToken::String)) 1699 return Error(L, "unexpected token in '.machine' directive"); 1700 1701 StringRef CPU = Parser.getTok().getIdentifier(); 1702 1703 // FIXME: Right now, the parser always allows any available 1704 // instruction, so the .machine directive is not useful. 1705 // Implement ".machine any" (by doing nothing) for the benefit 1706 // of existing assembler code. Likewise, we can then implement 1707 // ".machine push" and ".machine pop" as no-op. 1708 if (CPU != "any" && CPU != "push" && CPU != "pop") 1709 return TokError("unrecognized machine type"); 1710 1711 Parser.Lex(); 1712 1713 if (parseToken(AsmToken::EndOfStatement)) 1714 return addErrorSuffix(" in '.machine' directive"); 1715 1716 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>( 1717 getParser().getStreamer().getTargetStreamer()); 1718 if (TStreamer != nullptr) 1719 TStreamer->emitMachine(CPU); 1720 1721 return false; 1722 } 1723 1724 /// ParseDarwinDirectiveMachine (Mach-o platforms) 1725 /// ::= .machine cpu-identifier 1726 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) { 1727 MCAsmParser &Parser = getParser(); 1728 if (Parser.getTok().isNot(AsmToken::Identifier) && 1729 Parser.getTok().isNot(AsmToken::String)) 1730 return Error(L, "unexpected token in directive"); 1731 1732 StringRef CPU = Parser.getTok().getIdentifier(); 1733 Parser.Lex(); 1734 1735 // FIXME: this is only the 'default' set of cpu variants. 1736 // However we don't act on this information at present, this is simply 1737 // allowing parsing to proceed with minimal sanity checking. 1738 if (check(CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64", L, 1739 "unrecognized cpu type") || 1740 check(isPPC64() && (CPU == "ppc7400" || CPU == "ppc"), L, 1741 "wrong cpu type specified for 64bit") || 1742 check(!isPPC64() && CPU == "ppc64", L, 1743 "wrong cpu type specified for 32bit") || 1744 parseToken(AsmToken::EndOfStatement)) 1745 return addErrorSuffix(" in '.machine' directive"); 1746 return false; 1747 } 1748 1749 /// ParseDirectiveAbiVersion 1750 /// ::= .abiversion constant-expression 1751 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) { 1752 int64_t AbiVersion; 1753 if (check(getParser().parseAbsoluteExpression(AbiVersion), L, 1754 "expected constant expression") || 1755 parseToken(AsmToken::EndOfStatement)) 1756 return addErrorSuffix(" in '.abiversion' directive"); 1757 1758 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>( 1759 getParser().getStreamer().getTargetStreamer()); 1760 if (TStreamer != nullptr) 1761 TStreamer->emitAbiVersion(AbiVersion); 1762 1763 return false; 1764 } 1765 1766 /// ParseDirectiveLocalEntry 1767 /// ::= .localentry symbol, expression 1768 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) { 1769 StringRef Name; 1770 if (getParser().parseIdentifier(Name)) 1771 return Error(L, "expected identifier in '.localentry' directive"); 1772 1773 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name)); 1774 const MCExpr *Expr; 1775 1776 if (parseToken(AsmToken::Comma) || 1777 check(getParser().parseExpression(Expr), L, "expected expression") || 1778 parseToken(AsmToken::EndOfStatement)) 1779 return addErrorSuffix(" in '.localentry' directive"); 1780 1781 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>( 1782 getParser().getStreamer().getTargetStreamer()); 1783 if (TStreamer != nullptr) 1784 TStreamer->emitLocalEntry(Sym, Expr); 1785 1786 return false; 1787 } 1788 1789 1790 1791 /// Force static initialization. 1792 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCAsmParser() { 1793 RegisterMCAsmParser<PPCAsmParser> A(getThePPC32Target()); 1794 RegisterMCAsmParser<PPCAsmParser> B(getThePPC64Target()); 1795 RegisterMCAsmParser<PPCAsmParser> C(getThePPC64LETarget()); 1796 } 1797 1798 #define GET_REGISTER_MATCHER 1799 #define GET_MATCHER_IMPLEMENTATION 1800 #define GET_MNEMONIC_SPELL_CHECKER 1801 #include "PPCGenAsmMatcher.inc" 1802 1803 // Define this matcher function after the auto-generated include so we 1804 // have the match class enum definitions. 1805 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, 1806 unsigned Kind) { 1807 // If the kind is a token for a literal immediate, check if our asm 1808 // operand matches. This is for InstAliases which have a fixed-value 1809 // immediate in the syntax. 1810 int64_t ImmVal; 1811 switch (Kind) { 1812 case MCK_0: ImmVal = 0; break; 1813 case MCK_1: ImmVal = 1; break; 1814 case MCK_2: ImmVal = 2; break; 1815 case MCK_3: ImmVal = 3; break; 1816 case MCK_4: ImmVal = 4; break; 1817 case MCK_5: ImmVal = 5; break; 1818 case MCK_6: ImmVal = 6; break; 1819 case MCK_7: ImmVal = 7; break; 1820 default: return Match_InvalidOperand; 1821 } 1822 1823 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp); 1824 if (Op.isImm() && Op.getImm() == ImmVal) 1825 return Match_Success; 1826 1827 return Match_InvalidOperand; 1828 } 1829 1830 const MCExpr * 1831 PPCAsmParser::applyModifierToExpr(const MCExpr *E, 1832 MCSymbolRefExpr::VariantKind Variant, 1833 MCContext &Ctx) { 1834 switch (Variant) { 1835 case MCSymbolRefExpr::VK_PPC_LO: 1836 return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, Ctx); 1837 case MCSymbolRefExpr::VK_PPC_HI: 1838 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, Ctx); 1839 case MCSymbolRefExpr::VK_PPC_HA: 1840 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, Ctx); 1841 case MCSymbolRefExpr::VK_PPC_HIGH: 1842 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGH, E, Ctx); 1843 case MCSymbolRefExpr::VK_PPC_HIGHA: 1844 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHA, E, Ctx); 1845 case MCSymbolRefExpr::VK_PPC_HIGHER: 1846 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, Ctx); 1847 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1848 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, Ctx); 1849 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1850 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, Ctx); 1851 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1852 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, Ctx); 1853 default: 1854 return nullptr; 1855 } 1856 } 1857