xref: /llvm-project/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (revision c93a9a2cb4593839b2cd495c53d5b1c9cf456830) 
1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCTargetAsmParser.h"
29 #include "llvm/Support/SourceMgr.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
32 
33 using namespace llvm;
34 
35 static const MCPhysReg RRegs[32] = {
36   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
37   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
38   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
39   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
40   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
41   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
42   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
43   PPC::R28, PPC::R29, PPC::R30, PPC::R31
44 };
45 static const MCPhysReg RRegsNoR0[32] = {
46   PPC::ZERO,
47             PPC::R1,  PPC::R2,  PPC::R3,
48   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
49   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
50   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
51   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
52   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
53   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
54   PPC::R28, PPC::R29, PPC::R30, PPC::R31
55 };
56 static const MCPhysReg XRegs[32] = {
57   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
58   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
59   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
60   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
61   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
62   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
63   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
64   PPC::X28, PPC::X29, PPC::X30, PPC::X31
65 };
66 static const MCPhysReg XRegsNoX0[32] = {
67   PPC::ZERO8,
68             PPC::X1,  PPC::X2,  PPC::X3,
69   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
70   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
71   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
72   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
73   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
74   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
75   PPC::X28, PPC::X29, PPC::X30, PPC::X31
76 };
77 static const MCPhysReg FRegs[32] = {
78   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
79   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
80   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
81   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
82   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
83   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
84   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
85   PPC::F28, PPC::F29, PPC::F30, PPC::F31
86 };
87 static const MCPhysReg VRegs[32] = {
88   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
89   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
90   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
91   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
92   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
93   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
94   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
95   PPC::V28, PPC::V29, PPC::V30, PPC::V31
96 };
97 static const MCPhysReg VSRegs[64] = {
98   PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
99   PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
100   PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
101   PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
102   PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
103   PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
104   PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
105   PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
106 
107   PPC::VSH0,  PPC::VSH1,  PPC::VSH2,  PPC::VSH3,
108   PPC::VSH4,  PPC::VSH5,  PPC::VSH6,  PPC::VSH7,
109   PPC::VSH8,  PPC::VSH9,  PPC::VSH10, PPC::VSH11,
110   PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
111   PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
112   PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
113   PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
114   PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
115 };
116 static const MCPhysReg VSFRegs[64] = {
117   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
118   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
119   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
120   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
121   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
122   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
123   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
124   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
125 
126   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
127   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
128   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
129   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
130   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
131   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
132   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
133   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
134 };
135 static unsigned QFRegs[32] = {
136   PPC::QF0,  PPC::QF1,  PPC::QF2,  PPC::QF3,
137   PPC::QF4,  PPC::QF5,  PPC::QF6,  PPC::QF7,
138   PPC::QF8,  PPC::QF9,  PPC::QF10, PPC::QF11,
139   PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
140   PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
141   PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
142   PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
143   PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
144 };
145 static const MCPhysReg CRBITRegs[32] = {
146   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
147   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
148   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
149   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
150   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
151   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
152   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
153   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
154 };
155 static const MCPhysReg CRRegs[8] = {
156   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
157   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
158 };
159 
160 // Evaluate an expression containing condition register
161 // or condition register field symbols.  Returns positive
162 // value on success, or -1 on error.
163 static int64_t
164 EvaluateCRExpr(const MCExpr *E) {
165   switch (E->getKind()) {
166   case MCExpr::Target:
167     return -1;
168 
169   case MCExpr::Constant: {
170     int64_t Res = cast<MCConstantExpr>(E)->getValue();
171     return Res < 0 ? -1 : Res;
172   }
173 
174   case MCExpr::SymbolRef: {
175     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
176     StringRef Name = SRE->getSymbol().getName();
177 
178     if (Name == "lt") return 0;
179     if (Name == "gt") return 1;
180     if (Name == "eq") return 2;
181     if (Name == "so") return 3;
182     if (Name == "un") return 3;
183 
184     if (Name == "cr0") return 0;
185     if (Name == "cr1") return 1;
186     if (Name == "cr2") return 2;
187     if (Name == "cr3") return 3;
188     if (Name == "cr4") return 4;
189     if (Name == "cr5") return 5;
190     if (Name == "cr6") return 6;
191     if (Name == "cr7") return 7;
192 
193     return -1;
194   }
195 
196   case MCExpr::Unary:
197     return -1;
198 
199   case MCExpr::Binary: {
200     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
201     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
202     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
203     int64_t Res;
204 
205     if (LHSVal < 0 || RHSVal < 0)
206       return -1;
207 
208     switch (BE->getOpcode()) {
209     default: return -1;
210     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
211     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
212     }
213 
214     return Res < 0 ? -1 : Res;
215   }
216   }
217 
218   llvm_unreachable("Invalid expression kind!");
219 }
220 
221 namespace {
222 
223 struct PPCOperand;
224 
225 class PPCAsmParser : public MCTargetAsmParser {
226   MCSubtargetInfo &STI;
227   const MCInstrInfo &MII;
228   bool IsPPC64;
229   bool IsDarwin;
230 
231   void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
232   bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
233 
234   bool isPPC64() const { return IsPPC64; }
235   bool isDarwin() const { return IsDarwin; }
236 
237   bool MatchRegisterName(const AsmToken &Tok,
238                          unsigned &RegNo, int64_t &IntVal);
239 
240   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
241 
242   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
243                                         PPCMCExpr::VariantKind &Variant);
244   const MCExpr *FixupVariantKind(const MCExpr *E);
245   bool ParseExpression(const MCExpr *&EVal);
246   bool ParseDarwinExpression(const MCExpr *&EVal);
247 
248   bool ParseOperand(OperandVector &Operands);
249 
250   bool ParseDirectiveWord(unsigned Size, SMLoc L);
251   bool ParseDirectiveTC(unsigned Size, SMLoc L);
252   bool ParseDirectiveMachine(SMLoc L);
253   bool ParseDarwinDirectiveMachine(SMLoc L);
254   bool ParseDirectiveAbiVersion(SMLoc L);
255   bool ParseDirectiveLocalEntry(SMLoc L);
256 
257   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
258                                OperandVector &Operands, MCStreamer &Out,
259                                uint64_t &ErrorInfo,
260                                bool MatchingInlineAsm) override;
261 
262   void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
263 
264   /// @name Auto-generated Match Functions
265   /// {
266 
267 #define GET_ASSEMBLER_HEADER
268 #include "PPCGenAsmMatcher.inc"
269 
270   /// }
271 
272 
273 public:
274   PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
275                const MCInstrInfo &_MII, const MCTargetOptions &Options)
276       : MCTargetAsmParser(), STI(_STI), MII(_MII) {
277     // Check for 64-bit vs. 32-bit pointer mode.
278     Triple TheTriple(STI.getTargetTriple());
279     IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
280                TheTriple.getArch() == Triple::ppc64le);
281     IsDarwin = TheTriple.isMacOSX();
282     // Initialize the set of available features.
283     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
284   }
285 
286   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
287                         SMLoc NameLoc, OperandVector &Operands) override;
288 
289   bool ParseDirective(AsmToken DirectiveID) override;
290 
291   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
292                                       unsigned Kind) override;
293 
294   const MCExpr *applyModifierToExpr(const MCExpr *E,
295                                     MCSymbolRefExpr::VariantKind,
296                                     MCContext &Ctx) override;
297 };
298 
299 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
300 /// instruction.
301 struct PPCOperand : public MCParsedAsmOperand {
302   enum KindTy {
303     Token,
304     Immediate,
305     ContextImmediate,
306     Expression,
307     TLSRegister
308   } Kind;
309 
310   SMLoc StartLoc, EndLoc;
311   bool IsPPC64;
312 
313   struct TokOp {
314     const char *Data;
315     unsigned Length;
316   };
317 
318   struct ImmOp {
319     int64_t Val;
320   };
321 
322   struct ExprOp {
323     const MCExpr *Val;
324     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
325   };
326 
327   struct TLSRegOp {
328     const MCSymbolRefExpr *Sym;
329   };
330 
331   union {
332     struct TokOp Tok;
333     struct ImmOp Imm;
334     struct ExprOp Expr;
335     struct TLSRegOp TLSReg;
336   };
337 
338   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
339 public:
340   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
341     Kind = o.Kind;
342     StartLoc = o.StartLoc;
343     EndLoc = o.EndLoc;
344     IsPPC64 = o.IsPPC64;
345     switch (Kind) {
346     case Token:
347       Tok = o.Tok;
348       break;
349     case Immediate:
350     case ContextImmediate:
351       Imm = o.Imm;
352       break;
353     case Expression:
354       Expr = o.Expr;
355       break;
356     case TLSRegister:
357       TLSReg = o.TLSReg;
358       break;
359     }
360   }
361 
362   /// getStartLoc - Get the location of the first token of this operand.
363   SMLoc getStartLoc() const override { return StartLoc; }
364 
365   /// getEndLoc - Get the location of the last token of this operand.
366   SMLoc getEndLoc() const override { return EndLoc; }
367 
368   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
369   bool isPPC64() const { return IsPPC64; }
370 
371   int64_t getImm() const {
372     assert(Kind == Immediate && "Invalid access!");
373     return Imm.Val;
374   }
375   int64_t getImmS16Context() const {
376     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
377     if (Kind == Immediate)
378       return Imm.Val;
379     return static_cast<int16_t>(Imm.Val);
380   }
381   int64_t getImmU16Context() const {
382     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
383     return Imm.Val;
384   }
385 
386   const MCExpr *getExpr() const {
387     assert(Kind == Expression && "Invalid access!");
388     return Expr.Val;
389   }
390 
391   int64_t getExprCRVal() const {
392     assert(Kind == Expression && "Invalid access!");
393     return Expr.CRVal;
394   }
395 
396   const MCExpr *getTLSReg() const {
397     assert(Kind == TLSRegister && "Invalid access!");
398     return TLSReg.Sym;
399   }
400 
401   unsigned getReg() const override {
402     assert(isRegNumber() && "Invalid access!");
403     return (unsigned) Imm.Val;
404   }
405 
406   unsigned getVSReg() const {
407     assert(isVSRegNumber() && "Invalid access!");
408     return (unsigned) Imm.Val;
409   }
410 
411   unsigned getCCReg() const {
412     assert(isCCRegNumber() && "Invalid access!");
413     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
414   }
415 
416   unsigned getCRBit() const {
417     assert(isCRBitNumber() && "Invalid access!");
418     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
419   }
420 
421   unsigned getCRBitMask() const {
422     assert(isCRBitMask() && "Invalid access!");
423     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
424   }
425 
426   bool isToken() const override { return Kind == Token; }
427   bool isImm() const override { return Kind == Immediate || Kind == Expression; }
428   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
429   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
430   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
431   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
432   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
433   bool isU6ImmX2() const { return Kind == Immediate &&
434                                   isUInt<6>(getImm()) &&
435                                   (getImm() & 1) == 0; }
436   bool isU7ImmX4() const { return Kind == Immediate &&
437                                   isUInt<7>(getImm()) &&
438                                   (getImm() & 3) == 0; }
439   bool isU8ImmX8() const { return Kind == Immediate &&
440                                   isUInt<8>(getImm()) &&
441                                   (getImm() & 7) == 0; }
442   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
443   bool isU16Imm() const {
444     switch (Kind) {
445       case Expression:
446         return true;
447       case Immediate:
448       case ContextImmediate:
449         return isUInt<16>(getImmU16Context());
450       default:
451         return false;
452     }
453   }
454   bool isS16Imm() const {
455     switch (Kind) {
456       case Expression:
457         return true;
458       case Immediate:
459       case ContextImmediate:
460         return isInt<16>(getImmS16Context());
461       default:
462         return false;
463     }
464   }
465   bool isS16ImmX4() const { return Kind == Expression ||
466                                    (Kind == Immediate && isInt<16>(getImm()) &&
467                                     (getImm() & 3) == 0); }
468   bool isS17Imm() const {
469     switch (Kind) {
470       case Expression:
471         return true;
472       case Immediate:
473       case ContextImmediate:
474         return isInt<17>(getImmS16Context());
475       default:
476         return false;
477     }
478   }
479   bool isTLSReg() const { return Kind == TLSRegister; }
480   bool isDirectBr() const {
481     if (Kind == Expression)
482       return true;
483     if (Kind != Immediate)
484       return false;
485     // Operand must be 64-bit aligned, signed 27-bit immediate.
486     if ((getImm() & 3) != 0)
487       return false;
488     if (isInt<26>(getImm()))
489       return true;
490     if (!IsPPC64) {
491       // In 32-bit mode, large 32-bit quantities wrap around.
492       if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
493         return true;
494     }
495     return false;
496   }
497   bool isCondBr() const { return Kind == Expression ||
498                                  (Kind == Immediate && isInt<16>(getImm()) &&
499                                   (getImm() & 3) == 0); }
500   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
501   bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
502   bool isCCRegNumber() const { return (Kind == Expression
503                                        && isUInt<3>(getExprCRVal())) ||
504                                       (Kind == Immediate
505                                        && isUInt<3>(getImm())); }
506   bool isCRBitNumber() const { return (Kind == Expression
507                                        && isUInt<5>(getExprCRVal())) ||
508                                       (Kind == Immediate
509                                        && isUInt<5>(getImm())); }
510   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
511                                     isPowerOf2_32(getImm()); }
512   bool isMem() const override { return false; }
513   bool isReg() const override { return false; }
514 
515   void addRegOperands(MCInst &Inst, unsigned N) const {
516     llvm_unreachable("addRegOperands");
517   }
518 
519   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
520     assert(N == 1 && "Invalid number of operands!");
521     Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
522   }
523 
524   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
525     assert(N == 1 && "Invalid number of operands!");
526     Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
527   }
528 
529   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
530     assert(N == 1 && "Invalid number of operands!");
531     Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
532   }
533 
534   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
535     assert(N == 1 && "Invalid number of operands!");
536     Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
537   }
538 
539   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
540     if (isPPC64())
541       addRegG8RCOperands(Inst, N);
542     else
543       addRegGPRCOperands(Inst, N);
544   }
545 
546   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
547     if (isPPC64())
548       addRegG8RCNoX0Operands(Inst, N);
549     else
550       addRegGPRCNoR0Operands(Inst, N);
551   }
552 
553   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
554     assert(N == 1 && "Invalid number of operands!");
555     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
556   }
557 
558   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
559     assert(N == 1 && "Invalid number of operands!");
560     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
561   }
562 
563   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
564     assert(N == 1 && "Invalid number of operands!");
565     Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
566   }
567 
568   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
569     assert(N == 1 && "Invalid number of operands!");
570     Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
571   }
572 
573   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
574     assert(N == 1 && "Invalid number of operands!");
575     Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
576   }
577 
578   void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
579     assert(N == 1 && "Invalid number of operands!");
580     Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
581   }
582 
583   void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
584     assert(N == 1 && "Invalid number of operands!");
585     Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
586   }
587 
588   void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
589     assert(N == 1 && "Invalid number of operands!");
590     Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
591   }
592 
593   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
594     assert(N == 1 && "Invalid number of operands!");
595     Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
596   }
597 
598   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
599     assert(N == 1 && "Invalid number of operands!");
600     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
601   }
602 
603   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
604     assert(N == 1 && "Invalid number of operands!");
605     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
606   }
607 
608   void addImmOperands(MCInst &Inst, unsigned N) const {
609     assert(N == 1 && "Invalid number of operands!");
610     if (Kind == Immediate)
611       Inst.addOperand(MCOperand::CreateImm(getImm()));
612     else
613       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
614   }
615 
616   void addS16ImmOperands(MCInst &Inst, unsigned N) const {
617     assert(N == 1 && "Invalid number of operands!");
618     switch (Kind) {
619       case Immediate:
620         Inst.addOperand(MCOperand::CreateImm(getImm()));
621         break;
622       case ContextImmediate:
623         Inst.addOperand(MCOperand::CreateImm(getImmS16Context()));
624         break;
625       default:
626         Inst.addOperand(MCOperand::CreateExpr(getExpr()));
627         break;
628     }
629   }
630 
631   void addU16ImmOperands(MCInst &Inst, unsigned N) const {
632     assert(N == 1 && "Invalid number of operands!");
633     switch (Kind) {
634       case Immediate:
635         Inst.addOperand(MCOperand::CreateImm(getImm()));
636         break;
637       case ContextImmediate:
638         Inst.addOperand(MCOperand::CreateImm(getImmU16Context()));
639         break;
640       default:
641         Inst.addOperand(MCOperand::CreateExpr(getExpr()));
642         break;
643     }
644   }
645 
646   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
647     assert(N == 1 && "Invalid number of operands!");
648     if (Kind == Immediate)
649       Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
650     else
651       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
652   }
653 
654   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
655     assert(N == 1 && "Invalid number of operands!");
656     Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
657   }
658 
659   StringRef getToken() const {
660     assert(Kind == Token && "Invalid access!");
661     return StringRef(Tok.Data, Tok.Length);
662   }
663 
664   void print(raw_ostream &OS) const override;
665 
666   static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
667                                                  bool IsPPC64) {
668     auto Op = make_unique<PPCOperand>(Token);
669     Op->Tok.Data = Str.data();
670     Op->Tok.Length = Str.size();
671     Op->StartLoc = S;
672     Op->EndLoc = S;
673     Op->IsPPC64 = IsPPC64;
674     return Op;
675   }
676 
677   static std::unique_ptr<PPCOperand>
678   CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
679     // Allocate extra memory for the string and copy it.
680     // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
681     // deleter which will destroy them by simply using "delete", not correctly
682     // calling operator delete on this extra memory after calling the dtor
683     // explicitly.
684     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
685     std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
686     Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
687     Op->Tok.Length = Str.size();
688     std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
689     Op->StartLoc = S;
690     Op->EndLoc = S;
691     Op->IsPPC64 = IsPPC64;
692     return Op;
693   }
694 
695   static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
696                                                bool IsPPC64) {
697     auto Op = make_unique<PPCOperand>(Immediate);
698     Op->Imm.Val = Val;
699     Op->StartLoc = S;
700     Op->EndLoc = E;
701     Op->IsPPC64 = IsPPC64;
702     return Op;
703   }
704 
705   static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
706                                                 SMLoc E, bool IsPPC64) {
707     auto Op = make_unique<PPCOperand>(Expression);
708     Op->Expr.Val = Val;
709     Op->Expr.CRVal = EvaluateCRExpr(Val);
710     Op->StartLoc = S;
711     Op->EndLoc = E;
712     Op->IsPPC64 = IsPPC64;
713     return Op;
714   }
715 
716   static std::unique_ptr<PPCOperand>
717   CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
718     auto Op = make_unique<PPCOperand>(TLSRegister);
719     Op->TLSReg.Sym = Sym;
720     Op->StartLoc = S;
721     Op->EndLoc = E;
722     Op->IsPPC64 = IsPPC64;
723     return Op;
724   }
725 
726   static std::unique_ptr<PPCOperand>
727   CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
728     auto Op = make_unique<PPCOperand>(ContextImmediate);
729     Op->Imm.Val = Val;
730     Op->StartLoc = S;
731     Op->EndLoc = E;
732     Op->IsPPC64 = IsPPC64;
733     return Op;
734   }
735 
736   static std::unique_ptr<PPCOperand>
737   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
738     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
739       return CreateImm(CE->getValue(), S, E, IsPPC64);
740 
741     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
742       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
743         return CreateTLSReg(SRE, S, E, IsPPC64);
744 
745     if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
746       int64_t Res;
747       if (TE->EvaluateAsConstant(Res))
748         return CreateContextImm(Res, S, E, IsPPC64);
749     }
750 
751     return CreateExpr(Val, S, E, IsPPC64);
752   }
753 };
754 
755 } // end anonymous namespace.
756 
757 void PPCOperand::print(raw_ostream &OS) const {
758   switch (Kind) {
759   case Token:
760     OS << "'" << getToken() << "'";
761     break;
762   case Immediate:
763   case ContextImmediate:
764     OS << getImm();
765     break;
766   case Expression:
767     getExpr()->print(OS);
768     break;
769   case TLSRegister:
770     getTLSReg()->print(OS);
771     break;
772   }
773 }
774 
775 static void
776 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
777   if (Op.isImm()) {
778     Inst.addOperand(MCOperand::CreateImm(-Op.getImm()));
779     return;
780   }
781   const MCExpr *Expr = Op.getExpr();
782   if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
783     if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
784       Inst.addOperand(MCOperand::CreateExpr(UnExpr->getSubExpr()));
785       return;
786     }
787   } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
788     if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
789       const MCExpr *NE = MCBinaryExpr::CreateSub(BinExpr->getRHS(),
790                                                  BinExpr->getLHS(), Ctx);
791       Inst.addOperand(MCOperand::CreateExpr(NE));
792       return;
793     }
794   }
795   Inst.addOperand(MCOperand::CreateExpr(MCUnaryExpr::CreateMinus(Expr, Ctx)));
796 }
797 
798 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
799                                       const OperandVector &Operands) {
800   int Opcode = Inst.getOpcode();
801   switch (Opcode) {
802   case PPC::LAx: {
803     MCInst TmpInst;
804     TmpInst.setOpcode(PPC::LA);
805     TmpInst.addOperand(Inst.getOperand(0));
806     TmpInst.addOperand(Inst.getOperand(2));
807     TmpInst.addOperand(Inst.getOperand(1));
808     Inst = TmpInst;
809     break;
810   }
811   case PPC::SUBI: {
812     MCInst TmpInst;
813     TmpInst.setOpcode(PPC::ADDI);
814     TmpInst.addOperand(Inst.getOperand(0));
815     TmpInst.addOperand(Inst.getOperand(1));
816     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
817     Inst = TmpInst;
818     break;
819   }
820   case PPC::SUBIS: {
821     MCInst TmpInst;
822     TmpInst.setOpcode(PPC::ADDIS);
823     TmpInst.addOperand(Inst.getOperand(0));
824     TmpInst.addOperand(Inst.getOperand(1));
825     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
826     Inst = TmpInst;
827     break;
828   }
829   case PPC::SUBIC: {
830     MCInst TmpInst;
831     TmpInst.setOpcode(PPC::ADDIC);
832     TmpInst.addOperand(Inst.getOperand(0));
833     TmpInst.addOperand(Inst.getOperand(1));
834     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
835     Inst = TmpInst;
836     break;
837   }
838   case PPC::SUBICo: {
839     MCInst TmpInst;
840     TmpInst.setOpcode(PPC::ADDICo);
841     TmpInst.addOperand(Inst.getOperand(0));
842     TmpInst.addOperand(Inst.getOperand(1));
843     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
844     Inst = TmpInst;
845     break;
846   }
847   case PPC::EXTLWI:
848   case PPC::EXTLWIo: {
849     MCInst TmpInst;
850     int64_t N = Inst.getOperand(2).getImm();
851     int64_t B = Inst.getOperand(3).getImm();
852     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
853     TmpInst.addOperand(Inst.getOperand(0));
854     TmpInst.addOperand(Inst.getOperand(1));
855     TmpInst.addOperand(MCOperand::CreateImm(B));
856     TmpInst.addOperand(MCOperand::CreateImm(0));
857     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
858     Inst = TmpInst;
859     break;
860   }
861   case PPC::EXTRWI:
862   case PPC::EXTRWIo: {
863     MCInst TmpInst;
864     int64_t N = Inst.getOperand(2).getImm();
865     int64_t B = Inst.getOperand(3).getImm();
866     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
867     TmpInst.addOperand(Inst.getOperand(0));
868     TmpInst.addOperand(Inst.getOperand(1));
869     TmpInst.addOperand(MCOperand::CreateImm(B + N));
870     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
871     TmpInst.addOperand(MCOperand::CreateImm(31));
872     Inst = TmpInst;
873     break;
874   }
875   case PPC::INSLWI:
876   case PPC::INSLWIo: {
877     MCInst TmpInst;
878     int64_t N = Inst.getOperand(2).getImm();
879     int64_t B = Inst.getOperand(3).getImm();
880     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
881     TmpInst.addOperand(Inst.getOperand(0));
882     TmpInst.addOperand(Inst.getOperand(0));
883     TmpInst.addOperand(Inst.getOperand(1));
884     TmpInst.addOperand(MCOperand::CreateImm(32 - B));
885     TmpInst.addOperand(MCOperand::CreateImm(B));
886     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
887     Inst = TmpInst;
888     break;
889   }
890   case PPC::INSRWI:
891   case PPC::INSRWIo: {
892     MCInst TmpInst;
893     int64_t N = Inst.getOperand(2).getImm();
894     int64_t B = Inst.getOperand(3).getImm();
895     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
896     TmpInst.addOperand(Inst.getOperand(0));
897     TmpInst.addOperand(Inst.getOperand(0));
898     TmpInst.addOperand(Inst.getOperand(1));
899     TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
900     TmpInst.addOperand(MCOperand::CreateImm(B));
901     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
902     Inst = TmpInst;
903     break;
904   }
905   case PPC::ROTRWI:
906   case PPC::ROTRWIo: {
907     MCInst TmpInst;
908     int64_t N = Inst.getOperand(2).getImm();
909     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
910     TmpInst.addOperand(Inst.getOperand(0));
911     TmpInst.addOperand(Inst.getOperand(1));
912     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
913     TmpInst.addOperand(MCOperand::CreateImm(0));
914     TmpInst.addOperand(MCOperand::CreateImm(31));
915     Inst = TmpInst;
916     break;
917   }
918   case PPC::SLWI:
919   case PPC::SLWIo: {
920     MCInst TmpInst;
921     int64_t N = Inst.getOperand(2).getImm();
922     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
923     TmpInst.addOperand(Inst.getOperand(0));
924     TmpInst.addOperand(Inst.getOperand(1));
925     TmpInst.addOperand(MCOperand::CreateImm(N));
926     TmpInst.addOperand(MCOperand::CreateImm(0));
927     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
928     Inst = TmpInst;
929     break;
930   }
931   case PPC::SRWI:
932   case PPC::SRWIo: {
933     MCInst TmpInst;
934     int64_t N = Inst.getOperand(2).getImm();
935     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
936     TmpInst.addOperand(Inst.getOperand(0));
937     TmpInst.addOperand(Inst.getOperand(1));
938     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
939     TmpInst.addOperand(MCOperand::CreateImm(N));
940     TmpInst.addOperand(MCOperand::CreateImm(31));
941     Inst = TmpInst;
942     break;
943   }
944   case PPC::CLRRWI:
945   case PPC::CLRRWIo: {
946     MCInst TmpInst;
947     int64_t N = Inst.getOperand(2).getImm();
948     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
949     TmpInst.addOperand(Inst.getOperand(0));
950     TmpInst.addOperand(Inst.getOperand(1));
951     TmpInst.addOperand(MCOperand::CreateImm(0));
952     TmpInst.addOperand(MCOperand::CreateImm(0));
953     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
954     Inst = TmpInst;
955     break;
956   }
957   case PPC::CLRLSLWI:
958   case PPC::CLRLSLWIo: {
959     MCInst TmpInst;
960     int64_t B = Inst.getOperand(2).getImm();
961     int64_t N = Inst.getOperand(3).getImm();
962     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
963     TmpInst.addOperand(Inst.getOperand(0));
964     TmpInst.addOperand(Inst.getOperand(1));
965     TmpInst.addOperand(MCOperand::CreateImm(N));
966     TmpInst.addOperand(MCOperand::CreateImm(B - N));
967     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
968     Inst = TmpInst;
969     break;
970   }
971   case PPC::EXTLDI:
972   case PPC::EXTLDIo: {
973     MCInst TmpInst;
974     int64_t N = Inst.getOperand(2).getImm();
975     int64_t B = Inst.getOperand(3).getImm();
976     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
977     TmpInst.addOperand(Inst.getOperand(0));
978     TmpInst.addOperand(Inst.getOperand(1));
979     TmpInst.addOperand(MCOperand::CreateImm(B));
980     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
981     Inst = TmpInst;
982     break;
983   }
984   case PPC::EXTRDI:
985   case PPC::EXTRDIo: {
986     MCInst TmpInst;
987     int64_t N = Inst.getOperand(2).getImm();
988     int64_t B = Inst.getOperand(3).getImm();
989     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
990     TmpInst.addOperand(Inst.getOperand(0));
991     TmpInst.addOperand(Inst.getOperand(1));
992     TmpInst.addOperand(MCOperand::CreateImm(B + N));
993     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
994     Inst = TmpInst;
995     break;
996   }
997   case PPC::INSRDI:
998   case PPC::INSRDIo: {
999     MCInst TmpInst;
1000     int64_t N = Inst.getOperand(2).getImm();
1001     int64_t B = Inst.getOperand(3).getImm();
1002     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1003     TmpInst.addOperand(Inst.getOperand(0));
1004     TmpInst.addOperand(Inst.getOperand(0));
1005     TmpInst.addOperand(Inst.getOperand(1));
1006     TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
1007     TmpInst.addOperand(MCOperand::CreateImm(B));
1008     Inst = TmpInst;
1009     break;
1010   }
1011   case PPC::ROTRDI:
1012   case PPC::ROTRDIo: {
1013     MCInst TmpInst;
1014     int64_t N = Inst.getOperand(2).getImm();
1015     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1016     TmpInst.addOperand(Inst.getOperand(0));
1017     TmpInst.addOperand(Inst.getOperand(1));
1018     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1019     TmpInst.addOperand(MCOperand::CreateImm(0));
1020     Inst = TmpInst;
1021     break;
1022   }
1023   case PPC::SLDI:
1024   case PPC::SLDIo: {
1025     MCInst TmpInst;
1026     int64_t N = Inst.getOperand(2).getImm();
1027     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1028     TmpInst.addOperand(Inst.getOperand(0));
1029     TmpInst.addOperand(Inst.getOperand(1));
1030     TmpInst.addOperand(MCOperand::CreateImm(N));
1031     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1032     Inst = TmpInst;
1033     break;
1034   }
1035   case PPC::SRDI:
1036   case PPC::SRDIo: {
1037     MCInst TmpInst;
1038     int64_t N = Inst.getOperand(2).getImm();
1039     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1040     TmpInst.addOperand(Inst.getOperand(0));
1041     TmpInst.addOperand(Inst.getOperand(1));
1042     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1043     TmpInst.addOperand(MCOperand::CreateImm(N));
1044     Inst = TmpInst;
1045     break;
1046   }
1047   case PPC::CLRRDI:
1048   case PPC::CLRRDIo: {
1049     MCInst TmpInst;
1050     int64_t N = Inst.getOperand(2).getImm();
1051     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1052     TmpInst.addOperand(Inst.getOperand(0));
1053     TmpInst.addOperand(Inst.getOperand(1));
1054     TmpInst.addOperand(MCOperand::CreateImm(0));
1055     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1056     Inst = TmpInst;
1057     break;
1058   }
1059   case PPC::CLRLSLDI:
1060   case PPC::CLRLSLDIo: {
1061     MCInst TmpInst;
1062     int64_t B = Inst.getOperand(2).getImm();
1063     int64_t N = Inst.getOperand(3).getImm();
1064     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1065     TmpInst.addOperand(Inst.getOperand(0));
1066     TmpInst.addOperand(Inst.getOperand(1));
1067     TmpInst.addOperand(MCOperand::CreateImm(N));
1068     TmpInst.addOperand(MCOperand::CreateImm(B - N));
1069     Inst = TmpInst;
1070     break;
1071   }
1072   }
1073 }
1074 
1075 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1076                                            OperandVector &Operands,
1077                                            MCStreamer &Out, uint64_t &ErrorInfo,
1078                                            bool MatchingInlineAsm) {
1079   MCInst Inst;
1080 
1081   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1082   case Match_Success:
1083     // Post-process instructions (typically extended mnemonics)
1084     ProcessInstruction(Inst, Operands);
1085     Inst.setLoc(IDLoc);
1086     Out.EmitInstruction(Inst, STI);
1087     return false;
1088   case Match_MissingFeature:
1089     return Error(IDLoc, "instruction use requires an option to be enabled");
1090   case Match_MnemonicFail:
1091     return Error(IDLoc, "unrecognized instruction mnemonic");
1092   case Match_InvalidOperand: {
1093     SMLoc ErrorLoc = IDLoc;
1094     if (ErrorInfo != ~0ULL) {
1095       if (ErrorInfo >= Operands.size())
1096         return Error(IDLoc, "too few operands for instruction");
1097 
1098       ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1099       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1100     }
1101 
1102     return Error(ErrorLoc, "invalid operand for instruction");
1103   }
1104   }
1105 
1106   llvm_unreachable("Implement any new match types added!");
1107 }
1108 
1109 bool PPCAsmParser::
1110 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1111   if (Tok.is(AsmToken::Identifier)) {
1112     StringRef Name = Tok.getString();
1113 
1114     if (Name.equals_lower("lr")) {
1115       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1116       IntVal = 8;
1117       return false;
1118     } else if (Name.equals_lower("ctr")) {
1119       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1120       IntVal = 9;
1121       return false;
1122     } else if (Name.equals_lower("vrsave")) {
1123       RegNo = PPC::VRSAVE;
1124       IntVal = 256;
1125       return false;
1126     } else if (Name.startswith_lower("r") &&
1127                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1128       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1129       return false;
1130     } else if (Name.startswith_lower("f") &&
1131                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1132       RegNo = FRegs[IntVal];
1133       return false;
1134     } else if (Name.startswith_lower("v") &&
1135                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1136       RegNo = VRegs[IntVal];
1137       return false;
1138     } else if (Name.startswith_lower("cr") &&
1139                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1140       RegNo = CRRegs[IntVal];
1141       return false;
1142     }
1143   }
1144 
1145   return true;
1146 }
1147 
1148 bool PPCAsmParser::
1149 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1150   MCAsmParser &Parser = getParser();
1151   const AsmToken &Tok = Parser.getTok();
1152   StartLoc = Tok.getLoc();
1153   EndLoc = Tok.getEndLoc();
1154   RegNo = 0;
1155   int64_t IntVal;
1156 
1157   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1158     Parser.Lex(); // Eat identifier token.
1159     return false;
1160   }
1161 
1162   return Error(StartLoc, "invalid register name");
1163 }
1164 
1165 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1166 /// the expression and check for VK_PPC_LO/HI/HA
1167 /// symbol variants.  If all symbols with modifier use the same
1168 /// variant, return the corresponding PPCMCExpr::VariantKind,
1169 /// and a modified expression using the default symbol variant.
1170 /// Otherwise, return NULL.
1171 const MCExpr *PPCAsmParser::
1172 ExtractModifierFromExpr(const MCExpr *E,
1173                         PPCMCExpr::VariantKind &Variant) {
1174   MCContext &Context = getParser().getContext();
1175   Variant = PPCMCExpr::VK_PPC_None;
1176 
1177   switch (E->getKind()) {
1178   case MCExpr::Target:
1179   case MCExpr::Constant:
1180     return nullptr;
1181 
1182   case MCExpr::SymbolRef: {
1183     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1184 
1185     switch (SRE->getKind()) {
1186     case MCSymbolRefExpr::VK_PPC_LO:
1187       Variant = PPCMCExpr::VK_PPC_LO;
1188       break;
1189     case MCSymbolRefExpr::VK_PPC_HI:
1190       Variant = PPCMCExpr::VK_PPC_HI;
1191       break;
1192     case MCSymbolRefExpr::VK_PPC_HA:
1193       Variant = PPCMCExpr::VK_PPC_HA;
1194       break;
1195     case MCSymbolRefExpr::VK_PPC_HIGHER:
1196       Variant = PPCMCExpr::VK_PPC_HIGHER;
1197       break;
1198     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1199       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1200       break;
1201     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1202       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1203       break;
1204     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1205       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1206       break;
1207     default:
1208       return nullptr;
1209     }
1210 
1211     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1212   }
1213 
1214   case MCExpr::Unary: {
1215     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1216     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1217     if (!Sub)
1218       return nullptr;
1219     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1220   }
1221 
1222   case MCExpr::Binary: {
1223     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1224     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1225     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1226     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1227 
1228     if (!LHS && !RHS)
1229       return nullptr;
1230 
1231     if (!LHS) LHS = BE->getLHS();
1232     if (!RHS) RHS = BE->getRHS();
1233 
1234     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1235       Variant = RHSVariant;
1236     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1237       Variant = LHSVariant;
1238     else if (LHSVariant == RHSVariant)
1239       Variant = LHSVariant;
1240     else
1241       return nullptr;
1242 
1243     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1244   }
1245   }
1246 
1247   llvm_unreachable("Invalid expression kind!");
1248 }
1249 
1250 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1251 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1252 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1253 /// FIXME: This is a hack.
1254 const MCExpr *PPCAsmParser::
1255 FixupVariantKind(const MCExpr *E) {
1256   MCContext &Context = getParser().getContext();
1257 
1258   switch (E->getKind()) {
1259   case MCExpr::Target:
1260   case MCExpr::Constant:
1261     return E;
1262 
1263   case MCExpr::SymbolRef: {
1264     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1265     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1266 
1267     switch (SRE->getKind()) {
1268     case MCSymbolRefExpr::VK_TLSGD:
1269       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1270       break;
1271     case MCSymbolRefExpr::VK_TLSLD:
1272       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1273       break;
1274     default:
1275       return E;
1276     }
1277     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1278   }
1279 
1280   case MCExpr::Unary: {
1281     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1282     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1283     if (Sub == UE->getSubExpr())
1284       return E;
1285     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1286   }
1287 
1288   case MCExpr::Binary: {
1289     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1290     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1291     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1292     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1293       return E;
1294     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1295   }
1296   }
1297 
1298   llvm_unreachable("Invalid expression kind!");
1299 }
1300 
1301 /// ParseExpression.  This differs from the default "parseExpression" in that
1302 /// it handles modifiers.
1303 bool PPCAsmParser::
1304 ParseExpression(const MCExpr *&EVal) {
1305 
1306   if (isDarwin())
1307     return ParseDarwinExpression(EVal);
1308 
1309   // (ELF Platforms)
1310   // Handle \code @l/@ha \endcode
1311   if (getParser().parseExpression(EVal))
1312     return true;
1313 
1314   EVal = FixupVariantKind(EVal);
1315 
1316   PPCMCExpr::VariantKind Variant;
1317   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1318   if (E)
1319     EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1320 
1321   return false;
1322 }
1323 
1324 /// ParseDarwinExpression.  (MachO Platforms)
1325 /// This differs from the default "parseExpression" in that it handles detection
1326 /// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1327 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1328 /// syntax form so it is done here.  TODO: Determine if there is merit in arranging
1329 /// for this to be done at a higher level.
1330 bool PPCAsmParser::
1331 ParseDarwinExpression(const MCExpr *&EVal) {
1332   MCAsmParser &Parser = getParser();
1333   PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1334   switch (getLexer().getKind()) {
1335   default:
1336     break;
1337   case AsmToken::Identifier:
1338     // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1339     // something starting with any other char should be part of the
1340     // asm syntax.  If handwritten asm includes an identifier like lo16,
1341     // then all bets are off - but no-one would do that, right?
1342     StringRef poss = Parser.getTok().getString();
1343     if (poss.equals_lower("lo16")) {
1344       Variant = PPCMCExpr::VK_PPC_LO;
1345     } else if (poss.equals_lower("hi16")) {
1346       Variant = PPCMCExpr::VK_PPC_HI;
1347     } else if (poss.equals_lower("ha16")) {
1348       Variant = PPCMCExpr::VK_PPC_HA;
1349     }
1350     if (Variant != PPCMCExpr::VK_PPC_None) {
1351       Parser.Lex(); // Eat the xx16
1352       if (getLexer().isNot(AsmToken::LParen))
1353         return Error(Parser.getTok().getLoc(), "expected '('");
1354       Parser.Lex(); // Eat the '('
1355     }
1356     break;
1357   }
1358 
1359   if (getParser().parseExpression(EVal))
1360     return true;
1361 
1362   if (Variant != PPCMCExpr::VK_PPC_None) {
1363     if (getLexer().isNot(AsmToken::RParen))
1364       return Error(Parser.getTok().getLoc(), "expected ')'");
1365     Parser.Lex(); // Eat the ')'
1366     EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1367   }
1368   return false;
1369 }
1370 
1371 /// ParseOperand
1372 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1373 /// rNN for MachO.
1374 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1375   MCAsmParser &Parser = getParser();
1376   SMLoc S = Parser.getTok().getLoc();
1377   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1378   const MCExpr *EVal;
1379 
1380   // Attempt to parse the next token as an immediate
1381   switch (getLexer().getKind()) {
1382   // Special handling for register names.  These are interpreted
1383   // as immediates corresponding to the register number.
1384   case AsmToken::Percent:
1385     Parser.Lex(); // Eat the '%'.
1386     unsigned RegNo;
1387     int64_t IntVal;
1388     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1389       Parser.Lex(); // Eat the identifier token.
1390       Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1391       return false;
1392     }
1393     return Error(S, "invalid register name");
1394 
1395   case AsmToken::Identifier:
1396     // Note that non-register-name identifiers from the compiler will begin
1397     // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1398     // identifiers like r31foo - so we fall through in the event that parsing
1399     // a register name fails.
1400     if (isDarwin()) {
1401       unsigned RegNo;
1402       int64_t IntVal;
1403       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1404         Parser.Lex(); // Eat the identifier token.
1405         Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1406         return false;
1407       }
1408     }
1409   // Fall-through to process non-register-name identifiers as expression.
1410   // All other expressions
1411   case AsmToken::LParen:
1412   case AsmToken::Plus:
1413   case AsmToken::Minus:
1414   case AsmToken::Integer:
1415   case AsmToken::Dot:
1416   case AsmToken::Dollar:
1417   case AsmToken::Exclaim:
1418   case AsmToken::Tilde:
1419     if (!ParseExpression(EVal))
1420       break;
1421     /* fall through */
1422   default:
1423     return Error(S, "unknown operand");
1424   }
1425 
1426   // Push the parsed operand into the list of operands
1427   Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1428 
1429   // Check whether this is a TLS call expression
1430   bool TLSCall = false;
1431   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1432     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1433 
1434   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1435     const MCExpr *TLSSym;
1436 
1437     Parser.Lex(); // Eat the '('.
1438     S = Parser.getTok().getLoc();
1439     if (ParseExpression(TLSSym))
1440       return Error(S, "invalid TLS call expression");
1441     if (getLexer().isNot(AsmToken::RParen))
1442       return Error(Parser.getTok().getLoc(), "missing ')'");
1443     E = Parser.getTok().getLoc();
1444     Parser.Lex(); // Eat the ')'.
1445 
1446     Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1447   }
1448 
1449   // Otherwise, check for D-form memory operands
1450   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1451     Parser.Lex(); // Eat the '('.
1452     S = Parser.getTok().getLoc();
1453 
1454     int64_t IntVal;
1455     switch (getLexer().getKind()) {
1456     case AsmToken::Percent:
1457       Parser.Lex(); // Eat the '%'.
1458       unsigned RegNo;
1459       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1460         return Error(S, "invalid register name");
1461       Parser.Lex(); // Eat the identifier token.
1462       break;
1463 
1464     case AsmToken::Integer:
1465       if (!isDarwin()) {
1466         if (getParser().parseAbsoluteExpression(IntVal) ||
1467           IntVal < 0 || IntVal > 31)
1468         return Error(S, "invalid register number");
1469       } else {
1470         return Error(S, "unexpected integer value");
1471       }
1472       break;
1473 
1474    case AsmToken::Identifier:
1475     if (isDarwin()) {
1476       unsigned RegNo;
1477       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1478         Parser.Lex(); // Eat the identifier token.
1479         break;
1480       }
1481     }
1482     // Fall-through..
1483 
1484     default:
1485       return Error(S, "invalid memory operand");
1486     }
1487 
1488     if (getLexer().isNot(AsmToken::RParen))
1489       return Error(Parser.getTok().getLoc(), "missing ')'");
1490     E = Parser.getTok().getLoc();
1491     Parser.Lex(); // Eat the ')'.
1492 
1493     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1494   }
1495 
1496   return false;
1497 }
1498 
1499 /// Parse an instruction mnemonic followed by its operands.
1500 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1501                                     SMLoc NameLoc, OperandVector &Operands) {
1502   // The first operand is the token for the instruction name.
1503   // If the next character is a '+' or '-', we need to add it to the
1504   // instruction name, to match what TableGen is doing.
1505   std::string NewOpcode;
1506   if (getLexer().is(AsmToken::Plus)) {
1507     getLexer().Lex();
1508     NewOpcode = Name;
1509     NewOpcode += '+';
1510     Name = NewOpcode;
1511   }
1512   if (getLexer().is(AsmToken::Minus)) {
1513     getLexer().Lex();
1514     NewOpcode = Name;
1515     NewOpcode += '-';
1516     Name = NewOpcode;
1517   }
1518   // If the instruction ends in a '.', we need to create a separate
1519   // token for it, to match what TableGen is doing.
1520   size_t Dot = Name.find('.');
1521   StringRef Mnemonic = Name.slice(0, Dot);
1522   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1523     Operands.push_back(
1524         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1525   else
1526     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1527   if (Dot != StringRef::npos) {
1528     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1529     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1530     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1531       Operands.push_back(
1532           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1533     else
1534       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1535   }
1536 
1537   // If there are no more operands then finish
1538   if (getLexer().is(AsmToken::EndOfStatement))
1539     return false;
1540 
1541   // Parse the first operand
1542   if (ParseOperand(Operands))
1543     return true;
1544 
1545   while (getLexer().isNot(AsmToken::EndOfStatement) &&
1546          getLexer().is(AsmToken::Comma)) {
1547     // Consume the comma token
1548     getLexer().Lex();
1549 
1550     // Parse the next operand
1551     if (ParseOperand(Operands))
1552       return true;
1553   }
1554 
1555   return false;
1556 }
1557 
1558 /// ParseDirective parses the PPC specific directives
1559 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1560   StringRef IDVal = DirectiveID.getIdentifier();
1561   if (!isDarwin()) {
1562     if (IDVal == ".word")
1563       return ParseDirectiveWord(2, DirectiveID.getLoc());
1564     if (IDVal == ".llong")
1565       return ParseDirectiveWord(8, DirectiveID.getLoc());
1566     if (IDVal == ".tc")
1567       return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1568     if (IDVal == ".machine")
1569       return ParseDirectiveMachine(DirectiveID.getLoc());
1570     if (IDVal == ".abiversion")
1571       return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1572     if (IDVal == ".localentry")
1573       return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1574   } else {
1575     if (IDVal == ".machine")
1576       return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1577   }
1578   return true;
1579 }
1580 
1581 /// ParseDirectiveWord
1582 ///  ::= .word [ expression (, expression)* ]
1583 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1584   MCAsmParser &Parser = getParser();
1585   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1586     for (;;) {
1587       const MCExpr *Value;
1588       if (getParser().parseExpression(Value))
1589         return false;
1590 
1591       getParser().getStreamer().EmitValue(Value, Size);
1592 
1593       if (getLexer().is(AsmToken::EndOfStatement))
1594         break;
1595 
1596       if (getLexer().isNot(AsmToken::Comma))
1597         return Error(L, "unexpected token in directive");
1598       Parser.Lex();
1599     }
1600   }
1601 
1602   Parser.Lex();
1603   return false;
1604 }
1605 
1606 /// ParseDirectiveTC
1607 ///  ::= .tc [ symbol (, expression)* ]
1608 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1609   MCAsmParser &Parser = getParser();
1610   // Skip TC symbol, which is only used with XCOFF.
1611   while (getLexer().isNot(AsmToken::EndOfStatement)
1612          && getLexer().isNot(AsmToken::Comma))
1613     Parser.Lex();
1614   if (getLexer().isNot(AsmToken::Comma)) {
1615     Error(L, "unexpected token in directive");
1616     return false;
1617   }
1618   Parser.Lex();
1619 
1620   // Align to word size.
1621   getParser().getStreamer().EmitValueToAlignment(Size);
1622 
1623   // Emit expressions.
1624   return ParseDirectiveWord(Size, L);
1625 }
1626 
1627 /// ParseDirectiveMachine (ELF platforms)
1628 ///  ::= .machine [ cpu | "push" | "pop" ]
1629 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1630   MCAsmParser &Parser = getParser();
1631   if (getLexer().isNot(AsmToken::Identifier) &&
1632       getLexer().isNot(AsmToken::String)) {
1633     Error(L, "unexpected token in directive");
1634     return false;
1635   }
1636 
1637   StringRef CPU = Parser.getTok().getIdentifier();
1638   Parser.Lex();
1639 
1640   // FIXME: Right now, the parser always allows any available
1641   // instruction, so the .machine directive is not useful.
1642   // Implement ".machine any" (by doing nothing) for the benefit
1643   // of existing assembler code.  Likewise, we can then implement
1644   // ".machine push" and ".machine pop" as no-op.
1645   if (CPU != "any" && CPU != "push" && CPU != "pop") {
1646     Error(L, "unrecognized machine type");
1647     return false;
1648   }
1649 
1650   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1651     Error(L, "unexpected token in directive");
1652     return false;
1653   }
1654   PPCTargetStreamer &TStreamer =
1655       *static_cast<PPCTargetStreamer *>(
1656            getParser().getStreamer().getTargetStreamer());
1657   TStreamer.emitMachine(CPU);
1658 
1659   return false;
1660 }
1661 
1662 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1663 ///  ::= .machine cpu-identifier
1664 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1665   MCAsmParser &Parser = getParser();
1666   if (getLexer().isNot(AsmToken::Identifier) &&
1667       getLexer().isNot(AsmToken::String)) {
1668     Error(L, "unexpected token in directive");
1669     return false;
1670   }
1671 
1672   StringRef CPU = Parser.getTok().getIdentifier();
1673   Parser.Lex();
1674 
1675   // FIXME: this is only the 'default' set of cpu variants.
1676   // However we don't act on this information at present, this is simply
1677   // allowing parsing to proceed with minimal sanity checking.
1678   if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1679     Error(L, "unrecognized cpu type");
1680     return false;
1681   }
1682 
1683   if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1684     Error(L, "wrong cpu type specified for 64bit");
1685     return false;
1686   }
1687   if (!isPPC64() && CPU == "ppc64") {
1688     Error(L, "wrong cpu type specified for 32bit");
1689     return false;
1690   }
1691 
1692   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1693     Error(L, "unexpected token in directive");
1694     return false;
1695   }
1696 
1697   return false;
1698 }
1699 
1700 /// ParseDirectiveAbiVersion
1701 ///  ::= .abiversion constant-expression
1702 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1703   int64_t AbiVersion;
1704   if (getParser().parseAbsoluteExpression(AbiVersion)){
1705     Error(L, "expected constant expression");
1706     return false;
1707   }
1708   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1709     Error(L, "unexpected token in directive");
1710     return false;
1711   }
1712 
1713   PPCTargetStreamer &TStreamer =
1714       *static_cast<PPCTargetStreamer *>(
1715            getParser().getStreamer().getTargetStreamer());
1716   TStreamer.emitAbiVersion(AbiVersion);
1717 
1718   return false;
1719 }
1720 
1721 /// ParseDirectiveLocalEntry
1722 ///  ::= .localentry symbol, expression
1723 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1724   StringRef Name;
1725   if (getParser().parseIdentifier(Name)) {
1726     Error(L, "expected identifier in directive");
1727     return false;
1728   }
1729   MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
1730 
1731   if (getLexer().isNot(AsmToken::Comma)) {
1732     Error(L, "unexpected token in directive");
1733     return false;
1734   }
1735   Lex();
1736 
1737   const MCExpr *Expr;
1738   if (getParser().parseExpression(Expr)) {
1739     Error(L, "expected expression");
1740     return false;
1741   }
1742 
1743   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1744     Error(L, "unexpected token in directive");
1745     return false;
1746   }
1747 
1748   PPCTargetStreamer &TStreamer =
1749       *static_cast<PPCTargetStreamer *>(
1750            getParser().getStreamer().getTargetStreamer());
1751   TStreamer.emitLocalEntry(Sym, Expr);
1752 
1753   return false;
1754 }
1755 
1756 
1757 
1758 /// Force static initialization.
1759 extern "C" void LLVMInitializePowerPCAsmParser() {
1760   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1761   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1762   RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1763 }
1764 
1765 #define GET_REGISTER_MATCHER
1766 #define GET_MATCHER_IMPLEMENTATION
1767 #include "PPCGenAsmMatcher.inc"
1768 
1769 // Define this matcher function after the auto-generated include so we
1770 // have the match class enum definitions.
1771 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1772                                                   unsigned Kind) {
1773   // If the kind is a token for a literal immediate, check if our asm
1774   // operand matches. This is for InstAliases which have a fixed-value
1775   // immediate in the syntax.
1776   int64_t ImmVal;
1777   switch (Kind) {
1778     case MCK_0: ImmVal = 0; break;
1779     case MCK_1: ImmVal = 1; break;
1780     case MCK_2: ImmVal = 2; break;
1781     case MCK_3: ImmVal = 3; break;
1782     case MCK_4: ImmVal = 4; break;
1783     case MCK_5: ImmVal = 5; break;
1784     case MCK_6: ImmVal = 6; break;
1785     case MCK_7: ImmVal = 7; break;
1786     default: return Match_InvalidOperand;
1787   }
1788 
1789   PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1790   if (Op.isImm() && Op.getImm() == ImmVal)
1791     return Match_Success;
1792 
1793   return Match_InvalidOperand;
1794 }
1795 
1796 const MCExpr *
1797 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1798                                   MCSymbolRefExpr::VariantKind Variant,
1799                                   MCContext &Ctx) {
1800   switch (Variant) {
1801   case MCSymbolRefExpr::VK_PPC_LO:
1802     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1803   case MCSymbolRefExpr::VK_PPC_HI:
1804     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1805   case MCSymbolRefExpr::VK_PPC_HA:
1806     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1807   case MCSymbolRefExpr::VK_PPC_HIGHER:
1808     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1809   case MCSymbolRefExpr::VK_PPC_HIGHERA:
1810     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1811   case MCSymbolRefExpr::VK_PPC_HIGHEST:
1812     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1813   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1814     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1815   default:
1816     return nullptr;
1817   }
1818 }
1819