xref: /llvm-project/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (revision c2a2830e94720fdccc3b94e03e28962889cd312b) 
1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCExpr.h"
11 #include "MCTargetDesc/PPCMCTargetDesc.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/MC/MCSymbolELF.h"
30 #include "llvm/Support/SourceMgr.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Support/raw_ostream.h"
33 
34 using namespace llvm;
35 
36 static const MCPhysReg RRegs[32] = {
37   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
38   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
39   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
40   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
41   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
42   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
43   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
44   PPC::R28, PPC::R29, PPC::R30, PPC::R31
45 };
46 static const MCPhysReg RRegsNoR0[32] = {
47   PPC::ZERO,
48             PPC::R1,  PPC::R2,  PPC::R3,
49   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
50   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
51   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
52   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
53   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
54   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
55   PPC::R28, PPC::R29, PPC::R30, PPC::R31
56 };
57 static const MCPhysReg XRegs[32] = {
58   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
59   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
60   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
61   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
62   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
63   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
64   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
65   PPC::X28, PPC::X29, PPC::X30, PPC::X31
66 };
67 static const MCPhysReg XRegsNoX0[32] = {
68   PPC::ZERO8,
69             PPC::X1,  PPC::X2,  PPC::X3,
70   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
71   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
72   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
73   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
74   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
75   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
76   PPC::X28, PPC::X29, PPC::X30, PPC::X31
77 };
78 static const MCPhysReg FRegs[32] = {
79   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
80   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
81   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
82   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
83   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
84   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
85   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
86   PPC::F28, PPC::F29, PPC::F30, PPC::F31
87 };
88 static const MCPhysReg VRegs[32] = {
89   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
90   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
91   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
92   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
93   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
94   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
95   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
96   PPC::V28, PPC::V29, PPC::V30, PPC::V31
97 };
98 static const MCPhysReg VSRegs[64] = {
99   PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
100   PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
101   PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
102   PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
103   PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
104   PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
105   PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
106   PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
107 
108   PPC::VSH0,  PPC::VSH1,  PPC::VSH2,  PPC::VSH3,
109   PPC::VSH4,  PPC::VSH5,  PPC::VSH6,  PPC::VSH7,
110   PPC::VSH8,  PPC::VSH9,  PPC::VSH10, PPC::VSH11,
111   PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
112   PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
113   PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
114   PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
115   PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
116 };
117 static const MCPhysReg VSFRegs[64] = {
118   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
119   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
120   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
121   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
122   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
123   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
124   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
125   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
126 
127   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
128   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
129   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
130   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
131   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
132   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
133   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
134   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
135 };
136 static const MCPhysReg VSSRegs[64] = {
137   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
138   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
139   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
140   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
141   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
142   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
143   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
144   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
145 
146   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
147   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
148   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
149   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
150   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
151   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
152   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
153   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
154 };
155 static unsigned QFRegs[32] = {
156   PPC::QF0,  PPC::QF1,  PPC::QF2,  PPC::QF3,
157   PPC::QF4,  PPC::QF5,  PPC::QF6,  PPC::QF7,
158   PPC::QF8,  PPC::QF9,  PPC::QF10, PPC::QF11,
159   PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
160   PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
161   PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
162   PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
163   PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
164 };
165 static const MCPhysReg CRBITRegs[32] = {
166   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
167   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
168   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
169   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
170   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
171   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
172   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
173   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
174 };
175 static const MCPhysReg CRRegs[8] = {
176   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
177   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
178 };
179 
180 // Evaluate an expression containing condition register
181 // or condition register field symbols.  Returns positive
182 // value on success, or -1 on error.
183 static int64_t
184 EvaluateCRExpr(const MCExpr *E) {
185   switch (E->getKind()) {
186   case MCExpr::Target:
187     return -1;
188 
189   case MCExpr::Constant: {
190     int64_t Res = cast<MCConstantExpr>(E)->getValue();
191     return Res < 0 ? -1 : Res;
192   }
193 
194   case MCExpr::SymbolRef: {
195     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
196     StringRef Name = SRE->getSymbol().getName();
197 
198     if (Name == "lt") return 0;
199     if (Name == "gt") return 1;
200     if (Name == "eq") return 2;
201     if (Name == "so") return 3;
202     if (Name == "un") return 3;
203 
204     if (Name == "cr0") return 0;
205     if (Name == "cr1") return 1;
206     if (Name == "cr2") return 2;
207     if (Name == "cr3") return 3;
208     if (Name == "cr4") return 4;
209     if (Name == "cr5") return 5;
210     if (Name == "cr6") return 6;
211     if (Name == "cr7") return 7;
212 
213     return -1;
214   }
215 
216   case MCExpr::Unary:
217     return -1;
218 
219   case MCExpr::Binary: {
220     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
221     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
222     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
223     int64_t Res;
224 
225     if (LHSVal < 0 || RHSVal < 0)
226       return -1;
227 
228     switch (BE->getOpcode()) {
229     default: return -1;
230     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
231     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
232     }
233 
234     return Res < 0 ? -1 : Res;
235   }
236   }
237 
238   llvm_unreachable("Invalid expression kind!");
239 }
240 
241 namespace {
242 
243 struct PPCOperand;
244 
245 class PPCAsmParser : public MCTargetAsmParser {
246   const MCInstrInfo &MII;
247   bool IsPPC64;
248   bool IsDarwin;
249 
250   void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
251   bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
252 
253   bool isPPC64() const { return IsPPC64; }
254   bool isDarwin() const { return IsDarwin; }
255 
256   bool MatchRegisterName(const AsmToken &Tok,
257                          unsigned &RegNo, int64_t &IntVal);
258 
259   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
260 
261   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
262                                         PPCMCExpr::VariantKind &Variant);
263   const MCExpr *FixupVariantKind(const MCExpr *E);
264   bool ParseExpression(const MCExpr *&EVal);
265   bool ParseDarwinExpression(const MCExpr *&EVal);
266 
267   bool ParseOperand(OperandVector &Operands);
268 
269   bool ParseDirectiveWord(unsigned Size, SMLoc L);
270   bool ParseDirectiveTC(unsigned Size, SMLoc L);
271   bool ParseDirectiveMachine(SMLoc L);
272   bool ParseDarwinDirectiveMachine(SMLoc L);
273   bool ParseDirectiveAbiVersion(SMLoc L);
274   bool ParseDirectiveLocalEntry(SMLoc L);
275 
276   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
277                                OperandVector &Operands, MCStreamer &Out,
278                                uint64_t &ErrorInfo,
279                                bool MatchingInlineAsm) override;
280 
281   void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
282 
283   /// @name Auto-generated Match Functions
284   /// {
285 
286 #define GET_ASSEMBLER_HEADER
287 #include "PPCGenAsmMatcher.inc"
288 
289   /// }
290 
291 
292 public:
293   PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
294                const MCInstrInfo &MII, const MCTargetOptions &Options)
295     : MCTargetAsmParser(Options, STI), MII(MII) {
296     // Check for 64-bit vs. 32-bit pointer mode.
297     Triple TheTriple(STI.getTargetTriple());
298     IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
299                TheTriple.getArch() == Triple::ppc64le);
300     IsDarwin = TheTriple.isMacOSX();
301     // Initialize the set of available features.
302     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
303   }
304 
305   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
306                         SMLoc NameLoc, OperandVector &Operands) override;
307 
308   bool ParseDirective(AsmToken DirectiveID) override;
309 
310   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
311                                       unsigned Kind) override;
312 
313   const MCExpr *applyModifierToExpr(const MCExpr *E,
314                                     MCSymbolRefExpr::VariantKind,
315                                     MCContext &Ctx) override;
316 };
317 
318 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
319 /// instruction.
320 struct PPCOperand : public MCParsedAsmOperand {
321   enum KindTy {
322     Token,
323     Immediate,
324     ContextImmediate,
325     Expression,
326     TLSRegister
327   } Kind;
328 
329   SMLoc StartLoc, EndLoc;
330   bool IsPPC64;
331 
332   struct TokOp {
333     const char *Data;
334     unsigned Length;
335   };
336 
337   struct ImmOp {
338     int64_t Val;
339   };
340 
341   struct ExprOp {
342     const MCExpr *Val;
343     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
344   };
345 
346   struct TLSRegOp {
347     const MCSymbolRefExpr *Sym;
348   };
349 
350   union {
351     struct TokOp Tok;
352     struct ImmOp Imm;
353     struct ExprOp Expr;
354     struct TLSRegOp TLSReg;
355   };
356 
357   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
358 public:
359   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
360     Kind = o.Kind;
361     StartLoc = o.StartLoc;
362     EndLoc = o.EndLoc;
363     IsPPC64 = o.IsPPC64;
364     switch (Kind) {
365     case Token:
366       Tok = o.Tok;
367       break;
368     case Immediate:
369     case ContextImmediate:
370       Imm = o.Imm;
371       break;
372     case Expression:
373       Expr = o.Expr;
374       break;
375     case TLSRegister:
376       TLSReg = o.TLSReg;
377       break;
378     }
379   }
380 
381   // Disable use of sized deallocation due to overallocation of PPCOperand
382   // objects in CreateTokenWithStringCopy.
383   void operator delete(void *p) { ::operator delete(p); }
384 
385   /// getStartLoc - Get the location of the first token of this operand.
386   SMLoc getStartLoc() const override { return StartLoc; }
387 
388   /// getEndLoc - Get the location of the last token of this operand.
389   SMLoc getEndLoc() const override { return EndLoc; }
390 
391   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
392   bool isPPC64() const { return IsPPC64; }
393 
394   int64_t getImm() const {
395     assert(Kind == Immediate && "Invalid access!");
396     return Imm.Val;
397   }
398   int64_t getImmS16Context() const {
399     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
400     if (Kind == Immediate)
401       return Imm.Val;
402     return static_cast<int16_t>(Imm.Val);
403   }
404   int64_t getImmU16Context() const {
405     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
406     return Imm.Val;
407   }
408 
409   const MCExpr *getExpr() const {
410     assert(Kind == Expression && "Invalid access!");
411     return Expr.Val;
412   }
413 
414   int64_t getExprCRVal() const {
415     assert(Kind == Expression && "Invalid access!");
416     return Expr.CRVal;
417   }
418 
419   const MCExpr *getTLSReg() const {
420     assert(Kind == TLSRegister && "Invalid access!");
421     return TLSReg.Sym;
422   }
423 
424   unsigned getReg() const override {
425     assert(isRegNumber() && "Invalid access!");
426     return (unsigned) Imm.Val;
427   }
428 
429   unsigned getVSReg() const {
430     assert(isVSRegNumber() && "Invalid access!");
431     return (unsigned) Imm.Val;
432   }
433 
434   unsigned getCCReg() const {
435     assert(isCCRegNumber() && "Invalid access!");
436     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
437   }
438 
439   unsigned getCRBit() const {
440     assert(isCRBitNumber() && "Invalid access!");
441     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
442   }
443 
444   unsigned getCRBitMask() const {
445     assert(isCRBitMask() && "Invalid access!");
446     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
447   }
448 
449   bool isToken() const override { return Kind == Token; }
450   bool isImm() const override { return Kind == Immediate || Kind == Expression; }
451   bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
452   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
453   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
454   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
455   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
456   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
457   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
458   bool isU6ImmX2() const { return Kind == Immediate &&
459                                   isUInt<6>(getImm()) &&
460                                   (getImm() & 1) == 0; }
461   bool isU7ImmX4() const { return Kind == Immediate &&
462                                   isUInt<7>(getImm()) &&
463                                   (getImm() & 3) == 0; }
464   bool isU8ImmX8() const { return Kind == Immediate &&
465                                   isUInt<8>(getImm()) &&
466                                   (getImm() & 7) == 0; }
467 
468   bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
469   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
470   bool isU16Imm() const {
471     switch (Kind) {
472       case Expression:
473         return true;
474       case Immediate:
475       case ContextImmediate:
476         return isUInt<16>(getImmU16Context());
477       default:
478         return false;
479     }
480   }
481   bool isS16Imm() const {
482     switch (Kind) {
483       case Expression:
484         return true;
485       case Immediate:
486       case ContextImmediate:
487         return isInt<16>(getImmS16Context());
488       default:
489         return false;
490     }
491   }
492   bool isS16ImmX4() const { return Kind == Expression ||
493                                    (Kind == Immediate && isInt<16>(getImm()) &&
494                                     (getImm() & 3) == 0); }
495   bool isS17Imm() const {
496     switch (Kind) {
497       case Expression:
498         return true;
499       case Immediate:
500       case ContextImmediate:
501         return isInt<17>(getImmS16Context());
502       default:
503         return false;
504     }
505   }
506   bool isTLSReg() const { return Kind == TLSRegister; }
507   bool isDirectBr() const {
508     if (Kind == Expression)
509       return true;
510     if (Kind != Immediate)
511       return false;
512     // Operand must be 64-bit aligned, signed 27-bit immediate.
513     if ((getImm() & 3) != 0)
514       return false;
515     if (isInt<26>(getImm()))
516       return true;
517     if (!IsPPC64) {
518       // In 32-bit mode, large 32-bit quantities wrap around.
519       if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
520         return true;
521     }
522     return false;
523   }
524   bool isCondBr() const { return Kind == Expression ||
525                                  (Kind == Immediate && isInt<16>(getImm()) &&
526                                   (getImm() & 3) == 0); }
527   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
528   bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
529   bool isCCRegNumber() const { return (Kind == Expression
530                                        && isUInt<3>(getExprCRVal())) ||
531                                       (Kind == Immediate
532                                        && isUInt<3>(getImm())); }
533   bool isCRBitNumber() const { return (Kind == Expression
534                                        && isUInt<5>(getExprCRVal())) ||
535                                       (Kind == Immediate
536                                        && isUInt<5>(getImm())); }
537   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
538                                     isPowerOf2_32(getImm()); }
539   bool isMem() const override { return false; }
540   bool isReg() const override { return false; }
541 
542   void addRegOperands(MCInst &Inst, unsigned N) const {
543     llvm_unreachable("addRegOperands");
544   }
545 
546   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
547     assert(N == 1 && "Invalid number of operands!");
548     Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
549   }
550 
551   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
552     assert(N == 1 && "Invalid number of operands!");
553     Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
554   }
555 
556   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
557     assert(N == 1 && "Invalid number of operands!");
558     Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
559   }
560 
561   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
562     assert(N == 1 && "Invalid number of operands!");
563     Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
564   }
565 
566   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
567     if (isPPC64())
568       addRegG8RCOperands(Inst, N);
569     else
570       addRegGPRCOperands(Inst, N);
571   }
572 
573   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
574     if (isPPC64())
575       addRegG8RCNoX0Operands(Inst, N);
576     else
577       addRegGPRCNoR0Operands(Inst, N);
578   }
579 
580   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
581     assert(N == 1 && "Invalid number of operands!");
582     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
583   }
584 
585   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
586     assert(N == 1 && "Invalid number of operands!");
587     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
588   }
589 
590   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
591     assert(N == 1 && "Invalid number of operands!");
592     Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
593   }
594 
595   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
596     assert(N == 1 && "Invalid number of operands!");
597     Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
598   }
599 
600   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
601     assert(N == 1 && "Invalid number of operands!");
602     Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
603   }
604 
605   void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
606     assert(N == 1 && "Invalid number of operands!");
607     Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
608   }
609 
610   void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
611     assert(N == 1 && "Invalid number of operands!");
612     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
613   }
614 
615   void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
616     assert(N == 1 && "Invalid number of operands!");
617     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
618   }
619 
620   void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
621     assert(N == 1 && "Invalid number of operands!");
622     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
623   }
624 
625   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
626     assert(N == 1 && "Invalid number of operands!");
627     Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
628   }
629 
630   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
631     assert(N == 1 && "Invalid number of operands!");
632     Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
633   }
634 
635   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
636     assert(N == 1 && "Invalid number of operands!");
637     Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
638   }
639 
640   void addImmOperands(MCInst &Inst, unsigned N) const {
641     assert(N == 1 && "Invalid number of operands!");
642     if (Kind == Immediate)
643       Inst.addOperand(MCOperand::createImm(getImm()));
644     else
645       Inst.addOperand(MCOperand::createExpr(getExpr()));
646   }
647 
648   void addS16ImmOperands(MCInst &Inst, unsigned N) const {
649     assert(N == 1 && "Invalid number of operands!");
650     switch (Kind) {
651       case Immediate:
652         Inst.addOperand(MCOperand::createImm(getImm()));
653         break;
654       case ContextImmediate:
655         Inst.addOperand(MCOperand::createImm(getImmS16Context()));
656         break;
657       default:
658         Inst.addOperand(MCOperand::createExpr(getExpr()));
659         break;
660     }
661   }
662 
663   void addU16ImmOperands(MCInst &Inst, unsigned N) const {
664     assert(N == 1 && "Invalid number of operands!");
665     switch (Kind) {
666       case Immediate:
667         Inst.addOperand(MCOperand::createImm(getImm()));
668         break;
669       case ContextImmediate:
670         Inst.addOperand(MCOperand::createImm(getImmU16Context()));
671         break;
672       default:
673         Inst.addOperand(MCOperand::createExpr(getExpr()));
674         break;
675     }
676   }
677 
678   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
679     assert(N == 1 && "Invalid number of operands!");
680     if (Kind == Immediate)
681       Inst.addOperand(MCOperand::createImm(getImm() / 4));
682     else
683       Inst.addOperand(MCOperand::createExpr(getExpr()));
684   }
685 
686   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
687     assert(N == 1 && "Invalid number of operands!");
688     Inst.addOperand(MCOperand::createExpr(getTLSReg()));
689   }
690 
691   StringRef getToken() const {
692     assert(Kind == Token && "Invalid access!");
693     return StringRef(Tok.Data, Tok.Length);
694   }
695 
696   void print(raw_ostream &OS) const override;
697 
698   static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
699                                                  bool IsPPC64) {
700     auto Op = make_unique<PPCOperand>(Token);
701     Op->Tok.Data = Str.data();
702     Op->Tok.Length = Str.size();
703     Op->StartLoc = S;
704     Op->EndLoc = S;
705     Op->IsPPC64 = IsPPC64;
706     return Op;
707   }
708 
709   static std::unique_ptr<PPCOperand>
710   CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
711     // Allocate extra memory for the string and copy it.
712     // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
713     // deleter which will destroy them by simply using "delete", not correctly
714     // calling operator delete on this extra memory after calling the dtor
715     // explicitly.
716     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
717     std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
718     Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
719     Op->Tok.Length = Str.size();
720     std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
721     Op->StartLoc = S;
722     Op->EndLoc = S;
723     Op->IsPPC64 = IsPPC64;
724     return Op;
725   }
726 
727   static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
728                                                bool IsPPC64) {
729     auto Op = make_unique<PPCOperand>(Immediate);
730     Op->Imm.Val = Val;
731     Op->StartLoc = S;
732     Op->EndLoc = E;
733     Op->IsPPC64 = IsPPC64;
734     return Op;
735   }
736 
737   static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
738                                                 SMLoc E, bool IsPPC64) {
739     auto Op = make_unique<PPCOperand>(Expression);
740     Op->Expr.Val = Val;
741     Op->Expr.CRVal = EvaluateCRExpr(Val);
742     Op->StartLoc = S;
743     Op->EndLoc = E;
744     Op->IsPPC64 = IsPPC64;
745     return Op;
746   }
747 
748   static std::unique_ptr<PPCOperand>
749   CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
750     auto Op = make_unique<PPCOperand>(TLSRegister);
751     Op->TLSReg.Sym = Sym;
752     Op->StartLoc = S;
753     Op->EndLoc = E;
754     Op->IsPPC64 = IsPPC64;
755     return Op;
756   }
757 
758   static std::unique_ptr<PPCOperand>
759   CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
760     auto Op = make_unique<PPCOperand>(ContextImmediate);
761     Op->Imm.Val = Val;
762     Op->StartLoc = S;
763     Op->EndLoc = E;
764     Op->IsPPC64 = IsPPC64;
765     return Op;
766   }
767 
768   static std::unique_ptr<PPCOperand>
769   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
770     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
771       return CreateImm(CE->getValue(), S, E, IsPPC64);
772 
773     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
774       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
775         return CreateTLSReg(SRE, S, E, IsPPC64);
776 
777     if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
778       int64_t Res;
779       if (TE->evaluateAsConstant(Res))
780         return CreateContextImm(Res, S, E, IsPPC64);
781     }
782 
783     return CreateExpr(Val, S, E, IsPPC64);
784   }
785 };
786 
787 } // end anonymous namespace.
788 
789 void PPCOperand::print(raw_ostream &OS) const {
790   switch (Kind) {
791   case Token:
792     OS << "'" << getToken() << "'";
793     break;
794   case Immediate:
795   case ContextImmediate:
796     OS << getImm();
797     break;
798   case Expression:
799     OS << *getExpr();
800     break;
801   case TLSRegister:
802     OS << *getTLSReg();
803     break;
804   }
805 }
806 
807 static void
808 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
809   if (Op.isImm()) {
810     Inst.addOperand(MCOperand::createImm(-Op.getImm()));
811     return;
812   }
813   const MCExpr *Expr = Op.getExpr();
814   if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
815     if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
816       Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
817       return;
818     }
819   } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
820     if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
821       const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
822                                                  BinExpr->getLHS(), Ctx);
823       Inst.addOperand(MCOperand::createExpr(NE));
824       return;
825     }
826   }
827   Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx)));
828 }
829 
830 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
831                                       const OperandVector &Operands) {
832   int Opcode = Inst.getOpcode();
833   switch (Opcode) {
834   case PPC::DCBTx:
835   case PPC::DCBTT:
836   case PPC::DCBTSTx:
837   case PPC::DCBTSTT: {
838     MCInst TmpInst;
839     TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
840                       PPC::DCBT : PPC::DCBTST);
841     TmpInst.addOperand(MCOperand::createImm(
842       (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
843     TmpInst.addOperand(Inst.getOperand(0));
844     TmpInst.addOperand(Inst.getOperand(1));
845     Inst = TmpInst;
846     break;
847   }
848   case PPC::DCBTCT:
849   case PPC::DCBTDS: {
850     MCInst TmpInst;
851     TmpInst.setOpcode(PPC::DCBT);
852     TmpInst.addOperand(Inst.getOperand(2));
853     TmpInst.addOperand(Inst.getOperand(0));
854     TmpInst.addOperand(Inst.getOperand(1));
855     Inst = TmpInst;
856     break;
857   }
858   case PPC::DCBTSTCT:
859   case PPC::DCBTSTDS: {
860     MCInst TmpInst;
861     TmpInst.setOpcode(PPC::DCBTST);
862     TmpInst.addOperand(Inst.getOperand(2));
863     TmpInst.addOperand(Inst.getOperand(0));
864     TmpInst.addOperand(Inst.getOperand(1));
865     Inst = TmpInst;
866     break;
867   }
868   case PPC::LAx: {
869     MCInst TmpInst;
870     TmpInst.setOpcode(PPC::LA);
871     TmpInst.addOperand(Inst.getOperand(0));
872     TmpInst.addOperand(Inst.getOperand(2));
873     TmpInst.addOperand(Inst.getOperand(1));
874     Inst = TmpInst;
875     break;
876   }
877   case PPC::SUBI: {
878     MCInst TmpInst;
879     TmpInst.setOpcode(PPC::ADDI);
880     TmpInst.addOperand(Inst.getOperand(0));
881     TmpInst.addOperand(Inst.getOperand(1));
882     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
883     Inst = TmpInst;
884     break;
885   }
886   case PPC::SUBIS: {
887     MCInst TmpInst;
888     TmpInst.setOpcode(PPC::ADDIS);
889     TmpInst.addOperand(Inst.getOperand(0));
890     TmpInst.addOperand(Inst.getOperand(1));
891     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
892     Inst = TmpInst;
893     break;
894   }
895   case PPC::SUBIC: {
896     MCInst TmpInst;
897     TmpInst.setOpcode(PPC::ADDIC);
898     TmpInst.addOperand(Inst.getOperand(0));
899     TmpInst.addOperand(Inst.getOperand(1));
900     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
901     Inst = TmpInst;
902     break;
903   }
904   case PPC::SUBICo: {
905     MCInst TmpInst;
906     TmpInst.setOpcode(PPC::ADDICo);
907     TmpInst.addOperand(Inst.getOperand(0));
908     TmpInst.addOperand(Inst.getOperand(1));
909     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
910     Inst = TmpInst;
911     break;
912   }
913   case PPC::EXTLWI:
914   case PPC::EXTLWIo: {
915     MCInst TmpInst;
916     int64_t N = Inst.getOperand(2).getImm();
917     int64_t B = Inst.getOperand(3).getImm();
918     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
919     TmpInst.addOperand(Inst.getOperand(0));
920     TmpInst.addOperand(Inst.getOperand(1));
921     TmpInst.addOperand(MCOperand::createImm(B));
922     TmpInst.addOperand(MCOperand::createImm(0));
923     TmpInst.addOperand(MCOperand::createImm(N - 1));
924     Inst = TmpInst;
925     break;
926   }
927   case PPC::EXTRWI:
928   case PPC::EXTRWIo: {
929     MCInst TmpInst;
930     int64_t N = Inst.getOperand(2).getImm();
931     int64_t B = Inst.getOperand(3).getImm();
932     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
933     TmpInst.addOperand(Inst.getOperand(0));
934     TmpInst.addOperand(Inst.getOperand(1));
935     TmpInst.addOperand(MCOperand::createImm(B + N));
936     TmpInst.addOperand(MCOperand::createImm(32 - N));
937     TmpInst.addOperand(MCOperand::createImm(31));
938     Inst = TmpInst;
939     break;
940   }
941   case PPC::INSLWI:
942   case PPC::INSLWIo: {
943     MCInst TmpInst;
944     int64_t N = Inst.getOperand(2).getImm();
945     int64_t B = Inst.getOperand(3).getImm();
946     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
947     TmpInst.addOperand(Inst.getOperand(0));
948     TmpInst.addOperand(Inst.getOperand(0));
949     TmpInst.addOperand(Inst.getOperand(1));
950     TmpInst.addOperand(MCOperand::createImm(32 - B));
951     TmpInst.addOperand(MCOperand::createImm(B));
952     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
953     Inst = TmpInst;
954     break;
955   }
956   case PPC::INSRWI:
957   case PPC::INSRWIo: {
958     MCInst TmpInst;
959     int64_t N = Inst.getOperand(2).getImm();
960     int64_t B = Inst.getOperand(3).getImm();
961     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
962     TmpInst.addOperand(Inst.getOperand(0));
963     TmpInst.addOperand(Inst.getOperand(0));
964     TmpInst.addOperand(Inst.getOperand(1));
965     TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
966     TmpInst.addOperand(MCOperand::createImm(B));
967     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
968     Inst = TmpInst;
969     break;
970   }
971   case PPC::ROTRWI:
972   case PPC::ROTRWIo: {
973     MCInst TmpInst;
974     int64_t N = Inst.getOperand(2).getImm();
975     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
976     TmpInst.addOperand(Inst.getOperand(0));
977     TmpInst.addOperand(Inst.getOperand(1));
978     TmpInst.addOperand(MCOperand::createImm(32 - N));
979     TmpInst.addOperand(MCOperand::createImm(0));
980     TmpInst.addOperand(MCOperand::createImm(31));
981     Inst = TmpInst;
982     break;
983   }
984   case PPC::SLWI:
985   case PPC::SLWIo: {
986     MCInst TmpInst;
987     int64_t N = Inst.getOperand(2).getImm();
988     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
989     TmpInst.addOperand(Inst.getOperand(0));
990     TmpInst.addOperand(Inst.getOperand(1));
991     TmpInst.addOperand(MCOperand::createImm(N));
992     TmpInst.addOperand(MCOperand::createImm(0));
993     TmpInst.addOperand(MCOperand::createImm(31 - N));
994     Inst = TmpInst;
995     break;
996   }
997   case PPC::SRWI:
998   case PPC::SRWIo: {
999     MCInst TmpInst;
1000     int64_t N = Inst.getOperand(2).getImm();
1001     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
1002     TmpInst.addOperand(Inst.getOperand(0));
1003     TmpInst.addOperand(Inst.getOperand(1));
1004     TmpInst.addOperand(MCOperand::createImm(32 - N));
1005     TmpInst.addOperand(MCOperand::createImm(N));
1006     TmpInst.addOperand(MCOperand::createImm(31));
1007     Inst = TmpInst;
1008     break;
1009   }
1010   case PPC::CLRRWI:
1011   case PPC::CLRRWIo: {
1012     MCInst TmpInst;
1013     int64_t N = Inst.getOperand(2).getImm();
1014     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
1015     TmpInst.addOperand(Inst.getOperand(0));
1016     TmpInst.addOperand(Inst.getOperand(1));
1017     TmpInst.addOperand(MCOperand::createImm(0));
1018     TmpInst.addOperand(MCOperand::createImm(0));
1019     TmpInst.addOperand(MCOperand::createImm(31 - N));
1020     Inst = TmpInst;
1021     break;
1022   }
1023   case PPC::CLRLSLWI:
1024   case PPC::CLRLSLWIo: {
1025     MCInst TmpInst;
1026     int64_t B = Inst.getOperand(2).getImm();
1027     int64_t N = Inst.getOperand(3).getImm();
1028     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
1029     TmpInst.addOperand(Inst.getOperand(0));
1030     TmpInst.addOperand(Inst.getOperand(1));
1031     TmpInst.addOperand(MCOperand::createImm(N));
1032     TmpInst.addOperand(MCOperand::createImm(B - N));
1033     TmpInst.addOperand(MCOperand::createImm(31 - N));
1034     Inst = TmpInst;
1035     break;
1036   }
1037   case PPC::EXTLDI:
1038   case PPC::EXTLDIo: {
1039     MCInst TmpInst;
1040     int64_t N = Inst.getOperand(2).getImm();
1041     int64_t B = Inst.getOperand(3).getImm();
1042     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1043     TmpInst.addOperand(Inst.getOperand(0));
1044     TmpInst.addOperand(Inst.getOperand(1));
1045     TmpInst.addOperand(MCOperand::createImm(B));
1046     TmpInst.addOperand(MCOperand::createImm(N - 1));
1047     Inst = TmpInst;
1048     break;
1049   }
1050   case PPC::EXTRDI:
1051   case PPC::EXTRDIo: {
1052     MCInst TmpInst;
1053     int64_t N = Inst.getOperand(2).getImm();
1054     int64_t B = Inst.getOperand(3).getImm();
1055     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1056     TmpInst.addOperand(Inst.getOperand(0));
1057     TmpInst.addOperand(Inst.getOperand(1));
1058     TmpInst.addOperand(MCOperand::createImm(B + N));
1059     TmpInst.addOperand(MCOperand::createImm(64 - N));
1060     Inst = TmpInst;
1061     break;
1062   }
1063   case PPC::INSRDI:
1064   case PPC::INSRDIo: {
1065     MCInst TmpInst;
1066     int64_t N = Inst.getOperand(2).getImm();
1067     int64_t B = Inst.getOperand(3).getImm();
1068     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1069     TmpInst.addOperand(Inst.getOperand(0));
1070     TmpInst.addOperand(Inst.getOperand(0));
1071     TmpInst.addOperand(Inst.getOperand(1));
1072     TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
1073     TmpInst.addOperand(MCOperand::createImm(B));
1074     Inst = TmpInst;
1075     break;
1076   }
1077   case PPC::ROTRDI:
1078   case PPC::ROTRDIo: {
1079     MCInst TmpInst;
1080     int64_t N = Inst.getOperand(2).getImm();
1081     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1082     TmpInst.addOperand(Inst.getOperand(0));
1083     TmpInst.addOperand(Inst.getOperand(1));
1084     TmpInst.addOperand(MCOperand::createImm(64 - N));
1085     TmpInst.addOperand(MCOperand::createImm(0));
1086     Inst = TmpInst;
1087     break;
1088   }
1089   case PPC::SLDI:
1090   case PPC::SLDIo: {
1091     MCInst TmpInst;
1092     int64_t N = Inst.getOperand(2).getImm();
1093     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1094     TmpInst.addOperand(Inst.getOperand(0));
1095     TmpInst.addOperand(Inst.getOperand(1));
1096     TmpInst.addOperand(MCOperand::createImm(N));
1097     TmpInst.addOperand(MCOperand::createImm(63 - N));
1098     Inst = TmpInst;
1099     break;
1100   }
1101   case PPC::SRDI:
1102   case PPC::SRDIo: {
1103     MCInst TmpInst;
1104     int64_t N = Inst.getOperand(2).getImm();
1105     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1106     TmpInst.addOperand(Inst.getOperand(0));
1107     TmpInst.addOperand(Inst.getOperand(1));
1108     TmpInst.addOperand(MCOperand::createImm(64 - N));
1109     TmpInst.addOperand(MCOperand::createImm(N));
1110     Inst = TmpInst;
1111     break;
1112   }
1113   case PPC::CLRRDI:
1114   case PPC::CLRRDIo: {
1115     MCInst TmpInst;
1116     int64_t N = Inst.getOperand(2).getImm();
1117     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1118     TmpInst.addOperand(Inst.getOperand(0));
1119     TmpInst.addOperand(Inst.getOperand(1));
1120     TmpInst.addOperand(MCOperand::createImm(0));
1121     TmpInst.addOperand(MCOperand::createImm(63 - N));
1122     Inst = TmpInst;
1123     break;
1124   }
1125   case PPC::CLRLSLDI:
1126   case PPC::CLRLSLDIo: {
1127     MCInst TmpInst;
1128     int64_t B = Inst.getOperand(2).getImm();
1129     int64_t N = Inst.getOperand(3).getImm();
1130     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1131     TmpInst.addOperand(Inst.getOperand(0));
1132     TmpInst.addOperand(Inst.getOperand(1));
1133     TmpInst.addOperand(MCOperand::createImm(N));
1134     TmpInst.addOperand(MCOperand::createImm(B - N));
1135     Inst = TmpInst;
1136     break;
1137   }
1138   case PPC::RLWINMbm:
1139   case PPC::RLWINMobm: {
1140     unsigned MB, ME;
1141     int64_t BM = Inst.getOperand(3).getImm();
1142     if (!isRunOfOnes(BM, MB, ME))
1143       break;
1144 
1145     MCInst TmpInst;
1146     TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1147     TmpInst.addOperand(Inst.getOperand(0));
1148     TmpInst.addOperand(Inst.getOperand(1));
1149     TmpInst.addOperand(Inst.getOperand(2));
1150     TmpInst.addOperand(MCOperand::createImm(MB));
1151     TmpInst.addOperand(MCOperand::createImm(ME));
1152     Inst = TmpInst;
1153     break;
1154   }
1155   case PPC::RLWIMIbm:
1156   case PPC::RLWIMIobm: {
1157     unsigned MB, ME;
1158     int64_t BM = Inst.getOperand(3).getImm();
1159     if (!isRunOfOnes(BM, MB, ME))
1160       break;
1161 
1162     MCInst TmpInst;
1163     TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1164     TmpInst.addOperand(Inst.getOperand(0));
1165     TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1166     TmpInst.addOperand(Inst.getOperand(1));
1167     TmpInst.addOperand(Inst.getOperand(2));
1168     TmpInst.addOperand(MCOperand::createImm(MB));
1169     TmpInst.addOperand(MCOperand::createImm(ME));
1170     Inst = TmpInst;
1171     break;
1172   }
1173   case PPC::RLWNMbm:
1174   case PPC::RLWNMobm: {
1175     unsigned MB, ME;
1176     int64_t BM = Inst.getOperand(3).getImm();
1177     if (!isRunOfOnes(BM, MB, ME))
1178       break;
1179 
1180     MCInst TmpInst;
1181     TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1182     TmpInst.addOperand(Inst.getOperand(0));
1183     TmpInst.addOperand(Inst.getOperand(1));
1184     TmpInst.addOperand(Inst.getOperand(2));
1185     TmpInst.addOperand(MCOperand::createImm(MB));
1186     TmpInst.addOperand(MCOperand::createImm(ME));
1187     Inst = TmpInst;
1188     break;
1189   }
1190   case PPC::MFTB: {
1191     if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1192       assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1193       Inst.setOpcode(PPC::MFSPR);
1194     }
1195     break;
1196   }
1197   }
1198 }
1199 
1200 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1201                                            OperandVector &Operands,
1202                                            MCStreamer &Out, uint64_t &ErrorInfo,
1203                                            bool MatchingInlineAsm) {
1204   MCInst Inst;
1205 
1206   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1207   case Match_Success:
1208     // Post-process instructions (typically extended mnemonics)
1209     ProcessInstruction(Inst, Operands);
1210     Inst.setLoc(IDLoc);
1211     Out.EmitInstruction(Inst, getSTI());
1212     return false;
1213   case Match_MissingFeature:
1214     return Error(IDLoc, "instruction use requires an option to be enabled");
1215   case Match_MnemonicFail:
1216     return Error(IDLoc, "unrecognized instruction mnemonic");
1217   case Match_InvalidOperand: {
1218     SMLoc ErrorLoc = IDLoc;
1219     if (ErrorInfo != ~0ULL) {
1220       if (ErrorInfo >= Operands.size())
1221         return Error(IDLoc, "too few operands for instruction");
1222 
1223       ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1224       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1225     }
1226 
1227     return Error(ErrorLoc, "invalid operand for instruction");
1228   }
1229   }
1230 
1231   llvm_unreachable("Implement any new match types added!");
1232 }
1233 
1234 bool PPCAsmParser::
1235 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1236   if (Tok.is(AsmToken::Identifier)) {
1237     StringRef Name = Tok.getString();
1238 
1239     if (Name.equals_lower("lr")) {
1240       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1241       IntVal = 8;
1242       return false;
1243     } else if (Name.equals_lower("ctr")) {
1244       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1245       IntVal = 9;
1246       return false;
1247     } else if (Name.equals_lower("vrsave")) {
1248       RegNo = PPC::VRSAVE;
1249       IntVal = 256;
1250       return false;
1251     } else if (Name.startswith_lower("r") &&
1252                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1253       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1254       return false;
1255     } else if (Name.startswith_lower("f") &&
1256                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1257       RegNo = FRegs[IntVal];
1258       return false;
1259     } else if (Name.startswith_lower("vs") &&
1260                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1261       RegNo = VSRegs[IntVal];
1262       return false;
1263     } else if (Name.startswith_lower("v") &&
1264                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1265       RegNo = VRegs[IntVal];
1266       return false;
1267     } else if (Name.startswith_lower("q") &&
1268                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1269       RegNo = QFRegs[IntVal];
1270       return false;
1271     } else if (Name.startswith_lower("cr") &&
1272                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1273       RegNo = CRRegs[IntVal];
1274       return false;
1275     }
1276   }
1277 
1278   return true;
1279 }
1280 
1281 bool PPCAsmParser::
1282 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1283   MCAsmParser &Parser = getParser();
1284   const AsmToken &Tok = Parser.getTok();
1285   StartLoc = Tok.getLoc();
1286   EndLoc = Tok.getEndLoc();
1287   RegNo = 0;
1288   int64_t IntVal;
1289 
1290   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1291     Parser.Lex(); // Eat identifier token.
1292     return false;
1293   }
1294 
1295   return Error(StartLoc, "invalid register name");
1296 }
1297 
1298 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1299 /// the expression and check for VK_PPC_LO/HI/HA
1300 /// symbol variants.  If all symbols with modifier use the same
1301 /// variant, return the corresponding PPCMCExpr::VariantKind,
1302 /// and a modified expression using the default symbol variant.
1303 /// Otherwise, return NULL.
1304 const MCExpr *PPCAsmParser::
1305 ExtractModifierFromExpr(const MCExpr *E,
1306                         PPCMCExpr::VariantKind &Variant) {
1307   MCContext &Context = getParser().getContext();
1308   Variant = PPCMCExpr::VK_PPC_None;
1309 
1310   switch (E->getKind()) {
1311   case MCExpr::Target:
1312   case MCExpr::Constant:
1313     return nullptr;
1314 
1315   case MCExpr::SymbolRef: {
1316     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1317 
1318     switch (SRE->getKind()) {
1319     case MCSymbolRefExpr::VK_PPC_LO:
1320       Variant = PPCMCExpr::VK_PPC_LO;
1321       break;
1322     case MCSymbolRefExpr::VK_PPC_HI:
1323       Variant = PPCMCExpr::VK_PPC_HI;
1324       break;
1325     case MCSymbolRefExpr::VK_PPC_HA:
1326       Variant = PPCMCExpr::VK_PPC_HA;
1327       break;
1328     case MCSymbolRefExpr::VK_PPC_HIGHER:
1329       Variant = PPCMCExpr::VK_PPC_HIGHER;
1330       break;
1331     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1332       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1333       break;
1334     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1335       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1336       break;
1337     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1338       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1339       break;
1340     default:
1341       return nullptr;
1342     }
1343 
1344     return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1345   }
1346 
1347   case MCExpr::Unary: {
1348     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1349     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1350     if (!Sub)
1351       return nullptr;
1352     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1353   }
1354 
1355   case MCExpr::Binary: {
1356     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1357     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1358     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1359     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1360 
1361     if (!LHS && !RHS)
1362       return nullptr;
1363 
1364     if (!LHS) LHS = BE->getLHS();
1365     if (!RHS) RHS = BE->getRHS();
1366 
1367     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1368       Variant = RHSVariant;
1369     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1370       Variant = LHSVariant;
1371     else if (LHSVariant == RHSVariant)
1372       Variant = LHSVariant;
1373     else
1374       return nullptr;
1375 
1376     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1377   }
1378   }
1379 
1380   llvm_unreachable("Invalid expression kind!");
1381 }
1382 
1383 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1384 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1385 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1386 /// FIXME: This is a hack.
1387 const MCExpr *PPCAsmParser::
1388 FixupVariantKind(const MCExpr *E) {
1389   MCContext &Context = getParser().getContext();
1390 
1391   switch (E->getKind()) {
1392   case MCExpr::Target:
1393   case MCExpr::Constant:
1394     return E;
1395 
1396   case MCExpr::SymbolRef: {
1397     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1398     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1399 
1400     switch (SRE->getKind()) {
1401     case MCSymbolRefExpr::VK_TLSGD:
1402       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1403       break;
1404     case MCSymbolRefExpr::VK_TLSLD:
1405       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1406       break;
1407     default:
1408       return E;
1409     }
1410     return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1411   }
1412 
1413   case MCExpr::Unary: {
1414     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1415     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1416     if (Sub == UE->getSubExpr())
1417       return E;
1418     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1419   }
1420 
1421   case MCExpr::Binary: {
1422     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1423     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1424     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1425     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1426       return E;
1427     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1428   }
1429   }
1430 
1431   llvm_unreachable("Invalid expression kind!");
1432 }
1433 
1434 /// ParseExpression.  This differs from the default "parseExpression" in that
1435 /// it handles modifiers.
1436 bool PPCAsmParser::
1437 ParseExpression(const MCExpr *&EVal) {
1438 
1439   if (isDarwin())
1440     return ParseDarwinExpression(EVal);
1441 
1442   // (ELF Platforms)
1443   // Handle \code @l/@ha \endcode
1444   if (getParser().parseExpression(EVal))
1445     return true;
1446 
1447   EVal = FixupVariantKind(EVal);
1448 
1449   PPCMCExpr::VariantKind Variant;
1450   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1451   if (E)
1452     EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext());
1453 
1454   return false;
1455 }
1456 
1457 /// ParseDarwinExpression.  (MachO Platforms)
1458 /// This differs from the default "parseExpression" in that it handles detection
1459 /// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1460 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1461 /// syntax form so it is done here.  TODO: Determine if there is merit in arranging
1462 /// for this to be done at a higher level.
1463 bool PPCAsmParser::
1464 ParseDarwinExpression(const MCExpr *&EVal) {
1465   MCAsmParser &Parser = getParser();
1466   PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1467   switch (getLexer().getKind()) {
1468   default:
1469     break;
1470   case AsmToken::Identifier:
1471     // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1472     // something starting with any other char should be part of the
1473     // asm syntax.  If handwritten asm includes an identifier like lo16,
1474     // then all bets are off - but no-one would do that, right?
1475     StringRef poss = Parser.getTok().getString();
1476     if (poss.equals_lower("lo16")) {
1477       Variant = PPCMCExpr::VK_PPC_LO;
1478     } else if (poss.equals_lower("hi16")) {
1479       Variant = PPCMCExpr::VK_PPC_HI;
1480     } else if (poss.equals_lower("ha16")) {
1481       Variant = PPCMCExpr::VK_PPC_HA;
1482     }
1483     if (Variant != PPCMCExpr::VK_PPC_None) {
1484       Parser.Lex(); // Eat the xx16
1485       if (getLexer().isNot(AsmToken::LParen))
1486         return Error(Parser.getTok().getLoc(), "expected '('");
1487       Parser.Lex(); // Eat the '('
1488     }
1489     break;
1490   }
1491 
1492   if (getParser().parseExpression(EVal))
1493     return true;
1494 
1495   if (Variant != PPCMCExpr::VK_PPC_None) {
1496     if (getLexer().isNot(AsmToken::RParen))
1497       return Error(Parser.getTok().getLoc(), "expected ')'");
1498     Parser.Lex(); // Eat the ')'
1499     EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext());
1500   }
1501   return false;
1502 }
1503 
1504 /// ParseOperand
1505 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1506 /// rNN for MachO.
1507 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1508   MCAsmParser &Parser = getParser();
1509   SMLoc S = Parser.getTok().getLoc();
1510   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1511   const MCExpr *EVal;
1512 
1513   // Attempt to parse the next token as an immediate
1514   switch (getLexer().getKind()) {
1515   // Special handling for register names.  These are interpreted
1516   // as immediates corresponding to the register number.
1517   case AsmToken::Percent:
1518     Parser.Lex(); // Eat the '%'.
1519     unsigned RegNo;
1520     int64_t IntVal;
1521     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1522       Parser.Lex(); // Eat the identifier token.
1523       Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1524       return false;
1525     }
1526     return Error(S, "invalid register name");
1527 
1528   case AsmToken::Identifier:
1529     // Note that non-register-name identifiers from the compiler will begin
1530     // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1531     // identifiers like r31foo - so we fall through in the event that parsing
1532     // a register name fails.
1533     if (isDarwin()) {
1534       unsigned RegNo;
1535       int64_t IntVal;
1536       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1537         Parser.Lex(); // Eat the identifier token.
1538         Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1539         return false;
1540       }
1541     }
1542   // Fall-through to process non-register-name identifiers as expression.
1543   // All other expressions
1544   case AsmToken::LParen:
1545   case AsmToken::Plus:
1546   case AsmToken::Minus:
1547   case AsmToken::Integer:
1548   case AsmToken::Dot:
1549   case AsmToken::Dollar:
1550   case AsmToken::Exclaim:
1551   case AsmToken::Tilde:
1552     if (!ParseExpression(EVal))
1553       break;
1554     /* fall through */
1555   default:
1556     return Error(S, "unknown operand");
1557   }
1558 
1559   // Push the parsed operand into the list of operands
1560   Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1561 
1562   // Check whether this is a TLS call expression
1563   bool TLSCall = false;
1564   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1565     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1566 
1567   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1568     const MCExpr *TLSSym;
1569 
1570     Parser.Lex(); // Eat the '('.
1571     S = Parser.getTok().getLoc();
1572     if (ParseExpression(TLSSym))
1573       return Error(S, "invalid TLS call expression");
1574     if (getLexer().isNot(AsmToken::RParen))
1575       return Error(Parser.getTok().getLoc(), "missing ')'");
1576     E = Parser.getTok().getLoc();
1577     Parser.Lex(); // Eat the ')'.
1578 
1579     Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1580   }
1581 
1582   // Otherwise, check for D-form memory operands
1583   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1584     Parser.Lex(); // Eat the '('.
1585     S = Parser.getTok().getLoc();
1586 
1587     int64_t IntVal;
1588     switch (getLexer().getKind()) {
1589     case AsmToken::Percent:
1590       Parser.Lex(); // Eat the '%'.
1591       unsigned RegNo;
1592       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1593         return Error(S, "invalid register name");
1594       Parser.Lex(); // Eat the identifier token.
1595       break;
1596 
1597     case AsmToken::Integer:
1598       if (!isDarwin()) {
1599         if (getParser().parseAbsoluteExpression(IntVal) ||
1600           IntVal < 0 || IntVal > 31)
1601         return Error(S, "invalid register number");
1602       } else {
1603         return Error(S, "unexpected integer value");
1604       }
1605       break;
1606 
1607    case AsmToken::Identifier:
1608     if (isDarwin()) {
1609       unsigned RegNo;
1610       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1611         Parser.Lex(); // Eat the identifier token.
1612         break;
1613       }
1614     }
1615     // Fall-through..
1616 
1617     default:
1618       return Error(S, "invalid memory operand");
1619     }
1620 
1621     if (getLexer().isNot(AsmToken::RParen))
1622       return Error(Parser.getTok().getLoc(), "missing ')'");
1623     E = Parser.getTok().getLoc();
1624     Parser.Lex(); // Eat the ')'.
1625 
1626     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1627   }
1628 
1629   return false;
1630 }
1631 
1632 /// Parse an instruction mnemonic followed by its operands.
1633 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1634                                     SMLoc NameLoc, OperandVector &Operands) {
1635   // The first operand is the token for the instruction name.
1636   // If the next character is a '+' or '-', we need to add it to the
1637   // instruction name, to match what TableGen is doing.
1638   std::string NewOpcode;
1639   if (getLexer().is(AsmToken::Plus)) {
1640     getLexer().Lex();
1641     NewOpcode = Name;
1642     NewOpcode += '+';
1643     Name = NewOpcode;
1644   }
1645   if (getLexer().is(AsmToken::Minus)) {
1646     getLexer().Lex();
1647     NewOpcode = Name;
1648     NewOpcode += '-';
1649     Name = NewOpcode;
1650   }
1651   // If the instruction ends in a '.', we need to create a separate
1652   // token for it, to match what TableGen is doing.
1653   size_t Dot = Name.find('.');
1654   StringRef Mnemonic = Name.slice(0, Dot);
1655   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1656     Operands.push_back(
1657         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1658   else
1659     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1660   if (Dot != StringRef::npos) {
1661     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1662     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1663     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1664       Operands.push_back(
1665           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1666     else
1667       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1668   }
1669 
1670   // If there are no more operands then finish
1671   if (getLexer().is(AsmToken::EndOfStatement))
1672     return false;
1673 
1674   // Parse the first operand
1675   if (ParseOperand(Operands))
1676     return true;
1677 
1678   while (getLexer().isNot(AsmToken::EndOfStatement) &&
1679          getLexer().is(AsmToken::Comma)) {
1680     // Consume the comma token
1681     getLexer().Lex();
1682 
1683     // Parse the next operand
1684     if (ParseOperand(Operands))
1685       return true;
1686   }
1687 
1688   // We'll now deal with an unfortunate special case: the syntax for the dcbt
1689   // and dcbtst instructions differs for server vs. embedded cores.
1690   //  The syntax for dcbt is:
1691   //    dcbt ra, rb, th [server]
1692   //    dcbt th, ra, rb [embedded]
1693   //  where th can be omitted when it is 0. dcbtst is the same. We take the
1694   //  server form to be the default, so swap the operands if we're parsing for
1695   //  an embedded core (they'll be swapped again upon printing).
1696   if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1697       Operands.size() == 4 &&
1698       (Name == "dcbt" || Name == "dcbtst")) {
1699     std::swap(Operands[1], Operands[3]);
1700     std::swap(Operands[2], Operands[1]);
1701   }
1702 
1703   return false;
1704 }
1705 
1706 /// ParseDirective parses the PPC specific directives
1707 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1708   StringRef IDVal = DirectiveID.getIdentifier();
1709   if (!isDarwin()) {
1710     if (IDVal == ".word")
1711       return ParseDirectiveWord(2, DirectiveID.getLoc());
1712     if (IDVal == ".llong")
1713       return ParseDirectiveWord(8, DirectiveID.getLoc());
1714     if (IDVal == ".tc")
1715       return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1716     if (IDVal == ".machine")
1717       return ParseDirectiveMachine(DirectiveID.getLoc());
1718     if (IDVal == ".abiversion")
1719       return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1720     if (IDVal == ".localentry")
1721       return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1722   } else {
1723     if (IDVal == ".machine")
1724       return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1725   }
1726   return true;
1727 }
1728 
1729 /// ParseDirectiveWord
1730 ///  ::= .word [ expression (, expression)* ]
1731 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1732   MCAsmParser &Parser = getParser();
1733   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1734     for (;;) {
1735       const MCExpr *Value;
1736       SMLoc ExprLoc = getLexer().getLoc();
1737       if (getParser().parseExpression(Value))
1738         return false;
1739 
1740       if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1741         assert(Size <= 8 && "Invalid size");
1742         uint64_t IntValue = MCE->getValue();
1743         if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
1744           return Error(ExprLoc, "literal value out of range for directive");
1745         getStreamer().EmitIntValue(IntValue, Size);
1746       } else {
1747         getStreamer().EmitValue(Value, Size, ExprLoc);
1748       }
1749 
1750       if (getLexer().is(AsmToken::EndOfStatement))
1751         break;
1752 
1753       if (getLexer().isNot(AsmToken::Comma))
1754         return Error(L, "unexpected token in directive");
1755       Parser.Lex();
1756     }
1757   }
1758 
1759   Parser.Lex();
1760   return false;
1761 }
1762 
1763 /// ParseDirectiveTC
1764 ///  ::= .tc [ symbol (, expression)* ]
1765 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1766   MCAsmParser &Parser = getParser();
1767   // Skip TC symbol, which is only used with XCOFF.
1768   while (getLexer().isNot(AsmToken::EndOfStatement)
1769          && getLexer().isNot(AsmToken::Comma))
1770     Parser.Lex();
1771   if (getLexer().isNot(AsmToken::Comma)) {
1772     Error(L, "unexpected token in directive");
1773     return false;
1774   }
1775   Parser.Lex();
1776 
1777   // Align to word size.
1778   getParser().getStreamer().EmitValueToAlignment(Size);
1779 
1780   // Emit expressions.
1781   return ParseDirectiveWord(Size, L);
1782 }
1783 
1784 /// ParseDirectiveMachine (ELF platforms)
1785 ///  ::= .machine [ cpu | "push" | "pop" ]
1786 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1787   MCAsmParser &Parser = getParser();
1788   if (getLexer().isNot(AsmToken::Identifier) &&
1789       getLexer().isNot(AsmToken::String)) {
1790     Error(L, "unexpected token in directive");
1791     return false;
1792   }
1793 
1794   StringRef CPU = Parser.getTok().getIdentifier();
1795   Parser.Lex();
1796 
1797   // FIXME: Right now, the parser always allows any available
1798   // instruction, so the .machine directive is not useful.
1799   // Implement ".machine any" (by doing nothing) for the benefit
1800   // of existing assembler code.  Likewise, we can then implement
1801   // ".machine push" and ".machine pop" as no-op.
1802   if (CPU != "any" && CPU != "push" && CPU != "pop") {
1803     Error(L, "unrecognized machine type");
1804     return false;
1805   }
1806 
1807   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1808     Error(L, "unexpected token in directive");
1809     return false;
1810   }
1811   PPCTargetStreamer &TStreamer =
1812       *static_cast<PPCTargetStreamer *>(
1813            getParser().getStreamer().getTargetStreamer());
1814   TStreamer.emitMachine(CPU);
1815 
1816   return false;
1817 }
1818 
1819 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1820 ///  ::= .machine cpu-identifier
1821 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1822   MCAsmParser &Parser = getParser();
1823   if (getLexer().isNot(AsmToken::Identifier) &&
1824       getLexer().isNot(AsmToken::String)) {
1825     Error(L, "unexpected token in directive");
1826     return false;
1827   }
1828 
1829   StringRef CPU = Parser.getTok().getIdentifier();
1830   Parser.Lex();
1831 
1832   // FIXME: this is only the 'default' set of cpu variants.
1833   // However we don't act on this information at present, this is simply
1834   // allowing parsing to proceed with minimal sanity checking.
1835   if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1836     Error(L, "unrecognized cpu type");
1837     return false;
1838   }
1839 
1840   if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1841     Error(L, "wrong cpu type specified for 64bit");
1842     return false;
1843   }
1844   if (!isPPC64() && CPU == "ppc64") {
1845     Error(L, "wrong cpu type specified for 32bit");
1846     return false;
1847   }
1848 
1849   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1850     Error(L, "unexpected token in directive");
1851     return false;
1852   }
1853 
1854   return false;
1855 }
1856 
1857 /// ParseDirectiveAbiVersion
1858 ///  ::= .abiversion constant-expression
1859 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1860   int64_t AbiVersion;
1861   if (getParser().parseAbsoluteExpression(AbiVersion)){
1862     Error(L, "expected constant expression");
1863     return false;
1864   }
1865   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1866     Error(L, "unexpected token in directive");
1867     return false;
1868   }
1869 
1870   PPCTargetStreamer &TStreamer =
1871       *static_cast<PPCTargetStreamer *>(
1872            getParser().getStreamer().getTargetStreamer());
1873   TStreamer.emitAbiVersion(AbiVersion);
1874 
1875   return false;
1876 }
1877 
1878 /// ParseDirectiveLocalEntry
1879 ///  ::= .localentry symbol, expression
1880 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1881   StringRef Name;
1882   if (getParser().parseIdentifier(Name)) {
1883     Error(L, "expected identifier in directive");
1884     return false;
1885   }
1886   MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1887 
1888   if (getLexer().isNot(AsmToken::Comma)) {
1889     Error(L, "unexpected token in directive");
1890     return false;
1891   }
1892   Lex();
1893 
1894   const MCExpr *Expr;
1895   if (getParser().parseExpression(Expr)) {
1896     Error(L, "expected expression");
1897     return false;
1898   }
1899 
1900   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1901     Error(L, "unexpected token in directive");
1902     return false;
1903   }
1904 
1905   PPCTargetStreamer &TStreamer =
1906       *static_cast<PPCTargetStreamer *>(
1907            getParser().getStreamer().getTargetStreamer());
1908   TStreamer.emitLocalEntry(Sym, Expr);
1909 
1910   return false;
1911 }
1912 
1913 
1914 
1915 /// Force static initialization.
1916 extern "C" void LLVMInitializePowerPCAsmParser() {
1917   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1918   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1919   RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1920 }
1921 
1922 #define GET_REGISTER_MATCHER
1923 #define GET_MATCHER_IMPLEMENTATION
1924 #include "PPCGenAsmMatcher.inc"
1925 
1926 // Define this matcher function after the auto-generated include so we
1927 // have the match class enum definitions.
1928 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1929                                                   unsigned Kind) {
1930   // If the kind is a token for a literal immediate, check if our asm
1931   // operand matches. This is for InstAliases which have a fixed-value
1932   // immediate in the syntax.
1933   int64_t ImmVal;
1934   switch (Kind) {
1935     case MCK_0: ImmVal = 0; break;
1936     case MCK_1: ImmVal = 1; break;
1937     case MCK_2: ImmVal = 2; break;
1938     case MCK_3: ImmVal = 3; break;
1939     case MCK_4: ImmVal = 4; break;
1940     case MCK_5: ImmVal = 5; break;
1941     case MCK_6: ImmVal = 6; break;
1942     case MCK_7: ImmVal = 7; break;
1943     default: return Match_InvalidOperand;
1944   }
1945 
1946   PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1947   if (Op.isImm() && Op.getImm() == ImmVal)
1948     return Match_Success;
1949 
1950   return Match_InvalidOperand;
1951 }
1952 
1953 const MCExpr *
1954 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1955                                   MCSymbolRefExpr::VariantKind Variant,
1956                                   MCContext &Ctx) {
1957   switch (Variant) {
1958   case MCSymbolRefExpr::VK_PPC_LO:
1959     return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1960   case MCSymbolRefExpr::VK_PPC_HI:
1961     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1962   case MCSymbolRefExpr::VK_PPC_HA:
1963     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1964   case MCSymbolRefExpr::VK_PPC_HIGHER:
1965     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1966   case MCSymbolRefExpr::VK_PPC_HIGHERA:
1967     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1968   case MCSymbolRefExpr::VK_PPC_HIGHEST:
1969     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1970   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1971     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1972   default:
1973     return nullptr;
1974   }
1975 }
1976