xref: /llvm-project/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (revision bd9fc28444c256bd1ed1e29a59bd938160c60674) 
1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSymbolELF.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/MC/MCTargetAsmParser.h"
30 #include "llvm/Support/SourceMgr.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Support/raw_ostream.h"
33 
34 using namespace llvm;
35 
36 static const MCPhysReg RRegs[32] = {
37   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
38   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
39   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
40   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
41   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
42   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
43   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
44   PPC::R28, PPC::R29, PPC::R30, PPC::R31
45 };
46 static const MCPhysReg RRegsNoR0[32] = {
47   PPC::ZERO,
48             PPC::R1,  PPC::R2,  PPC::R3,
49   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
50   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
51   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
52   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
53   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
54   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
55   PPC::R28, PPC::R29, PPC::R30, PPC::R31
56 };
57 static const MCPhysReg XRegs[32] = {
58   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
59   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
60   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
61   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
62   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
63   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
64   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
65   PPC::X28, PPC::X29, PPC::X30, PPC::X31
66 };
67 static const MCPhysReg XRegsNoX0[32] = {
68   PPC::ZERO8,
69             PPC::X1,  PPC::X2,  PPC::X3,
70   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
71   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
72   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
73   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
74   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
75   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
76   PPC::X28, PPC::X29, PPC::X30, PPC::X31
77 };
78 static const MCPhysReg FRegs[32] = {
79   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
80   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
81   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
82   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
83   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
84   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
85   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
86   PPC::F28, PPC::F29, PPC::F30, PPC::F31
87 };
88 static const MCPhysReg VRegs[32] = {
89   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
90   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
91   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
92   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
93   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
94   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
95   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
96   PPC::V28, PPC::V29, PPC::V30, PPC::V31
97 };
98 static const MCPhysReg VSRegs[64] = {
99   PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
100   PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
101   PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
102   PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
103   PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
104   PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
105   PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
106   PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
107 
108   PPC::VSH0,  PPC::VSH1,  PPC::VSH2,  PPC::VSH3,
109   PPC::VSH4,  PPC::VSH5,  PPC::VSH6,  PPC::VSH7,
110   PPC::VSH8,  PPC::VSH9,  PPC::VSH10, PPC::VSH11,
111   PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
112   PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
113   PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
114   PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
115   PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
116 };
117 static const MCPhysReg VSFRegs[64] = {
118   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
119   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
120   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
121   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
122   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
123   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
124   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
125   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
126 
127   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
128   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
129   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
130   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
131   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
132   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
133   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
134   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
135 };
136 static const MCPhysReg VSSRegs[64] = {
137   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
138   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
139   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
140   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
141   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
142   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
143   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
144   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
145 
146   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
147   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
148   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
149   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
150   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
151   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
152   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
153   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
154 };
155 static unsigned QFRegs[32] = {
156   PPC::QF0,  PPC::QF1,  PPC::QF2,  PPC::QF3,
157   PPC::QF4,  PPC::QF5,  PPC::QF6,  PPC::QF7,
158   PPC::QF8,  PPC::QF9,  PPC::QF10, PPC::QF11,
159   PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
160   PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
161   PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
162   PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
163   PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
164 };
165 static const MCPhysReg CRBITRegs[32] = {
166   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
167   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
168   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
169   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
170   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
171   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
172   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
173   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
174 };
175 static const MCPhysReg CRRegs[8] = {
176   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
177   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
178 };
179 
180 // Evaluate an expression containing condition register
181 // or condition register field symbols.  Returns positive
182 // value on success, or -1 on error.
183 static int64_t
184 EvaluateCRExpr(const MCExpr *E) {
185   switch (E->getKind()) {
186   case MCExpr::Target:
187     return -1;
188 
189   case MCExpr::Constant: {
190     int64_t Res = cast<MCConstantExpr>(E)->getValue();
191     return Res < 0 ? -1 : Res;
192   }
193 
194   case MCExpr::SymbolRef: {
195     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
196     StringRef Name = SRE->getSymbol().getName();
197 
198     if (Name == "lt") return 0;
199     if (Name == "gt") return 1;
200     if (Name == "eq") return 2;
201     if (Name == "so") return 3;
202     if (Name == "un") return 3;
203 
204     if (Name == "cr0") return 0;
205     if (Name == "cr1") return 1;
206     if (Name == "cr2") return 2;
207     if (Name == "cr3") return 3;
208     if (Name == "cr4") return 4;
209     if (Name == "cr5") return 5;
210     if (Name == "cr6") return 6;
211     if (Name == "cr7") return 7;
212 
213     return -1;
214   }
215 
216   case MCExpr::Unary:
217     return -1;
218 
219   case MCExpr::Binary: {
220     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
221     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
222     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
223     int64_t Res;
224 
225     if (LHSVal < 0 || RHSVal < 0)
226       return -1;
227 
228     switch (BE->getOpcode()) {
229     default: return -1;
230     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
231     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
232     }
233 
234     return Res < 0 ? -1 : Res;
235   }
236   }
237 
238   llvm_unreachable("Invalid expression kind!");
239 }
240 
241 namespace {
242 
243 struct PPCOperand;
244 
245 class PPCAsmParser : public MCTargetAsmParser {
246   const MCInstrInfo &MII;
247   bool IsPPC64;
248   bool IsDarwin;
249 
250   void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
251   bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
252 
253   bool isPPC64() const { return IsPPC64; }
254   bool isDarwin() const { return IsDarwin; }
255 
256   bool MatchRegisterName(const AsmToken &Tok,
257                          unsigned &RegNo, int64_t &IntVal);
258 
259   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
260 
261   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
262                                         PPCMCExpr::VariantKind &Variant);
263   const MCExpr *FixupVariantKind(const MCExpr *E);
264   bool ParseExpression(const MCExpr *&EVal);
265   bool ParseDarwinExpression(const MCExpr *&EVal);
266 
267   bool ParseOperand(OperandVector &Operands);
268 
269   bool ParseDirectiveWord(unsigned Size, SMLoc L);
270   bool ParseDirectiveTC(unsigned Size, SMLoc L);
271   bool ParseDirectiveMachine(SMLoc L);
272   bool ParseDarwinDirectiveMachine(SMLoc L);
273   bool ParseDirectiveAbiVersion(SMLoc L);
274   bool ParseDirectiveLocalEntry(SMLoc L);
275 
276   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
277                                OperandVector &Operands, MCStreamer &Out,
278                                uint64_t &ErrorInfo,
279                                bool MatchingInlineAsm) override;
280 
281   void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
282 
283   /// @name Auto-generated Match Functions
284   /// {
285 
286 #define GET_ASSEMBLER_HEADER
287 #include "PPCGenAsmMatcher.inc"
288 
289   /// }
290 
291 
292 public:
293   PPCAsmParser(MCSubtargetInfo &STI, MCAsmParser &,
294                const MCInstrInfo &MII, const MCTargetOptions &Options)
295     : MCTargetAsmParser(Options, STI), MII(MII) {
296     // Check for 64-bit vs. 32-bit pointer mode.
297     Triple TheTriple(STI.getTargetTriple());
298     IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
299                TheTriple.getArch() == Triple::ppc64le);
300     IsDarwin = TheTriple.isMacOSX();
301     // Initialize the set of available features.
302     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
303   }
304 
305   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
306                         SMLoc NameLoc, OperandVector &Operands) override;
307 
308   bool ParseDirective(AsmToken DirectiveID) override;
309 
310   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
311                                       unsigned Kind) override;
312 
313   const MCExpr *applyModifierToExpr(const MCExpr *E,
314                                     MCSymbolRefExpr::VariantKind,
315                                     MCContext &Ctx) override;
316 };
317 
318 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
319 /// instruction.
320 struct PPCOperand : public MCParsedAsmOperand {
321   enum KindTy {
322     Token,
323     Immediate,
324     ContextImmediate,
325     Expression,
326     TLSRegister
327   } Kind;
328 
329   SMLoc StartLoc, EndLoc;
330   bool IsPPC64;
331 
332   struct TokOp {
333     const char *Data;
334     unsigned Length;
335   };
336 
337   struct ImmOp {
338     int64_t Val;
339   };
340 
341   struct ExprOp {
342     const MCExpr *Val;
343     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
344   };
345 
346   struct TLSRegOp {
347     const MCSymbolRefExpr *Sym;
348   };
349 
350   union {
351     struct TokOp Tok;
352     struct ImmOp Imm;
353     struct ExprOp Expr;
354     struct TLSRegOp TLSReg;
355   };
356 
357   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
358 public:
359   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
360     Kind = o.Kind;
361     StartLoc = o.StartLoc;
362     EndLoc = o.EndLoc;
363     IsPPC64 = o.IsPPC64;
364     switch (Kind) {
365     case Token:
366       Tok = o.Tok;
367       break;
368     case Immediate:
369     case ContextImmediate:
370       Imm = o.Imm;
371       break;
372     case Expression:
373       Expr = o.Expr;
374       break;
375     case TLSRegister:
376       TLSReg = o.TLSReg;
377       break;
378     }
379   }
380 
381   /// getStartLoc - Get the location of the first token of this operand.
382   SMLoc getStartLoc() const override { return StartLoc; }
383 
384   /// getEndLoc - Get the location of the last token of this operand.
385   SMLoc getEndLoc() const override { return EndLoc; }
386 
387   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
388   bool isPPC64() const { return IsPPC64; }
389 
390   int64_t getImm() const {
391     assert(Kind == Immediate && "Invalid access!");
392     return Imm.Val;
393   }
394   int64_t getImmS16Context() const {
395     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
396     if (Kind == Immediate)
397       return Imm.Val;
398     return static_cast<int16_t>(Imm.Val);
399   }
400   int64_t getImmU16Context() const {
401     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
402     return Imm.Val;
403   }
404 
405   const MCExpr *getExpr() const {
406     assert(Kind == Expression && "Invalid access!");
407     return Expr.Val;
408   }
409 
410   int64_t getExprCRVal() const {
411     assert(Kind == Expression && "Invalid access!");
412     return Expr.CRVal;
413   }
414 
415   const MCExpr *getTLSReg() const {
416     assert(Kind == TLSRegister && "Invalid access!");
417     return TLSReg.Sym;
418   }
419 
420   unsigned getReg() const override {
421     assert(isRegNumber() && "Invalid access!");
422     return (unsigned) Imm.Val;
423   }
424 
425   unsigned getVSReg() const {
426     assert(isVSRegNumber() && "Invalid access!");
427     return (unsigned) Imm.Val;
428   }
429 
430   unsigned getCCReg() const {
431     assert(isCCRegNumber() && "Invalid access!");
432     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
433   }
434 
435   unsigned getCRBit() const {
436     assert(isCRBitNumber() && "Invalid access!");
437     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
438   }
439 
440   unsigned getCRBitMask() const {
441     assert(isCRBitMask() && "Invalid access!");
442     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
443   }
444 
445   bool isToken() const override { return Kind == Token; }
446   bool isImm() const override { return Kind == Immediate || Kind == Expression; }
447   bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
448   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
449   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
450   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
451   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
452   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
453   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
454   bool isU6ImmX2() const { return Kind == Immediate &&
455                                   isUInt<6>(getImm()) &&
456                                   (getImm() & 1) == 0; }
457   bool isU7ImmX4() const { return Kind == Immediate &&
458                                   isUInt<7>(getImm()) &&
459                                   (getImm() & 3) == 0; }
460   bool isU8ImmX8() const { return Kind == Immediate &&
461                                   isUInt<8>(getImm()) &&
462                                   (getImm() & 7) == 0; }
463 
464   bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
465   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
466   bool isU16Imm() const {
467     switch (Kind) {
468       case Expression:
469         return true;
470       case Immediate:
471       case ContextImmediate:
472         return isUInt<16>(getImmU16Context());
473       default:
474         return false;
475     }
476   }
477   bool isS16Imm() const {
478     switch (Kind) {
479       case Expression:
480         return true;
481       case Immediate:
482       case ContextImmediate:
483         return isInt<16>(getImmS16Context());
484       default:
485         return false;
486     }
487   }
488   bool isS16ImmX4() const { return Kind == Expression ||
489                                    (Kind == Immediate && isInt<16>(getImm()) &&
490                                     (getImm() & 3) == 0); }
491   bool isS17Imm() const {
492     switch (Kind) {
493       case Expression:
494         return true;
495       case Immediate:
496       case ContextImmediate:
497         return isInt<17>(getImmS16Context());
498       default:
499         return false;
500     }
501   }
502   bool isTLSReg() const { return Kind == TLSRegister; }
503   bool isDirectBr() const {
504     if (Kind == Expression)
505       return true;
506     if (Kind != Immediate)
507       return false;
508     // Operand must be 64-bit aligned, signed 27-bit immediate.
509     if ((getImm() & 3) != 0)
510       return false;
511     if (isInt<26>(getImm()))
512       return true;
513     if (!IsPPC64) {
514       // In 32-bit mode, large 32-bit quantities wrap around.
515       if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
516         return true;
517     }
518     return false;
519   }
520   bool isCondBr() const { return Kind == Expression ||
521                                  (Kind == Immediate && isInt<16>(getImm()) &&
522                                   (getImm() & 3) == 0); }
523   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
524   bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
525   bool isCCRegNumber() const { return (Kind == Expression
526                                        && isUInt<3>(getExprCRVal())) ||
527                                       (Kind == Immediate
528                                        && isUInt<3>(getImm())); }
529   bool isCRBitNumber() const { return (Kind == Expression
530                                        && isUInt<5>(getExprCRVal())) ||
531                                       (Kind == Immediate
532                                        && isUInt<5>(getImm())); }
533   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
534                                     isPowerOf2_32(getImm()); }
535   bool isMem() const override { return false; }
536   bool isReg() const override { return false; }
537 
538   void addRegOperands(MCInst &Inst, unsigned N) const {
539     llvm_unreachable("addRegOperands");
540   }
541 
542   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
543     assert(N == 1 && "Invalid number of operands!");
544     Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
545   }
546 
547   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
548     assert(N == 1 && "Invalid number of operands!");
549     Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
550   }
551 
552   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
553     assert(N == 1 && "Invalid number of operands!");
554     Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
555   }
556 
557   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
558     assert(N == 1 && "Invalid number of operands!");
559     Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
560   }
561 
562   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
563     if (isPPC64())
564       addRegG8RCOperands(Inst, N);
565     else
566       addRegGPRCOperands(Inst, N);
567   }
568 
569   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
570     if (isPPC64())
571       addRegG8RCNoX0Operands(Inst, N);
572     else
573       addRegGPRCNoR0Operands(Inst, N);
574   }
575 
576   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
577     assert(N == 1 && "Invalid number of operands!");
578     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
579   }
580 
581   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
582     assert(N == 1 && "Invalid number of operands!");
583     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
584   }
585 
586   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
587     assert(N == 1 && "Invalid number of operands!");
588     Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
589   }
590 
591   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
592     assert(N == 1 && "Invalid number of operands!");
593     Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
594   }
595 
596   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
597     assert(N == 1 && "Invalid number of operands!");
598     Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
599   }
600 
601   void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
602     assert(N == 1 && "Invalid number of operands!");
603     Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
604   }
605 
606   void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
607     assert(N == 1 && "Invalid number of operands!");
608     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
609   }
610 
611   void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
612     assert(N == 1 && "Invalid number of operands!");
613     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
614   }
615 
616   void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
617     assert(N == 1 && "Invalid number of operands!");
618     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
619   }
620 
621   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
622     assert(N == 1 && "Invalid number of operands!");
623     Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
624   }
625 
626   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
627     assert(N == 1 && "Invalid number of operands!");
628     Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
629   }
630 
631   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
632     assert(N == 1 && "Invalid number of operands!");
633     Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
634   }
635 
636   void addImmOperands(MCInst &Inst, unsigned N) const {
637     assert(N == 1 && "Invalid number of operands!");
638     if (Kind == Immediate)
639       Inst.addOperand(MCOperand::createImm(getImm()));
640     else
641       Inst.addOperand(MCOperand::createExpr(getExpr()));
642   }
643 
644   void addS16ImmOperands(MCInst &Inst, unsigned N) const {
645     assert(N == 1 && "Invalid number of operands!");
646     switch (Kind) {
647       case Immediate:
648         Inst.addOperand(MCOperand::createImm(getImm()));
649         break;
650       case ContextImmediate:
651         Inst.addOperand(MCOperand::createImm(getImmS16Context()));
652         break;
653       default:
654         Inst.addOperand(MCOperand::createExpr(getExpr()));
655         break;
656     }
657   }
658 
659   void addU16ImmOperands(MCInst &Inst, unsigned N) const {
660     assert(N == 1 && "Invalid number of operands!");
661     switch (Kind) {
662       case Immediate:
663         Inst.addOperand(MCOperand::createImm(getImm()));
664         break;
665       case ContextImmediate:
666         Inst.addOperand(MCOperand::createImm(getImmU16Context()));
667         break;
668       default:
669         Inst.addOperand(MCOperand::createExpr(getExpr()));
670         break;
671     }
672   }
673 
674   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
675     assert(N == 1 && "Invalid number of operands!");
676     if (Kind == Immediate)
677       Inst.addOperand(MCOperand::createImm(getImm() / 4));
678     else
679       Inst.addOperand(MCOperand::createExpr(getExpr()));
680   }
681 
682   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
683     assert(N == 1 && "Invalid number of operands!");
684     Inst.addOperand(MCOperand::createExpr(getTLSReg()));
685   }
686 
687   StringRef getToken() const {
688     assert(Kind == Token && "Invalid access!");
689     return StringRef(Tok.Data, Tok.Length);
690   }
691 
692   void print(raw_ostream &OS) const override;
693 
694   static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
695                                                  bool IsPPC64) {
696     auto Op = make_unique<PPCOperand>(Token);
697     Op->Tok.Data = Str.data();
698     Op->Tok.Length = Str.size();
699     Op->StartLoc = S;
700     Op->EndLoc = S;
701     Op->IsPPC64 = IsPPC64;
702     return Op;
703   }
704 
705   static std::unique_ptr<PPCOperand>
706   CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
707     // Allocate extra memory for the string and copy it.
708     // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
709     // deleter which will destroy them by simply using "delete", not correctly
710     // calling operator delete on this extra memory after calling the dtor
711     // explicitly.
712     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
713     std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
714     Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
715     Op->Tok.Length = Str.size();
716     std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
717     Op->StartLoc = S;
718     Op->EndLoc = S;
719     Op->IsPPC64 = IsPPC64;
720     return Op;
721   }
722 
723   static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
724                                                bool IsPPC64) {
725     auto Op = make_unique<PPCOperand>(Immediate);
726     Op->Imm.Val = Val;
727     Op->StartLoc = S;
728     Op->EndLoc = E;
729     Op->IsPPC64 = IsPPC64;
730     return Op;
731   }
732 
733   static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
734                                                 SMLoc E, bool IsPPC64) {
735     auto Op = make_unique<PPCOperand>(Expression);
736     Op->Expr.Val = Val;
737     Op->Expr.CRVal = EvaluateCRExpr(Val);
738     Op->StartLoc = S;
739     Op->EndLoc = E;
740     Op->IsPPC64 = IsPPC64;
741     return Op;
742   }
743 
744   static std::unique_ptr<PPCOperand>
745   CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
746     auto Op = make_unique<PPCOperand>(TLSRegister);
747     Op->TLSReg.Sym = Sym;
748     Op->StartLoc = S;
749     Op->EndLoc = E;
750     Op->IsPPC64 = IsPPC64;
751     return Op;
752   }
753 
754   static std::unique_ptr<PPCOperand>
755   CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
756     auto Op = make_unique<PPCOperand>(ContextImmediate);
757     Op->Imm.Val = Val;
758     Op->StartLoc = S;
759     Op->EndLoc = E;
760     Op->IsPPC64 = IsPPC64;
761     return Op;
762   }
763 
764   static std::unique_ptr<PPCOperand>
765   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
766     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
767       return CreateImm(CE->getValue(), S, E, IsPPC64);
768 
769     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
770       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
771         return CreateTLSReg(SRE, S, E, IsPPC64);
772 
773     if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
774       int64_t Res;
775       if (TE->evaluateAsConstant(Res))
776         return CreateContextImm(Res, S, E, IsPPC64);
777     }
778 
779     return CreateExpr(Val, S, E, IsPPC64);
780   }
781 };
782 
783 } // end anonymous namespace.
784 
785 void PPCOperand::print(raw_ostream &OS) const {
786   switch (Kind) {
787   case Token:
788     OS << "'" << getToken() << "'";
789     break;
790   case Immediate:
791   case ContextImmediate:
792     OS << getImm();
793     break;
794   case Expression:
795     OS << *getExpr();
796     break;
797   case TLSRegister:
798     OS << *getTLSReg();
799     break;
800   }
801 }
802 
803 static void
804 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
805   if (Op.isImm()) {
806     Inst.addOperand(MCOperand::createImm(-Op.getImm()));
807     return;
808   }
809   const MCExpr *Expr = Op.getExpr();
810   if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
811     if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
812       Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
813       return;
814     }
815   } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
816     if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
817       const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
818                                                  BinExpr->getLHS(), Ctx);
819       Inst.addOperand(MCOperand::createExpr(NE));
820       return;
821     }
822   }
823   Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx)));
824 }
825 
826 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
827                                       const OperandVector &Operands) {
828   int Opcode = Inst.getOpcode();
829   switch (Opcode) {
830   case PPC::DCBTx:
831   case PPC::DCBTT:
832   case PPC::DCBTSTx:
833   case PPC::DCBTSTT: {
834     MCInst TmpInst;
835     TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
836                       PPC::DCBT : PPC::DCBTST);
837     TmpInst.addOperand(MCOperand::createImm(
838       (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
839     TmpInst.addOperand(Inst.getOperand(0));
840     TmpInst.addOperand(Inst.getOperand(1));
841     Inst = TmpInst;
842     break;
843   }
844   case PPC::DCBTCT:
845   case PPC::DCBTDS: {
846     MCInst TmpInst;
847     TmpInst.setOpcode(PPC::DCBT);
848     TmpInst.addOperand(Inst.getOperand(2));
849     TmpInst.addOperand(Inst.getOperand(0));
850     TmpInst.addOperand(Inst.getOperand(1));
851     Inst = TmpInst;
852     break;
853   }
854   case PPC::DCBTSTCT:
855   case PPC::DCBTSTDS: {
856     MCInst TmpInst;
857     TmpInst.setOpcode(PPC::DCBTST);
858     TmpInst.addOperand(Inst.getOperand(2));
859     TmpInst.addOperand(Inst.getOperand(0));
860     TmpInst.addOperand(Inst.getOperand(1));
861     Inst = TmpInst;
862     break;
863   }
864   case PPC::LAx: {
865     MCInst TmpInst;
866     TmpInst.setOpcode(PPC::LA);
867     TmpInst.addOperand(Inst.getOperand(0));
868     TmpInst.addOperand(Inst.getOperand(2));
869     TmpInst.addOperand(Inst.getOperand(1));
870     Inst = TmpInst;
871     break;
872   }
873   case PPC::SUBI: {
874     MCInst TmpInst;
875     TmpInst.setOpcode(PPC::ADDI);
876     TmpInst.addOperand(Inst.getOperand(0));
877     TmpInst.addOperand(Inst.getOperand(1));
878     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
879     Inst = TmpInst;
880     break;
881   }
882   case PPC::SUBIS: {
883     MCInst TmpInst;
884     TmpInst.setOpcode(PPC::ADDIS);
885     TmpInst.addOperand(Inst.getOperand(0));
886     TmpInst.addOperand(Inst.getOperand(1));
887     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
888     Inst = TmpInst;
889     break;
890   }
891   case PPC::SUBIC: {
892     MCInst TmpInst;
893     TmpInst.setOpcode(PPC::ADDIC);
894     TmpInst.addOperand(Inst.getOperand(0));
895     TmpInst.addOperand(Inst.getOperand(1));
896     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
897     Inst = TmpInst;
898     break;
899   }
900   case PPC::SUBICo: {
901     MCInst TmpInst;
902     TmpInst.setOpcode(PPC::ADDICo);
903     TmpInst.addOperand(Inst.getOperand(0));
904     TmpInst.addOperand(Inst.getOperand(1));
905     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
906     Inst = TmpInst;
907     break;
908   }
909   case PPC::EXTLWI:
910   case PPC::EXTLWIo: {
911     MCInst TmpInst;
912     int64_t N = Inst.getOperand(2).getImm();
913     int64_t B = Inst.getOperand(3).getImm();
914     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
915     TmpInst.addOperand(Inst.getOperand(0));
916     TmpInst.addOperand(Inst.getOperand(1));
917     TmpInst.addOperand(MCOperand::createImm(B));
918     TmpInst.addOperand(MCOperand::createImm(0));
919     TmpInst.addOperand(MCOperand::createImm(N - 1));
920     Inst = TmpInst;
921     break;
922   }
923   case PPC::EXTRWI:
924   case PPC::EXTRWIo: {
925     MCInst TmpInst;
926     int64_t N = Inst.getOperand(2).getImm();
927     int64_t B = Inst.getOperand(3).getImm();
928     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
929     TmpInst.addOperand(Inst.getOperand(0));
930     TmpInst.addOperand(Inst.getOperand(1));
931     TmpInst.addOperand(MCOperand::createImm(B + N));
932     TmpInst.addOperand(MCOperand::createImm(32 - N));
933     TmpInst.addOperand(MCOperand::createImm(31));
934     Inst = TmpInst;
935     break;
936   }
937   case PPC::INSLWI:
938   case PPC::INSLWIo: {
939     MCInst TmpInst;
940     int64_t N = Inst.getOperand(2).getImm();
941     int64_t B = Inst.getOperand(3).getImm();
942     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
943     TmpInst.addOperand(Inst.getOperand(0));
944     TmpInst.addOperand(Inst.getOperand(0));
945     TmpInst.addOperand(Inst.getOperand(1));
946     TmpInst.addOperand(MCOperand::createImm(32 - B));
947     TmpInst.addOperand(MCOperand::createImm(B));
948     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
949     Inst = TmpInst;
950     break;
951   }
952   case PPC::INSRWI:
953   case PPC::INSRWIo: {
954     MCInst TmpInst;
955     int64_t N = Inst.getOperand(2).getImm();
956     int64_t B = Inst.getOperand(3).getImm();
957     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
958     TmpInst.addOperand(Inst.getOperand(0));
959     TmpInst.addOperand(Inst.getOperand(0));
960     TmpInst.addOperand(Inst.getOperand(1));
961     TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
962     TmpInst.addOperand(MCOperand::createImm(B));
963     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
964     Inst = TmpInst;
965     break;
966   }
967   case PPC::ROTRWI:
968   case PPC::ROTRWIo: {
969     MCInst TmpInst;
970     int64_t N = Inst.getOperand(2).getImm();
971     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
972     TmpInst.addOperand(Inst.getOperand(0));
973     TmpInst.addOperand(Inst.getOperand(1));
974     TmpInst.addOperand(MCOperand::createImm(32 - N));
975     TmpInst.addOperand(MCOperand::createImm(0));
976     TmpInst.addOperand(MCOperand::createImm(31));
977     Inst = TmpInst;
978     break;
979   }
980   case PPC::SLWI:
981   case PPC::SLWIo: {
982     MCInst TmpInst;
983     int64_t N = Inst.getOperand(2).getImm();
984     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
985     TmpInst.addOperand(Inst.getOperand(0));
986     TmpInst.addOperand(Inst.getOperand(1));
987     TmpInst.addOperand(MCOperand::createImm(N));
988     TmpInst.addOperand(MCOperand::createImm(0));
989     TmpInst.addOperand(MCOperand::createImm(31 - N));
990     Inst = TmpInst;
991     break;
992   }
993   case PPC::SRWI:
994   case PPC::SRWIo: {
995     MCInst TmpInst;
996     int64_t N = Inst.getOperand(2).getImm();
997     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
998     TmpInst.addOperand(Inst.getOperand(0));
999     TmpInst.addOperand(Inst.getOperand(1));
1000     TmpInst.addOperand(MCOperand::createImm(32 - N));
1001     TmpInst.addOperand(MCOperand::createImm(N));
1002     TmpInst.addOperand(MCOperand::createImm(31));
1003     Inst = TmpInst;
1004     break;
1005   }
1006   case PPC::CLRRWI:
1007   case PPC::CLRRWIo: {
1008     MCInst TmpInst;
1009     int64_t N = Inst.getOperand(2).getImm();
1010     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
1011     TmpInst.addOperand(Inst.getOperand(0));
1012     TmpInst.addOperand(Inst.getOperand(1));
1013     TmpInst.addOperand(MCOperand::createImm(0));
1014     TmpInst.addOperand(MCOperand::createImm(0));
1015     TmpInst.addOperand(MCOperand::createImm(31 - N));
1016     Inst = TmpInst;
1017     break;
1018   }
1019   case PPC::CLRLSLWI:
1020   case PPC::CLRLSLWIo: {
1021     MCInst TmpInst;
1022     int64_t B = Inst.getOperand(2).getImm();
1023     int64_t N = Inst.getOperand(3).getImm();
1024     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
1025     TmpInst.addOperand(Inst.getOperand(0));
1026     TmpInst.addOperand(Inst.getOperand(1));
1027     TmpInst.addOperand(MCOperand::createImm(N));
1028     TmpInst.addOperand(MCOperand::createImm(B - N));
1029     TmpInst.addOperand(MCOperand::createImm(31 - N));
1030     Inst = TmpInst;
1031     break;
1032   }
1033   case PPC::EXTLDI:
1034   case PPC::EXTLDIo: {
1035     MCInst TmpInst;
1036     int64_t N = Inst.getOperand(2).getImm();
1037     int64_t B = Inst.getOperand(3).getImm();
1038     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1039     TmpInst.addOperand(Inst.getOperand(0));
1040     TmpInst.addOperand(Inst.getOperand(1));
1041     TmpInst.addOperand(MCOperand::createImm(B));
1042     TmpInst.addOperand(MCOperand::createImm(N - 1));
1043     Inst = TmpInst;
1044     break;
1045   }
1046   case PPC::EXTRDI:
1047   case PPC::EXTRDIo: {
1048     MCInst TmpInst;
1049     int64_t N = Inst.getOperand(2).getImm();
1050     int64_t B = Inst.getOperand(3).getImm();
1051     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1052     TmpInst.addOperand(Inst.getOperand(0));
1053     TmpInst.addOperand(Inst.getOperand(1));
1054     TmpInst.addOperand(MCOperand::createImm(B + N));
1055     TmpInst.addOperand(MCOperand::createImm(64 - N));
1056     Inst = TmpInst;
1057     break;
1058   }
1059   case PPC::INSRDI:
1060   case PPC::INSRDIo: {
1061     MCInst TmpInst;
1062     int64_t N = Inst.getOperand(2).getImm();
1063     int64_t B = Inst.getOperand(3).getImm();
1064     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1065     TmpInst.addOperand(Inst.getOperand(0));
1066     TmpInst.addOperand(Inst.getOperand(0));
1067     TmpInst.addOperand(Inst.getOperand(1));
1068     TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
1069     TmpInst.addOperand(MCOperand::createImm(B));
1070     Inst = TmpInst;
1071     break;
1072   }
1073   case PPC::ROTRDI:
1074   case PPC::ROTRDIo: {
1075     MCInst TmpInst;
1076     int64_t N = Inst.getOperand(2).getImm();
1077     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1078     TmpInst.addOperand(Inst.getOperand(0));
1079     TmpInst.addOperand(Inst.getOperand(1));
1080     TmpInst.addOperand(MCOperand::createImm(64 - N));
1081     TmpInst.addOperand(MCOperand::createImm(0));
1082     Inst = TmpInst;
1083     break;
1084   }
1085   case PPC::SLDI:
1086   case PPC::SLDIo: {
1087     MCInst TmpInst;
1088     int64_t N = Inst.getOperand(2).getImm();
1089     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1090     TmpInst.addOperand(Inst.getOperand(0));
1091     TmpInst.addOperand(Inst.getOperand(1));
1092     TmpInst.addOperand(MCOperand::createImm(N));
1093     TmpInst.addOperand(MCOperand::createImm(63 - N));
1094     Inst = TmpInst;
1095     break;
1096   }
1097   case PPC::SRDI:
1098   case PPC::SRDIo: {
1099     MCInst TmpInst;
1100     int64_t N = Inst.getOperand(2).getImm();
1101     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1102     TmpInst.addOperand(Inst.getOperand(0));
1103     TmpInst.addOperand(Inst.getOperand(1));
1104     TmpInst.addOperand(MCOperand::createImm(64 - N));
1105     TmpInst.addOperand(MCOperand::createImm(N));
1106     Inst = TmpInst;
1107     break;
1108   }
1109   case PPC::CLRRDI:
1110   case PPC::CLRRDIo: {
1111     MCInst TmpInst;
1112     int64_t N = Inst.getOperand(2).getImm();
1113     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1114     TmpInst.addOperand(Inst.getOperand(0));
1115     TmpInst.addOperand(Inst.getOperand(1));
1116     TmpInst.addOperand(MCOperand::createImm(0));
1117     TmpInst.addOperand(MCOperand::createImm(63 - N));
1118     Inst = TmpInst;
1119     break;
1120   }
1121   case PPC::CLRLSLDI:
1122   case PPC::CLRLSLDIo: {
1123     MCInst TmpInst;
1124     int64_t B = Inst.getOperand(2).getImm();
1125     int64_t N = Inst.getOperand(3).getImm();
1126     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1127     TmpInst.addOperand(Inst.getOperand(0));
1128     TmpInst.addOperand(Inst.getOperand(1));
1129     TmpInst.addOperand(MCOperand::createImm(N));
1130     TmpInst.addOperand(MCOperand::createImm(B - N));
1131     Inst = TmpInst;
1132     break;
1133   }
1134   case PPC::RLWINMbm:
1135   case PPC::RLWINMobm: {
1136     unsigned MB, ME;
1137     int64_t BM = Inst.getOperand(3).getImm();
1138     if (!isRunOfOnes(BM, MB, ME))
1139       break;
1140 
1141     MCInst TmpInst;
1142     TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1143     TmpInst.addOperand(Inst.getOperand(0));
1144     TmpInst.addOperand(Inst.getOperand(1));
1145     TmpInst.addOperand(Inst.getOperand(2));
1146     TmpInst.addOperand(MCOperand::createImm(MB));
1147     TmpInst.addOperand(MCOperand::createImm(ME));
1148     Inst = TmpInst;
1149     break;
1150   }
1151   case PPC::RLWIMIbm:
1152   case PPC::RLWIMIobm: {
1153     unsigned MB, ME;
1154     int64_t BM = Inst.getOperand(3).getImm();
1155     if (!isRunOfOnes(BM, MB, ME))
1156       break;
1157 
1158     MCInst TmpInst;
1159     TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1160     TmpInst.addOperand(Inst.getOperand(0));
1161     TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1162     TmpInst.addOperand(Inst.getOperand(1));
1163     TmpInst.addOperand(Inst.getOperand(2));
1164     TmpInst.addOperand(MCOperand::createImm(MB));
1165     TmpInst.addOperand(MCOperand::createImm(ME));
1166     Inst = TmpInst;
1167     break;
1168   }
1169   case PPC::RLWNMbm:
1170   case PPC::RLWNMobm: {
1171     unsigned MB, ME;
1172     int64_t BM = Inst.getOperand(3).getImm();
1173     if (!isRunOfOnes(BM, MB, ME))
1174       break;
1175 
1176     MCInst TmpInst;
1177     TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1178     TmpInst.addOperand(Inst.getOperand(0));
1179     TmpInst.addOperand(Inst.getOperand(1));
1180     TmpInst.addOperand(Inst.getOperand(2));
1181     TmpInst.addOperand(MCOperand::createImm(MB));
1182     TmpInst.addOperand(MCOperand::createImm(ME));
1183     Inst = TmpInst;
1184     break;
1185   }
1186   case PPC::MFTB: {
1187     if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1188       assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1189       Inst.setOpcode(PPC::MFSPR);
1190     }
1191     break;
1192   }
1193   }
1194 }
1195 
1196 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1197                                            OperandVector &Operands,
1198                                            MCStreamer &Out, uint64_t &ErrorInfo,
1199                                            bool MatchingInlineAsm) {
1200   MCInst Inst;
1201 
1202   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1203   case Match_Success:
1204     // Post-process instructions (typically extended mnemonics)
1205     ProcessInstruction(Inst, Operands);
1206     Inst.setLoc(IDLoc);
1207     Out.EmitInstruction(Inst, getSTI());
1208     return false;
1209   case Match_MissingFeature:
1210     return Error(IDLoc, "instruction use requires an option to be enabled");
1211   case Match_MnemonicFail:
1212     return Error(IDLoc, "unrecognized instruction mnemonic");
1213   case Match_InvalidOperand: {
1214     SMLoc ErrorLoc = IDLoc;
1215     if (ErrorInfo != ~0ULL) {
1216       if (ErrorInfo >= Operands.size())
1217         return Error(IDLoc, "too few operands for instruction");
1218 
1219       ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1220       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1221     }
1222 
1223     return Error(ErrorLoc, "invalid operand for instruction");
1224   }
1225   }
1226 
1227   llvm_unreachable("Implement any new match types added!");
1228 }
1229 
1230 bool PPCAsmParser::
1231 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1232   if (Tok.is(AsmToken::Identifier)) {
1233     StringRef Name = Tok.getString();
1234 
1235     if (Name.equals_lower("lr")) {
1236       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1237       IntVal = 8;
1238       return false;
1239     } else if (Name.equals_lower("ctr")) {
1240       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1241       IntVal = 9;
1242       return false;
1243     } else if (Name.equals_lower("vrsave")) {
1244       RegNo = PPC::VRSAVE;
1245       IntVal = 256;
1246       return false;
1247     } else if (Name.startswith_lower("r") &&
1248                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1249       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1250       return false;
1251     } else if (Name.startswith_lower("f") &&
1252                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1253       RegNo = FRegs[IntVal];
1254       return false;
1255     } else if (Name.startswith_lower("vs") &&
1256                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1257       RegNo = VSRegs[IntVal];
1258       return false;
1259     } else if (Name.startswith_lower("v") &&
1260                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1261       RegNo = VRegs[IntVal];
1262       return false;
1263     } else if (Name.startswith_lower("q") &&
1264                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1265       RegNo = QFRegs[IntVal];
1266       return false;
1267     } else if (Name.startswith_lower("cr") &&
1268                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1269       RegNo = CRRegs[IntVal];
1270       return false;
1271     }
1272   }
1273 
1274   return true;
1275 }
1276 
1277 bool PPCAsmParser::
1278 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1279   MCAsmParser &Parser = getParser();
1280   const AsmToken &Tok = Parser.getTok();
1281   StartLoc = Tok.getLoc();
1282   EndLoc = Tok.getEndLoc();
1283   RegNo = 0;
1284   int64_t IntVal;
1285 
1286   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1287     Parser.Lex(); // Eat identifier token.
1288     return false;
1289   }
1290 
1291   return Error(StartLoc, "invalid register name");
1292 }
1293 
1294 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1295 /// the expression and check for VK_PPC_LO/HI/HA
1296 /// symbol variants.  If all symbols with modifier use the same
1297 /// variant, return the corresponding PPCMCExpr::VariantKind,
1298 /// and a modified expression using the default symbol variant.
1299 /// Otherwise, return NULL.
1300 const MCExpr *PPCAsmParser::
1301 ExtractModifierFromExpr(const MCExpr *E,
1302                         PPCMCExpr::VariantKind &Variant) {
1303   MCContext &Context = getParser().getContext();
1304   Variant = PPCMCExpr::VK_PPC_None;
1305 
1306   switch (E->getKind()) {
1307   case MCExpr::Target:
1308   case MCExpr::Constant:
1309     return nullptr;
1310 
1311   case MCExpr::SymbolRef: {
1312     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1313 
1314     switch (SRE->getKind()) {
1315     case MCSymbolRefExpr::VK_PPC_LO:
1316       Variant = PPCMCExpr::VK_PPC_LO;
1317       break;
1318     case MCSymbolRefExpr::VK_PPC_HI:
1319       Variant = PPCMCExpr::VK_PPC_HI;
1320       break;
1321     case MCSymbolRefExpr::VK_PPC_HA:
1322       Variant = PPCMCExpr::VK_PPC_HA;
1323       break;
1324     case MCSymbolRefExpr::VK_PPC_HIGHER:
1325       Variant = PPCMCExpr::VK_PPC_HIGHER;
1326       break;
1327     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1328       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1329       break;
1330     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1331       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1332       break;
1333     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1334       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1335       break;
1336     default:
1337       return nullptr;
1338     }
1339 
1340     return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1341   }
1342 
1343   case MCExpr::Unary: {
1344     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1345     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1346     if (!Sub)
1347       return nullptr;
1348     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1349   }
1350 
1351   case MCExpr::Binary: {
1352     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1353     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1354     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1355     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1356 
1357     if (!LHS && !RHS)
1358       return nullptr;
1359 
1360     if (!LHS) LHS = BE->getLHS();
1361     if (!RHS) RHS = BE->getRHS();
1362 
1363     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1364       Variant = RHSVariant;
1365     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1366       Variant = LHSVariant;
1367     else if (LHSVariant == RHSVariant)
1368       Variant = LHSVariant;
1369     else
1370       return nullptr;
1371 
1372     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1373   }
1374   }
1375 
1376   llvm_unreachable("Invalid expression kind!");
1377 }
1378 
1379 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1380 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1381 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1382 /// FIXME: This is a hack.
1383 const MCExpr *PPCAsmParser::
1384 FixupVariantKind(const MCExpr *E) {
1385   MCContext &Context = getParser().getContext();
1386 
1387   switch (E->getKind()) {
1388   case MCExpr::Target:
1389   case MCExpr::Constant:
1390     return E;
1391 
1392   case MCExpr::SymbolRef: {
1393     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1394     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1395 
1396     switch (SRE->getKind()) {
1397     case MCSymbolRefExpr::VK_TLSGD:
1398       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1399       break;
1400     case MCSymbolRefExpr::VK_TLSLD:
1401       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1402       break;
1403     default:
1404       return E;
1405     }
1406     return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1407   }
1408 
1409   case MCExpr::Unary: {
1410     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1411     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1412     if (Sub == UE->getSubExpr())
1413       return E;
1414     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1415   }
1416 
1417   case MCExpr::Binary: {
1418     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1419     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1420     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1421     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1422       return E;
1423     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1424   }
1425   }
1426 
1427   llvm_unreachable("Invalid expression kind!");
1428 }
1429 
1430 /// ParseExpression.  This differs from the default "parseExpression" in that
1431 /// it handles modifiers.
1432 bool PPCAsmParser::
1433 ParseExpression(const MCExpr *&EVal) {
1434 
1435   if (isDarwin())
1436     return ParseDarwinExpression(EVal);
1437 
1438   // (ELF Platforms)
1439   // Handle \code @l/@ha \endcode
1440   if (getParser().parseExpression(EVal))
1441     return true;
1442 
1443   EVal = FixupVariantKind(EVal);
1444 
1445   PPCMCExpr::VariantKind Variant;
1446   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1447   if (E)
1448     EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext());
1449 
1450   return false;
1451 }
1452 
1453 /// ParseDarwinExpression.  (MachO Platforms)
1454 /// This differs from the default "parseExpression" in that it handles detection
1455 /// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1456 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1457 /// syntax form so it is done here.  TODO: Determine if there is merit in arranging
1458 /// for this to be done at a higher level.
1459 bool PPCAsmParser::
1460 ParseDarwinExpression(const MCExpr *&EVal) {
1461   MCAsmParser &Parser = getParser();
1462   PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1463   switch (getLexer().getKind()) {
1464   default:
1465     break;
1466   case AsmToken::Identifier:
1467     // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1468     // something starting with any other char should be part of the
1469     // asm syntax.  If handwritten asm includes an identifier like lo16,
1470     // then all bets are off - but no-one would do that, right?
1471     StringRef poss = Parser.getTok().getString();
1472     if (poss.equals_lower("lo16")) {
1473       Variant = PPCMCExpr::VK_PPC_LO;
1474     } else if (poss.equals_lower("hi16")) {
1475       Variant = PPCMCExpr::VK_PPC_HI;
1476     } else if (poss.equals_lower("ha16")) {
1477       Variant = PPCMCExpr::VK_PPC_HA;
1478     }
1479     if (Variant != PPCMCExpr::VK_PPC_None) {
1480       Parser.Lex(); // Eat the xx16
1481       if (getLexer().isNot(AsmToken::LParen))
1482         return Error(Parser.getTok().getLoc(), "expected '('");
1483       Parser.Lex(); // Eat the '('
1484     }
1485     break;
1486   }
1487 
1488   if (getParser().parseExpression(EVal))
1489     return true;
1490 
1491   if (Variant != PPCMCExpr::VK_PPC_None) {
1492     if (getLexer().isNot(AsmToken::RParen))
1493       return Error(Parser.getTok().getLoc(), "expected ')'");
1494     Parser.Lex(); // Eat the ')'
1495     EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext());
1496   }
1497   return false;
1498 }
1499 
1500 /// ParseOperand
1501 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1502 /// rNN for MachO.
1503 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1504   MCAsmParser &Parser = getParser();
1505   SMLoc S = Parser.getTok().getLoc();
1506   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1507   const MCExpr *EVal;
1508 
1509   // Attempt to parse the next token as an immediate
1510   switch (getLexer().getKind()) {
1511   // Special handling for register names.  These are interpreted
1512   // as immediates corresponding to the register number.
1513   case AsmToken::Percent:
1514     Parser.Lex(); // Eat the '%'.
1515     unsigned RegNo;
1516     int64_t IntVal;
1517     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1518       Parser.Lex(); // Eat the identifier token.
1519       Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1520       return false;
1521     }
1522     return Error(S, "invalid register name");
1523 
1524   case AsmToken::Identifier:
1525     // Note that non-register-name identifiers from the compiler will begin
1526     // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1527     // identifiers like r31foo - so we fall through in the event that parsing
1528     // a register name fails.
1529     if (isDarwin()) {
1530       unsigned RegNo;
1531       int64_t IntVal;
1532       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1533         Parser.Lex(); // Eat the identifier token.
1534         Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1535         return false;
1536       }
1537     }
1538   // Fall-through to process non-register-name identifiers as expression.
1539   // All other expressions
1540   case AsmToken::LParen:
1541   case AsmToken::Plus:
1542   case AsmToken::Minus:
1543   case AsmToken::Integer:
1544   case AsmToken::Dot:
1545   case AsmToken::Dollar:
1546   case AsmToken::Exclaim:
1547   case AsmToken::Tilde:
1548     if (!ParseExpression(EVal))
1549       break;
1550     /* fall through */
1551   default:
1552     return Error(S, "unknown operand");
1553   }
1554 
1555   // Push the parsed operand into the list of operands
1556   Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1557 
1558   // Check whether this is a TLS call expression
1559   bool TLSCall = false;
1560   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1561     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1562 
1563   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1564     const MCExpr *TLSSym;
1565 
1566     Parser.Lex(); // Eat the '('.
1567     S = Parser.getTok().getLoc();
1568     if (ParseExpression(TLSSym))
1569       return Error(S, "invalid TLS call expression");
1570     if (getLexer().isNot(AsmToken::RParen))
1571       return Error(Parser.getTok().getLoc(), "missing ')'");
1572     E = Parser.getTok().getLoc();
1573     Parser.Lex(); // Eat the ')'.
1574 
1575     Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1576   }
1577 
1578   // Otherwise, check for D-form memory operands
1579   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1580     Parser.Lex(); // Eat the '('.
1581     S = Parser.getTok().getLoc();
1582 
1583     int64_t IntVal;
1584     switch (getLexer().getKind()) {
1585     case AsmToken::Percent:
1586       Parser.Lex(); // Eat the '%'.
1587       unsigned RegNo;
1588       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1589         return Error(S, "invalid register name");
1590       Parser.Lex(); // Eat the identifier token.
1591       break;
1592 
1593     case AsmToken::Integer:
1594       if (!isDarwin()) {
1595         if (getParser().parseAbsoluteExpression(IntVal) ||
1596           IntVal < 0 || IntVal > 31)
1597         return Error(S, "invalid register number");
1598       } else {
1599         return Error(S, "unexpected integer value");
1600       }
1601       break;
1602 
1603    case AsmToken::Identifier:
1604     if (isDarwin()) {
1605       unsigned RegNo;
1606       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1607         Parser.Lex(); // Eat the identifier token.
1608         break;
1609       }
1610     }
1611     // Fall-through..
1612 
1613     default:
1614       return Error(S, "invalid memory operand");
1615     }
1616 
1617     if (getLexer().isNot(AsmToken::RParen))
1618       return Error(Parser.getTok().getLoc(), "missing ')'");
1619     E = Parser.getTok().getLoc();
1620     Parser.Lex(); // Eat the ')'.
1621 
1622     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1623   }
1624 
1625   return false;
1626 }
1627 
1628 /// Parse an instruction mnemonic followed by its operands.
1629 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1630                                     SMLoc NameLoc, OperandVector &Operands) {
1631   // The first operand is the token for the instruction name.
1632   // If the next character is a '+' or '-', we need to add it to the
1633   // instruction name, to match what TableGen is doing.
1634   std::string NewOpcode;
1635   if (getLexer().is(AsmToken::Plus)) {
1636     getLexer().Lex();
1637     NewOpcode = Name;
1638     NewOpcode += '+';
1639     Name = NewOpcode;
1640   }
1641   if (getLexer().is(AsmToken::Minus)) {
1642     getLexer().Lex();
1643     NewOpcode = Name;
1644     NewOpcode += '-';
1645     Name = NewOpcode;
1646   }
1647   // If the instruction ends in a '.', we need to create a separate
1648   // token for it, to match what TableGen is doing.
1649   size_t Dot = Name.find('.');
1650   StringRef Mnemonic = Name.slice(0, Dot);
1651   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1652     Operands.push_back(
1653         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1654   else
1655     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1656   if (Dot != StringRef::npos) {
1657     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1658     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1659     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1660       Operands.push_back(
1661           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1662     else
1663       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1664   }
1665 
1666   // If there are no more operands then finish
1667   if (getLexer().is(AsmToken::EndOfStatement))
1668     return false;
1669 
1670   // Parse the first operand
1671   if (ParseOperand(Operands))
1672     return true;
1673 
1674   while (getLexer().isNot(AsmToken::EndOfStatement) &&
1675          getLexer().is(AsmToken::Comma)) {
1676     // Consume the comma token
1677     getLexer().Lex();
1678 
1679     // Parse the next operand
1680     if (ParseOperand(Operands))
1681       return true;
1682   }
1683 
1684   // We'll now deal with an unfortunate special case: the syntax for the dcbt
1685   // and dcbtst instructions differs for server vs. embedded cores.
1686   //  The syntax for dcbt is:
1687   //    dcbt ra, rb, th [server]
1688   //    dcbt th, ra, rb [embedded]
1689   //  where th can be omitted when it is 0. dcbtst is the same. We take the
1690   //  server form to be the default, so swap the operands if we're parsing for
1691   //  an embedded core (they'll be swapped again upon printing).
1692   if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1693       Operands.size() == 4 &&
1694       (Name == "dcbt" || Name == "dcbtst")) {
1695     std::swap(Operands[1], Operands[3]);
1696     std::swap(Operands[2], Operands[1]);
1697   }
1698 
1699   return false;
1700 }
1701 
1702 /// ParseDirective parses the PPC specific directives
1703 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1704   StringRef IDVal = DirectiveID.getIdentifier();
1705   if (!isDarwin()) {
1706     if (IDVal == ".word")
1707       return ParseDirectiveWord(2, DirectiveID.getLoc());
1708     if (IDVal == ".llong")
1709       return ParseDirectiveWord(8, DirectiveID.getLoc());
1710     if (IDVal == ".tc")
1711       return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1712     if (IDVal == ".machine")
1713       return ParseDirectiveMachine(DirectiveID.getLoc());
1714     if (IDVal == ".abiversion")
1715       return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1716     if (IDVal == ".localentry")
1717       return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1718   } else {
1719     if (IDVal == ".machine")
1720       return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1721   }
1722   return true;
1723 }
1724 
1725 /// ParseDirectiveWord
1726 ///  ::= .word [ expression (, expression)* ]
1727 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1728   MCAsmParser &Parser = getParser();
1729   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1730     for (;;) {
1731       const MCExpr *Value;
1732       SMLoc ExprLoc = getLexer().getLoc();
1733       if (getParser().parseExpression(Value))
1734         return false;
1735 
1736       if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1737         assert(Size <= 8 && "Invalid size");
1738         uint64_t IntValue = MCE->getValue();
1739         if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
1740           return Error(ExprLoc, "literal value out of range for directive");
1741         getStreamer().EmitIntValue(IntValue, Size);
1742       } else {
1743         getStreamer().EmitValue(Value, Size, ExprLoc);
1744       }
1745 
1746       if (getLexer().is(AsmToken::EndOfStatement))
1747         break;
1748 
1749       if (getLexer().isNot(AsmToken::Comma))
1750         return Error(L, "unexpected token in directive");
1751       Parser.Lex();
1752     }
1753   }
1754 
1755   Parser.Lex();
1756   return false;
1757 }
1758 
1759 /// ParseDirectiveTC
1760 ///  ::= .tc [ symbol (, expression)* ]
1761 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1762   MCAsmParser &Parser = getParser();
1763   // Skip TC symbol, which is only used with XCOFF.
1764   while (getLexer().isNot(AsmToken::EndOfStatement)
1765          && getLexer().isNot(AsmToken::Comma))
1766     Parser.Lex();
1767   if (getLexer().isNot(AsmToken::Comma)) {
1768     Error(L, "unexpected token in directive");
1769     return false;
1770   }
1771   Parser.Lex();
1772 
1773   // Align to word size.
1774   getParser().getStreamer().EmitValueToAlignment(Size);
1775 
1776   // Emit expressions.
1777   return ParseDirectiveWord(Size, L);
1778 }
1779 
1780 /// ParseDirectiveMachine (ELF platforms)
1781 ///  ::= .machine [ cpu | "push" | "pop" ]
1782 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1783   MCAsmParser &Parser = getParser();
1784   if (getLexer().isNot(AsmToken::Identifier) &&
1785       getLexer().isNot(AsmToken::String)) {
1786     Error(L, "unexpected token in directive");
1787     return false;
1788   }
1789 
1790   StringRef CPU = Parser.getTok().getIdentifier();
1791   Parser.Lex();
1792 
1793   // FIXME: Right now, the parser always allows any available
1794   // instruction, so the .machine directive is not useful.
1795   // Implement ".machine any" (by doing nothing) for the benefit
1796   // of existing assembler code.  Likewise, we can then implement
1797   // ".machine push" and ".machine pop" as no-op.
1798   if (CPU != "any" && CPU != "push" && CPU != "pop") {
1799     Error(L, "unrecognized machine type");
1800     return false;
1801   }
1802 
1803   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1804     Error(L, "unexpected token in directive");
1805     return false;
1806   }
1807   PPCTargetStreamer &TStreamer =
1808       *static_cast<PPCTargetStreamer *>(
1809            getParser().getStreamer().getTargetStreamer());
1810   TStreamer.emitMachine(CPU);
1811 
1812   return false;
1813 }
1814 
1815 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1816 ///  ::= .machine cpu-identifier
1817 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1818   MCAsmParser &Parser = getParser();
1819   if (getLexer().isNot(AsmToken::Identifier) &&
1820       getLexer().isNot(AsmToken::String)) {
1821     Error(L, "unexpected token in directive");
1822     return false;
1823   }
1824 
1825   StringRef CPU = Parser.getTok().getIdentifier();
1826   Parser.Lex();
1827 
1828   // FIXME: this is only the 'default' set of cpu variants.
1829   // However we don't act on this information at present, this is simply
1830   // allowing parsing to proceed with minimal sanity checking.
1831   if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1832     Error(L, "unrecognized cpu type");
1833     return false;
1834   }
1835 
1836   if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1837     Error(L, "wrong cpu type specified for 64bit");
1838     return false;
1839   }
1840   if (!isPPC64() && CPU == "ppc64") {
1841     Error(L, "wrong cpu type specified for 32bit");
1842     return false;
1843   }
1844 
1845   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1846     Error(L, "unexpected token in directive");
1847     return false;
1848   }
1849 
1850   return false;
1851 }
1852 
1853 /// ParseDirectiveAbiVersion
1854 ///  ::= .abiversion constant-expression
1855 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1856   int64_t AbiVersion;
1857   if (getParser().parseAbsoluteExpression(AbiVersion)){
1858     Error(L, "expected constant expression");
1859     return false;
1860   }
1861   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1862     Error(L, "unexpected token in directive");
1863     return false;
1864   }
1865 
1866   PPCTargetStreamer &TStreamer =
1867       *static_cast<PPCTargetStreamer *>(
1868            getParser().getStreamer().getTargetStreamer());
1869   TStreamer.emitAbiVersion(AbiVersion);
1870 
1871   return false;
1872 }
1873 
1874 /// ParseDirectiveLocalEntry
1875 ///  ::= .localentry symbol, expression
1876 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1877   StringRef Name;
1878   if (getParser().parseIdentifier(Name)) {
1879     Error(L, "expected identifier in directive");
1880     return false;
1881   }
1882   MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1883 
1884   if (getLexer().isNot(AsmToken::Comma)) {
1885     Error(L, "unexpected token in directive");
1886     return false;
1887   }
1888   Lex();
1889 
1890   const MCExpr *Expr;
1891   if (getParser().parseExpression(Expr)) {
1892     Error(L, "expected expression");
1893     return false;
1894   }
1895 
1896   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1897     Error(L, "unexpected token in directive");
1898     return false;
1899   }
1900 
1901   PPCTargetStreamer &TStreamer =
1902       *static_cast<PPCTargetStreamer *>(
1903            getParser().getStreamer().getTargetStreamer());
1904   TStreamer.emitLocalEntry(Sym, Expr);
1905 
1906   return false;
1907 }
1908 
1909 
1910 
1911 /// Force static initialization.
1912 extern "C" void LLVMInitializePowerPCAsmParser() {
1913   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1914   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1915   RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1916 }
1917 
1918 #define GET_REGISTER_MATCHER
1919 #define GET_MATCHER_IMPLEMENTATION
1920 #include "PPCGenAsmMatcher.inc"
1921 
1922 // Define this matcher function after the auto-generated include so we
1923 // have the match class enum definitions.
1924 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1925                                                   unsigned Kind) {
1926   // If the kind is a token for a literal immediate, check if our asm
1927   // operand matches. This is for InstAliases which have a fixed-value
1928   // immediate in the syntax.
1929   int64_t ImmVal;
1930   switch (Kind) {
1931     case MCK_0: ImmVal = 0; break;
1932     case MCK_1: ImmVal = 1; break;
1933     case MCK_2: ImmVal = 2; break;
1934     case MCK_3: ImmVal = 3; break;
1935     case MCK_4: ImmVal = 4; break;
1936     case MCK_5: ImmVal = 5; break;
1937     case MCK_6: ImmVal = 6; break;
1938     case MCK_7: ImmVal = 7; break;
1939     default: return Match_InvalidOperand;
1940   }
1941 
1942   PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1943   if (Op.isImm() && Op.getImm() == ImmVal)
1944     return Match_Success;
1945 
1946   return Match_InvalidOperand;
1947 }
1948 
1949 const MCExpr *
1950 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1951                                   MCSymbolRefExpr::VariantKind Variant,
1952                                   MCContext &Ctx) {
1953   switch (Variant) {
1954   case MCSymbolRefExpr::VK_PPC_LO:
1955     return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1956   case MCSymbolRefExpr::VK_PPC_HI:
1957     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1958   case MCSymbolRefExpr::VK_PPC_HA:
1959     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1960   case MCSymbolRefExpr::VK_PPC_HIGHER:
1961     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1962   case MCSymbolRefExpr::VK_PPC_HIGHERA:
1963     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1964   case MCSymbolRefExpr::VK_PPC_HIGHEST:
1965     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1966   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1967     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1968   default:
1969     return nullptr;
1970   }
1971 }
1972