xref: /llvm-project/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (revision ba532dc81648aca4cdf9ba4f5f16ecbc971e811c) 
1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCExpr.h"
11 #include "MCTargetDesc/PPCMCTargetDesc.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/MC/MCSymbolELF.h"
30 #include "llvm/Support/SourceMgr.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Support/raw_ostream.h"
33 
34 using namespace llvm;
35 
36 static const MCPhysReg RRegs[32] = {
37   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
38   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
39   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
40   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
41   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
42   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
43   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
44   PPC::R28, PPC::R29, PPC::R30, PPC::R31
45 };
46 static const MCPhysReg RRegsNoR0[32] = {
47   PPC::ZERO,
48             PPC::R1,  PPC::R2,  PPC::R3,
49   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
50   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
51   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
52   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
53   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
54   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
55   PPC::R28, PPC::R29, PPC::R30, PPC::R31
56 };
57 static const MCPhysReg XRegs[32] = {
58   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
59   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
60   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
61   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
62   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
63   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
64   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
65   PPC::X28, PPC::X29, PPC::X30, PPC::X31
66 };
67 static const MCPhysReg XRegsNoX0[32] = {
68   PPC::ZERO8,
69             PPC::X1,  PPC::X2,  PPC::X3,
70   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
71   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
72   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
73   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
74   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
75   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
76   PPC::X28, PPC::X29, PPC::X30, PPC::X31
77 };
78 static const MCPhysReg FRegs[32] = {
79   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
80   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
81   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
82   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
83   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
84   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
85   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
86   PPC::F28, PPC::F29, PPC::F30, PPC::F31
87 };
88 static const MCPhysReg VRegs[32] = {
89   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
90   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
91   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
92   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
93   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
94   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
95   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
96   PPC::V28, PPC::V29, PPC::V30, PPC::V31
97 };
98 static const MCPhysReg VSRegs[64] = {
99   PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
100   PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
101   PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
102   PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
103   PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
104   PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
105   PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
106   PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
107 
108   PPC::VSH0,  PPC::VSH1,  PPC::VSH2,  PPC::VSH3,
109   PPC::VSH4,  PPC::VSH5,  PPC::VSH6,  PPC::VSH7,
110   PPC::VSH8,  PPC::VSH9,  PPC::VSH10, PPC::VSH11,
111   PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
112   PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
113   PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
114   PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
115   PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
116 };
117 static const MCPhysReg VSFRegs[64] = {
118   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
119   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
120   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
121   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
122   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
123   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
124   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
125   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
126 
127   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
128   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
129   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
130   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
131   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
132   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
133   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
134   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
135 };
136 static const MCPhysReg VSSRegs[64] = {
137   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
138   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
139   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
140   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
141   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
142   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
143   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
144   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
145 
146   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
147   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
148   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
149   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
150   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
151   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
152   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
153   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
154 };
155 static unsigned QFRegs[32] = {
156   PPC::QF0,  PPC::QF1,  PPC::QF2,  PPC::QF3,
157   PPC::QF4,  PPC::QF5,  PPC::QF6,  PPC::QF7,
158   PPC::QF8,  PPC::QF9,  PPC::QF10, PPC::QF11,
159   PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
160   PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
161   PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
162   PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
163   PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
164 };
165 static const MCPhysReg CRBITRegs[32] = {
166   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
167   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
168   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
169   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
170   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
171   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
172   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
173   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
174 };
175 static const MCPhysReg CRRegs[8] = {
176   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
177   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
178 };
179 
180 // Evaluate an expression containing condition register
181 // or condition register field symbols.  Returns positive
182 // value on success, or -1 on error.
183 static int64_t
184 EvaluateCRExpr(const MCExpr *E) {
185   switch (E->getKind()) {
186   case MCExpr::Target:
187     return -1;
188 
189   case MCExpr::Constant: {
190     int64_t Res = cast<MCConstantExpr>(E)->getValue();
191     return Res < 0 ? -1 : Res;
192   }
193 
194   case MCExpr::SymbolRef: {
195     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
196     StringRef Name = SRE->getSymbol().getName();
197 
198     if (Name == "lt") return 0;
199     if (Name == "gt") return 1;
200     if (Name == "eq") return 2;
201     if (Name == "so") return 3;
202     if (Name == "un") return 3;
203 
204     if (Name == "cr0") return 0;
205     if (Name == "cr1") return 1;
206     if (Name == "cr2") return 2;
207     if (Name == "cr3") return 3;
208     if (Name == "cr4") return 4;
209     if (Name == "cr5") return 5;
210     if (Name == "cr6") return 6;
211     if (Name == "cr7") return 7;
212 
213     return -1;
214   }
215 
216   case MCExpr::Unary:
217     return -1;
218 
219   case MCExpr::Binary: {
220     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
221     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
222     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
223     int64_t Res;
224 
225     if (LHSVal < 0 || RHSVal < 0)
226       return -1;
227 
228     switch (BE->getOpcode()) {
229     default: return -1;
230     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
231     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
232     }
233 
234     return Res < 0 ? -1 : Res;
235   }
236   }
237 
238   llvm_unreachable("Invalid expression kind!");
239 }
240 
241 namespace {
242 
243 struct PPCOperand;
244 
245 class PPCAsmParser : public MCTargetAsmParser {
246   const MCInstrInfo &MII;
247   bool IsPPC64;
248   bool IsDarwin;
249 
250   void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
251   bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
252 
253   bool isPPC64() const { return IsPPC64; }
254   bool isDarwin() const { return IsDarwin; }
255 
256   bool MatchRegisterName(const AsmToken &Tok,
257                          unsigned &RegNo, int64_t &IntVal);
258 
259   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
260 
261   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
262                                         PPCMCExpr::VariantKind &Variant);
263   const MCExpr *FixupVariantKind(const MCExpr *E);
264   bool ParseExpression(const MCExpr *&EVal);
265   bool ParseDarwinExpression(const MCExpr *&EVal);
266 
267   bool ParseOperand(OperandVector &Operands);
268 
269   bool ParseDirectiveWord(unsigned Size, SMLoc L);
270   bool ParseDirectiveTC(unsigned Size, SMLoc L);
271   bool ParseDirectiveMachine(SMLoc L);
272   bool ParseDarwinDirectiveMachine(SMLoc L);
273   bool ParseDirectiveAbiVersion(SMLoc L);
274   bool ParseDirectiveLocalEntry(SMLoc L);
275 
276   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
277                                OperandVector &Operands, MCStreamer &Out,
278                                uint64_t &ErrorInfo,
279                                bool MatchingInlineAsm) override;
280 
281   void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
282 
283   /// @name Auto-generated Match Functions
284   /// {
285 
286 #define GET_ASSEMBLER_HEADER
287 #include "PPCGenAsmMatcher.inc"
288 
289   /// }
290 
291 
292 public:
293   PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
294                const MCInstrInfo &MII, const MCTargetOptions &Options)
295     : MCTargetAsmParser(Options, STI), MII(MII) {
296     // Check for 64-bit vs. 32-bit pointer mode.
297     Triple TheTriple(STI.getTargetTriple());
298     IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
299                TheTriple.getArch() == Triple::ppc64le);
300     IsDarwin = TheTriple.isMacOSX();
301     // Initialize the set of available features.
302     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
303   }
304 
305   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
306                         SMLoc NameLoc, OperandVector &Operands) override;
307 
308   bool ParseDirective(AsmToken DirectiveID) override;
309 
310   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
311                                       unsigned Kind) override;
312 
313   const MCExpr *applyModifierToExpr(const MCExpr *E,
314                                     MCSymbolRefExpr::VariantKind,
315                                     MCContext &Ctx) override;
316 };
317 
318 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
319 /// instruction.
320 struct PPCOperand : public MCParsedAsmOperand {
321   enum KindTy {
322     Token,
323     Immediate,
324     ContextImmediate,
325     Expression,
326     TLSRegister
327   } Kind;
328 
329   SMLoc StartLoc, EndLoc;
330   bool IsPPC64;
331 
332   struct TokOp {
333     const char *Data;
334     unsigned Length;
335   };
336 
337   struct ImmOp {
338     int64_t Val;
339   };
340 
341   struct ExprOp {
342     const MCExpr *Val;
343     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
344   };
345 
346   struct TLSRegOp {
347     const MCSymbolRefExpr *Sym;
348   };
349 
350   union {
351     struct TokOp Tok;
352     struct ImmOp Imm;
353     struct ExprOp Expr;
354     struct TLSRegOp TLSReg;
355   };
356 
357   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
358 public:
359   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
360     Kind = o.Kind;
361     StartLoc = o.StartLoc;
362     EndLoc = o.EndLoc;
363     IsPPC64 = o.IsPPC64;
364     switch (Kind) {
365     case Token:
366       Tok = o.Tok;
367       break;
368     case Immediate:
369     case ContextImmediate:
370       Imm = o.Imm;
371       break;
372     case Expression:
373       Expr = o.Expr;
374       break;
375     case TLSRegister:
376       TLSReg = o.TLSReg;
377       break;
378     }
379   }
380 
381   // Disable use of sized deallocation due to overallocation of PPCOperand
382   // objects in CreateTokenWithStringCopy.
383   void operator delete(void *p) { ::operator delete(p); }
384 
385   /// getStartLoc - Get the location of the first token of this operand.
386   SMLoc getStartLoc() const override { return StartLoc; }
387 
388   /// getEndLoc - Get the location of the last token of this operand.
389   SMLoc getEndLoc() const override { return EndLoc; }
390 
391   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
392   bool isPPC64() const { return IsPPC64; }
393 
394   int64_t getImm() const {
395     assert(Kind == Immediate && "Invalid access!");
396     return Imm.Val;
397   }
398   int64_t getImmS16Context() const {
399     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
400     if (Kind == Immediate)
401       return Imm.Val;
402     return static_cast<int16_t>(Imm.Val);
403   }
404   int64_t getImmU16Context() const {
405     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
406     return Imm.Val;
407   }
408 
409   const MCExpr *getExpr() const {
410     assert(Kind == Expression && "Invalid access!");
411     return Expr.Val;
412   }
413 
414   int64_t getExprCRVal() const {
415     assert(Kind == Expression && "Invalid access!");
416     return Expr.CRVal;
417   }
418 
419   const MCExpr *getTLSReg() const {
420     assert(Kind == TLSRegister && "Invalid access!");
421     return TLSReg.Sym;
422   }
423 
424   unsigned getReg() const override {
425     assert(isRegNumber() && "Invalid access!");
426     return (unsigned) Imm.Val;
427   }
428 
429   unsigned getVSReg() const {
430     assert(isVSRegNumber() && "Invalid access!");
431     return (unsigned) Imm.Val;
432   }
433 
434   unsigned getCCReg() const {
435     assert(isCCRegNumber() && "Invalid access!");
436     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
437   }
438 
439   unsigned getCRBit() const {
440     assert(isCRBitNumber() && "Invalid access!");
441     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
442   }
443 
444   unsigned getCRBitMask() const {
445     assert(isCRBitMask() && "Invalid access!");
446     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
447   }
448 
449   bool isToken() const override { return Kind == Token; }
450   bool isImm() const override { return Kind == Immediate || Kind == Expression; }
451   bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
452   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
453   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
454   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
455   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
456   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
457   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
458   bool isU6ImmX2() const { return Kind == Immediate &&
459                                   isUInt<6>(getImm()) &&
460                                   (getImm() & 1) == 0; }
461   bool isU7ImmX4() const { return Kind == Immediate &&
462                                   isUInt<7>(getImm()) &&
463                                   (getImm() & 3) == 0; }
464   bool isU8ImmX8() const { return Kind == Immediate &&
465                                   isUInt<8>(getImm()) &&
466                                   (getImm() & 7) == 0; }
467 
468   bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
469   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
470   bool isU16Imm() const {
471     switch (Kind) {
472       case Expression:
473         return true;
474       case Immediate:
475       case ContextImmediate:
476         return isUInt<16>(getImmU16Context());
477       default:
478         return false;
479     }
480   }
481   bool isS16Imm() const {
482     switch (Kind) {
483       case Expression:
484         return true;
485       case Immediate:
486       case ContextImmediate:
487         return isInt<16>(getImmS16Context());
488       default:
489         return false;
490     }
491   }
492   bool isS16ImmX4() const { return Kind == Expression ||
493                                    (Kind == Immediate && isInt<16>(getImm()) &&
494                                     (getImm() & 3) == 0); }
495   bool isS16ImmX16() const { return Kind == Expression ||
496                                     (Kind == Immediate && isInt<16>(getImm()) &&
497                                      (getImm() & 15) == 0); }
498   bool isS17Imm() const {
499     switch (Kind) {
500       case Expression:
501         return true;
502       case Immediate:
503       case ContextImmediate:
504         return isInt<17>(getImmS16Context());
505       default:
506         return false;
507     }
508   }
509   bool isTLSReg() const { return Kind == TLSRegister; }
510   bool isDirectBr() const {
511     if (Kind == Expression)
512       return true;
513     if (Kind != Immediate)
514       return false;
515     // Operand must be 64-bit aligned, signed 27-bit immediate.
516     if ((getImm() & 3) != 0)
517       return false;
518     if (isInt<26>(getImm()))
519       return true;
520     if (!IsPPC64) {
521       // In 32-bit mode, large 32-bit quantities wrap around.
522       if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
523         return true;
524     }
525     return false;
526   }
527   bool isCondBr() const { return Kind == Expression ||
528                                  (Kind == Immediate && isInt<16>(getImm()) &&
529                                   (getImm() & 3) == 0); }
530   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
531   bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
532   bool isCCRegNumber() const { return (Kind == Expression
533                                        && isUInt<3>(getExprCRVal())) ||
534                                       (Kind == Immediate
535                                        && isUInt<3>(getImm())); }
536   bool isCRBitNumber() const { return (Kind == Expression
537                                        && isUInt<5>(getExprCRVal())) ||
538                                       (Kind == Immediate
539                                        && isUInt<5>(getImm())); }
540   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
541                                     isPowerOf2_32(getImm()); }
542   bool isMem() const override { return false; }
543   bool isReg() const override { return false; }
544 
545   void addRegOperands(MCInst &Inst, unsigned N) const {
546     llvm_unreachable("addRegOperands");
547   }
548 
549   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
550     assert(N == 1 && "Invalid number of operands!");
551     Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
552   }
553 
554   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
555     assert(N == 1 && "Invalid number of operands!");
556     Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
557   }
558 
559   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
560     assert(N == 1 && "Invalid number of operands!");
561     Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
562   }
563 
564   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
565     assert(N == 1 && "Invalid number of operands!");
566     Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
567   }
568 
569   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
570     if (isPPC64())
571       addRegG8RCOperands(Inst, N);
572     else
573       addRegGPRCOperands(Inst, N);
574   }
575 
576   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
577     if (isPPC64())
578       addRegG8RCNoX0Operands(Inst, N);
579     else
580       addRegGPRCNoR0Operands(Inst, N);
581   }
582 
583   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
584     assert(N == 1 && "Invalid number of operands!");
585     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
586   }
587 
588   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
589     assert(N == 1 && "Invalid number of operands!");
590     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
591   }
592 
593   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
594     assert(N == 1 && "Invalid number of operands!");
595     Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
596   }
597 
598   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
599     assert(N == 1 && "Invalid number of operands!");
600     Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
601   }
602 
603   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
604     assert(N == 1 && "Invalid number of operands!");
605     Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
606   }
607 
608   void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
609     assert(N == 1 && "Invalid number of operands!");
610     Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
611   }
612 
613   void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
614     assert(N == 1 && "Invalid number of operands!");
615     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
616   }
617 
618   void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
619     assert(N == 1 && "Invalid number of operands!");
620     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
621   }
622 
623   void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
624     assert(N == 1 && "Invalid number of operands!");
625     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
626   }
627 
628   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
629     assert(N == 1 && "Invalid number of operands!");
630     Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
631   }
632 
633   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
634     assert(N == 1 && "Invalid number of operands!");
635     Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
636   }
637 
638   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
639     assert(N == 1 && "Invalid number of operands!");
640     Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
641   }
642 
643   void addImmOperands(MCInst &Inst, unsigned N) const {
644     assert(N == 1 && "Invalid number of operands!");
645     if (Kind == Immediate)
646       Inst.addOperand(MCOperand::createImm(getImm()));
647     else
648       Inst.addOperand(MCOperand::createExpr(getExpr()));
649   }
650 
651   void addS16ImmOperands(MCInst &Inst, unsigned N) const {
652     assert(N == 1 && "Invalid number of operands!");
653     switch (Kind) {
654       case Immediate:
655         Inst.addOperand(MCOperand::createImm(getImm()));
656         break;
657       case ContextImmediate:
658         Inst.addOperand(MCOperand::createImm(getImmS16Context()));
659         break;
660       default:
661         Inst.addOperand(MCOperand::createExpr(getExpr()));
662         break;
663     }
664   }
665 
666   void addU16ImmOperands(MCInst &Inst, unsigned N) const {
667     assert(N == 1 && "Invalid number of operands!");
668     switch (Kind) {
669       case Immediate:
670         Inst.addOperand(MCOperand::createImm(getImm()));
671         break;
672       case ContextImmediate:
673         Inst.addOperand(MCOperand::createImm(getImmU16Context()));
674         break;
675       default:
676         Inst.addOperand(MCOperand::createExpr(getExpr()));
677         break;
678     }
679   }
680 
681   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
682     assert(N == 1 && "Invalid number of operands!");
683     if (Kind == Immediate)
684       Inst.addOperand(MCOperand::createImm(getImm() / 4));
685     else
686       Inst.addOperand(MCOperand::createExpr(getExpr()));
687   }
688 
689   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
690     assert(N == 1 && "Invalid number of operands!");
691     Inst.addOperand(MCOperand::createExpr(getTLSReg()));
692   }
693 
694   StringRef getToken() const {
695     assert(Kind == Token && "Invalid access!");
696     return StringRef(Tok.Data, Tok.Length);
697   }
698 
699   void print(raw_ostream &OS) const override;
700 
701   static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
702                                                  bool IsPPC64) {
703     auto Op = make_unique<PPCOperand>(Token);
704     Op->Tok.Data = Str.data();
705     Op->Tok.Length = Str.size();
706     Op->StartLoc = S;
707     Op->EndLoc = S;
708     Op->IsPPC64 = IsPPC64;
709     return Op;
710   }
711 
712   static std::unique_ptr<PPCOperand>
713   CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
714     // Allocate extra memory for the string and copy it.
715     // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
716     // deleter which will destroy them by simply using "delete", not correctly
717     // calling operator delete on this extra memory after calling the dtor
718     // explicitly.
719     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
720     std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
721     Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
722     Op->Tok.Length = Str.size();
723     std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
724     Op->StartLoc = S;
725     Op->EndLoc = S;
726     Op->IsPPC64 = IsPPC64;
727     return Op;
728   }
729 
730   static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
731                                                bool IsPPC64) {
732     auto Op = make_unique<PPCOperand>(Immediate);
733     Op->Imm.Val = Val;
734     Op->StartLoc = S;
735     Op->EndLoc = E;
736     Op->IsPPC64 = IsPPC64;
737     return Op;
738   }
739 
740   static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
741                                                 SMLoc E, bool IsPPC64) {
742     auto Op = make_unique<PPCOperand>(Expression);
743     Op->Expr.Val = Val;
744     Op->Expr.CRVal = EvaluateCRExpr(Val);
745     Op->StartLoc = S;
746     Op->EndLoc = E;
747     Op->IsPPC64 = IsPPC64;
748     return Op;
749   }
750 
751   static std::unique_ptr<PPCOperand>
752   CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
753     auto Op = make_unique<PPCOperand>(TLSRegister);
754     Op->TLSReg.Sym = Sym;
755     Op->StartLoc = S;
756     Op->EndLoc = E;
757     Op->IsPPC64 = IsPPC64;
758     return Op;
759   }
760 
761   static std::unique_ptr<PPCOperand>
762   CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
763     auto Op = make_unique<PPCOperand>(ContextImmediate);
764     Op->Imm.Val = Val;
765     Op->StartLoc = S;
766     Op->EndLoc = E;
767     Op->IsPPC64 = IsPPC64;
768     return Op;
769   }
770 
771   static std::unique_ptr<PPCOperand>
772   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
773     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
774       return CreateImm(CE->getValue(), S, E, IsPPC64);
775 
776     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
777       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
778         return CreateTLSReg(SRE, S, E, IsPPC64);
779 
780     if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
781       int64_t Res;
782       if (TE->evaluateAsConstant(Res))
783         return CreateContextImm(Res, S, E, IsPPC64);
784     }
785 
786     return CreateExpr(Val, S, E, IsPPC64);
787   }
788 };
789 
790 } // end anonymous namespace.
791 
792 void PPCOperand::print(raw_ostream &OS) const {
793   switch (Kind) {
794   case Token:
795     OS << "'" << getToken() << "'";
796     break;
797   case Immediate:
798   case ContextImmediate:
799     OS << getImm();
800     break;
801   case Expression:
802     OS << *getExpr();
803     break;
804   case TLSRegister:
805     OS << *getTLSReg();
806     break;
807   }
808 }
809 
810 static void
811 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
812   if (Op.isImm()) {
813     Inst.addOperand(MCOperand::createImm(-Op.getImm()));
814     return;
815   }
816   const MCExpr *Expr = Op.getExpr();
817   if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
818     if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
819       Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
820       return;
821     }
822   } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
823     if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
824       const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
825                                                  BinExpr->getLHS(), Ctx);
826       Inst.addOperand(MCOperand::createExpr(NE));
827       return;
828     }
829   }
830   Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx)));
831 }
832 
833 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
834                                       const OperandVector &Operands) {
835   int Opcode = Inst.getOpcode();
836   switch (Opcode) {
837   case PPC::DCBTx:
838   case PPC::DCBTT:
839   case PPC::DCBTSTx:
840   case PPC::DCBTSTT: {
841     MCInst TmpInst;
842     TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
843                       PPC::DCBT : PPC::DCBTST);
844     TmpInst.addOperand(MCOperand::createImm(
845       (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
846     TmpInst.addOperand(Inst.getOperand(0));
847     TmpInst.addOperand(Inst.getOperand(1));
848     Inst = TmpInst;
849     break;
850   }
851   case PPC::DCBTCT:
852   case PPC::DCBTDS: {
853     MCInst TmpInst;
854     TmpInst.setOpcode(PPC::DCBT);
855     TmpInst.addOperand(Inst.getOperand(2));
856     TmpInst.addOperand(Inst.getOperand(0));
857     TmpInst.addOperand(Inst.getOperand(1));
858     Inst = TmpInst;
859     break;
860   }
861   case PPC::DCBTSTCT:
862   case PPC::DCBTSTDS: {
863     MCInst TmpInst;
864     TmpInst.setOpcode(PPC::DCBTST);
865     TmpInst.addOperand(Inst.getOperand(2));
866     TmpInst.addOperand(Inst.getOperand(0));
867     TmpInst.addOperand(Inst.getOperand(1));
868     Inst = TmpInst;
869     break;
870   }
871   case PPC::LAx: {
872     MCInst TmpInst;
873     TmpInst.setOpcode(PPC::LA);
874     TmpInst.addOperand(Inst.getOperand(0));
875     TmpInst.addOperand(Inst.getOperand(2));
876     TmpInst.addOperand(Inst.getOperand(1));
877     Inst = TmpInst;
878     break;
879   }
880   case PPC::SUBI: {
881     MCInst TmpInst;
882     TmpInst.setOpcode(PPC::ADDI);
883     TmpInst.addOperand(Inst.getOperand(0));
884     TmpInst.addOperand(Inst.getOperand(1));
885     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
886     Inst = TmpInst;
887     break;
888   }
889   case PPC::SUBIS: {
890     MCInst TmpInst;
891     TmpInst.setOpcode(PPC::ADDIS);
892     TmpInst.addOperand(Inst.getOperand(0));
893     TmpInst.addOperand(Inst.getOperand(1));
894     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
895     Inst = TmpInst;
896     break;
897   }
898   case PPC::SUBIC: {
899     MCInst TmpInst;
900     TmpInst.setOpcode(PPC::ADDIC);
901     TmpInst.addOperand(Inst.getOperand(0));
902     TmpInst.addOperand(Inst.getOperand(1));
903     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
904     Inst = TmpInst;
905     break;
906   }
907   case PPC::SUBICo: {
908     MCInst TmpInst;
909     TmpInst.setOpcode(PPC::ADDICo);
910     TmpInst.addOperand(Inst.getOperand(0));
911     TmpInst.addOperand(Inst.getOperand(1));
912     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
913     Inst = TmpInst;
914     break;
915   }
916   case PPC::EXTLWI:
917   case PPC::EXTLWIo: {
918     MCInst TmpInst;
919     int64_t N = Inst.getOperand(2).getImm();
920     int64_t B = Inst.getOperand(3).getImm();
921     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
922     TmpInst.addOperand(Inst.getOperand(0));
923     TmpInst.addOperand(Inst.getOperand(1));
924     TmpInst.addOperand(MCOperand::createImm(B));
925     TmpInst.addOperand(MCOperand::createImm(0));
926     TmpInst.addOperand(MCOperand::createImm(N - 1));
927     Inst = TmpInst;
928     break;
929   }
930   case PPC::EXTRWI:
931   case PPC::EXTRWIo: {
932     MCInst TmpInst;
933     int64_t N = Inst.getOperand(2).getImm();
934     int64_t B = Inst.getOperand(3).getImm();
935     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
936     TmpInst.addOperand(Inst.getOperand(0));
937     TmpInst.addOperand(Inst.getOperand(1));
938     TmpInst.addOperand(MCOperand::createImm(B + N));
939     TmpInst.addOperand(MCOperand::createImm(32 - N));
940     TmpInst.addOperand(MCOperand::createImm(31));
941     Inst = TmpInst;
942     break;
943   }
944   case PPC::INSLWI:
945   case PPC::INSLWIo: {
946     MCInst TmpInst;
947     int64_t N = Inst.getOperand(2).getImm();
948     int64_t B = Inst.getOperand(3).getImm();
949     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
950     TmpInst.addOperand(Inst.getOperand(0));
951     TmpInst.addOperand(Inst.getOperand(0));
952     TmpInst.addOperand(Inst.getOperand(1));
953     TmpInst.addOperand(MCOperand::createImm(32 - B));
954     TmpInst.addOperand(MCOperand::createImm(B));
955     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
956     Inst = TmpInst;
957     break;
958   }
959   case PPC::INSRWI:
960   case PPC::INSRWIo: {
961     MCInst TmpInst;
962     int64_t N = Inst.getOperand(2).getImm();
963     int64_t B = Inst.getOperand(3).getImm();
964     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
965     TmpInst.addOperand(Inst.getOperand(0));
966     TmpInst.addOperand(Inst.getOperand(0));
967     TmpInst.addOperand(Inst.getOperand(1));
968     TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
969     TmpInst.addOperand(MCOperand::createImm(B));
970     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
971     Inst = TmpInst;
972     break;
973   }
974   case PPC::ROTRWI:
975   case PPC::ROTRWIo: {
976     MCInst TmpInst;
977     int64_t N = Inst.getOperand(2).getImm();
978     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
979     TmpInst.addOperand(Inst.getOperand(0));
980     TmpInst.addOperand(Inst.getOperand(1));
981     TmpInst.addOperand(MCOperand::createImm(32 - N));
982     TmpInst.addOperand(MCOperand::createImm(0));
983     TmpInst.addOperand(MCOperand::createImm(31));
984     Inst = TmpInst;
985     break;
986   }
987   case PPC::SLWI:
988   case PPC::SLWIo: {
989     MCInst TmpInst;
990     int64_t N = Inst.getOperand(2).getImm();
991     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
992     TmpInst.addOperand(Inst.getOperand(0));
993     TmpInst.addOperand(Inst.getOperand(1));
994     TmpInst.addOperand(MCOperand::createImm(N));
995     TmpInst.addOperand(MCOperand::createImm(0));
996     TmpInst.addOperand(MCOperand::createImm(31 - N));
997     Inst = TmpInst;
998     break;
999   }
1000   case PPC::SRWI:
1001   case PPC::SRWIo: {
1002     MCInst TmpInst;
1003     int64_t N = Inst.getOperand(2).getImm();
1004     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
1005     TmpInst.addOperand(Inst.getOperand(0));
1006     TmpInst.addOperand(Inst.getOperand(1));
1007     TmpInst.addOperand(MCOperand::createImm(32 - N));
1008     TmpInst.addOperand(MCOperand::createImm(N));
1009     TmpInst.addOperand(MCOperand::createImm(31));
1010     Inst = TmpInst;
1011     break;
1012   }
1013   case PPC::CLRRWI:
1014   case PPC::CLRRWIo: {
1015     MCInst TmpInst;
1016     int64_t N = Inst.getOperand(2).getImm();
1017     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
1018     TmpInst.addOperand(Inst.getOperand(0));
1019     TmpInst.addOperand(Inst.getOperand(1));
1020     TmpInst.addOperand(MCOperand::createImm(0));
1021     TmpInst.addOperand(MCOperand::createImm(0));
1022     TmpInst.addOperand(MCOperand::createImm(31 - N));
1023     Inst = TmpInst;
1024     break;
1025   }
1026   case PPC::CLRLSLWI:
1027   case PPC::CLRLSLWIo: {
1028     MCInst TmpInst;
1029     int64_t B = Inst.getOperand(2).getImm();
1030     int64_t N = Inst.getOperand(3).getImm();
1031     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
1032     TmpInst.addOperand(Inst.getOperand(0));
1033     TmpInst.addOperand(Inst.getOperand(1));
1034     TmpInst.addOperand(MCOperand::createImm(N));
1035     TmpInst.addOperand(MCOperand::createImm(B - N));
1036     TmpInst.addOperand(MCOperand::createImm(31 - N));
1037     Inst = TmpInst;
1038     break;
1039   }
1040   case PPC::EXTLDI:
1041   case PPC::EXTLDIo: {
1042     MCInst TmpInst;
1043     int64_t N = Inst.getOperand(2).getImm();
1044     int64_t B = Inst.getOperand(3).getImm();
1045     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1046     TmpInst.addOperand(Inst.getOperand(0));
1047     TmpInst.addOperand(Inst.getOperand(1));
1048     TmpInst.addOperand(MCOperand::createImm(B));
1049     TmpInst.addOperand(MCOperand::createImm(N - 1));
1050     Inst = TmpInst;
1051     break;
1052   }
1053   case PPC::EXTRDI:
1054   case PPC::EXTRDIo: {
1055     MCInst TmpInst;
1056     int64_t N = Inst.getOperand(2).getImm();
1057     int64_t B = Inst.getOperand(3).getImm();
1058     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1059     TmpInst.addOperand(Inst.getOperand(0));
1060     TmpInst.addOperand(Inst.getOperand(1));
1061     TmpInst.addOperand(MCOperand::createImm(B + N));
1062     TmpInst.addOperand(MCOperand::createImm(64 - N));
1063     Inst = TmpInst;
1064     break;
1065   }
1066   case PPC::INSRDI:
1067   case PPC::INSRDIo: {
1068     MCInst TmpInst;
1069     int64_t N = Inst.getOperand(2).getImm();
1070     int64_t B = Inst.getOperand(3).getImm();
1071     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1072     TmpInst.addOperand(Inst.getOperand(0));
1073     TmpInst.addOperand(Inst.getOperand(0));
1074     TmpInst.addOperand(Inst.getOperand(1));
1075     TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
1076     TmpInst.addOperand(MCOperand::createImm(B));
1077     Inst = TmpInst;
1078     break;
1079   }
1080   case PPC::ROTRDI:
1081   case PPC::ROTRDIo: {
1082     MCInst TmpInst;
1083     int64_t N = Inst.getOperand(2).getImm();
1084     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1085     TmpInst.addOperand(Inst.getOperand(0));
1086     TmpInst.addOperand(Inst.getOperand(1));
1087     TmpInst.addOperand(MCOperand::createImm(64 - N));
1088     TmpInst.addOperand(MCOperand::createImm(0));
1089     Inst = TmpInst;
1090     break;
1091   }
1092   case PPC::SLDI:
1093   case PPC::SLDIo: {
1094     MCInst TmpInst;
1095     int64_t N = Inst.getOperand(2).getImm();
1096     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1097     TmpInst.addOperand(Inst.getOperand(0));
1098     TmpInst.addOperand(Inst.getOperand(1));
1099     TmpInst.addOperand(MCOperand::createImm(N));
1100     TmpInst.addOperand(MCOperand::createImm(63 - N));
1101     Inst = TmpInst;
1102     break;
1103   }
1104   case PPC::SRDI:
1105   case PPC::SRDIo: {
1106     MCInst TmpInst;
1107     int64_t N = Inst.getOperand(2).getImm();
1108     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1109     TmpInst.addOperand(Inst.getOperand(0));
1110     TmpInst.addOperand(Inst.getOperand(1));
1111     TmpInst.addOperand(MCOperand::createImm(64 - N));
1112     TmpInst.addOperand(MCOperand::createImm(N));
1113     Inst = TmpInst;
1114     break;
1115   }
1116   case PPC::CLRRDI:
1117   case PPC::CLRRDIo: {
1118     MCInst TmpInst;
1119     int64_t N = Inst.getOperand(2).getImm();
1120     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1121     TmpInst.addOperand(Inst.getOperand(0));
1122     TmpInst.addOperand(Inst.getOperand(1));
1123     TmpInst.addOperand(MCOperand::createImm(0));
1124     TmpInst.addOperand(MCOperand::createImm(63 - N));
1125     Inst = TmpInst;
1126     break;
1127   }
1128   case PPC::CLRLSLDI:
1129   case PPC::CLRLSLDIo: {
1130     MCInst TmpInst;
1131     int64_t B = Inst.getOperand(2).getImm();
1132     int64_t N = Inst.getOperand(3).getImm();
1133     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1134     TmpInst.addOperand(Inst.getOperand(0));
1135     TmpInst.addOperand(Inst.getOperand(1));
1136     TmpInst.addOperand(MCOperand::createImm(N));
1137     TmpInst.addOperand(MCOperand::createImm(B - N));
1138     Inst = TmpInst;
1139     break;
1140   }
1141   case PPC::RLWINMbm:
1142   case PPC::RLWINMobm: {
1143     unsigned MB, ME;
1144     int64_t BM = Inst.getOperand(3).getImm();
1145     if (!isRunOfOnes(BM, MB, ME))
1146       break;
1147 
1148     MCInst TmpInst;
1149     TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1150     TmpInst.addOperand(Inst.getOperand(0));
1151     TmpInst.addOperand(Inst.getOperand(1));
1152     TmpInst.addOperand(Inst.getOperand(2));
1153     TmpInst.addOperand(MCOperand::createImm(MB));
1154     TmpInst.addOperand(MCOperand::createImm(ME));
1155     Inst = TmpInst;
1156     break;
1157   }
1158   case PPC::RLWIMIbm:
1159   case PPC::RLWIMIobm: {
1160     unsigned MB, ME;
1161     int64_t BM = Inst.getOperand(3).getImm();
1162     if (!isRunOfOnes(BM, MB, ME))
1163       break;
1164 
1165     MCInst TmpInst;
1166     TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1167     TmpInst.addOperand(Inst.getOperand(0));
1168     TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1169     TmpInst.addOperand(Inst.getOperand(1));
1170     TmpInst.addOperand(Inst.getOperand(2));
1171     TmpInst.addOperand(MCOperand::createImm(MB));
1172     TmpInst.addOperand(MCOperand::createImm(ME));
1173     Inst = TmpInst;
1174     break;
1175   }
1176   case PPC::RLWNMbm:
1177   case PPC::RLWNMobm: {
1178     unsigned MB, ME;
1179     int64_t BM = Inst.getOperand(3).getImm();
1180     if (!isRunOfOnes(BM, MB, ME))
1181       break;
1182 
1183     MCInst TmpInst;
1184     TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1185     TmpInst.addOperand(Inst.getOperand(0));
1186     TmpInst.addOperand(Inst.getOperand(1));
1187     TmpInst.addOperand(Inst.getOperand(2));
1188     TmpInst.addOperand(MCOperand::createImm(MB));
1189     TmpInst.addOperand(MCOperand::createImm(ME));
1190     Inst = TmpInst;
1191     break;
1192   }
1193   case PPC::MFTB: {
1194     if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1195       assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1196       Inst.setOpcode(PPC::MFSPR);
1197     }
1198     break;
1199   }
1200   }
1201 }
1202 
1203 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1204                                            OperandVector &Operands,
1205                                            MCStreamer &Out, uint64_t &ErrorInfo,
1206                                            bool MatchingInlineAsm) {
1207   MCInst Inst;
1208 
1209   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1210   case Match_Success:
1211     // Post-process instructions (typically extended mnemonics)
1212     ProcessInstruction(Inst, Operands);
1213     Inst.setLoc(IDLoc);
1214     Out.EmitInstruction(Inst, getSTI());
1215     return false;
1216   case Match_MissingFeature:
1217     return Error(IDLoc, "instruction use requires an option to be enabled");
1218   case Match_MnemonicFail:
1219     return Error(IDLoc, "unrecognized instruction mnemonic");
1220   case Match_InvalidOperand: {
1221     SMLoc ErrorLoc = IDLoc;
1222     if (ErrorInfo != ~0ULL) {
1223       if (ErrorInfo >= Operands.size())
1224         return Error(IDLoc, "too few operands for instruction");
1225 
1226       ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1227       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1228     }
1229 
1230     return Error(ErrorLoc, "invalid operand for instruction");
1231   }
1232   }
1233 
1234   llvm_unreachable("Implement any new match types added!");
1235 }
1236 
1237 bool PPCAsmParser::
1238 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1239   if (Tok.is(AsmToken::Identifier)) {
1240     StringRef Name = Tok.getString();
1241 
1242     if (Name.equals_lower("lr")) {
1243       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1244       IntVal = 8;
1245       return false;
1246     } else if (Name.equals_lower("ctr")) {
1247       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1248       IntVal = 9;
1249       return false;
1250     } else if (Name.equals_lower("vrsave")) {
1251       RegNo = PPC::VRSAVE;
1252       IntVal = 256;
1253       return false;
1254     } else if (Name.startswith_lower("r") &&
1255                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1256       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1257       return false;
1258     } else if (Name.startswith_lower("f") &&
1259                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1260       RegNo = FRegs[IntVal];
1261       return false;
1262     } else if (Name.startswith_lower("vs") &&
1263                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1264       RegNo = VSRegs[IntVal];
1265       return false;
1266     } else if (Name.startswith_lower("v") &&
1267                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1268       RegNo = VRegs[IntVal];
1269       return false;
1270     } else if (Name.startswith_lower("q") &&
1271                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1272       RegNo = QFRegs[IntVal];
1273       return false;
1274     } else if (Name.startswith_lower("cr") &&
1275                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1276       RegNo = CRRegs[IntVal];
1277       return false;
1278     }
1279   }
1280 
1281   return true;
1282 }
1283 
1284 bool PPCAsmParser::
1285 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1286   MCAsmParser &Parser = getParser();
1287   const AsmToken &Tok = Parser.getTok();
1288   StartLoc = Tok.getLoc();
1289   EndLoc = Tok.getEndLoc();
1290   RegNo = 0;
1291   int64_t IntVal;
1292 
1293   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1294     Parser.Lex(); // Eat identifier token.
1295     return false;
1296   }
1297 
1298   return Error(StartLoc, "invalid register name");
1299 }
1300 
1301 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1302 /// the expression and check for VK_PPC_LO/HI/HA
1303 /// symbol variants.  If all symbols with modifier use the same
1304 /// variant, return the corresponding PPCMCExpr::VariantKind,
1305 /// and a modified expression using the default symbol variant.
1306 /// Otherwise, return NULL.
1307 const MCExpr *PPCAsmParser::
1308 ExtractModifierFromExpr(const MCExpr *E,
1309                         PPCMCExpr::VariantKind &Variant) {
1310   MCContext &Context = getParser().getContext();
1311   Variant = PPCMCExpr::VK_PPC_None;
1312 
1313   switch (E->getKind()) {
1314   case MCExpr::Target:
1315   case MCExpr::Constant:
1316     return nullptr;
1317 
1318   case MCExpr::SymbolRef: {
1319     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1320 
1321     switch (SRE->getKind()) {
1322     case MCSymbolRefExpr::VK_PPC_LO:
1323       Variant = PPCMCExpr::VK_PPC_LO;
1324       break;
1325     case MCSymbolRefExpr::VK_PPC_HI:
1326       Variant = PPCMCExpr::VK_PPC_HI;
1327       break;
1328     case MCSymbolRefExpr::VK_PPC_HA:
1329       Variant = PPCMCExpr::VK_PPC_HA;
1330       break;
1331     case MCSymbolRefExpr::VK_PPC_HIGHER:
1332       Variant = PPCMCExpr::VK_PPC_HIGHER;
1333       break;
1334     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1335       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1336       break;
1337     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1338       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1339       break;
1340     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1341       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1342       break;
1343     default:
1344       return nullptr;
1345     }
1346 
1347     return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1348   }
1349 
1350   case MCExpr::Unary: {
1351     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1352     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1353     if (!Sub)
1354       return nullptr;
1355     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1356   }
1357 
1358   case MCExpr::Binary: {
1359     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1360     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1361     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1362     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1363 
1364     if (!LHS && !RHS)
1365       return nullptr;
1366 
1367     if (!LHS) LHS = BE->getLHS();
1368     if (!RHS) RHS = BE->getRHS();
1369 
1370     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1371       Variant = RHSVariant;
1372     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1373       Variant = LHSVariant;
1374     else if (LHSVariant == RHSVariant)
1375       Variant = LHSVariant;
1376     else
1377       return nullptr;
1378 
1379     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1380   }
1381   }
1382 
1383   llvm_unreachable("Invalid expression kind!");
1384 }
1385 
1386 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1387 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1388 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1389 /// FIXME: This is a hack.
1390 const MCExpr *PPCAsmParser::
1391 FixupVariantKind(const MCExpr *E) {
1392   MCContext &Context = getParser().getContext();
1393 
1394   switch (E->getKind()) {
1395   case MCExpr::Target:
1396   case MCExpr::Constant:
1397     return E;
1398 
1399   case MCExpr::SymbolRef: {
1400     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1401     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1402 
1403     switch (SRE->getKind()) {
1404     case MCSymbolRefExpr::VK_TLSGD:
1405       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1406       break;
1407     case MCSymbolRefExpr::VK_TLSLD:
1408       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1409       break;
1410     default:
1411       return E;
1412     }
1413     return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1414   }
1415 
1416   case MCExpr::Unary: {
1417     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1418     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1419     if (Sub == UE->getSubExpr())
1420       return E;
1421     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1422   }
1423 
1424   case MCExpr::Binary: {
1425     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1426     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1427     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1428     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1429       return E;
1430     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1431   }
1432   }
1433 
1434   llvm_unreachable("Invalid expression kind!");
1435 }
1436 
1437 /// ParseExpression.  This differs from the default "parseExpression" in that
1438 /// it handles modifiers.
1439 bool PPCAsmParser::
1440 ParseExpression(const MCExpr *&EVal) {
1441 
1442   if (isDarwin())
1443     return ParseDarwinExpression(EVal);
1444 
1445   // (ELF Platforms)
1446   // Handle \code @l/@ha \endcode
1447   if (getParser().parseExpression(EVal))
1448     return true;
1449 
1450   EVal = FixupVariantKind(EVal);
1451 
1452   PPCMCExpr::VariantKind Variant;
1453   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1454   if (E)
1455     EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext());
1456 
1457   return false;
1458 }
1459 
1460 /// ParseDarwinExpression.  (MachO Platforms)
1461 /// This differs from the default "parseExpression" in that it handles detection
1462 /// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1463 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1464 /// syntax form so it is done here.  TODO: Determine if there is merit in arranging
1465 /// for this to be done at a higher level.
1466 bool PPCAsmParser::
1467 ParseDarwinExpression(const MCExpr *&EVal) {
1468   MCAsmParser &Parser = getParser();
1469   PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1470   switch (getLexer().getKind()) {
1471   default:
1472     break;
1473   case AsmToken::Identifier:
1474     // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1475     // something starting with any other char should be part of the
1476     // asm syntax.  If handwritten asm includes an identifier like lo16,
1477     // then all bets are off - but no-one would do that, right?
1478     StringRef poss = Parser.getTok().getString();
1479     if (poss.equals_lower("lo16")) {
1480       Variant = PPCMCExpr::VK_PPC_LO;
1481     } else if (poss.equals_lower("hi16")) {
1482       Variant = PPCMCExpr::VK_PPC_HI;
1483     } else if (poss.equals_lower("ha16")) {
1484       Variant = PPCMCExpr::VK_PPC_HA;
1485     }
1486     if (Variant != PPCMCExpr::VK_PPC_None) {
1487       Parser.Lex(); // Eat the xx16
1488       if (getLexer().isNot(AsmToken::LParen))
1489         return Error(Parser.getTok().getLoc(), "expected '('");
1490       Parser.Lex(); // Eat the '('
1491     }
1492     break;
1493   }
1494 
1495   if (getParser().parseExpression(EVal))
1496     return true;
1497 
1498   if (Variant != PPCMCExpr::VK_PPC_None) {
1499     if (getLexer().isNot(AsmToken::RParen))
1500       return Error(Parser.getTok().getLoc(), "expected ')'");
1501     Parser.Lex(); // Eat the ')'
1502     EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext());
1503   }
1504   return false;
1505 }
1506 
1507 /// ParseOperand
1508 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1509 /// rNN for MachO.
1510 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1511   MCAsmParser &Parser = getParser();
1512   SMLoc S = Parser.getTok().getLoc();
1513   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1514   const MCExpr *EVal;
1515 
1516   // Attempt to parse the next token as an immediate
1517   switch (getLexer().getKind()) {
1518   // Special handling for register names.  These are interpreted
1519   // as immediates corresponding to the register number.
1520   case AsmToken::Percent:
1521     Parser.Lex(); // Eat the '%'.
1522     unsigned RegNo;
1523     int64_t IntVal;
1524     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1525       Parser.Lex(); // Eat the identifier token.
1526       Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1527       return false;
1528     }
1529     return Error(S, "invalid register name");
1530 
1531   case AsmToken::Identifier:
1532     // Note that non-register-name identifiers from the compiler will begin
1533     // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1534     // identifiers like r31foo - so we fall through in the event that parsing
1535     // a register name fails.
1536     if (isDarwin()) {
1537       unsigned RegNo;
1538       int64_t IntVal;
1539       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1540         Parser.Lex(); // Eat the identifier token.
1541         Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1542         return false;
1543       }
1544     }
1545   // Fall-through to process non-register-name identifiers as expression.
1546   // All other expressions
1547   case AsmToken::LParen:
1548   case AsmToken::Plus:
1549   case AsmToken::Minus:
1550   case AsmToken::Integer:
1551   case AsmToken::Dot:
1552   case AsmToken::Dollar:
1553   case AsmToken::Exclaim:
1554   case AsmToken::Tilde:
1555     if (!ParseExpression(EVal))
1556       break;
1557     /* fall through */
1558   default:
1559     return Error(S, "unknown operand");
1560   }
1561 
1562   // Push the parsed operand into the list of operands
1563   Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1564 
1565   // Check whether this is a TLS call expression
1566   bool TLSCall = false;
1567   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1568     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1569 
1570   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1571     const MCExpr *TLSSym;
1572 
1573     Parser.Lex(); // Eat the '('.
1574     S = Parser.getTok().getLoc();
1575     if (ParseExpression(TLSSym))
1576       return Error(S, "invalid TLS call expression");
1577     if (getLexer().isNot(AsmToken::RParen))
1578       return Error(Parser.getTok().getLoc(), "missing ')'");
1579     E = Parser.getTok().getLoc();
1580     Parser.Lex(); // Eat the ')'.
1581 
1582     Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1583   }
1584 
1585   // Otherwise, check for D-form memory operands
1586   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1587     Parser.Lex(); // Eat the '('.
1588     S = Parser.getTok().getLoc();
1589 
1590     int64_t IntVal;
1591     switch (getLexer().getKind()) {
1592     case AsmToken::Percent:
1593       Parser.Lex(); // Eat the '%'.
1594       unsigned RegNo;
1595       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1596         return Error(S, "invalid register name");
1597       Parser.Lex(); // Eat the identifier token.
1598       break;
1599 
1600     case AsmToken::Integer:
1601       if (!isDarwin()) {
1602         if (getParser().parseAbsoluteExpression(IntVal) ||
1603           IntVal < 0 || IntVal > 31)
1604         return Error(S, "invalid register number");
1605       } else {
1606         return Error(S, "unexpected integer value");
1607       }
1608       break;
1609 
1610    case AsmToken::Identifier:
1611     if (isDarwin()) {
1612       unsigned RegNo;
1613       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1614         Parser.Lex(); // Eat the identifier token.
1615         break;
1616       }
1617     }
1618     // Fall-through..
1619 
1620     default:
1621       return Error(S, "invalid memory operand");
1622     }
1623 
1624     if (getLexer().isNot(AsmToken::RParen))
1625       return Error(Parser.getTok().getLoc(), "missing ')'");
1626     E = Parser.getTok().getLoc();
1627     Parser.Lex(); // Eat the ')'.
1628 
1629     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1630   }
1631 
1632   return false;
1633 }
1634 
1635 /// Parse an instruction mnemonic followed by its operands.
1636 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1637                                     SMLoc NameLoc, OperandVector &Operands) {
1638   // The first operand is the token for the instruction name.
1639   // If the next character is a '+' or '-', we need to add it to the
1640   // instruction name, to match what TableGen is doing.
1641   std::string NewOpcode;
1642   if (getLexer().is(AsmToken::Plus)) {
1643     getLexer().Lex();
1644     NewOpcode = Name;
1645     NewOpcode += '+';
1646     Name = NewOpcode;
1647   }
1648   if (getLexer().is(AsmToken::Minus)) {
1649     getLexer().Lex();
1650     NewOpcode = Name;
1651     NewOpcode += '-';
1652     Name = NewOpcode;
1653   }
1654   // If the instruction ends in a '.', we need to create a separate
1655   // token for it, to match what TableGen is doing.
1656   size_t Dot = Name.find('.');
1657   StringRef Mnemonic = Name.slice(0, Dot);
1658   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1659     Operands.push_back(
1660         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1661   else
1662     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1663   if (Dot != StringRef::npos) {
1664     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1665     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1666     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1667       Operands.push_back(
1668           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1669     else
1670       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1671   }
1672 
1673   // If there are no more operands then finish
1674   if (getLexer().is(AsmToken::EndOfStatement))
1675     return false;
1676 
1677   // Parse the first operand
1678   if (ParseOperand(Operands))
1679     return true;
1680 
1681   while (getLexer().isNot(AsmToken::EndOfStatement) &&
1682          getLexer().is(AsmToken::Comma)) {
1683     // Consume the comma token
1684     getLexer().Lex();
1685 
1686     // Parse the next operand
1687     if (ParseOperand(Operands))
1688       return true;
1689   }
1690 
1691   // We'll now deal with an unfortunate special case: the syntax for the dcbt
1692   // and dcbtst instructions differs for server vs. embedded cores.
1693   //  The syntax for dcbt is:
1694   //    dcbt ra, rb, th [server]
1695   //    dcbt th, ra, rb [embedded]
1696   //  where th can be omitted when it is 0. dcbtst is the same. We take the
1697   //  server form to be the default, so swap the operands if we're parsing for
1698   //  an embedded core (they'll be swapped again upon printing).
1699   if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1700       Operands.size() == 4 &&
1701       (Name == "dcbt" || Name == "dcbtst")) {
1702     std::swap(Operands[1], Operands[3]);
1703     std::swap(Operands[2], Operands[1]);
1704   }
1705 
1706   return false;
1707 }
1708 
1709 /// ParseDirective parses the PPC specific directives
1710 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1711   StringRef IDVal = DirectiveID.getIdentifier();
1712   if (!isDarwin()) {
1713     if (IDVal == ".word")
1714       return ParseDirectiveWord(2, DirectiveID.getLoc());
1715     if (IDVal == ".llong")
1716       return ParseDirectiveWord(8, DirectiveID.getLoc());
1717     if (IDVal == ".tc")
1718       return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1719     if (IDVal == ".machine")
1720       return ParseDirectiveMachine(DirectiveID.getLoc());
1721     if (IDVal == ".abiversion")
1722       return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1723     if (IDVal == ".localentry")
1724       return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1725   } else {
1726     if (IDVal == ".machine")
1727       return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1728   }
1729   return true;
1730 }
1731 
1732 /// ParseDirectiveWord
1733 ///  ::= .word [ expression (, expression)* ]
1734 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1735   MCAsmParser &Parser = getParser();
1736   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1737     for (;;) {
1738       const MCExpr *Value;
1739       SMLoc ExprLoc = getLexer().getLoc();
1740       if (getParser().parseExpression(Value))
1741         return false;
1742 
1743       if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1744         assert(Size <= 8 && "Invalid size");
1745         uint64_t IntValue = MCE->getValue();
1746         if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
1747           return Error(ExprLoc, "literal value out of range for directive");
1748         getStreamer().EmitIntValue(IntValue, Size);
1749       } else {
1750         getStreamer().EmitValue(Value, Size, ExprLoc);
1751       }
1752 
1753       if (getLexer().is(AsmToken::EndOfStatement))
1754         break;
1755 
1756       if (getLexer().isNot(AsmToken::Comma))
1757         return Error(L, "unexpected token in directive");
1758       Parser.Lex();
1759     }
1760   }
1761 
1762   Parser.Lex();
1763   return false;
1764 }
1765 
1766 /// ParseDirectiveTC
1767 ///  ::= .tc [ symbol (, expression)* ]
1768 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1769   MCAsmParser &Parser = getParser();
1770   // Skip TC symbol, which is only used with XCOFF.
1771   while (getLexer().isNot(AsmToken::EndOfStatement)
1772          && getLexer().isNot(AsmToken::Comma))
1773     Parser.Lex();
1774   if (getLexer().isNot(AsmToken::Comma)) {
1775     Error(L, "unexpected token in directive");
1776     return false;
1777   }
1778   Parser.Lex();
1779 
1780   // Align to word size.
1781   getParser().getStreamer().EmitValueToAlignment(Size);
1782 
1783   // Emit expressions.
1784   return ParseDirectiveWord(Size, L);
1785 }
1786 
1787 /// ParseDirectiveMachine (ELF platforms)
1788 ///  ::= .machine [ cpu | "push" | "pop" ]
1789 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1790   MCAsmParser &Parser = getParser();
1791   if (getLexer().isNot(AsmToken::Identifier) &&
1792       getLexer().isNot(AsmToken::String)) {
1793     Error(L, "unexpected token in directive");
1794     return false;
1795   }
1796 
1797   StringRef CPU = Parser.getTok().getIdentifier();
1798   Parser.Lex();
1799 
1800   // FIXME: Right now, the parser always allows any available
1801   // instruction, so the .machine directive is not useful.
1802   // Implement ".machine any" (by doing nothing) for the benefit
1803   // of existing assembler code.  Likewise, we can then implement
1804   // ".machine push" and ".machine pop" as no-op.
1805   if (CPU != "any" && CPU != "push" && CPU != "pop") {
1806     Error(L, "unrecognized machine type");
1807     return false;
1808   }
1809 
1810   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1811     Error(L, "unexpected token in directive");
1812     return false;
1813   }
1814   PPCTargetStreamer &TStreamer =
1815       *static_cast<PPCTargetStreamer *>(
1816            getParser().getStreamer().getTargetStreamer());
1817   TStreamer.emitMachine(CPU);
1818 
1819   return false;
1820 }
1821 
1822 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1823 ///  ::= .machine cpu-identifier
1824 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1825   MCAsmParser &Parser = getParser();
1826   if (getLexer().isNot(AsmToken::Identifier) &&
1827       getLexer().isNot(AsmToken::String)) {
1828     Error(L, "unexpected token in directive");
1829     return false;
1830   }
1831 
1832   StringRef CPU = Parser.getTok().getIdentifier();
1833   Parser.Lex();
1834 
1835   // FIXME: this is only the 'default' set of cpu variants.
1836   // However we don't act on this information at present, this is simply
1837   // allowing parsing to proceed with minimal sanity checking.
1838   if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1839     Error(L, "unrecognized cpu type");
1840     return false;
1841   }
1842 
1843   if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1844     Error(L, "wrong cpu type specified for 64bit");
1845     return false;
1846   }
1847   if (!isPPC64() && CPU == "ppc64") {
1848     Error(L, "wrong cpu type specified for 32bit");
1849     return false;
1850   }
1851 
1852   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1853     Error(L, "unexpected token in directive");
1854     return false;
1855   }
1856 
1857   return false;
1858 }
1859 
1860 /// ParseDirectiveAbiVersion
1861 ///  ::= .abiversion constant-expression
1862 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1863   int64_t AbiVersion;
1864   if (getParser().parseAbsoluteExpression(AbiVersion)){
1865     Error(L, "expected constant expression");
1866     return false;
1867   }
1868   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1869     Error(L, "unexpected token in directive");
1870     return false;
1871   }
1872 
1873   PPCTargetStreamer &TStreamer =
1874       *static_cast<PPCTargetStreamer *>(
1875            getParser().getStreamer().getTargetStreamer());
1876   TStreamer.emitAbiVersion(AbiVersion);
1877 
1878   return false;
1879 }
1880 
1881 /// ParseDirectiveLocalEntry
1882 ///  ::= .localentry symbol, expression
1883 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1884   StringRef Name;
1885   if (getParser().parseIdentifier(Name)) {
1886     Error(L, "expected identifier in directive");
1887     return false;
1888   }
1889   MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1890 
1891   if (getLexer().isNot(AsmToken::Comma)) {
1892     Error(L, "unexpected token in directive");
1893     return false;
1894   }
1895   Lex();
1896 
1897   const MCExpr *Expr;
1898   if (getParser().parseExpression(Expr)) {
1899     Error(L, "expected expression");
1900     return false;
1901   }
1902 
1903   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1904     Error(L, "unexpected token in directive");
1905     return false;
1906   }
1907 
1908   PPCTargetStreamer &TStreamer =
1909       *static_cast<PPCTargetStreamer *>(
1910            getParser().getStreamer().getTargetStreamer());
1911   TStreamer.emitLocalEntry(Sym, Expr);
1912 
1913   return false;
1914 }
1915 
1916 
1917 
1918 /// Force static initialization.
1919 extern "C" void LLVMInitializePowerPCAsmParser() {
1920   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1921   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1922   RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1923 }
1924 
1925 #define GET_REGISTER_MATCHER
1926 #define GET_MATCHER_IMPLEMENTATION
1927 #include "PPCGenAsmMatcher.inc"
1928 
1929 // Define this matcher function after the auto-generated include so we
1930 // have the match class enum definitions.
1931 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1932                                                   unsigned Kind) {
1933   // If the kind is a token for a literal immediate, check if our asm
1934   // operand matches. This is for InstAliases which have a fixed-value
1935   // immediate in the syntax.
1936   int64_t ImmVal;
1937   switch (Kind) {
1938     case MCK_0: ImmVal = 0; break;
1939     case MCK_1: ImmVal = 1; break;
1940     case MCK_2: ImmVal = 2; break;
1941     case MCK_3: ImmVal = 3; break;
1942     case MCK_4: ImmVal = 4; break;
1943     case MCK_5: ImmVal = 5; break;
1944     case MCK_6: ImmVal = 6; break;
1945     case MCK_7: ImmVal = 7; break;
1946     default: return Match_InvalidOperand;
1947   }
1948 
1949   PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1950   if (Op.isImm() && Op.getImm() == ImmVal)
1951     return Match_Success;
1952 
1953   return Match_InvalidOperand;
1954 }
1955 
1956 const MCExpr *
1957 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1958                                   MCSymbolRefExpr::VariantKind Variant,
1959                                   MCContext &Ctx) {
1960   switch (Variant) {
1961   case MCSymbolRefExpr::VK_PPC_LO:
1962     return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1963   case MCSymbolRefExpr::VK_PPC_HI:
1964     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1965   case MCSymbolRefExpr::VK_PPC_HA:
1966     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1967   case MCSymbolRefExpr::VK_PPC_HIGHER:
1968     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1969   case MCSymbolRefExpr::VK_PPC_HIGHERA:
1970     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1971   case MCSymbolRefExpr::VK_PPC_HIGHEST:
1972     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1973   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1974     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1975   default:
1976     return nullptr;
1977   }
1978 }
1979