xref: /llvm-project/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (revision b86cb7d04be194b37df4bfbb0e506736cf73de14) 
1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "llvm/MC/MCTargetAsmParser.h"
13 #include "llvm/MC/MCStreamer.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/ADT/Twine.h"
25 #include "llvm/Support/SourceMgr.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
28 
29 using namespace llvm;
30 
31 namespace {
32 
33 static unsigned RRegs[32] = {
34   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
35   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
36   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
37   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
38   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
39   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
40   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
41   PPC::R28, PPC::R29, PPC::R30, PPC::R31
42 };
43 static unsigned RRegsNoR0[32] = {
44   PPC::ZERO,
45             PPC::R1,  PPC::R2,  PPC::R3,
46   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
47   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
48   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
49   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
50   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
51   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
52   PPC::R28, PPC::R29, PPC::R30, PPC::R31
53 };
54 static unsigned XRegs[32] = {
55   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
56   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
57   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
58   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
59   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
60   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
61   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
62   PPC::X28, PPC::X29, PPC::X30, PPC::X31
63 };
64 static unsigned XRegsNoX0[32] = {
65   PPC::ZERO8,
66             PPC::X1,  PPC::X2,  PPC::X3,
67   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
68   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
69   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
70   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
71   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
72   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
73   PPC::X28, PPC::X29, PPC::X30, PPC::X31
74 };
75 static unsigned FRegs[32] = {
76   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
77   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
78   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
79   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
80   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
81   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
82   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
83   PPC::F28, PPC::F29, PPC::F30, PPC::F31
84 };
85 static unsigned VRegs[32] = {
86   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
87   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
88   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
89   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
90   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
91   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
92   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
93   PPC::V28, PPC::V29, PPC::V30, PPC::V31
94 };
95 static unsigned CRBITRegs[32] = {
96   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
97   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
98   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
99   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
100   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
101   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
102   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
103   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
104 };
105 static unsigned CRRegs[8] = {
106   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
107   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
108 };
109 
110 // Evaluate an expression containing condition register
111 // or condition register field symbols.  Returns positive
112 // value on success, or -1 on error.
113 static int64_t
114 EvaluateCRExpr(const MCExpr *E) {
115   switch (E->getKind()) {
116   case MCExpr::Target:
117     return -1;
118 
119   case MCExpr::Constant: {
120     int64_t Res = cast<MCConstantExpr>(E)->getValue();
121     return Res < 0 ? -1 : Res;
122   }
123 
124   case MCExpr::SymbolRef: {
125     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
126     StringRef Name = SRE->getSymbol().getName();
127 
128     if (Name == "lt") return 0;
129     if (Name == "gt") return 1;
130     if (Name == "eq") return 2;
131     if (Name == "so") return 3;
132     if (Name == "un") return 3;
133 
134     if (Name == "cr0") return 0;
135     if (Name == "cr1") return 1;
136     if (Name == "cr2") return 2;
137     if (Name == "cr3") return 3;
138     if (Name == "cr4") return 4;
139     if (Name == "cr5") return 5;
140     if (Name == "cr6") return 6;
141     if (Name == "cr7") return 7;
142 
143     return -1;
144   }
145 
146   case MCExpr::Unary:
147     return -1;
148 
149   case MCExpr::Binary: {
150     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
151     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
152     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
153     int64_t Res;
154 
155     if (LHSVal < 0 || RHSVal < 0)
156       return -1;
157 
158     switch (BE->getOpcode()) {
159     default: return -1;
160     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
161     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
162     }
163 
164     return Res < 0 ? -1 : Res;
165   }
166   }
167 
168   llvm_unreachable("Invalid expression kind!");
169 }
170 
171 struct PPCOperand;
172 
173 class PPCAsmParser : public MCTargetAsmParser {
174   MCSubtargetInfo &STI;
175   MCAsmParser &Parser;
176   bool IsPPC64;
177 
178   MCAsmParser &getParser() const { return Parser; }
179   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
180 
181   void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
182   bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
183 
184   bool isPPC64() const { return IsPPC64; }
185 
186   bool MatchRegisterName(const AsmToken &Tok,
187                          unsigned &RegNo, int64_t &IntVal);
188 
189   virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
190 
191   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
192                                         PPCMCExpr::VariantKind &Variant);
193   bool ParseExpression(const MCExpr *&EVal);
194 
195   bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
196 
197   bool ParseDirectiveWord(unsigned Size, SMLoc L);
198   bool ParseDirectiveTC(unsigned Size, SMLoc L);
199 
200   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
201                                SmallVectorImpl<MCParsedAsmOperand*> &Operands,
202                                MCStreamer &Out, unsigned &ErrorInfo,
203                                bool MatchingInlineAsm);
204 
205   void ProcessInstruction(MCInst &Inst,
206                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
207 
208   /// @name Auto-generated Match Functions
209   /// {
210 
211 #define GET_ASSEMBLER_HEADER
212 #include "PPCGenAsmMatcher.inc"
213 
214   /// }
215 
216 
217 public:
218   PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
219     : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
220     // Check for 64-bit vs. 32-bit pointer mode.
221     Triple TheTriple(STI.getTargetTriple());
222     IsPPC64 = TheTriple.getArch() == Triple::ppc64;
223     // Initialize the set of available features.
224     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
225   }
226 
227   virtual bool ParseInstruction(ParseInstructionInfo &Info,
228                                 StringRef Name, SMLoc NameLoc,
229                                 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
230 
231   virtual bool ParseDirective(AsmToken DirectiveID);
232 };
233 
234 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
235 /// instruction.
236 struct PPCOperand : public MCParsedAsmOperand {
237   enum KindTy {
238     Token,
239     Immediate,
240     Expression
241   } Kind;
242 
243   SMLoc StartLoc, EndLoc;
244   bool IsPPC64;
245 
246   struct TokOp {
247     const char *Data;
248     unsigned Length;
249   };
250 
251   struct ImmOp {
252     int64_t Val;
253   };
254 
255   struct ExprOp {
256     const MCExpr *Val;
257     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
258   };
259 
260   union {
261     struct TokOp Tok;
262     struct ImmOp Imm;
263     struct ExprOp Expr;
264   };
265 
266   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
267 public:
268   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
269     Kind = o.Kind;
270     StartLoc = o.StartLoc;
271     EndLoc = o.EndLoc;
272     IsPPC64 = o.IsPPC64;
273     switch (Kind) {
274     case Token:
275       Tok = o.Tok;
276       break;
277     case Immediate:
278       Imm = o.Imm;
279       break;
280     case Expression:
281       Expr = o.Expr;
282       break;
283     }
284   }
285 
286   /// getStartLoc - Get the location of the first token of this operand.
287   SMLoc getStartLoc() const { return StartLoc; }
288 
289   /// getEndLoc - Get the location of the last token of this operand.
290   SMLoc getEndLoc() const { return EndLoc; }
291 
292   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
293   bool isPPC64() const { return IsPPC64; }
294 
295   int64_t getImm() const {
296     assert(Kind == Immediate && "Invalid access!");
297     return Imm.Val;
298   }
299 
300   const MCExpr *getExpr() const {
301     assert(Kind == Expression && "Invalid access!");
302     return Expr.Val;
303   }
304 
305   int64_t getExprCRVal() const {
306     assert(Kind == Expression && "Invalid access!");
307     return Expr.CRVal;
308   }
309 
310   unsigned getReg() const {
311     assert(isRegNumber() && "Invalid access!");
312     return (unsigned) Imm.Val;
313   }
314 
315   unsigned getCCReg() const {
316     assert(isCCRegNumber() && "Invalid access!");
317     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
318   }
319 
320   unsigned getCRBit() const {
321     assert(isCRBitNumber() && "Invalid access!");
322     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
323   }
324 
325   unsigned getCRBitMask() const {
326     assert(isCRBitMask() && "Invalid access!");
327     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
328   }
329 
330   bool isToken() const { return Kind == Token; }
331   bool isImm() const { return Kind == Immediate || Kind == Expression; }
332   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
333   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
334   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
335   bool isU16Imm() const { return Kind == Expression ||
336                                  (Kind == Immediate && isUInt<16>(getImm())); }
337   bool isS16Imm() const { return Kind == Expression ||
338                                  (Kind == Immediate && isInt<16>(getImm())); }
339   bool isS16ImmX4() const { return Kind == Expression ||
340                                    (Kind == Immediate && isInt<16>(getImm()) &&
341                                     (getImm() & 3) == 0); }
342   bool isS17Imm() const { return Kind == Expression ||
343                                  (Kind == Immediate && isInt<17>(getImm())); }
344   bool isDirectBr() const { return Kind == Expression ||
345                                    (Kind == Immediate && isInt<26>(getImm()) &&
346                                     (getImm() & 3) == 0); }
347   bool isCondBr() const { return Kind == Expression ||
348                                  (Kind == Immediate && isInt<16>(getImm()) &&
349                                   (getImm() & 3) == 0); }
350   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
351   bool isCCRegNumber() const { return (Kind == Expression
352                                        && isUInt<3>(getExprCRVal())) ||
353                                       (Kind == Immediate
354                                        && isUInt<3>(getImm())); }
355   bool isCRBitNumber() const { return (Kind == Expression
356                                        && isUInt<5>(getExprCRVal())) ||
357                                       (Kind == Immediate
358                                        && isUInt<5>(getImm())); }
359   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
360                                     isPowerOf2_32(getImm()); }
361   bool isMem() const { return false; }
362   bool isReg() const { return false; }
363 
364   void addRegOperands(MCInst &Inst, unsigned N) const {
365     llvm_unreachable("addRegOperands");
366   }
367 
368   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
369     assert(N == 1 && "Invalid number of operands!");
370     Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
371   }
372 
373   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
374     assert(N == 1 && "Invalid number of operands!");
375     Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
376   }
377 
378   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
379     assert(N == 1 && "Invalid number of operands!");
380     Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
381   }
382 
383   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
384     assert(N == 1 && "Invalid number of operands!");
385     Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
386   }
387 
388   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
389     if (isPPC64())
390       addRegG8RCOperands(Inst, N);
391     else
392       addRegGPRCOperands(Inst, N);
393   }
394 
395   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
396     if (isPPC64())
397       addRegG8RCNoX0Operands(Inst, N);
398     else
399       addRegGPRCNoR0Operands(Inst, N);
400   }
401 
402   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
403     assert(N == 1 && "Invalid number of operands!");
404     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
405   }
406 
407   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
408     assert(N == 1 && "Invalid number of operands!");
409     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
410   }
411 
412   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
413     assert(N == 1 && "Invalid number of operands!");
414     Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
415   }
416 
417   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
418     assert(N == 1 && "Invalid number of operands!");
419     Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
420   }
421 
422   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
423     assert(N == 1 && "Invalid number of operands!");
424     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
425   }
426 
427   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
428     assert(N == 1 && "Invalid number of operands!");
429     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
430   }
431 
432   void addImmOperands(MCInst &Inst, unsigned N) const {
433     assert(N == 1 && "Invalid number of operands!");
434     if (Kind == Immediate)
435       Inst.addOperand(MCOperand::CreateImm(getImm()));
436     else
437       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
438   }
439 
440   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
441     assert(N == 1 && "Invalid number of operands!");
442     if (Kind == Immediate)
443       Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
444     else
445       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
446   }
447 
448   StringRef getToken() const {
449     assert(Kind == Token && "Invalid access!");
450     return StringRef(Tok.Data, Tok.Length);
451   }
452 
453   virtual void print(raw_ostream &OS) const;
454 
455   static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
456     PPCOperand *Op = new PPCOperand(Token);
457     Op->Tok.Data = Str.data();
458     Op->Tok.Length = Str.size();
459     Op->StartLoc = S;
460     Op->EndLoc = S;
461     Op->IsPPC64 = IsPPC64;
462     return Op;
463   }
464 
465   static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
466     PPCOperand *Op = new PPCOperand(Immediate);
467     Op->Imm.Val = Val;
468     Op->StartLoc = S;
469     Op->EndLoc = E;
470     Op->IsPPC64 = IsPPC64;
471     return Op;
472   }
473 
474   static PPCOperand *CreateExpr(const MCExpr *Val,
475                                 SMLoc S, SMLoc E, bool IsPPC64) {
476     PPCOperand *Op = new PPCOperand(Expression);
477     Op->Expr.Val = Val;
478     Op->Expr.CRVal = EvaluateCRExpr(Val);
479     Op->StartLoc = S;
480     Op->EndLoc = E;
481     Op->IsPPC64 = IsPPC64;
482     return Op;
483   }
484 };
485 
486 } // end anonymous namespace.
487 
488 void PPCOperand::print(raw_ostream &OS) const {
489   switch (Kind) {
490   case Token:
491     OS << "'" << getToken() << "'";
492     break;
493   case Immediate:
494     OS << getImm();
495     break;
496   case Expression:
497     getExpr()->print(OS);
498     break;
499   }
500 }
501 
502 
503 void PPCAsmParser::
504 ProcessInstruction(MCInst &Inst,
505                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
506   int Opcode = Inst.getOpcode();
507   switch (Opcode) {
508   case PPC::LAx: {
509     MCInst TmpInst;
510     TmpInst.setOpcode(PPC::LA);
511     TmpInst.addOperand(Inst.getOperand(0));
512     TmpInst.addOperand(Inst.getOperand(2));
513     TmpInst.addOperand(Inst.getOperand(1));
514     Inst = TmpInst;
515     break;
516   }
517   case PPC::SUBI: {
518     MCInst TmpInst;
519     int64_t N = Inst.getOperand(2).getImm();
520     TmpInst.setOpcode(PPC::ADDI);
521     TmpInst.addOperand(Inst.getOperand(0));
522     TmpInst.addOperand(Inst.getOperand(1));
523     TmpInst.addOperand(MCOperand::CreateImm(-N));
524     Inst = TmpInst;
525     break;
526   }
527   case PPC::SUBIS: {
528     MCInst TmpInst;
529     int64_t N = Inst.getOperand(2).getImm();
530     TmpInst.setOpcode(PPC::ADDIS);
531     TmpInst.addOperand(Inst.getOperand(0));
532     TmpInst.addOperand(Inst.getOperand(1));
533     TmpInst.addOperand(MCOperand::CreateImm(-N));
534     Inst = TmpInst;
535     break;
536   }
537   case PPC::SUBIC: {
538     MCInst TmpInst;
539     int64_t N = Inst.getOperand(2).getImm();
540     TmpInst.setOpcode(PPC::ADDIC);
541     TmpInst.addOperand(Inst.getOperand(0));
542     TmpInst.addOperand(Inst.getOperand(1));
543     TmpInst.addOperand(MCOperand::CreateImm(-N));
544     Inst = TmpInst;
545     break;
546   }
547   case PPC::SUBICo: {
548     MCInst TmpInst;
549     int64_t N = Inst.getOperand(2).getImm();
550     TmpInst.setOpcode(PPC::ADDICo);
551     TmpInst.addOperand(Inst.getOperand(0));
552     TmpInst.addOperand(Inst.getOperand(1));
553     TmpInst.addOperand(MCOperand::CreateImm(-N));
554     Inst = TmpInst;
555     break;
556   }
557   case PPC::EXTLWI:
558   case PPC::EXTLWIo: {
559     MCInst TmpInst;
560     int64_t N = Inst.getOperand(2).getImm();
561     int64_t B = Inst.getOperand(3).getImm();
562     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
563     TmpInst.addOperand(Inst.getOperand(0));
564     TmpInst.addOperand(Inst.getOperand(1));
565     TmpInst.addOperand(MCOperand::CreateImm(B));
566     TmpInst.addOperand(MCOperand::CreateImm(0));
567     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
568     Inst = TmpInst;
569     break;
570   }
571   case PPC::EXTRWI:
572   case PPC::EXTRWIo: {
573     MCInst TmpInst;
574     int64_t N = Inst.getOperand(2).getImm();
575     int64_t B = Inst.getOperand(3).getImm();
576     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
577     TmpInst.addOperand(Inst.getOperand(0));
578     TmpInst.addOperand(Inst.getOperand(1));
579     TmpInst.addOperand(MCOperand::CreateImm(B + N));
580     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
581     TmpInst.addOperand(MCOperand::CreateImm(31));
582     Inst = TmpInst;
583     break;
584   }
585   case PPC::INSLWI:
586   case PPC::INSLWIo: {
587     MCInst TmpInst;
588     int64_t N = Inst.getOperand(2).getImm();
589     int64_t B = Inst.getOperand(3).getImm();
590     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
591     TmpInst.addOperand(Inst.getOperand(0));
592     TmpInst.addOperand(Inst.getOperand(0));
593     TmpInst.addOperand(Inst.getOperand(1));
594     TmpInst.addOperand(MCOperand::CreateImm(32 - B));
595     TmpInst.addOperand(MCOperand::CreateImm(B));
596     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
597     Inst = TmpInst;
598     break;
599   }
600   case PPC::INSRWI:
601   case PPC::INSRWIo: {
602     MCInst TmpInst;
603     int64_t N = Inst.getOperand(2).getImm();
604     int64_t B = Inst.getOperand(3).getImm();
605     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
606     TmpInst.addOperand(Inst.getOperand(0));
607     TmpInst.addOperand(Inst.getOperand(0));
608     TmpInst.addOperand(Inst.getOperand(1));
609     TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
610     TmpInst.addOperand(MCOperand::CreateImm(B));
611     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
612     Inst = TmpInst;
613     break;
614   }
615   case PPC::ROTRWI:
616   case PPC::ROTRWIo: {
617     MCInst TmpInst;
618     int64_t N = Inst.getOperand(2).getImm();
619     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
620     TmpInst.addOperand(Inst.getOperand(0));
621     TmpInst.addOperand(Inst.getOperand(1));
622     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
623     TmpInst.addOperand(MCOperand::CreateImm(0));
624     TmpInst.addOperand(MCOperand::CreateImm(31));
625     Inst = TmpInst;
626     break;
627   }
628   case PPC::SLWI:
629   case PPC::SLWIo: {
630     MCInst TmpInst;
631     int64_t N = Inst.getOperand(2).getImm();
632     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
633     TmpInst.addOperand(Inst.getOperand(0));
634     TmpInst.addOperand(Inst.getOperand(1));
635     TmpInst.addOperand(MCOperand::CreateImm(N));
636     TmpInst.addOperand(MCOperand::CreateImm(0));
637     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
638     Inst = TmpInst;
639     break;
640   }
641   case PPC::SRWI:
642   case PPC::SRWIo: {
643     MCInst TmpInst;
644     int64_t N = Inst.getOperand(2).getImm();
645     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
646     TmpInst.addOperand(Inst.getOperand(0));
647     TmpInst.addOperand(Inst.getOperand(1));
648     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
649     TmpInst.addOperand(MCOperand::CreateImm(N));
650     TmpInst.addOperand(MCOperand::CreateImm(31));
651     Inst = TmpInst;
652     break;
653   }
654   case PPC::CLRRWI:
655   case PPC::CLRRWIo: {
656     MCInst TmpInst;
657     int64_t N = Inst.getOperand(2).getImm();
658     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
659     TmpInst.addOperand(Inst.getOperand(0));
660     TmpInst.addOperand(Inst.getOperand(1));
661     TmpInst.addOperand(MCOperand::CreateImm(0));
662     TmpInst.addOperand(MCOperand::CreateImm(0));
663     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
664     Inst = TmpInst;
665     break;
666   }
667   case PPC::CLRLSLWI:
668   case PPC::CLRLSLWIo: {
669     MCInst TmpInst;
670     int64_t B = Inst.getOperand(2).getImm();
671     int64_t N = Inst.getOperand(3).getImm();
672     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
673     TmpInst.addOperand(Inst.getOperand(0));
674     TmpInst.addOperand(Inst.getOperand(1));
675     TmpInst.addOperand(MCOperand::CreateImm(N));
676     TmpInst.addOperand(MCOperand::CreateImm(B - N));
677     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
678     Inst = TmpInst;
679     break;
680   }
681   case PPC::EXTLDI:
682   case PPC::EXTLDIo: {
683     MCInst TmpInst;
684     int64_t N = Inst.getOperand(2).getImm();
685     int64_t B = Inst.getOperand(3).getImm();
686     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
687     TmpInst.addOperand(Inst.getOperand(0));
688     TmpInst.addOperand(Inst.getOperand(1));
689     TmpInst.addOperand(MCOperand::CreateImm(B));
690     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
691     Inst = TmpInst;
692     break;
693   }
694   case PPC::EXTRDI:
695   case PPC::EXTRDIo: {
696     MCInst TmpInst;
697     int64_t N = Inst.getOperand(2).getImm();
698     int64_t B = Inst.getOperand(3).getImm();
699     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
700     TmpInst.addOperand(Inst.getOperand(0));
701     TmpInst.addOperand(Inst.getOperand(1));
702     TmpInst.addOperand(MCOperand::CreateImm(B + N));
703     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
704     Inst = TmpInst;
705     break;
706   }
707   case PPC::INSRDI:
708   case PPC::INSRDIo: {
709     MCInst TmpInst;
710     int64_t N = Inst.getOperand(2).getImm();
711     int64_t B = Inst.getOperand(3).getImm();
712     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
713     TmpInst.addOperand(Inst.getOperand(0));
714     TmpInst.addOperand(Inst.getOperand(0));
715     TmpInst.addOperand(Inst.getOperand(1));
716     TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
717     TmpInst.addOperand(MCOperand::CreateImm(B));
718     Inst = TmpInst;
719     break;
720   }
721   case PPC::ROTRDI:
722   case PPC::ROTRDIo: {
723     MCInst TmpInst;
724     int64_t N = Inst.getOperand(2).getImm();
725     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
726     TmpInst.addOperand(Inst.getOperand(0));
727     TmpInst.addOperand(Inst.getOperand(1));
728     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
729     TmpInst.addOperand(MCOperand::CreateImm(0));
730     Inst = TmpInst;
731     break;
732   }
733   case PPC::SLDI:
734   case PPC::SLDIo: {
735     MCInst TmpInst;
736     int64_t N = Inst.getOperand(2).getImm();
737     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
738     TmpInst.addOperand(Inst.getOperand(0));
739     TmpInst.addOperand(Inst.getOperand(1));
740     TmpInst.addOperand(MCOperand::CreateImm(N));
741     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
742     Inst = TmpInst;
743     break;
744   }
745   case PPC::SRDI:
746   case PPC::SRDIo: {
747     MCInst TmpInst;
748     int64_t N = Inst.getOperand(2).getImm();
749     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
750     TmpInst.addOperand(Inst.getOperand(0));
751     TmpInst.addOperand(Inst.getOperand(1));
752     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
753     TmpInst.addOperand(MCOperand::CreateImm(N));
754     Inst = TmpInst;
755     break;
756   }
757   case PPC::CLRRDI:
758   case PPC::CLRRDIo: {
759     MCInst TmpInst;
760     int64_t N = Inst.getOperand(2).getImm();
761     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
762     TmpInst.addOperand(Inst.getOperand(0));
763     TmpInst.addOperand(Inst.getOperand(1));
764     TmpInst.addOperand(MCOperand::CreateImm(0));
765     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
766     Inst = TmpInst;
767     break;
768   }
769   case PPC::CLRLSLDI:
770   case PPC::CLRLSLDIo: {
771     MCInst TmpInst;
772     int64_t B = Inst.getOperand(2).getImm();
773     int64_t N = Inst.getOperand(3).getImm();
774     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
775     TmpInst.addOperand(Inst.getOperand(0));
776     TmpInst.addOperand(Inst.getOperand(1));
777     TmpInst.addOperand(MCOperand::CreateImm(N));
778     TmpInst.addOperand(MCOperand::CreateImm(B - N));
779     Inst = TmpInst;
780     break;
781   }
782   }
783 }
784 
785 bool PPCAsmParser::
786 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
787                         SmallVectorImpl<MCParsedAsmOperand*> &Operands,
788                         MCStreamer &Out, unsigned &ErrorInfo,
789                         bool MatchingInlineAsm) {
790   MCInst Inst;
791 
792   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
793   default: break;
794   case Match_Success:
795     // Post-process instructions (typically extended mnemonics)
796     ProcessInstruction(Inst, Operands);
797     Inst.setLoc(IDLoc);
798     Out.EmitInstruction(Inst);
799     return false;
800   case Match_MissingFeature:
801     return Error(IDLoc, "instruction use requires an option to be enabled");
802   case Match_MnemonicFail:
803       return Error(IDLoc, "unrecognized instruction mnemonic");
804   case Match_InvalidOperand: {
805     SMLoc ErrorLoc = IDLoc;
806     if (ErrorInfo != ~0U) {
807       if (ErrorInfo >= Operands.size())
808         return Error(IDLoc, "too few operands for instruction");
809 
810       ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
811       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
812     }
813 
814     return Error(ErrorLoc, "invalid operand for instruction");
815   }
816   }
817 
818   llvm_unreachable("Implement any new match types added!");
819 }
820 
821 bool PPCAsmParser::
822 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
823   if (Tok.is(AsmToken::Identifier)) {
824     StringRef Name = Tok.getString();
825 
826     if (Name.equals_lower("lr")) {
827       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
828       IntVal = 8;
829       return false;
830     } else if (Name.equals_lower("ctr")) {
831       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
832       IntVal = 9;
833       return false;
834     } else if (Name.equals_lower("vrsave")) {
835       RegNo = PPC::VRSAVE;
836       IntVal = 256;
837       return false;
838     } else if (Name.substr(0, 1).equals_lower("r") &&
839                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
840       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
841       return false;
842     } else if (Name.substr(0, 1).equals_lower("f") &&
843                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
844       RegNo = FRegs[IntVal];
845       return false;
846     } else if (Name.substr(0, 1).equals_lower("v") &&
847                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
848       RegNo = VRegs[IntVal];
849       return false;
850     } else if (Name.substr(0, 2).equals_lower("cr") &&
851                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
852       RegNo = CRRegs[IntVal];
853       return false;
854     }
855   }
856 
857   return true;
858 }
859 
860 bool PPCAsmParser::
861 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
862   const AsmToken &Tok = Parser.getTok();
863   StartLoc = Tok.getLoc();
864   EndLoc = Tok.getEndLoc();
865   RegNo = 0;
866   int64_t IntVal;
867 
868   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
869     Parser.Lex(); // Eat identifier token.
870     return false;
871   }
872 
873   return Error(StartLoc, "invalid register name");
874 }
875 
876 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
877 /// the expression and check for VK_PPC_LO/HI/HA
878 /// symbol variants.  If all symbols with modifier use the same
879 /// variant, return the corresponding PPCMCExpr::VariantKind,
880 /// and a modified expression using the default symbol variant.
881 /// Otherwise, return NULL.
882 const MCExpr *PPCAsmParser::
883 ExtractModifierFromExpr(const MCExpr *E,
884                         PPCMCExpr::VariantKind &Variant) {
885   MCContext &Context = getParser().getContext();
886   Variant = PPCMCExpr::VK_PPC_None;
887 
888   switch (E->getKind()) {
889   case MCExpr::Target:
890   case MCExpr::Constant:
891     return 0;
892 
893   case MCExpr::SymbolRef: {
894     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
895 
896     switch (SRE->getKind()) {
897     case MCSymbolRefExpr::VK_PPC_LO:
898       Variant = PPCMCExpr::VK_PPC_LO;
899       break;
900     case MCSymbolRefExpr::VK_PPC_HI:
901       Variant = PPCMCExpr::VK_PPC_HI;
902       break;
903     case MCSymbolRefExpr::VK_PPC_HA:
904       Variant = PPCMCExpr::VK_PPC_HA;
905       break;
906     case MCSymbolRefExpr::VK_PPC_HIGHER:
907       Variant = PPCMCExpr::VK_PPC_HIGHER;
908       break;
909     case MCSymbolRefExpr::VK_PPC_HIGHERA:
910       Variant = PPCMCExpr::VK_PPC_HIGHERA;
911       break;
912     case MCSymbolRefExpr::VK_PPC_HIGHEST:
913       Variant = PPCMCExpr::VK_PPC_HIGHEST;
914       break;
915     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
916       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
917       break;
918     default:
919       return 0;
920     }
921 
922     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
923   }
924 
925   case MCExpr::Unary: {
926     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
927     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
928     if (!Sub)
929       return 0;
930     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
931   }
932 
933   case MCExpr::Binary: {
934     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
935     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
936     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
937     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
938 
939     if (!LHS && !RHS)
940       return 0;
941 
942     if (!LHS) LHS = BE->getLHS();
943     if (!RHS) RHS = BE->getRHS();
944 
945     if (LHSVariant == PPCMCExpr::VK_PPC_None)
946       Variant = RHSVariant;
947     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
948       Variant = LHSVariant;
949     else if (LHSVariant == RHSVariant)
950       Variant = LHSVariant;
951     else
952       return 0;
953 
954     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
955   }
956   }
957 
958   llvm_unreachable("Invalid expression kind!");
959 }
960 
961 /// Parse an expression.  This differs from the default "parseExpression"
962 /// in that it handles complex \code @l/@ha \endcode modifiers.
963 bool PPCAsmParser::
964 ParseExpression(const MCExpr *&EVal) {
965   if (getParser().parseExpression(EVal))
966     return true;
967 
968   PPCMCExpr::VariantKind Variant;
969   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
970   if (E)
971     EVal = PPCMCExpr::Create(Variant, E, getParser().getContext());
972 
973   return false;
974 }
975 
976 bool PPCAsmParser::
977 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
978   SMLoc S = Parser.getTok().getLoc();
979   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
980   const MCExpr *EVal;
981   PPCOperand *Op;
982 
983   // Attempt to parse the next token as an immediate
984   switch (getLexer().getKind()) {
985   // Special handling for register names.  These are interpreted
986   // as immediates corresponding to the register number.
987   case AsmToken::Percent:
988     Parser.Lex(); // Eat the '%'.
989     unsigned RegNo;
990     int64_t IntVal;
991     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
992       Parser.Lex(); // Eat the identifier token.
993       Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
994       Operands.push_back(Op);
995       return false;
996     }
997     return Error(S, "invalid register name");
998 
999   // All other expressions
1000   case AsmToken::LParen:
1001   case AsmToken::Plus:
1002   case AsmToken::Minus:
1003   case AsmToken::Integer:
1004   case AsmToken::Identifier:
1005   case AsmToken::Dot:
1006   case AsmToken::Dollar:
1007     if (!ParseExpression(EVal))
1008       break;
1009     /* fall through */
1010   default:
1011     return Error(S, "unknown operand");
1012   }
1013 
1014   if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(EVal))
1015     Op = PPCOperand::CreateImm(CE->getValue(), S, E, isPPC64());
1016   else
1017     Op = PPCOperand::CreateExpr(EVal, S, E, isPPC64());
1018 
1019   // Push the parsed operand into the list of operands
1020   Operands.push_back(Op);
1021 
1022   // Check whether this is a TLS call expression
1023   bool TLSCall = false;
1024   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1025     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1026 
1027   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1028     const MCExpr *TLSSym;
1029 
1030     Parser.Lex(); // Eat the '('.
1031     S = Parser.getTok().getLoc();
1032     if (ParseExpression(TLSSym))
1033       return Error(S, "invalid TLS call expression");
1034     if (getLexer().isNot(AsmToken::RParen))
1035       return Error(Parser.getTok().getLoc(), "missing ')'");
1036     E = Parser.getTok().getLoc();
1037     Parser.Lex(); // Eat the ')'.
1038 
1039     Op = PPCOperand::CreateExpr(TLSSym, S, E, isPPC64());
1040     Operands.push_back(Op);
1041   }
1042 
1043   // Otherwise, check for D-form memory operands
1044   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1045     Parser.Lex(); // Eat the '('.
1046     S = Parser.getTok().getLoc();
1047 
1048     int64_t IntVal;
1049     switch (getLexer().getKind()) {
1050     case AsmToken::Percent:
1051       Parser.Lex(); // Eat the '%'.
1052       unsigned RegNo;
1053       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1054         return Error(S, "invalid register name");
1055       Parser.Lex(); // Eat the identifier token.
1056       break;
1057 
1058     case AsmToken::Integer:
1059       if (getParser().parseAbsoluteExpression(IntVal) ||
1060           IntVal < 0 || IntVal > 31)
1061         return Error(S, "invalid register number");
1062       break;
1063 
1064     default:
1065       return Error(S, "invalid memory operand");
1066     }
1067 
1068     if (getLexer().isNot(AsmToken::RParen))
1069       return Error(Parser.getTok().getLoc(), "missing ')'");
1070     E = Parser.getTok().getLoc();
1071     Parser.Lex(); // Eat the ')'.
1072 
1073     Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1074     Operands.push_back(Op);
1075   }
1076 
1077   return false;
1078 }
1079 
1080 /// Parse an instruction mnemonic followed by its operands.
1081 bool PPCAsmParser::
1082 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1083                  SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1084   // The first operand is the token for the instruction name.
1085   // If the next character is a '+' or '-', we need to add it to the
1086   // instruction name, to match what TableGen is doing.
1087   if (getLexer().is(AsmToken::Plus)) {
1088     getLexer().Lex();
1089     char *NewOpcode = new char[Name.size() + 1];
1090     memcpy(NewOpcode, Name.data(), Name.size());
1091     NewOpcode[Name.size()] = '+';
1092     Name = StringRef(NewOpcode, Name.size() + 1);
1093   }
1094   if (getLexer().is(AsmToken::Minus)) {
1095     getLexer().Lex();
1096     char *NewOpcode = new char[Name.size() + 1];
1097     memcpy(NewOpcode, Name.data(), Name.size());
1098     NewOpcode[Name.size()] = '-';
1099     Name = StringRef(NewOpcode, Name.size() + 1);
1100   }
1101   // If the instruction ends in a '.', we need to create a separate
1102   // token for it, to match what TableGen is doing.
1103   size_t Dot = Name.find('.');
1104   StringRef Mnemonic = Name.slice(0, Dot);
1105   Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1106   if (Dot != StringRef::npos) {
1107     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1108     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1109     Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1110   }
1111 
1112   // If there are no more operands then finish
1113   if (getLexer().is(AsmToken::EndOfStatement))
1114     return false;
1115 
1116   // Parse the first operand
1117   if (ParseOperand(Operands))
1118     return true;
1119 
1120   while (getLexer().isNot(AsmToken::EndOfStatement) &&
1121          getLexer().is(AsmToken::Comma)) {
1122     // Consume the comma token
1123     getLexer().Lex();
1124 
1125     // Parse the next operand
1126     if (ParseOperand(Operands))
1127       return true;
1128   }
1129 
1130   return false;
1131 }
1132 
1133 /// ParseDirective parses the PPC specific directives
1134 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1135   StringRef IDVal = DirectiveID.getIdentifier();
1136   if (IDVal == ".word")
1137     return ParseDirectiveWord(4, DirectiveID.getLoc());
1138   if (IDVal == ".tc")
1139     return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1140   return true;
1141 }
1142 
1143 /// ParseDirectiveWord
1144 ///  ::= .word [ expression (, expression)* ]
1145 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1146   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1147     for (;;) {
1148       const MCExpr *Value;
1149       if (getParser().parseExpression(Value))
1150         return true;
1151 
1152       getParser().getStreamer().EmitValue(Value, Size);
1153 
1154       if (getLexer().is(AsmToken::EndOfStatement))
1155         break;
1156 
1157       if (getLexer().isNot(AsmToken::Comma))
1158         return Error(L, "unexpected token in directive");
1159       Parser.Lex();
1160     }
1161   }
1162 
1163   Parser.Lex();
1164   return false;
1165 }
1166 
1167 /// ParseDirectiveTC
1168 ///  ::= .tc [ symbol (, expression)* ]
1169 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1170   // Skip TC symbol, which is only used with XCOFF.
1171   while (getLexer().isNot(AsmToken::EndOfStatement)
1172          && getLexer().isNot(AsmToken::Comma))
1173     Parser.Lex();
1174   if (getLexer().isNot(AsmToken::Comma))
1175     return Error(L, "unexpected token in directive");
1176   Parser.Lex();
1177 
1178   // Align to word size.
1179   getParser().getStreamer().EmitValueToAlignment(Size);
1180 
1181   // Emit expressions.
1182   return ParseDirectiveWord(Size, L);
1183 }
1184 
1185 /// Force static initialization.
1186 extern "C" void LLVMInitializePowerPCAsmParser() {
1187   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1188   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1189 }
1190 
1191 #define GET_REGISTER_MATCHER
1192 #define GET_MATCHER_IMPLEMENTATION
1193 #include "PPCGenAsmMatcher.inc"
1194