1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/PPCMCTargetDesc.h" 11 #include "MCTargetDesc/PPCMCExpr.h" 12 #include "llvm/MC/MCTargetAsmParser.h" 13 #include "llvm/MC/MCStreamer.h" 14 #include "llvm/MC/MCExpr.h" 15 #include "llvm/MC/MCInst.h" 16 #include "llvm/MC/MCRegisterInfo.h" 17 #include "llvm/MC/MCSubtargetInfo.h" 18 #include "llvm/MC/MCParser/MCAsmLexer.h" 19 #include "llvm/MC/MCParser/MCAsmParser.h" 20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 21 #include "llvm/ADT/SmallString.h" 22 #include "llvm/ADT/SmallVector.h" 23 #include "llvm/ADT/StringSwitch.h" 24 #include "llvm/ADT/Twine.h" 25 #include "llvm/Support/SourceMgr.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 using namespace llvm; 30 31 namespace { 32 33 static unsigned RRegs[32] = { 34 PPC::R0, PPC::R1, PPC::R2, PPC::R3, 35 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 36 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 37 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 38 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 39 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 40 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 41 PPC::R28, PPC::R29, PPC::R30, PPC::R31 42 }; 43 static unsigned RRegsNoR0[32] = { 44 PPC::ZERO, 45 PPC::R1, PPC::R2, PPC::R3, 46 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 47 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 48 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 49 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 50 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 51 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 52 PPC::R28, PPC::R29, PPC::R30, PPC::R31 53 }; 54 static unsigned XRegs[32] = { 55 PPC::X0, PPC::X1, PPC::X2, PPC::X3, 56 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 57 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 58 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 59 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 60 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 61 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 62 PPC::X28, PPC::X29, PPC::X30, PPC::X31 63 }; 64 static unsigned XRegsNoX0[32] = { 65 PPC::ZERO8, 66 PPC::X1, PPC::X2, PPC::X3, 67 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 68 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 69 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 70 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 71 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 72 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 73 PPC::X28, PPC::X29, PPC::X30, PPC::X31 74 }; 75 static unsigned FRegs[32] = { 76 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 77 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 78 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 79 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 80 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 81 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 82 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 83 PPC::F28, PPC::F29, PPC::F30, PPC::F31 84 }; 85 static unsigned VRegs[32] = { 86 PPC::V0, PPC::V1, PPC::V2, PPC::V3, 87 PPC::V4, PPC::V5, PPC::V6, PPC::V7, 88 PPC::V8, PPC::V9, PPC::V10, PPC::V11, 89 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 90 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 91 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 92 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 93 PPC::V28, PPC::V29, PPC::V30, PPC::V31 94 }; 95 static unsigned CRBITRegs[32] = { 96 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, 97 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, 98 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 99 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 100 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 101 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, 102 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, 103 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN 104 }; 105 static unsigned CRRegs[8] = { 106 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, 107 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7 108 }; 109 110 struct PPCOperand; 111 112 class PPCAsmParser : public MCTargetAsmParser { 113 MCSubtargetInfo &STI; 114 MCAsmParser &Parser; 115 bool IsPPC64; 116 117 MCAsmParser &getParser() const { return Parser; } 118 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 119 120 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 121 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 122 123 bool isPPC64() const { return IsPPC64; } 124 125 bool MatchRegisterName(const AsmToken &Tok, 126 unsigned &RegNo, int64_t &IntVal); 127 128 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 129 130 const MCExpr *ExtractModifierFromExpr(const MCExpr *E, 131 PPCMCExpr::VariantKind &Variant); 132 bool ParseExpression(const MCExpr *&EVal); 133 134 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 135 136 bool ParseDirectiveWord(unsigned Size, SMLoc L); 137 bool ParseDirectiveTC(unsigned Size, SMLoc L); 138 139 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 140 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 141 MCStreamer &Out, unsigned &ErrorInfo, 142 bool MatchingInlineAsm); 143 144 void ProcessInstruction(MCInst &Inst, 145 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 146 147 /// @name Auto-generated Match Functions 148 /// { 149 150 #define GET_ASSEMBLER_HEADER 151 #include "PPCGenAsmMatcher.inc" 152 153 /// } 154 155 156 public: 157 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 158 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 159 // Check for 64-bit vs. 32-bit pointer mode. 160 Triple TheTriple(STI.getTargetTriple()); 161 IsPPC64 = TheTriple.getArch() == Triple::ppc64; 162 // Initialize the set of available features. 163 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 164 } 165 166 virtual bool ParseInstruction(ParseInstructionInfo &Info, 167 StringRef Name, SMLoc NameLoc, 168 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 169 170 virtual bool ParseDirective(AsmToken DirectiveID); 171 }; 172 173 /// PPCOperand - Instances of this class represent a parsed PowerPC machine 174 /// instruction. 175 struct PPCOperand : public MCParsedAsmOperand { 176 enum KindTy { 177 Token, 178 Immediate, 179 Expression 180 } Kind; 181 182 SMLoc StartLoc, EndLoc; 183 bool IsPPC64; 184 185 struct TokOp { 186 const char *Data; 187 unsigned Length; 188 }; 189 190 struct ImmOp { 191 int64_t Val; 192 }; 193 194 struct ExprOp { 195 const MCExpr *Val; 196 }; 197 198 union { 199 struct TokOp Tok; 200 struct ImmOp Imm; 201 struct ExprOp Expr; 202 }; 203 204 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 205 public: 206 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() { 207 Kind = o.Kind; 208 StartLoc = o.StartLoc; 209 EndLoc = o.EndLoc; 210 IsPPC64 = o.IsPPC64; 211 switch (Kind) { 212 case Token: 213 Tok = o.Tok; 214 break; 215 case Immediate: 216 Imm = o.Imm; 217 break; 218 case Expression: 219 Expr = o.Expr; 220 break; 221 } 222 } 223 224 /// getStartLoc - Get the location of the first token of this operand. 225 SMLoc getStartLoc() const { return StartLoc; } 226 227 /// getEndLoc - Get the location of the last token of this operand. 228 SMLoc getEndLoc() const { return EndLoc; } 229 230 /// isPPC64 - True if this operand is for an instruction in 64-bit mode. 231 bool isPPC64() const { return IsPPC64; } 232 233 int64_t getImm() const { 234 assert(Kind == Immediate && "Invalid access!"); 235 return Imm.Val; 236 } 237 238 const MCExpr *getExpr() const { 239 assert(Kind == Expression && "Invalid access!"); 240 return Expr.Val; 241 } 242 243 unsigned getReg() const { 244 assert(isRegNumber() && "Invalid access!"); 245 return (unsigned) Imm.Val; 246 } 247 248 unsigned getCCReg() const { 249 assert(isCCRegNumber() && "Invalid access!"); 250 return (unsigned) Imm.Val; 251 } 252 253 unsigned getCRBitMask() const { 254 assert(isCRBitMask() && "Invalid access!"); 255 return 7 - countTrailingZeros<uint64_t>(Imm.Val); 256 } 257 258 bool isToken() const { return Kind == Token; } 259 bool isImm() const { return Kind == Immediate || Kind == Expression; } 260 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } 261 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } 262 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } 263 bool isU16Imm() const { return Kind == Expression || 264 (Kind == Immediate && isUInt<16>(getImm())); } 265 bool isS16Imm() const { return Kind == Expression || 266 (Kind == Immediate && isInt<16>(getImm())); } 267 bool isS16ImmX4() const { return Kind == Expression || 268 (Kind == Immediate && isInt<16>(getImm()) && 269 (getImm() & 3) == 0); } 270 bool isDirectBr() const { return Kind == Expression || 271 (Kind == Immediate && isInt<26>(getImm()) && 272 (getImm() & 3) == 0); } 273 bool isCondBr() const { return Kind == Expression || 274 (Kind == Immediate && isInt<16>(getImm()) && 275 (getImm() & 3) == 0); } 276 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } 277 bool isCCRegNumber() const { return Kind == Immediate && 278 isUInt<3>(getImm()); } 279 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) && 280 isPowerOf2_32(getImm()); } 281 bool isMem() const { return false; } 282 bool isReg() const { return false; } 283 284 void addRegOperands(MCInst &Inst, unsigned N) const { 285 llvm_unreachable("addRegOperands"); 286 } 287 288 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { 289 assert(N == 1 && "Invalid number of operands!"); 290 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()])); 291 } 292 293 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { 294 assert(N == 1 && "Invalid number of operands!"); 295 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()])); 296 } 297 298 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { 299 assert(N == 1 && "Invalid number of operands!"); 300 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()])); 301 } 302 303 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { 304 assert(N == 1 && "Invalid number of operands!"); 305 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()])); 306 } 307 308 void addRegGxRCOperands(MCInst &Inst, unsigned N) const { 309 if (isPPC64()) 310 addRegG8RCOperands(Inst, N); 311 else 312 addRegGPRCOperands(Inst, N); 313 } 314 315 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const { 316 if (isPPC64()) 317 addRegG8RCNoX0Operands(Inst, N); 318 else 319 addRegGPRCNoR0Operands(Inst, N); 320 } 321 322 void addRegF4RCOperands(MCInst &Inst, unsigned N) const { 323 assert(N == 1 && "Invalid number of operands!"); 324 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); 325 } 326 327 void addRegF8RCOperands(MCInst &Inst, unsigned N) const { 328 assert(N == 1 && "Invalid number of operands!"); 329 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); 330 } 331 332 void addRegVRRCOperands(MCInst &Inst, unsigned N) const { 333 assert(N == 1 && "Invalid number of operands!"); 334 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()])); 335 } 336 337 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const { 338 assert(N == 1 && "Invalid number of operands!"); 339 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getReg()])); 340 } 341 342 void addRegCRRCOperands(MCInst &Inst, unsigned N) const { 343 assert(N == 1 && "Invalid number of operands!"); 344 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()])); 345 } 346 347 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const { 348 assert(N == 1 && "Invalid number of operands!"); 349 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()])); 350 } 351 352 void addImmOperands(MCInst &Inst, unsigned N) const { 353 assert(N == 1 && "Invalid number of operands!"); 354 if (Kind == Immediate) 355 Inst.addOperand(MCOperand::CreateImm(getImm())); 356 else 357 Inst.addOperand(MCOperand::CreateExpr(getExpr())); 358 } 359 360 void addBranchTargetOperands(MCInst &Inst, unsigned N) const { 361 assert(N == 1 && "Invalid number of operands!"); 362 if (Kind == Immediate) 363 Inst.addOperand(MCOperand::CreateImm(getImm() / 4)); 364 else 365 Inst.addOperand(MCOperand::CreateExpr(getExpr())); 366 } 367 368 StringRef getToken() const { 369 assert(Kind == Token && "Invalid access!"); 370 return StringRef(Tok.Data, Tok.Length); 371 } 372 373 virtual void print(raw_ostream &OS) const; 374 375 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) { 376 PPCOperand *Op = new PPCOperand(Token); 377 Op->Tok.Data = Str.data(); 378 Op->Tok.Length = Str.size(); 379 Op->StartLoc = S; 380 Op->EndLoc = S; 381 Op->IsPPC64 = IsPPC64; 382 return Op; 383 } 384 385 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) { 386 PPCOperand *Op = new PPCOperand(Immediate); 387 Op->Imm.Val = Val; 388 Op->StartLoc = S; 389 Op->EndLoc = E; 390 Op->IsPPC64 = IsPPC64; 391 return Op; 392 } 393 394 static PPCOperand *CreateExpr(const MCExpr *Val, 395 SMLoc S, SMLoc E, bool IsPPC64) { 396 PPCOperand *Op = new PPCOperand(Expression); 397 Op->Expr.Val = Val; 398 Op->StartLoc = S; 399 Op->EndLoc = E; 400 Op->IsPPC64 = IsPPC64; 401 return Op; 402 } 403 }; 404 405 } // end anonymous namespace. 406 407 void PPCOperand::print(raw_ostream &OS) const { 408 switch (Kind) { 409 case Token: 410 OS << "'" << getToken() << "'"; 411 break; 412 case Immediate: 413 OS << getImm(); 414 break; 415 case Expression: 416 getExpr()->print(OS); 417 break; 418 } 419 } 420 421 422 void PPCAsmParser:: 423 ProcessInstruction(MCInst &Inst, 424 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 425 int Opcode = Inst.getOpcode(); 426 switch (Opcode) { 427 case PPC::LAx: { 428 MCInst TmpInst; 429 TmpInst.setOpcode(PPC::LA); 430 TmpInst.addOperand(Inst.getOperand(0)); 431 TmpInst.addOperand(Inst.getOperand(2)); 432 TmpInst.addOperand(Inst.getOperand(1)); 433 Inst = TmpInst; 434 break; 435 } 436 case PPC::SUBI: { 437 MCInst TmpInst; 438 int64_t N = Inst.getOperand(2).getImm(); 439 TmpInst.setOpcode(PPC::ADDI); 440 TmpInst.addOperand(Inst.getOperand(0)); 441 TmpInst.addOperand(Inst.getOperand(1)); 442 TmpInst.addOperand(MCOperand::CreateImm(-N)); 443 Inst = TmpInst; 444 break; 445 } 446 case PPC::SUBIS: { 447 MCInst TmpInst; 448 int64_t N = Inst.getOperand(2).getImm(); 449 TmpInst.setOpcode(PPC::ADDIS); 450 TmpInst.addOperand(Inst.getOperand(0)); 451 TmpInst.addOperand(Inst.getOperand(1)); 452 TmpInst.addOperand(MCOperand::CreateImm(-N)); 453 Inst = TmpInst; 454 break; 455 } 456 case PPC::SUBIC: { 457 MCInst TmpInst; 458 int64_t N = Inst.getOperand(2).getImm(); 459 TmpInst.setOpcode(PPC::ADDIC); 460 TmpInst.addOperand(Inst.getOperand(0)); 461 TmpInst.addOperand(Inst.getOperand(1)); 462 TmpInst.addOperand(MCOperand::CreateImm(-N)); 463 Inst = TmpInst; 464 break; 465 } 466 case PPC::SUBICo: { 467 MCInst TmpInst; 468 int64_t N = Inst.getOperand(2).getImm(); 469 TmpInst.setOpcode(PPC::ADDICo); 470 TmpInst.addOperand(Inst.getOperand(0)); 471 TmpInst.addOperand(Inst.getOperand(1)); 472 TmpInst.addOperand(MCOperand::CreateImm(-N)); 473 Inst = TmpInst; 474 break; 475 } 476 case PPC::EXTLWI: 477 case PPC::EXTLWIo: { 478 MCInst TmpInst; 479 int64_t N = Inst.getOperand(2).getImm(); 480 int64_t B = Inst.getOperand(3).getImm(); 481 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo); 482 TmpInst.addOperand(Inst.getOperand(0)); 483 TmpInst.addOperand(Inst.getOperand(1)); 484 TmpInst.addOperand(MCOperand::CreateImm(B)); 485 TmpInst.addOperand(MCOperand::CreateImm(0)); 486 TmpInst.addOperand(MCOperand::CreateImm(N - 1)); 487 Inst = TmpInst; 488 break; 489 } 490 case PPC::EXTRWI: 491 case PPC::EXTRWIo: { 492 MCInst TmpInst; 493 int64_t N = Inst.getOperand(2).getImm(); 494 int64_t B = Inst.getOperand(3).getImm(); 495 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo); 496 TmpInst.addOperand(Inst.getOperand(0)); 497 TmpInst.addOperand(Inst.getOperand(1)); 498 TmpInst.addOperand(MCOperand::CreateImm(B + N)); 499 TmpInst.addOperand(MCOperand::CreateImm(32 - N)); 500 TmpInst.addOperand(MCOperand::CreateImm(31)); 501 Inst = TmpInst; 502 break; 503 } 504 case PPC::INSLWI: 505 case PPC::INSLWIo: { 506 MCInst TmpInst; 507 int64_t N = Inst.getOperand(2).getImm(); 508 int64_t B = Inst.getOperand(3).getImm(); 509 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo); 510 TmpInst.addOperand(Inst.getOperand(0)); 511 TmpInst.addOperand(Inst.getOperand(0)); 512 TmpInst.addOperand(Inst.getOperand(1)); 513 TmpInst.addOperand(MCOperand::CreateImm(32 - B)); 514 TmpInst.addOperand(MCOperand::CreateImm(B)); 515 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1)); 516 Inst = TmpInst; 517 break; 518 } 519 case PPC::INSRWI: 520 case PPC::INSRWIo: { 521 MCInst TmpInst; 522 int64_t N = Inst.getOperand(2).getImm(); 523 int64_t B = Inst.getOperand(3).getImm(); 524 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo); 525 TmpInst.addOperand(Inst.getOperand(0)); 526 TmpInst.addOperand(Inst.getOperand(0)); 527 TmpInst.addOperand(Inst.getOperand(1)); 528 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N))); 529 TmpInst.addOperand(MCOperand::CreateImm(B)); 530 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1)); 531 Inst = TmpInst; 532 break; 533 } 534 case PPC::ROTRWI: 535 case PPC::ROTRWIo: { 536 MCInst TmpInst; 537 int64_t N = Inst.getOperand(2).getImm(); 538 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo); 539 TmpInst.addOperand(Inst.getOperand(0)); 540 TmpInst.addOperand(Inst.getOperand(1)); 541 TmpInst.addOperand(MCOperand::CreateImm(32 - N)); 542 TmpInst.addOperand(MCOperand::CreateImm(0)); 543 TmpInst.addOperand(MCOperand::CreateImm(31)); 544 Inst = TmpInst; 545 break; 546 } 547 case PPC::SLWI: 548 case PPC::SLWIo: { 549 MCInst TmpInst; 550 int64_t N = Inst.getOperand(2).getImm(); 551 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo); 552 TmpInst.addOperand(Inst.getOperand(0)); 553 TmpInst.addOperand(Inst.getOperand(1)); 554 TmpInst.addOperand(MCOperand::CreateImm(N)); 555 TmpInst.addOperand(MCOperand::CreateImm(0)); 556 TmpInst.addOperand(MCOperand::CreateImm(31 - N)); 557 Inst = TmpInst; 558 break; 559 } 560 case PPC::SRWI: 561 case PPC::SRWIo: { 562 MCInst TmpInst; 563 int64_t N = Inst.getOperand(2).getImm(); 564 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo); 565 TmpInst.addOperand(Inst.getOperand(0)); 566 TmpInst.addOperand(Inst.getOperand(1)); 567 TmpInst.addOperand(MCOperand::CreateImm(32 - N)); 568 TmpInst.addOperand(MCOperand::CreateImm(N)); 569 TmpInst.addOperand(MCOperand::CreateImm(31)); 570 Inst = TmpInst; 571 break; 572 } 573 case PPC::CLRRWI: 574 case PPC::CLRRWIo: { 575 MCInst TmpInst; 576 int64_t N = Inst.getOperand(2).getImm(); 577 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo); 578 TmpInst.addOperand(Inst.getOperand(0)); 579 TmpInst.addOperand(Inst.getOperand(1)); 580 TmpInst.addOperand(MCOperand::CreateImm(0)); 581 TmpInst.addOperand(MCOperand::CreateImm(0)); 582 TmpInst.addOperand(MCOperand::CreateImm(31 - N)); 583 Inst = TmpInst; 584 break; 585 } 586 case PPC::CLRLSLWI: 587 case PPC::CLRLSLWIo: { 588 MCInst TmpInst; 589 int64_t B = Inst.getOperand(2).getImm(); 590 int64_t N = Inst.getOperand(3).getImm(); 591 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo); 592 TmpInst.addOperand(Inst.getOperand(0)); 593 TmpInst.addOperand(Inst.getOperand(1)); 594 TmpInst.addOperand(MCOperand::CreateImm(N)); 595 TmpInst.addOperand(MCOperand::CreateImm(B - N)); 596 TmpInst.addOperand(MCOperand::CreateImm(31 - N)); 597 Inst = TmpInst; 598 break; 599 } 600 case PPC::EXTLDI: 601 case PPC::EXTLDIo: { 602 MCInst TmpInst; 603 int64_t N = Inst.getOperand(2).getImm(); 604 int64_t B = Inst.getOperand(3).getImm(); 605 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo); 606 TmpInst.addOperand(Inst.getOperand(0)); 607 TmpInst.addOperand(Inst.getOperand(1)); 608 TmpInst.addOperand(MCOperand::CreateImm(B)); 609 TmpInst.addOperand(MCOperand::CreateImm(N - 1)); 610 Inst = TmpInst; 611 break; 612 } 613 case PPC::EXTRDI: 614 case PPC::EXTRDIo: { 615 MCInst TmpInst; 616 int64_t N = Inst.getOperand(2).getImm(); 617 int64_t B = Inst.getOperand(3).getImm(); 618 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo); 619 TmpInst.addOperand(Inst.getOperand(0)); 620 TmpInst.addOperand(Inst.getOperand(1)); 621 TmpInst.addOperand(MCOperand::CreateImm(B + N)); 622 TmpInst.addOperand(MCOperand::CreateImm(64 - N)); 623 Inst = TmpInst; 624 break; 625 } 626 case PPC::INSRDI: 627 case PPC::INSRDIo: { 628 MCInst TmpInst; 629 int64_t N = Inst.getOperand(2).getImm(); 630 int64_t B = Inst.getOperand(3).getImm(); 631 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo); 632 TmpInst.addOperand(Inst.getOperand(0)); 633 TmpInst.addOperand(Inst.getOperand(0)); 634 TmpInst.addOperand(Inst.getOperand(1)); 635 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N))); 636 TmpInst.addOperand(MCOperand::CreateImm(B)); 637 Inst = TmpInst; 638 break; 639 } 640 case PPC::ROTRDI: 641 case PPC::ROTRDIo: { 642 MCInst TmpInst; 643 int64_t N = Inst.getOperand(2).getImm(); 644 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo); 645 TmpInst.addOperand(Inst.getOperand(0)); 646 TmpInst.addOperand(Inst.getOperand(1)); 647 TmpInst.addOperand(MCOperand::CreateImm(64 - N)); 648 TmpInst.addOperand(MCOperand::CreateImm(0)); 649 Inst = TmpInst; 650 break; 651 } 652 case PPC::SLDI: 653 case PPC::SLDIo: { 654 MCInst TmpInst; 655 int64_t N = Inst.getOperand(2).getImm(); 656 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo); 657 TmpInst.addOperand(Inst.getOperand(0)); 658 TmpInst.addOperand(Inst.getOperand(1)); 659 TmpInst.addOperand(MCOperand::CreateImm(N)); 660 TmpInst.addOperand(MCOperand::CreateImm(63 - N)); 661 Inst = TmpInst; 662 break; 663 } 664 case PPC::SRDI: 665 case PPC::SRDIo: { 666 MCInst TmpInst; 667 int64_t N = Inst.getOperand(2).getImm(); 668 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo); 669 TmpInst.addOperand(Inst.getOperand(0)); 670 TmpInst.addOperand(Inst.getOperand(1)); 671 TmpInst.addOperand(MCOperand::CreateImm(64 - N)); 672 TmpInst.addOperand(MCOperand::CreateImm(N)); 673 Inst = TmpInst; 674 break; 675 } 676 case PPC::CLRRDI: 677 case PPC::CLRRDIo: { 678 MCInst TmpInst; 679 int64_t N = Inst.getOperand(2).getImm(); 680 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo); 681 TmpInst.addOperand(Inst.getOperand(0)); 682 TmpInst.addOperand(Inst.getOperand(1)); 683 TmpInst.addOperand(MCOperand::CreateImm(0)); 684 TmpInst.addOperand(MCOperand::CreateImm(63 - N)); 685 Inst = TmpInst; 686 break; 687 } 688 case PPC::CLRLSLDI: 689 case PPC::CLRLSLDIo: { 690 MCInst TmpInst; 691 int64_t B = Inst.getOperand(2).getImm(); 692 int64_t N = Inst.getOperand(3).getImm(); 693 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo); 694 TmpInst.addOperand(Inst.getOperand(0)); 695 TmpInst.addOperand(Inst.getOperand(1)); 696 TmpInst.addOperand(MCOperand::CreateImm(N)); 697 TmpInst.addOperand(MCOperand::CreateImm(B - N)); 698 Inst = TmpInst; 699 break; 700 } 701 } 702 } 703 704 bool PPCAsmParser:: 705 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 706 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 707 MCStreamer &Out, unsigned &ErrorInfo, 708 bool MatchingInlineAsm) { 709 MCInst Inst; 710 711 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { 712 default: break; 713 case Match_Success: 714 // Post-process instructions (typically extended mnemonics) 715 ProcessInstruction(Inst, Operands); 716 Inst.setLoc(IDLoc); 717 Out.EmitInstruction(Inst); 718 return false; 719 case Match_MissingFeature: 720 return Error(IDLoc, "instruction use requires an option to be enabled"); 721 case Match_MnemonicFail: 722 return Error(IDLoc, "unrecognized instruction mnemonic"); 723 case Match_InvalidOperand: { 724 SMLoc ErrorLoc = IDLoc; 725 if (ErrorInfo != ~0U) { 726 if (ErrorInfo >= Operands.size()) 727 return Error(IDLoc, "too few operands for instruction"); 728 729 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc(); 730 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 731 } 732 733 return Error(ErrorLoc, "invalid operand for instruction"); 734 } 735 } 736 737 llvm_unreachable("Implement any new match types added!"); 738 } 739 740 bool PPCAsmParser:: 741 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) { 742 if (Tok.is(AsmToken::Identifier)) { 743 StringRef Name = Tok.getString(); 744 745 if (Name.equals_lower("lr")) { 746 RegNo = isPPC64()? PPC::LR8 : PPC::LR; 747 IntVal = 8; 748 return false; 749 } else if (Name.equals_lower("ctr")) { 750 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR; 751 IntVal = 9; 752 return false; 753 } else if (Name.substr(0, 1).equals_lower("r") && 754 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 755 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal]; 756 return false; 757 } else if (Name.substr(0, 1).equals_lower("f") && 758 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 759 RegNo = FRegs[IntVal]; 760 return false; 761 } else if (Name.substr(0, 1).equals_lower("v") && 762 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 763 RegNo = VRegs[IntVal]; 764 return false; 765 } else if (Name.substr(0, 2).equals_lower("cr") && 766 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { 767 RegNo = CRRegs[IntVal]; 768 return false; 769 } 770 } 771 772 return true; 773 } 774 775 bool PPCAsmParser:: 776 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 777 const AsmToken &Tok = Parser.getTok(); 778 StartLoc = Tok.getLoc(); 779 EndLoc = Tok.getEndLoc(); 780 RegNo = 0; 781 int64_t IntVal; 782 783 if (!MatchRegisterName(Tok, RegNo, IntVal)) { 784 Parser.Lex(); // Eat identifier token. 785 return false; 786 } 787 788 return Error(StartLoc, "invalid register name"); 789 } 790 791 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan 792 /// the expression and check for VK_PPC_LO/HI/HA 793 /// symbol variants. If all symbols with modifier use the same 794 /// variant, return the corresponding PPCMCExpr::VariantKind, 795 /// and a modified expression using the default symbol variant. 796 /// Otherwise, return NULL. 797 const MCExpr *PPCAsmParser:: 798 ExtractModifierFromExpr(const MCExpr *E, 799 PPCMCExpr::VariantKind &Variant) { 800 MCContext &Context = getParser().getContext(); 801 Variant = PPCMCExpr::VK_PPC_None; 802 803 switch (E->getKind()) { 804 case MCExpr::Target: 805 case MCExpr::Constant: 806 return 0; 807 808 case MCExpr::SymbolRef: { 809 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 810 811 switch (SRE->getKind()) { 812 case MCSymbolRefExpr::VK_PPC_LO: 813 Variant = PPCMCExpr::VK_PPC_LO; 814 break; 815 case MCSymbolRefExpr::VK_PPC_HI: 816 Variant = PPCMCExpr::VK_PPC_HI; 817 break; 818 case MCSymbolRefExpr::VK_PPC_HA: 819 Variant = PPCMCExpr::VK_PPC_HA; 820 break; 821 case MCSymbolRefExpr::VK_PPC_HIGHER: 822 Variant = PPCMCExpr::VK_PPC_HIGHER; 823 break; 824 case MCSymbolRefExpr::VK_PPC_HIGHERA: 825 Variant = PPCMCExpr::VK_PPC_HIGHERA; 826 break; 827 case MCSymbolRefExpr::VK_PPC_HIGHEST: 828 Variant = PPCMCExpr::VK_PPC_HIGHEST; 829 break; 830 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 831 Variant = PPCMCExpr::VK_PPC_HIGHESTA; 832 break; 833 default: 834 return 0; 835 } 836 837 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context); 838 } 839 840 case MCExpr::Unary: { 841 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 842 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant); 843 if (!Sub) 844 return 0; 845 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context); 846 } 847 848 case MCExpr::Binary: { 849 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 850 PPCMCExpr::VariantKind LHSVariant, RHSVariant; 851 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant); 852 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant); 853 854 if (!LHS && !RHS) 855 return 0; 856 857 if (!LHS) LHS = BE->getLHS(); 858 if (!RHS) RHS = BE->getRHS(); 859 860 if (LHSVariant == PPCMCExpr::VK_PPC_None) 861 Variant = RHSVariant; 862 else if (RHSVariant == PPCMCExpr::VK_PPC_None) 863 Variant = LHSVariant; 864 else if (LHSVariant == RHSVariant) 865 Variant = LHSVariant; 866 else 867 return 0; 868 869 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context); 870 } 871 } 872 873 llvm_unreachable("Invalid expression kind!"); 874 } 875 876 /// Parse an expression. This differs from the default "parseExpression" 877 /// in that it handles complex \code @l/@ha \endcode modifiers. 878 bool PPCAsmParser:: 879 ParseExpression(const MCExpr *&EVal) { 880 if (getParser().parseExpression(EVal)) 881 return true; 882 883 PPCMCExpr::VariantKind Variant; 884 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant); 885 if (E) 886 EVal = PPCMCExpr::Create(Variant, E, getParser().getContext()); 887 888 return false; 889 } 890 891 bool PPCAsmParser:: 892 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 893 SMLoc S = Parser.getTok().getLoc(); 894 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 895 const MCExpr *EVal; 896 PPCOperand *Op; 897 898 // Attempt to parse the next token as an immediate 899 switch (getLexer().getKind()) { 900 // Special handling for register names. These are interpreted 901 // as immediates corresponding to the register number. 902 case AsmToken::Percent: 903 Parser.Lex(); // Eat the '%'. 904 unsigned RegNo; 905 int64_t IntVal; 906 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) { 907 Parser.Lex(); // Eat the identifier token. 908 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64()); 909 Operands.push_back(Op); 910 return false; 911 } 912 return Error(S, "invalid register name"); 913 914 // All other expressions 915 case AsmToken::LParen: 916 case AsmToken::Plus: 917 case AsmToken::Minus: 918 case AsmToken::Integer: 919 case AsmToken::Identifier: 920 case AsmToken::Dot: 921 case AsmToken::Dollar: 922 if (!ParseExpression(EVal)) 923 break; 924 /* fall through */ 925 default: 926 return Error(S, "unknown operand"); 927 } 928 929 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(EVal)) 930 Op = PPCOperand::CreateImm(CE->getValue(), S, E, isPPC64()); 931 else 932 Op = PPCOperand::CreateExpr(EVal, S, E, isPPC64()); 933 934 // Push the parsed operand into the list of operands 935 Operands.push_back(Op); 936 937 // Check for D-form memory operands 938 if (getLexer().is(AsmToken::LParen)) { 939 Parser.Lex(); // Eat the '('. 940 S = Parser.getTok().getLoc(); 941 942 int64_t IntVal; 943 switch (getLexer().getKind()) { 944 case AsmToken::Percent: 945 Parser.Lex(); // Eat the '%'. 946 unsigned RegNo; 947 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal)) 948 return Error(S, "invalid register name"); 949 Parser.Lex(); // Eat the identifier token. 950 break; 951 952 case AsmToken::Integer: 953 if (getParser().parseAbsoluteExpression(IntVal) || 954 IntVal < 0 || IntVal > 31) 955 return Error(S, "invalid register number"); 956 break; 957 958 default: 959 return Error(S, "invalid memory operand"); 960 } 961 962 if (getLexer().isNot(AsmToken::RParen)) 963 return Error(Parser.getTok().getLoc(), "missing ')'"); 964 E = Parser.getTok().getLoc(); 965 Parser.Lex(); // Eat the ')'. 966 967 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64()); 968 Operands.push_back(Op); 969 } 970 971 return false; 972 } 973 974 /// Parse an instruction mnemonic followed by its operands. 975 bool PPCAsmParser:: 976 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, 977 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 978 // The first operand is the token for the instruction name. 979 // If the next character is a '+' or '-', we need to add it to the 980 // instruction name, to match what TableGen is doing. 981 if (getLexer().is(AsmToken::Plus)) { 982 getLexer().Lex(); 983 char *NewOpcode = new char[Name.size() + 1]; 984 memcpy(NewOpcode, Name.data(), Name.size()); 985 NewOpcode[Name.size()] = '+'; 986 Name = StringRef(NewOpcode, Name.size() + 1); 987 } 988 if (getLexer().is(AsmToken::Minus)) { 989 getLexer().Lex(); 990 char *NewOpcode = new char[Name.size() + 1]; 991 memcpy(NewOpcode, Name.data(), Name.size()); 992 NewOpcode[Name.size()] = '-'; 993 Name = StringRef(NewOpcode, Name.size() + 1); 994 } 995 // If the instruction ends in a '.', we need to create a separate 996 // token for it, to match what TableGen is doing. 997 size_t Dot = Name.find('.'); 998 StringRef Mnemonic = Name.slice(0, Dot); 999 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64())); 1000 if (Dot != StringRef::npos) { 1001 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot); 1002 StringRef DotStr = Name.slice(Dot, StringRef::npos); 1003 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64())); 1004 } 1005 1006 // If there are no more operands then finish 1007 if (getLexer().is(AsmToken::EndOfStatement)) 1008 return false; 1009 1010 // Parse the first operand 1011 if (ParseOperand(Operands)) 1012 return true; 1013 1014 while (getLexer().isNot(AsmToken::EndOfStatement) && 1015 getLexer().is(AsmToken::Comma)) { 1016 // Consume the comma token 1017 getLexer().Lex(); 1018 1019 // Parse the next operand 1020 if (ParseOperand(Operands)) 1021 return true; 1022 } 1023 1024 return false; 1025 } 1026 1027 /// ParseDirective parses the PPC specific directives 1028 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) { 1029 StringRef IDVal = DirectiveID.getIdentifier(); 1030 if (IDVal == ".word") 1031 return ParseDirectiveWord(4, DirectiveID.getLoc()); 1032 if (IDVal == ".tc") 1033 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc()); 1034 return true; 1035 } 1036 1037 /// ParseDirectiveWord 1038 /// ::= .word [ expression (, expression)* ] 1039 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) { 1040 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1041 for (;;) { 1042 const MCExpr *Value; 1043 if (getParser().parseExpression(Value)) 1044 return true; 1045 1046 getParser().getStreamer().EmitValue(Value, Size); 1047 1048 if (getLexer().is(AsmToken::EndOfStatement)) 1049 break; 1050 1051 if (getLexer().isNot(AsmToken::Comma)) 1052 return Error(L, "unexpected token in directive"); 1053 Parser.Lex(); 1054 } 1055 } 1056 1057 Parser.Lex(); 1058 return false; 1059 } 1060 1061 /// ParseDirectiveTC 1062 /// ::= .tc [ symbol (, expression)* ] 1063 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) { 1064 // Skip TC symbol, which is only used with XCOFF. 1065 while (getLexer().isNot(AsmToken::EndOfStatement) 1066 && getLexer().isNot(AsmToken::Comma)) 1067 Parser.Lex(); 1068 if (getLexer().isNot(AsmToken::Comma)) 1069 return Error(L, "unexpected token in directive"); 1070 Parser.Lex(); 1071 1072 // Align to word size. 1073 getParser().getStreamer().EmitValueToAlignment(Size); 1074 1075 // Emit expressions. 1076 return ParseDirectiveWord(Size, L); 1077 } 1078 1079 /// Force static initialization. 1080 extern "C" void LLVMInitializePowerPCAsmParser() { 1081 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target); 1082 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target); 1083 } 1084 1085 #define GET_REGISTER_MATCHER 1086 #define GET_MATCHER_IMPLEMENTATION 1087 #include "PPCGenAsmMatcher.inc" 1088