1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCExpr.h" 10 #include "MCTargetDesc/PPCMCTargetDesc.h" 11 #include "PPCTargetStreamer.h" 12 #include "TargetInfo/PowerPCTargetInfo.h" 13 #include "llvm/ADT/STLExtras.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Twine.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCParser/MCAsmLexer.h" 21 #include "llvm/MC/MCParser/MCAsmParser.h" 22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 23 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 24 #include "llvm/MC/MCStreamer.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/MC/MCSymbolELF.h" 27 #include "llvm/Support/SourceMgr.h" 28 #include "llvm/Support/TargetRegistry.h" 29 #include "llvm/Support/raw_ostream.h" 30 31 using namespace llvm; 32 33 DEFINE_PPC_REGCLASSES; 34 35 // Evaluate an expression containing condition register 36 // or condition register field symbols. Returns positive 37 // value on success, or -1 on error. 38 static int64_t 39 EvaluateCRExpr(const MCExpr *E) { 40 switch (E->getKind()) { 41 case MCExpr::Target: 42 return -1; 43 44 case MCExpr::Constant: { 45 int64_t Res = cast<MCConstantExpr>(E)->getValue(); 46 return Res < 0 ? -1 : Res; 47 } 48 49 case MCExpr::SymbolRef: { 50 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 51 StringRef Name = SRE->getSymbol().getName(); 52 53 if (Name == "lt") return 0; 54 if (Name == "gt") return 1; 55 if (Name == "eq") return 2; 56 if (Name == "so") return 3; 57 if (Name == "un") return 3; 58 59 if (Name == "cr0") return 0; 60 if (Name == "cr1") return 1; 61 if (Name == "cr2") return 2; 62 if (Name == "cr3") return 3; 63 if (Name == "cr4") return 4; 64 if (Name == "cr5") return 5; 65 if (Name == "cr6") return 6; 66 if (Name == "cr7") return 7; 67 68 return -1; 69 } 70 71 case MCExpr::Unary: 72 return -1; 73 74 case MCExpr::Binary: { 75 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 76 int64_t LHSVal = EvaluateCRExpr(BE->getLHS()); 77 int64_t RHSVal = EvaluateCRExpr(BE->getRHS()); 78 int64_t Res; 79 80 if (LHSVal < 0 || RHSVal < 0) 81 return -1; 82 83 switch (BE->getOpcode()) { 84 default: return -1; 85 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break; 86 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break; 87 } 88 89 return Res < 0 ? -1 : Res; 90 } 91 } 92 93 llvm_unreachable("Invalid expression kind!"); 94 } 95 96 namespace { 97 98 struct PPCOperand; 99 100 class PPCAsmParser : public MCTargetAsmParser { 101 bool IsPPC64; 102 bool IsDarwin; 103 104 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); } 105 106 bool isPPC64() const { return IsPPC64; } 107 bool isDarwin() const { return IsDarwin; } 108 109 bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal); 110 111 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 112 OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, 113 SMLoc &EndLoc) override; 114 115 const MCExpr *ExtractModifierFromExpr(const MCExpr *E, 116 PPCMCExpr::VariantKind &Variant); 117 const MCExpr *FixupVariantKind(const MCExpr *E); 118 bool ParseExpression(const MCExpr *&EVal); 119 bool ParseDarwinExpression(const MCExpr *&EVal); 120 121 bool ParseOperand(OperandVector &Operands); 122 123 bool ParseDirectiveWord(unsigned Size, AsmToken ID); 124 bool ParseDirectiveTC(unsigned Size, AsmToken ID); 125 bool ParseDirectiveMachine(SMLoc L); 126 bool ParseDarwinDirectiveMachine(SMLoc L); 127 bool ParseDirectiveAbiVersion(SMLoc L); 128 bool ParseDirectiveLocalEntry(SMLoc L); 129 130 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 131 OperandVector &Operands, MCStreamer &Out, 132 uint64_t &ErrorInfo, 133 bool MatchingInlineAsm) override; 134 135 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops); 136 137 /// @name Auto-generated Match Functions 138 /// { 139 140 #define GET_ASSEMBLER_HEADER 141 #include "PPCGenAsmMatcher.inc" 142 143 /// } 144 145 146 public: 147 PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &, 148 const MCInstrInfo &MII, const MCTargetOptions &Options) 149 : MCTargetAsmParser(Options, STI, MII) { 150 // Check for 64-bit vs. 32-bit pointer mode. 151 const Triple &TheTriple = STI.getTargetTriple(); 152 IsPPC64 = TheTriple.isPPC64(); 153 IsDarwin = TheTriple.isMacOSX(); 154 // Initialize the set of available features. 155 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 156 } 157 158 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 159 SMLoc NameLoc, OperandVector &Operands) override; 160 161 bool ParseDirective(AsmToken DirectiveID) override; 162 163 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 164 unsigned Kind) override; 165 166 const MCExpr *applyModifierToExpr(const MCExpr *E, 167 MCSymbolRefExpr::VariantKind, 168 MCContext &Ctx) override; 169 }; 170 171 /// PPCOperand - Instances of this class represent a parsed PowerPC machine 172 /// instruction. 173 struct PPCOperand : public MCParsedAsmOperand { 174 enum KindTy { 175 Token, 176 Immediate, 177 ContextImmediate, 178 Expression, 179 TLSRegister 180 } Kind; 181 182 SMLoc StartLoc, EndLoc; 183 bool IsPPC64; 184 185 struct TokOp { 186 const char *Data; 187 unsigned Length; 188 }; 189 190 struct ImmOp { 191 int64_t Val; 192 }; 193 194 struct ExprOp { 195 const MCExpr *Val; 196 int64_t CRVal; // Cached result of EvaluateCRExpr(Val) 197 }; 198 199 struct TLSRegOp { 200 const MCSymbolRefExpr *Sym; 201 }; 202 203 union { 204 struct TokOp Tok; 205 struct ImmOp Imm; 206 struct ExprOp Expr; 207 struct TLSRegOp TLSReg; 208 }; 209 210 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 211 public: 212 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() { 213 Kind = o.Kind; 214 StartLoc = o.StartLoc; 215 EndLoc = o.EndLoc; 216 IsPPC64 = o.IsPPC64; 217 switch (Kind) { 218 case Token: 219 Tok = o.Tok; 220 break; 221 case Immediate: 222 case ContextImmediate: 223 Imm = o.Imm; 224 break; 225 case Expression: 226 Expr = o.Expr; 227 break; 228 case TLSRegister: 229 TLSReg = o.TLSReg; 230 break; 231 } 232 } 233 234 // Disable use of sized deallocation due to overallocation of PPCOperand 235 // objects in CreateTokenWithStringCopy. 236 void operator delete(void *p) { ::operator delete(p); } 237 238 /// getStartLoc - Get the location of the first token of this operand. 239 SMLoc getStartLoc() const override { return StartLoc; } 240 241 /// getEndLoc - Get the location of the last token of this operand. 242 SMLoc getEndLoc() const override { return EndLoc; } 243 244 /// getLocRange - Get the range between the first and last token of this 245 /// operand. 246 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 247 248 /// isPPC64 - True if this operand is for an instruction in 64-bit mode. 249 bool isPPC64() const { return IsPPC64; } 250 251 int64_t getImm() const { 252 assert(Kind == Immediate && "Invalid access!"); 253 return Imm.Val; 254 } 255 int64_t getImmS16Context() const { 256 assert((Kind == Immediate || Kind == ContextImmediate) && 257 "Invalid access!"); 258 if (Kind == Immediate) 259 return Imm.Val; 260 return static_cast<int16_t>(Imm.Val); 261 } 262 int64_t getImmU16Context() const { 263 assert((Kind == Immediate || Kind == ContextImmediate) && 264 "Invalid access!"); 265 return Imm.Val; 266 } 267 268 const MCExpr *getExpr() const { 269 assert(Kind == Expression && "Invalid access!"); 270 return Expr.Val; 271 } 272 273 int64_t getExprCRVal() const { 274 assert(Kind == Expression && "Invalid access!"); 275 return Expr.CRVal; 276 } 277 278 const MCExpr *getTLSReg() const { 279 assert(Kind == TLSRegister && "Invalid access!"); 280 return TLSReg.Sym; 281 } 282 283 unsigned getReg() const override { 284 assert(isRegNumber() && "Invalid access!"); 285 return (unsigned) Imm.Val; 286 } 287 288 unsigned getVSReg() const { 289 assert(isVSRegNumber() && "Invalid access!"); 290 return (unsigned) Imm.Val; 291 } 292 293 unsigned getACCReg() const { 294 assert(isACCRegNumber() && "Invalid access!"); 295 return (unsigned) Imm.Val; 296 } 297 298 unsigned getVSRpEvenReg() const { 299 assert(isVSRpEvenRegNumber() && "Invalid access!"); 300 return (unsigned) Imm.Val >> 1; 301 } 302 303 unsigned getCCReg() const { 304 assert(isCCRegNumber() && "Invalid access!"); 305 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 306 } 307 308 unsigned getCRBit() const { 309 assert(isCRBitNumber() && "Invalid access!"); 310 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 311 } 312 313 unsigned getCRBitMask() const { 314 assert(isCRBitMask() && "Invalid access!"); 315 return 7 - countTrailingZeros<uint64_t>(Imm.Val); 316 } 317 318 bool isToken() const override { return Kind == Token; } 319 bool isImm() const override { 320 return Kind == Immediate || Kind == Expression; 321 } 322 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } 323 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } 324 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } 325 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } 326 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } 327 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } 328 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } 329 bool isU6ImmX2() const { return Kind == Immediate && 330 isUInt<6>(getImm()) && 331 (getImm() & 1) == 0; } 332 bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); } 333 bool isU7ImmX4() const { return Kind == Immediate && 334 isUInt<7>(getImm()) && 335 (getImm() & 3) == 0; } 336 bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); } 337 bool isU8ImmX8() const { return Kind == Immediate && 338 isUInt<8>(getImm()) && 339 (getImm() & 7) == 0; } 340 341 bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); } 342 bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); } 343 bool isU16Imm() const { 344 switch (Kind) { 345 case Expression: 346 return true; 347 case Immediate: 348 case ContextImmediate: 349 return isUInt<16>(getImmU16Context()); 350 default: 351 return false; 352 } 353 } 354 bool isS16Imm() const { 355 switch (Kind) { 356 case Expression: 357 return true; 358 case Immediate: 359 case ContextImmediate: 360 return isInt<16>(getImmS16Context()); 361 default: 362 return false; 363 } 364 } 365 bool isS16ImmX4() const { return Kind == Expression || 366 (Kind == Immediate && isInt<16>(getImm()) && 367 (getImm() & 3) == 0); } 368 bool isS16ImmX16() const { return Kind == Expression || 369 (Kind == Immediate && isInt<16>(getImm()) && 370 (getImm() & 15) == 0); } 371 bool isS34ImmX16() const { 372 return Kind == Expression || 373 (Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0); 374 } 375 bool isS34Imm() const { 376 // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit 377 // ContextImmediate is needed. 378 return Kind == Expression || (Kind == Immediate && isInt<34>(getImm())); 379 } 380 381 bool isS17Imm() const { 382 switch (Kind) { 383 case Expression: 384 return true; 385 case Immediate: 386 case ContextImmediate: 387 return isInt<17>(getImmS16Context()); 388 default: 389 return false; 390 } 391 } 392 bool isTLSReg() const { return Kind == TLSRegister; } 393 bool isDirectBr() const { 394 if (Kind == Expression) 395 return true; 396 if (Kind != Immediate) 397 return false; 398 // Operand must be 64-bit aligned, signed 27-bit immediate. 399 if ((getImm() & 3) != 0) 400 return false; 401 if (isInt<26>(getImm())) 402 return true; 403 if (!IsPPC64) { 404 // In 32-bit mode, large 32-bit quantities wrap around. 405 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm()))) 406 return true; 407 } 408 return false; 409 } 410 bool isCondBr() const { return Kind == Expression || 411 (Kind == Immediate && isInt<16>(getImm()) && 412 (getImm() & 3) == 0); } 413 bool isImmZero() const { return Kind == Immediate && getImm() == 0; } 414 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } 415 bool isACCRegNumber() const { 416 return Kind == Immediate && isUInt<3>(getImm()); 417 } 418 bool isVSRpEvenRegNumber() const { 419 return Kind == Immediate && isUInt<6>(getImm()) && ((getImm() & 1) == 0); 420 } 421 bool isVSRegNumber() const { 422 return Kind == Immediate && isUInt<6>(getImm()); 423 } 424 bool isCCRegNumber() const { return (Kind == Expression 425 && isUInt<3>(getExprCRVal())) || 426 (Kind == Immediate 427 && isUInt<3>(getImm())); } 428 bool isCRBitNumber() const { return (Kind == Expression 429 && isUInt<5>(getExprCRVal())) || 430 (Kind == Immediate 431 && isUInt<5>(getImm())); } 432 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) && 433 isPowerOf2_32(getImm()); } 434 bool isATBitsAsHint() const { return false; } 435 bool isMem() const override { return false; } 436 bool isReg() const override { return false; } 437 438 void addRegOperands(MCInst &Inst, unsigned N) const { 439 llvm_unreachable("addRegOperands"); 440 } 441 442 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { 443 assert(N == 1 && "Invalid number of operands!"); 444 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 445 } 446 447 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { 448 assert(N == 1 && "Invalid number of operands!"); 449 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); 450 } 451 452 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { 453 assert(N == 1 && "Invalid number of operands!"); 454 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); 455 } 456 457 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { 458 assert(N == 1 && "Invalid number of operands!"); 459 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); 460 } 461 462 void addRegGxRCOperands(MCInst &Inst, unsigned N) const { 463 if (isPPC64()) 464 addRegG8RCOperands(Inst, N); 465 else 466 addRegGPRCOperands(Inst, N); 467 } 468 469 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const { 470 if (isPPC64()) 471 addRegG8RCNoX0Operands(Inst, N); 472 else 473 addRegGPRCNoR0Operands(Inst, N); 474 } 475 476 void addRegF4RCOperands(MCInst &Inst, unsigned N) const { 477 assert(N == 1 && "Invalid number of operands!"); 478 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 479 } 480 481 void addRegF8RCOperands(MCInst &Inst, unsigned N) const { 482 assert(N == 1 && "Invalid number of operands!"); 483 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 484 } 485 486 void addRegVFRCOperands(MCInst &Inst, unsigned N) const { 487 assert(N == 1 && "Invalid number of operands!"); 488 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); 489 } 490 491 void addRegVRRCOperands(MCInst &Inst, unsigned N) const { 492 assert(N == 1 && "Invalid number of operands!"); 493 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); 494 } 495 496 void addRegVSRCOperands(MCInst &Inst, unsigned N) const { 497 assert(N == 1 && "Invalid number of operands!"); 498 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); 499 } 500 501 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const { 502 assert(N == 1 && "Invalid number of operands!"); 503 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); 504 } 505 506 void addRegVSSRCOperands(MCInst &Inst, unsigned N) const { 507 assert(N == 1 && "Invalid number of operands!"); 508 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); 509 } 510 511 void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const { 512 assert(N == 1 && "Invalid number of operands!"); 513 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 514 } 515 516 void addRegSPERCOperands(MCInst &Inst, unsigned N) const { 517 assert(N == 1 && "Invalid number of operands!"); 518 Inst.addOperand(MCOperand::createReg(SPERegs[getReg()])); 519 } 520 521 void addRegACCRCOperands(MCInst &Inst, unsigned N) const { 522 assert(N == 1 && "Invalid number of operands!"); 523 Inst.addOperand(MCOperand::createReg(ACCRegs[getACCReg()])); 524 } 525 526 void addRegVSRpRCOperands(MCInst &Inst, unsigned N) const { 527 assert(N == 1 && "Invalid number of operands!"); 528 Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()])); 529 } 530 531 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const { 532 assert(N == 1 && "Invalid number of operands!"); 533 Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()])); 534 } 535 536 void addRegCRRCOperands(MCInst &Inst, unsigned N) const { 537 assert(N == 1 && "Invalid number of operands!"); 538 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()])); 539 } 540 541 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const { 542 assert(N == 1 && "Invalid number of operands!"); 543 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()])); 544 } 545 546 void addImmOperands(MCInst &Inst, unsigned N) const { 547 assert(N == 1 && "Invalid number of operands!"); 548 if (Kind == Immediate) 549 Inst.addOperand(MCOperand::createImm(getImm())); 550 else 551 Inst.addOperand(MCOperand::createExpr(getExpr())); 552 } 553 554 void addS16ImmOperands(MCInst &Inst, unsigned N) const { 555 assert(N == 1 && "Invalid number of operands!"); 556 switch (Kind) { 557 case Immediate: 558 Inst.addOperand(MCOperand::createImm(getImm())); 559 break; 560 case ContextImmediate: 561 Inst.addOperand(MCOperand::createImm(getImmS16Context())); 562 break; 563 default: 564 Inst.addOperand(MCOperand::createExpr(getExpr())); 565 break; 566 } 567 } 568 569 void addU16ImmOperands(MCInst &Inst, unsigned N) const { 570 assert(N == 1 && "Invalid number of operands!"); 571 switch (Kind) { 572 case Immediate: 573 Inst.addOperand(MCOperand::createImm(getImm())); 574 break; 575 case ContextImmediate: 576 Inst.addOperand(MCOperand::createImm(getImmU16Context())); 577 break; 578 default: 579 Inst.addOperand(MCOperand::createExpr(getExpr())); 580 break; 581 } 582 } 583 584 void addBranchTargetOperands(MCInst &Inst, unsigned N) const { 585 assert(N == 1 && "Invalid number of operands!"); 586 if (Kind == Immediate) 587 Inst.addOperand(MCOperand::createImm(getImm() / 4)); 588 else 589 Inst.addOperand(MCOperand::createExpr(getExpr())); 590 } 591 592 void addTLSRegOperands(MCInst &Inst, unsigned N) const { 593 assert(N == 1 && "Invalid number of operands!"); 594 Inst.addOperand(MCOperand::createExpr(getTLSReg())); 595 } 596 597 StringRef getToken() const { 598 assert(Kind == Token && "Invalid access!"); 599 return StringRef(Tok.Data, Tok.Length); 600 } 601 602 void print(raw_ostream &OS) const override; 603 604 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S, 605 bool IsPPC64) { 606 auto Op = std::make_unique<PPCOperand>(Token); 607 Op->Tok.Data = Str.data(); 608 Op->Tok.Length = Str.size(); 609 Op->StartLoc = S; 610 Op->EndLoc = S; 611 Op->IsPPC64 = IsPPC64; 612 return Op; 613 } 614 615 static std::unique_ptr<PPCOperand> 616 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) { 617 // Allocate extra memory for the string and copy it. 618 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default 619 // deleter which will destroy them by simply using "delete", not correctly 620 // calling operator delete on this extra memory after calling the dtor 621 // explicitly. 622 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size()); 623 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token)); 624 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1); 625 Op->Tok.Length = Str.size(); 626 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size()); 627 Op->StartLoc = S; 628 Op->EndLoc = S; 629 Op->IsPPC64 = IsPPC64; 630 return Op; 631 } 632 633 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E, 634 bool IsPPC64) { 635 auto Op = std::make_unique<PPCOperand>(Immediate); 636 Op->Imm.Val = Val; 637 Op->StartLoc = S; 638 Op->EndLoc = E; 639 Op->IsPPC64 = IsPPC64; 640 return Op; 641 } 642 643 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S, 644 SMLoc E, bool IsPPC64) { 645 auto Op = std::make_unique<PPCOperand>(Expression); 646 Op->Expr.Val = Val; 647 Op->Expr.CRVal = EvaluateCRExpr(Val); 648 Op->StartLoc = S; 649 Op->EndLoc = E; 650 Op->IsPPC64 = IsPPC64; 651 return Op; 652 } 653 654 static std::unique_ptr<PPCOperand> 655 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) { 656 auto Op = std::make_unique<PPCOperand>(TLSRegister); 657 Op->TLSReg.Sym = Sym; 658 Op->StartLoc = S; 659 Op->EndLoc = E; 660 Op->IsPPC64 = IsPPC64; 661 return Op; 662 } 663 664 static std::unique_ptr<PPCOperand> 665 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) { 666 auto Op = std::make_unique<PPCOperand>(ContextImmediate); 667 Op->Imm.Val = Val; 668 Op->StartLoc = S; 669 Op->EndLoc = E; 670 Op->IsPPC64 = IsPPC64; 671 return Op; 672 } 673 674 static std::unique_ptr<PPCOperand> 675 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) { 676 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val)) 677 return CreateImm(CE->getValue(), S, E, IsPPC64); 678 679 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val)) 680 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS || 681 SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL) 682 return CreateTLSReg(SRE, S, E, IsPPC64); 683 684 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) { 685 int64_t Res; 686 if (TE->evaluateAsConstant(Res)) 687 return CreateContextImm(Res, S, E, IsPPC64); 688 } 689 690 return CreateExpr(Val, S, E, IsPPC64); 691 } 692 }; 693 694 } // end anonymous namespace. 695 696 void PPCOperand::print(raw_ostream &OS) const { 697 switch (Kind) { 698 case Token: 699 OS << "'" << getToken() << "'"; 700 break; 701 case Immediate: 702 case ContextImmediate: 703 OS << getImm(); 704 break; 705 case Expression: 706 OS << *getExpr(); 707 break; 708 case TLSRegister: 709 OS << *getTLSReg(); 710 break; 711 } 712 } 713 714 static void 715 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) { 716 if (Op.isImm()) { 717 Inst.addOperand(MCOperand::createImm(-Op.getImm())); 718 return; 719 } 720 const MCExpr *Expr = Op.getExpr(); 721 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) { 722 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) { 723 Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr())); 724 return; 725 } 726 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) { 727 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) { 728 const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(), 729 BinExpr->getLHS(), Ctx); 730 Inst.addOperand(MCOperand::createExpr(NE)); 731 return; 732 } 733 } 734 Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx))); 735 } 736 737 void PPCAsmParser::ProcessInstruction(MCInst &Inst, 738 const OperandVector &Operands) { 739 int Opcode = Inst.getOpcode(); 740 switch (Opcode) { 741 case PPC::DCBTx: 742 case PPC::DCBTT: 743 case PPC::DCBTSTx: 744 case PPC::DCBTSTT: { 745 MCInst TmpInst; 746 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? 747 PPC::DCBT : PPC::DCBTST); 748 TmpInst.addOperand(MCOperand::createImm( 749 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16)); 750 TmpInst.addOperand(Inst.getOperand(0)); 751 TmpInst.addOperand(Inst.getOperand(1)); 752 Inst = TmpInst; 753 break; 754 } 755 case PPC::DCBTCT: 756 case PPC::DCBTDS: { 757 MCInst TmpInst; 758 TmpInst.setOpcode(PPC::DCBT); 759 TmpInst.addOperand(Inst.getOperand(2)); 760 TmpInst.addOperand(Inst.getOperand(0)); 761 TmpInst.addOperand(Inst.getOperand(1)); 762 Inst = TmpInst; 763 break; 764 } 765 case PPC::DCBTSTCT: 766 case PPC::DCBTSTDS: { 767 MCInst TmpInst; 768 TmpInst.setOpcode(PPC::DCBTST); 769 TmpInst.addOperand(Inst.getOperand(2)); 770 TmpInst.addOperand(Inst.getOperand(0)); 771 TmpInst.addOperand(Inst.getOperand(1)); 772 Inst = TmpInst; 773 break; 774 } 775 case PPC::DCBFx: 776 case PPC::DCBFL: 777 case PPC::DCBFLP: { 778 int L = 0; 779 if (Opcode == PPC::DCBFL) 780 L = 1; 781 else if (Opcode == PPC::DCBFLP) 782 L = 3; 783 784 MCInst TmpInst; 785 TmpInst.setOpcode(PPC::DCBF); 786 TmpInst.addOperand(MCOperand::createImm(L)); 787 TmpInst.addOperand(Inst.getOperand(0)); 788 TmpInst.addOperand(Inst.getOperand(1)); 789 Inst = TmpInst; 790 break; 791 } 792 case PPC::LAx: { 793 MCInst TmpInst; 794 TmpInst.setOpcode(PPC::LA); 795 TmpInst.addOperand(Inst.getOperand(0)); 796 TmpInst.addOperand(Inst.getOperand(2)); 797 TmpInst.addOperand(Inst.getOperand(1)); 798 Inst = TmpInst; 799 break; 800 } 801 case PPC::SUBI: { 802 MCInst TmpInst; 803 TmpInst.setOpcode(PPC::ADDI); 804 TmpInst.addOperand(Inst.getOperand(0)); 805 TmpInst.addOperand(Inst.getOperand(1)); 806 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 807 Inst = TmpInst; 808 break; 809 } 810 case PPC::SUBIS: { 811 MCInst TmpInst; 812 TmpInst.setOpcode(PPC::ADDIS); 813 TmpInst.addOperand(Inst.getOperand(0)); 814 TmpInst.addOperand(Inst.getOperand(1)); 815 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 816 Inst = TmpInst; 817 break; 818 } 819 case PPC::SUBIC: { 820 MCInst TmpInst; 821 TmpInst.setOpcode(PPC::ADDIC); 822 TmpInst.addOperand(Inst.getOperand(0)); 823 TmpInst.addOperand(Inst.getOperand(1)); 824 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 825 Inst = TmpInst; 826 break; 827 } 828 case PPC::SUBIC_rec: { 829 MCInst TmpInst; 830 TmpInst.setOpcode(PPC::ADDIC_rec); 831 TmpInst.addOperand(Inst.getOperand(0)); 832 TmpInst.addOperand(Inst.getOperand(1)); 833 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 834 Inst = TmpInst; 835 break; 836 } 837 case PPC::EXTLWI: 838 case PPC::EXTLWI_rec: { 839 MCInst TmpInst; 840 int64_t N = Inst.getOperand(2).getImm(); 841 int64_t B = Inst.getOperand(3).getImm(); 842 TmpInst.setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec); 843 TmpInst.addOperand(Inst.getOperand(0)); 844 TmpInst.addOperand(Inst.getOperand(1)); 845 TmpInst.addOperand(MCOperand::createImm(B)); 846 TmpInst.addOperand(MCOperand::createImm(0)); 847 TmpInst.addOperand(MCOperand::createImm(N - 1)); 848 Inst = TmpInst; 849 break; 850 } 851 case PPC::EXTRWI: 852 case PPC::EXTRWI_rec: { 853 MCInst TmpInst; 854 int64_t N = Inst.getOperand(2).getImm(); 855 int64_t B = Inst.getOperand(3).getImm(); 856 TmpInst.setOpcode(Opcode == PPC::EXTRWI ? PPC::RLWINM : PPC::RLWINM_rec); 857 TmpInst.addOperand(Inst.getOperand(0)); 858 TmpInst.addOperand(Inst.getOperand(1)); 859 TmpInst.addOperand(MCOperand::createImm(B + N)); 860 TmpInst.addOperand(MCOperand::createImm(32 - N)); 861 TmpInst.addOperand(MCOperand::createImm(31)); 862 Inst = TmpInst; 863 break; 864 } 865 case PPC::INSLWI: 866 case PPC::INSLWI_rec: { 867 MCInst TmpInst; 868 int64_t N = Inst.getOperand(2).getImm(); 869 int64_t B = Inst.getOperand(3).getImm(); 870 TmpInst.setOpcode(Opcode == PPC::INSLWI ? PPC::RLWIMI : PPC::RLWIMI_rec); 871 TmpInst.addOperand(Inst.getOperand(0)); 872 TmpInst.addOperand(Inst.getOperand(0)); 873 TmpInst.addOperand(Inst.getOperand(1)); 874 TmpInst.addOperand(MCOperand::createImm(32 - B)); 875 TmpInst.addOperand(MCOperand::createImm(B)); 876 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 877 Inst = TmpInst; 878 break; 879 } 880 case PPC::INSRWI: 881 case PPC::INSRWI_rec: { 882 MCInst TmpInst; 883 int64_t N = Inst.getOperand(2).getImm(); 884 int64_t B = Inst.getOperand(3).getImm(); 885 TmpInst.setOpcode(Opcode == PPC::INSRWI ? PPC::RLWIMI : PPC::RLWIMI_rec); 886 TmpInst.addOperand(Inst.getOperand(0)); 887 TmpInst.addOperand(Inst.getOperand(0)); 888 TmpInst.addOperand(Inst.getOperand(1)); 889 TmpInst.addOperand(MCOperand::createImm(32 - (B + N))); 890 TmpInst.addOperand(MCOperand::createImm(B)); 891 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 892 Inst = TmpInst; 893 break; 894 } 895 case PPC::ROTRWI: 896 case PPC::ROTRWI_rec: { 897 MCInst TmpInst; 898 int64_t N = Inst.getOperand(2).getImm(); 899 TmpInst.setOpcode(Opcode == PPC::ROTRWI ? PPC::RLWINM : PPC::RLWINM_rec); 900 TmpInst.addOperand(Inst.getOperand(0)); 901 TmpInst.addOperand(Inst.getOperand(1)); 902 TmpInst.addOperand(MCOperand::createImm(32 - N)); 903 TmpInst.addOperand(MCOperand::createImm(0)); 904 TmpInst.addOperand(MCOperand::createImm(31)); 905 Inst = TmpInst; 906 break; 907 } 908 case PPC::SLWI: 909 case PPC::SLWI_rec: { 910 MCInst TmpInst; 911 int64_t N = Inst.getOperand(2).getImm(); 912 TmpInst.setOpcode(Opcode == PPC::SLWI ? PPC::RLWINM : PPC::RLWINM_rec); 913 TmpInst.addOperand(Inst.getOperand(0)); 914 TmpInst.addOperand(Inst.getOperand(1)); 915 TmpInst.addOperand(MCOperand::createImm(N)); 916 TmpInst.addOperand(MCOperand::createImm(0)); 917 TmpInst.addOperand(MCOperand::createImm(31 - N)); 918 Inst = TmpInst; 919 break; 920 } 921 case PPC::SRWI: 922 case PPC::SRWI_rec: { 923 MCInst TmpInst; 924 int64_t N = Inst.getOperand(2).getImm(); 925 TmpInst.setOpcode(Opcode == PPC::SRWI ? PPC::RLWINM : PPC::RLWINM_rec); 926 TmpInst.addOperand(Inst.getOperand(0)); 927 TmpInst.addOperand(Inst.getOperand(1)); 928 TmpInst.addOperand(MCOperand::createImm(32 - N)); 929 TmpInst.addOperand(MCOperand::createImm(N)); 930 TmpInst.addOperand(MCOperand::createImm(31)); 931 Inst = TmpInst; 932 break; 933 } 934 case PPC::CLRRWI: 935 case PPC::CLRRWI_rec: { 936 MCInst TmpInst; 937 int64_t N = Inst.getOperand(2).getImm(); 938 TmpInst.setOpcode(Opcode == PPC::CLRRWI ? PPC::RLWINM : PPC::RLWINM_rec); 939 TmpInst.addOperand(Inst.getOperand(0)); 940 TmpInst.addOperand(Inst.getOperand(1)); 941 TmpInst.addOperand(MCOperand::createImm(0)); 942 TmpInst.addOperand(MCOperand::createImm(0)); 943 TmpInst.addOperand(MCOperand::createImm(31 - N)); 944 Inst = TmpInst; 945 break; 946 } 947 case PPC::CLRLSLWI: 948 case PPC::CLRLSLWI_rec: { 949 MCInst TmpInst; 950 int64_t B = Inst.getOperand(2).getImm(); 951 int64_t N = Inst.getOperand(3).getImm(); 952 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI ? PPC::RLWINM : PPC::RLWINM_rec); 953 TmpInst.addOperand(Inst.getOperand(0)); 954 TmpInst.addOperand(Inst.getOperand(1)); 955 TmpInst.addOperand(MCOperand::createImm(N)); 956 TmpInst.addOperand(MCOperand::createImm(B - N)); 957 TmpInst.addOperand(MCOperand::createImm(31 - N)); 958 Inst = TmpInst; 959 break; 960 } 961 case PPC::EXTLDI: 962 case PPC::EXTLDI_rec: { 963 MCInst TmpInst; 964 int64_t N = Inst.getOperand(2).getImm(); 965 int64_t B = Inst.getOperand(3).getImm(); 966 TmpInst.setOpcode(Opcode == PPC::EXTLDI ? PPC::RLDICR : PPC::RLDICR_rec); 967 TmpInst.addOperand(Inst.getOperand(0)); 968 TmpInst.addOperand(Inst.getOperand(1)); 969 TmpInst.addOperand(MCOperand::createImm(B)); 970 TmpInst.addOperand(MCOperand::createImm(N - 1)); 971 Inst = TmpInst; 972 break; 973 } 974 case PPC::EXTRDI: 975 case PPC::EXTRDI_rec: { 976 MCInst TmpInst; 977 int64_t N = Inst.getOperand(2).getImm(); 978 int64_t B = Inst.getOperand(3).getImm(); 979 TmpInst.setOpcode(Opcode == PPC::EXTRDI ? PPC::RLDICL : PPC::RLDICL_rec); 980 TmpInst.addOperand(Inst.getOperand(0)); 981 TmpInst.addOperand(Inst.getOperand(1)); 982 TmpInst.addOperand(MCOperand::createImm(B + N)); 983 TmpInst.addOperand(MCOperand::createImm(64 - N)); 984 Inst = TmpInst; 985 break; 986 } 987 case PPC::INSRDI: 988 case PPC::INSRDI_rec: { 989 MCInst TmpInst; 990 int64_t N = Inst.getOperand(2).getImm(); 991 int64_t B = Inst.getOperand(3).getImm(); 992 TmpInst.setOpcode(Opcode == PPC::INSRDI ? PPC::RLDIMI : PPC::RLDIMI_rec); 993 TmpInst.addOperand(Inst.getOperand(0)); 994 TmpInst.addOperand(Inst.getOperand(0)); 995 TmpInst.addOperand(Inst.getOperand(1)); 996 TmpInst.addOperand(MCOperand::createImm(64 - (B + N))); 997 TmpInst.addOperand(MCOperand::createImm(B)); 998 Inst = TmpInst; 999 break; 1000 } 1001 case PPC::ROTRDI: 1002 case PPC::ROTRDI_rec: { 1003 MCInst TmpInst; 1004 int64_t N = Inst.getOperand(2).getImm(); 1005 TmpInst.setOpcode(Opcode == PPC::ROTRDI ? PPC::RLDICL : PPC::RLDICL_rec); 1006 TmpInst.addOperand(Inst.getOperand(0)); 1007 TmpInst.addOperand(Inst.getOperand(1)); 1008 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1009 TmpInst.addOperand(MCOperand::createImm(0)); 1010 Inst = TmpInst; 1011 break; 1012 } 1013 case PPC::SLDI: 1014 case PPC::SLDI_rec: { 1015 MCInst TmpInst; 1016 int64_t N = Inst.getOperand(2).getImm(); 1017 TmpInst.setOpcode(Opcode == PPC::SLDI ? PPC::RLDICR : PPC::RLDICR_rec); 1018 TmpInst.addOperand(Inst.getOperand(0)); 1019 TmpInst.addOperand(Inst.getOperand(1)); 1020 TmpInst.addOperand(MCOperand::createImm(N)); 1021 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1022 Inst = TmpInst; 1023 break; 1024 } 1025 case PPC::SUBPCIS: { 1026 MCInst TmpInst; 1027 int64_t N = Inst.getOperand(1).getImm(); 1028 TmpInst.setOpcode(PPC::ADDPCIS); 1029 TmpInst.addOperand(Inst.getOperand(0)); 1030 TmpInst.addOperand(MCOperand::createImm(-N)); 1031 Inst = TmpInst; 1032 break; 1033 } 1034 case PPC::SRDI: 1035 case PPC::SRDI_rec: { 1036 MCInst TmpInst; 1037 int64_t N = Inst.getOperand(2).getImm(); 1038 TmpInst.setOpcode(Opcode == PPC::SRDI ? PPC::RLDICL : PPC::RLDICL_rec); 1039 TmpInst.addOperand(Inst.getOperand(0)); 1040 TmpInst.addOperand(Inst.getOperand(1)); 1041 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1042 TmpInst.addOperand(MCOperand::createImm(N)); 1043 Inst = TmpInst; 1044 break; 1045 } 1046 case PPC::CLRRDI: 1047 case PPC::CLRRDI_rec: { 1048 MCInst TmpInst; 1049 int64_t N = Inst.getOperand(2).getImm(); 1050 TmpInst.setOpcode(Opcode == PPC::CLRRDI ? PPC::RLDICR : PPC::RLDICR_rec); 1051 TmpInst.addOperand(Inst.getOperand(0)); 1052 TmpInst.addOperand(Inst.getOperand(1)); 1053 TmpInst.addOperand(MCOperand::createImm(0)); 1054 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1055 Inst = TmpInst; 1056 break; 1057 } 1058 case PPC::CLRLSLDI: 1059 case PPC::CLRLSLDI_rec: { 1060 MCInst TmpInst; 1061 int64_t B = Inst.getOperand(2).getImm(); 1062 int64_t N = Inst.getOperand(3).getImm(); 1063 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI ? PPC::RLDIC : PPC::RLDIC_rec); 1064 TmpInst.addOperand(Inst.getOperand(0)); 1065 TmpInst.addOperand(Inst.getOperand(1)); 1066 TmpInst.addOperand(MCOperand::createImm(N)); 1067 TmpInst.addOperand(MCOperand::createImm(B - N)); 1068 Inst = TmpInst; 1069 break; 1070 } 1071 case PPC::RLWINMbm: 1072 case PPC::RLWINMbm_rec: { 1073 unsigned MB, ME; 1074 int64_t BM = Inst.getOperand(3).getImm(); 1075 if (!isRunOfOnes(BM, MB, ME)) 1076 break; 1077 1078 MCInst TmpInst; 1079 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINM_rec); 1080 TmpInst.addOperand(Inst.getOperand(0)); 1081 TmpInst.addOperand(Inst.getOperand(1)); 1082 TmpInst.addOperand(Inst.getOperand(2)); 1083 TmpInst.addOperand(MCOperand::createImm(MB)); 1084 TmpInst.addOperand(MCOperand::createImm(ME)); 1085 Inst = TmpInst; 1086 break; 1087 } 1088 case PPC::RLWIMIbm: 1089 case PPC::RLWIMIbm_rec: { 1090 unsigned MB, ME; 1091 int64_t BM = Inst.getOperand(3).getImm(); 1092 if (!isRunOfOnes(BM, MB, ME)) 1093 break; 1094 1095 MCInst TmpInst; 1096 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMI_rec); 1097 TmpInst.addOperand(Inst.getOperand(0)); 1098 TmpInst.addOperand(Inst.getOperand(0)); // The tied operand. 1099 TmpInst.addOperand(Inst.getOperand(1)); 1100 TmpInst.addOperand(Inst.getOperand(2)); 1101 TmpInst.addOperand(MCOperand::createImm(MB)); 1102 TmpInst.addOperand(MCOperand::createImm(ME)); 1103 Inst = TmpInst; 1104 break; 1105 } 1106 case PPC::RLWNMbm: 1107 case PPC::RLWNMbm_rec: { 1108 unsigned MB, ME; 1109 int64_t BM = Inst.getOperand(3).getImm(); 1110 if (!isRunOfOnes(BM, MB, ME)) 1111 break; 1112 1113 MCInst TmpInst; 1114 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNM_rec); 1115 TmpInst.addOperand(Inst.getOperand(0)); 1116 TmpInst.addOperand(Inst.getOperand(1)); 1117 TmpInst.addOperand(Inst.getOperand(2)); 1118 TmpInst.addOperand(MCOperand::createImm(MB)); 1119 TmpInst.addOperand(MCOperand::createImm(ME)); 1120 Inst = TmpInst; 1121 break; 1122 } 1123 case PPC::MFTB: { 1124 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) { 1125 assert(Inst.getNumOperands() == 2 && "Expecting two operands"); 1126 Inst.setOpcode(PPC::MFSPR); 1127 } 1128 break; 1129 } 1130 case PPC::CP_COPYx: 1131 case PPC::CP_COPY_FIRST: { 1132 MCInst TmpInst; 1133 TmpInst.setOpcode(PPC::CP_COPY); 1134 TmpInst.addOperand(Inst.getOperand(0)); 1135 TmpInst.addOperand(Inst.getOperand(1)); 1136 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1)); 1137 1138 Inst = TmpInst; 1139 break; 1140 } 1141 case PPC::CP_PASTEx : 1142 case PPC::CP_PASTE_LAST: { 1143 MCInst TmpInst; 1144 TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ? PPC::CP_PASTE 1145 : PPC::CP_PASTE_rec); 1146 TmpInst.addOperand(Inst.getOperand(0)); 1147 TmpInst.addOperand(Inst.getOperand(1)); 1148 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1)); 1149 1150 Inst = TmpInst; 1151 break; 1152 } 1153 } 1154 } 1155 1156 static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, 1157 unsigned VariantID = 0); 1158 1159 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 1160 OperandVector &Operands, 1161 MCStreamer &Out, uint64_t &ErrorInfo, 1162 bool MatchingInlineAsm) { 1163 MCInst Inst; 1164 1165 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { 1166 case Match_Success: 1167 // Post-process instructions (typically extended mnemonics) 1168 ProcessInstruction(Inst, Operands); 1169 Inst.setLoc(IDLoc); 1170 Out.emitInstruction(Inst, getSTI()); 1171 return false; 1172 case Match_MissingFeature: 1173 return Error(IDLoc, "instruction use requires an option to be enabled"); 1174 case Match_MnemonicFail: { 1175 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); 1176 std::string Suggestion = PPCMnemonicSpellCheck( 1177 ((PPCOperand &)*Operands[0]).getToken(), FBS); 1178 return Error(IDLoc, "invalid instruction" + Suggestion, 1179 ((PPCOperand &)*Operands[0]).getLocRange()); 1180 } 1181 case Match_InvalidOperand: { 1182 SMLoc ErrorLoc = IDLoc; 1183 if (ErrorInfo != ~0ULL) { 1184 if (ErrorInfo >= Operands.size()) 1185 return Error(IDLoc, "too few operands for instruction"); 1186 1187 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc(); 1188 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 1189 } 1190 1191 return Error(ErrorLoc, "invalid operand for instruction"); 1192 } 1193 } 1194 1195 llvm_unreachable("Implement any new match types added!"); 1196 } 1197 1198 bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) { 1199 if (getParser().getTok().is(AsmToken::Identifier)) { 1200 StringRef Name = getParser().getTok().getString(); 1201 if (Name.equals_lower("lr")) { 1202 RegNo = isPPC64()? PPC::LR8 : PPC::LR; 1203 IntVal = 8; 1204 } else if (Name.equals_lower("ctr")) { 1205 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR; 1206 IntVal = 9; 1207 } else if (Name.equals_lower("vrsave")) { 1208 RegNo = PPC::VRSAVE; 1209 IntVal = 256; 1210 } else if (Name.startswith_lower("r") && 1211 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1212 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal]; 1213 } else if (Name.startswith_lower("f") && 1214 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1215 RegNo = FRegs[IntVal]; 1216 } else if (Name.startswith_lower("vs") && 1217 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) { 1218 RegNo = VSRegs[IntVal]; 1219 } else if (Name.startswith_lower("v") && 1220 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1221 RegNo = VRegs[IntVal]; 1222 } else if (Name.startswith_lower("cr") && 1223 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { 1224 RegNo = CRRegs[IntVal]; 1225 } else 1226 return true; 1227 getParser().Lex(); 1228 return false; 1229 } 1230 return true; 1231 } 1232 1233 bool PPCAsmParser:: 1234 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 1235 if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success) 1236 return TokError("invalid register name"); 1237 return false; 1238 } 1239 1240 OperandMatchResultTy PPCAsmParser::tryParseRegister(unsigned &RegNo, 1241 SMLoc &StartLoc, 1242 SMLoc &EndLoc) { 1243 const AsmToken &Tok = getParser().getTok(); 1244 StartLoc = Tok.getLoc(); 1245 EndLoc = Tok.getEndLoc(); 1246 RegNo = 0; 1247 int64_t IntVal; 1248 if (MatchRegisterName(RegNo, IntVal)) 1249 return MatchOperand_NoMatch; 1250 return MatchOperand_Success; 1251 } 1252 1253 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan 1254 /// the expression and check for VK_PPC_LO/HI/HA 1255 /// symbol variants. If all symbols with modifier use the same 1256 /// variant, return the corresponding PPCMCExpr::VariantKind, 1257 /// and a modified expression using the default symbol variant. 1258 /// Otherwise, return NULL. 1259 const MCExpr *PPCAsmParser:: 1260 ExtractModifierFromExpr(const MCExpr *E, 1261 PPCMCExpr::VariantKind &Variant) { 1262 MCContext &Context = getParser().getContext(); 1263 Variant = PPCMCExpr::VK_PPC_None; 1264 1265 switch (E->getKind()) { 1266 case MCExpr::Target: 1267 case MCExpr::Constant: 1268 return nullptr; 1269 1270 case MCExpr::SymbolRef: { 1271 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1272 1273 switch (SRE->getKind()) { 1274 case MCSymbolRefExpr::VK_PPC_LO: 1275 Variant = PPCMCExpr::VK_PPC_LO; 1276 break; 1277 case MCSymbolRefExpr::VK_PPC_HI: 1278 Variant = PPCMCExpr::VK_PPC_HI; 1279 break; 1280 case MCSymbolRefExpr::VK_PPC_HA: 1281 Variant = PPCMCExpr::VK_PPC_HA; 1282 break; 1283 case MCSymbolRefExpr::VK_PPC_HIGH: 1284 Variant = PPCMCExpr::VK_PPC_HIGH; 1285 break; 1286 case MCSymbolRefExpr::VK_PPC_HIGHA: 1287 Variant = PPCMCExpr::VK_PPC_HIGHA; 1288 break; 1289 case MCSymbolRefExpr::VK_PPC_HIGHER: 1290 Variant = PPCMCExpr::VK_PPC_HIGHER; 1291 break; 1292 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1293 Variant = PPCMCExpr::VK_PPC_HIGHERA; 1294 break; 1295 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1296 Variant = PPCMCExpr::VK_PPC_HIGHEST; 1297 break; 1298 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1299 Variant = PPCMCExpr::VK_PPC_HIGHESTA; 1300 break; 1301 default: 1302 return nullptr; 1303 } 1304 1305 return MCSymbolRefExpr::create(&SRE->getSymbol(), Context); 1306 } 1307 1308 case MCExpr::Unary: { 1309 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1310 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant); 1311 if (!Sub) 1312 return nullptr; 1313 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1314 } 1315 1316 case MCExpr::Binary: { 1317 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1318 PPCMCExpr::VariantKind LHSVariant, RHSVariant; 1319 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant); 1320 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant); 1321 1322 if (!LHS && !RHS) 1323 return nullptr; 1324 1325 if (!LHS) LHS = BE->getLHS(); 1326 if (!RHS) RHS = BE->getRHS(); 1327 1328 if (LHSVariant == PPCMCExpr::VK_PPC_None) 1329 Variant = RHSVariant; 1330 else if (RHSVariant == PPCMCExpr::VK_PPC_None) 1331 Variant = LHSVariant; 1332 else if (LHSVariant == RHSVariant) 1333 Variant = LHSVariant; 1334 else 1335 return nullptr; 1336 1337 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1338 } 1339 } 1340 1341 llvm_unreachable("Invalid expression kind!"); 1342 } 1343 1344 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace 1345 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having 1346 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT. 1347 /// FIXME: This is a hack. 1348 const MCExpr *PPCAsmParser:: 1349 FixupVariantKind(const MCExpr *E) { 1350 MCContext &Context = getParser().getContext(); 1351 1352 switch (E->getKind()) { 1353 case MCExpr::Target: 1354 case MCExpr::Constant: 1355 return E; 1356 1357 case MCExpr::SymbolRef: { 1358 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1359 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; 1360 1361 switch (SRE->getKind()) { 1362 case MCSymbolRefExpr::VK_TLSGD: 1363 Variant = MCSymbolRefExpr::VK_PPC_TLSGD; 1364 break; 1365 case MCSymbolRefExpr::VK_TLSLD: 1366 Variant = MCSymbolRefExpr::VK_PPC_TLSLD; 1367 break; 1368 default: 1369 return E; 1370 } 1371 return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context); 1372 } 1373 1374 case MCExpr::Unary: { 1375 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1376 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr()); 1377 if (Sub == UE->getSubExpr()) 1378 return E; 1379 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1380 } 1381 1382 case MCExpr::Binary: { 1383 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1384 const MCExpr *LHS = FixupVariantKind(BE->getLHS()); 1385 const MCExpr *RHS = FixupVariantKind(BE->getRHS()); 1386 if (LHS == BE->getLHS() && RHS == BE->getRHS()) 1387 return E; 1388 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1389 } 1390 } 1391 1392 llvm_unreachable("Invalid expression kind!"); 1393 } 1394 1395 /// ParseExpression. This differs from the default "parseExpression" in that 1396 /// it handles modifiers. 1397 bool PPCAsmParser:: 1398 ParseExpression(const MCExpr *&EVal) { 1399 1400 if (isDarwin()) 1401 return ParseDarwinExpression(EVal); 1402 1403 // (ELF Platforms) 1404 // Handle \code @l/@ha \endcode 1405 if (getParser().parseExpression(EVal)) 1406 return true; 1407 1408 EVal = FixupVariantKind(EVal); 1409 1410 PPCMCExpr::VariantKind Variant; 1411 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant); 1412 if (E) 1413 EVal = PPCMCExpr::create(Variant, E, getParser().getContext()); 1414 1415 return false; 1416 } 1417 1418 /// ParseDarwinExpression. (MachO Platforms) 1419 /// This differs from the default "parseExpression" in that it handles detection 1420 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present, 1421 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO 1422 /// syntax form so it is done here. TODO: Determine if there is merit in 1423 /// arranging for this to be done at a higher level. 1424 bool PPCAsmParser:: 1425 ParseDarwinExpression(const MCExpr *&EVal) { 1426 MCAsmParser &Parser = getParser(); 1427 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None; 1428 switch (getLexer().getKind()) { 1429 default: 1430 break; 1431 case AsmToken::Identifier: 1432 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus 1433 // something starting with any other char should be part of the 1434 // asm syntax. If handwritten asm includes an identifier like lo16, 1435 // then all bets are off - but no-one would do that, right? 1436 StringRef poss = Parser.getTok().getString(); 1437 if (poss.equals_lower("lo16")) { 1438 Variant = PPCMCExpr::VK_PPC_LO; 1439 } else if (poss.equals_lower("hi16")) { 1440 Variant = PPCMCExpr::VK_PPC_HI; 1441 } else if (poss.equals_lower("ha16")) { 1442 Variant = PPCMCExpr::VK_PPC_HA; 1443 } 1444 if (Variant != PPCMCExpr::VK_PPC_None) { 1445 Parser.Lex(); // Eat the xx16 1446 if (getLexer().isNot(AsmToken::LParen)) 1447 return Error(Parser.getTok().getLoc(), "expected '('"); 1448 Parser.Lex(); // Eat the '(' 1449 } 1450 break; 1451 } 1452 1453 if (getParser().parseExpression(EVal)) 1454 return true; 1455 1456 if (Variant != PPCMCExpr::VK_PPC_None) { 1457 if (getLexer().isNot(AsmToken::RParen)) 1458 return Error(Parser.getTok().getLoc(), "expected ')'"); 1459 Parser.Lex(); // Eat the ')' 1460 EVal = PPCMCExpr::create(Variant, EVal, getParser().getContext()); 1461 } 1462 return false; 1463 } 1464 1465 /// ParseOperand 1466 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and 1467 /// rNN for MachO. 1468 bool PPCAsmParser::ParseOperand(OperandVector &Operands) { 1469 MCAsmParser &Parser = getParser(); 1470 SMLoc S = Parser.getTok().getLoc(); 1471 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1472 const MCExpr *EVal; 1473 1474 // Attempt to parse the next token as an immediate 1475 switch (getLexer().getKind()) { 1476 // Special handling for register names. These are interpreted 1477 // as immediates corresponding to the register number. 1478 case AsmToken::Percent: 1479 Parser.Lex(); // Eat the '%'. 1480 unsigned RegNo; 1481 int64_t IntVal; 1482 if (MatchRegisterName(RegNo, IntVal)) 1483 return Error(S, "invalid register name"); 1484 1485 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1486 return false; 1487 1488 case AsmToken::Identifier: 1489 case AsmToken::LParen: 1490 case AsmToken::Plus: 1491 case AsmToken::Minus: 1492 case AsmToken::Integer: 1493 case AsmToken::Dot: 1494 case AsmToken::Dollar: 1495 case AsmToken::Exclaim: 1496 case AsmToken::Tilde: 1497 // Note that non-register-name identifiers from the compiler will begin 1498 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include 1499 // identifiers like r31foo - so we fall through in the event that parsing 1500 // a register name fails. 1501 if (isDarwin()) { 1502 unsigned RegNo; 1503 int64_t IntVal; 1504 if (!MatchRegisterName(RegNo, IntVal)) { 1505 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1506 return false; 1507 } 1508 } 1509 // All other expressions 1510 1511 if (!ParseExpression(EVal)) 1512 break; 1513 // Fall-through 1514 LLVM_FALLTHROUGH; 1515 default: 1516 return Error(S, "unknown operand"); 1517 } 1518 1519 // Push the parsed operand into the list of operands 1520 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64())); 1521 1522 // Check whether this is a TLS call expression 1523 bool TLSCall = false; 1524 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal)) 1525 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr"; 1526 1527 if (TLSCall && getLexer().is(AsmToken::LParen)) { 1528 const MCExpr *TLSSym; 1529 1530 Parser.Lex(); // Eat the '('. 1531 S = Parser.getTok().getLoc(); 1532 if (ParseExpression(TLSSym)) 1533 return Error(S, "invalid TLS call expression"); 1534 if (getLexer().isNot(AsmToken::RParen)) 1535 return Error(Parser.getTok().getLoc(), "missing ')'"); 1536 E = Parser.getTok().getLoc(); 1537 Parser.Lex(); // Eat the ')'. 1538 1539 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64())); 1540 } 1541 1542 // Otherwise, check for D-form memory operands 1543 if (!TLSCall && getLexer().is(AsmToken::LParen)) { 1544 Parser.Lex(); // Eat the '('. 1545 S = Parser.getTok().getLoc(); 1546 1547 int64_t IntVal; 1548 switch (getLexer().getKind()) { 1549 case AsmToken::Percent: 1550 Parser.Lex(); // Eat the '%'. 1551 unsigned RegNo; 1552 if (MatchRegisterName(RegNo, IntVal)) 1553 return Error(S, "invalid register name"); 1554 break; 1555 1556 case AsmToken::Integer: 1557 if (isDarwin()) 1558 return Error(S, "unexpected integer value"); 1559 else if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 || 1560 IntVal > 31) 1561 return Error(S, "invalid register number"); 1562 break; 1563 case AsmToken::Identifier: 1564 if (isDarwin()) { 1565 unsigned RegNo; 1566 if (!MatchRegisterName(RegNo, IntVal)) { 1567 break; 1568 } 1569 } 1570 LLVM_FALLTHROUGH; 1571 1572 default: 1573 return Error(S, "invalid memory operand"); 1574 } 1575 1576 E = Parser.getTok().getLoc(); 1577 if (parseToken(AsmToken::RParen, "missing ')'")) 1578 return true; 1579 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1580 } 1581 1582 return false; 1583 } 1584 1585 /// Parse an instruction mnemonic followed by its operands. 1586 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 1587 SMLoc NameLoc, OperandVector &Operands) { 1588 // The first operand is the token for the instruction name. 1589 // If the next character is a '+' or '-', we need to add it to the 1590 // instruction name, to match what TableGen is doing. 1591 std::string NewOpcode; 1592 if (parseOptionalToken(AsmToken::Plus)) { 1593 NewOpcode = std::string(Name); 1594 NewOpcode += '+'; 1595 Name = NewOpcode; 1596 } 1597 if (parseOptionalToken(AsmToken::Minus)) { 1598 NewOpcode = std::string(Name); 1599 NewOpcode += '-'; 1600 Name = NewOpcode; 1601 } 1602 // If the instruction ends in a '.', we need to create a separate 1603 // token for it, to match what TableGen is doing. 1604 size_t Dot = Name.find('.'); 1605 StringRef Mnemonic = Name.slice(0, Dot); 1606 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1607 Operands.push_back( 1608 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64())); 1609 else 1610 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64())); 1611 if (Dot != StringRef::npos) { 1612 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot); 1613 StringRef DotStr = Name.slice(Dot, StringRef::npos); 1614 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1615 Operands.push_back( 1616 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64())); 1617 else 1618 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64())); 1619 } 1620 1621 // If there are no more operands then finish 1622 if (parseOptionalToken(AsmToken::EndOfStatement)) 1623 return false; 1624 1625 // Parse the first operand 1626 if (ParseOperand(Operands)) 1627 return true; 1628 1629 while (!parseOptionalToken(AsmToken::EndOfStatement)) { 1630 if (parseToken(AsmToken::Comma) || ParseOperand(Operands)) 1631 return true; 1632 } 1633 1634 // We'll now deal with an unfortunate special case: the syntax for the dcbt 1635 // and dcbtst instructions differs for server vs. embedded cores. 1636 // The syntax for dcbt is: 1637 // dcbt ra, rb, th [server] 1638 // dcbt th, ra, rb [embedded] 1639 // where th can be omitted when it is 0. dcbtst is the same. We take the 1640 // server form to be the default, so swap the operands if we're parsing for 1641 // an embedded core (they'll be swapped again upon printing). 1642 if (getSTI().getFeatureBits()[PPC::FeatureBookE] && 1643 Operands.size() == 4 && 1644 (Name == "dcbt" || Name == "dcbtst")) { 1645 std::swap(Operands[1], Operands[3]); 1646 std::swap(Operands[2], Operands[1]); 1647 } 1648 1649 return false; 1650 } 1651 1652 /// ParseDirective parses the PPC specific directives 1653 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) { 1654 StringRef IDVal = DirectiveID.getIdentifier(); 1655 if (isDarwin()) { 1656 if (IDVal == ".machine") 1657 ParseDarwinDirectiveMachine(DirectiveID.getLoc()); 1658 else 1659 return true; 1660 } else if (IDVal == ".word") 1661 ParseDirectiveWord(2, DirectiveID); 1662 else if (IDVal == ".llong") 1663 ParseDirectiveWord(8, DirectiveID); 1664 else if (IDVal == ".tc") 1665 ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID); 1666 else if (IDVal == ".machine") 1667 ParseDirectiveMachine(DirectiveID.getLoc()); 1668 else if (IDVal == ".abiversion") 1669 ParseDirectiveAbiVersion(DirectiveID.getLoc()); 1670 else if (IDVal == ".localentry") 1671 ParseDirectiveLocalEntry(DirectiveID.getLoc()); 1672 else 1673 return true; 1674 return false; 1675 } 1676 1677 /// ParseDirectiveWord 1678 /// ::= .word [ expression (, expression)* ] 1679 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) { 1680 auto parseOp = [&]() -> bool { 1681 const MCExpr *Value; 1682 SMLoc ExprLoc = getParser().getTok().getLoc(); 1683 if (getParser().parseExpression(Value)) 1684 return true; 1685 if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) { 1686 assert(Size <= 8 && "Invalid size"); 1687 uint64_t IntValue = MCE->getValue(); 1688 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue)) 1689 return Error(ExprLoc, "literal value out of range for '" + 1690 ID.getIdentifier() + "' directive"); 1691 getStreamer().emitIntValue(IntValue, Size); 1692 } else 1693 getStreamer().emitValue(Value, Size, ExprLoc); 1694 return false; 1695 }; 1696 1697 if (parseMany(parseOp)) 1698 return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive"); 1699 return false; 1700 } 1701 1702 /// ParseDirectiveTC 1703 /// ::= .tc [ symbol (, expression)* ] 1704 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) { 1705 MCAsmParser &Parser = getParser(); 1706 // Skip TC symbol, which is only used with XCOFF. 1707 while (getLexer().isNot(AsmToken::EndOfStatement) 1708 && getLexer().isNot(AsmToken::Comma)) 1709 Parser.Lex(); 1710 if (parseToken(AsmToken::Comma)) 1711 return addErrorSuffix(" in '.tc' directive"); 1712 1713 // Align to word size. 1714 getParser().getStreamer().emitValueToAlignment(Size); 1715 1716 // Emit expressions. 1717 return ParseDirectiveWord(Size, ID); 1718 } 1719 1720 /// ParseDirectiveMachine (ELF platforms) 1721 /// ::= .machine [ cpu | "push" | "pop" ] 1722 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) { 1723 MCAsmParser &Parser = getParser(); 1724 if (Parser.getTok().isNot(AsmToken::Identifier) && 1725 Parser.getTok().isNot(AsmToken::String)) 1726 return Error(L, "unexpected token in '.machine' directive"); 1727 1728 StringRef CPU = Parser.getTok().getIdentifier(); 1729 1730 // FIXME: Right now, the parser always allows any available 1731 // instruction, so the .machine directive is not useful. 1732 // Implement ".machine any" (by doing nothing) for the benefit 1733 // of existing assembler code. Likewise, we can then implement 1734 // ".machine push" and ".machine pop" as no-op. 1735 if (CPU != "any" && CPU != "push" && CPU != "pop") 1736 return TokError("unrecognized machine type"); 1737 1738 Parser.Lex(); 1739 1740 if (parseToken(AsmToken::EndOfStatement)) 1741 return addErrorSuffix(" in '.machine' directive"); 1742 1743 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>( 1744 getParser().getStreamer().getTargetStreamer()); 1745 if (TStreamer != nullptr) 1746 TStreamer->emitMachine(CPU); 1747 1748 return false; 1749 } 1750 1751 /// ParseDarwinDirectiveMachine (Mach-o platforms) 1752 /// ::= .machine cpu-identifier 1753 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) { 1754 MCAsmParser &Parser = getParser(); 1755 if (Parser.getTok().isNot(AsmToken::Identifier) && 1756 Parser.getTok().isNot(AsmToken::String)) 1757 return Error(L, "unexpected token in directive"); 1758 1759 StringRef CPU = Parser.getTok().getIdentifier(); 1760 Parser.Lex(); 1761 1762 // FIXME: this is only the 'default' set of cpu variants. 1763 // However we don't act on this information at present, this is simply 1764 // allowing parsing to proceed with minimal sanity checking. 1765 if (check(CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64", L, 1766 "unrecognized cpu type") || 1767 check(isPPC64() && (CPU == "ppc7400" || CPU == "ppc"), L, 1768 "wrong cpu type specified for 64bit") || 1769 check(!isPPC64() && CPU == "ppc64", L, 1770 "wrong cpu type specified for 32bit") || 1771 parseToken(AsmToken::EndOfStatement)) 1772 return addErrorSuffix(" in '.machine' directive"); 1773 return false; 1774 } 1775 1776 /// ParseDirectiveAbiVersion 1777 /// ::= .abiversion constant-expression 1778 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) { 1779 int64_t AbiVersion; 1780 if (check(getParser().parseAbsoluteExpression(AbiVersion), L, 1781 "expected constant expression") || 1782 parseToken(AsmToken::EndOfStatement)) 1783 return addErrorSuffix(" in '.abiversion' directive"); 1784 1785 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>( 1786 getParser().getStreamer().getTargetStreamer()); 1787 if (TStreamer != nullptr) 1788 TStreamer->emitAbiVersion(AbiVersion); 1789 1790 return false; 1791 } 1792 1793 /// ParseDirectiveLocalEntry 1794 /// ::= .localentry symbol, expression 1795 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) { 1796 StringRef Name; 1797 if (getParser().parseIdentifier(Name)) 1798 return Error(L, "expected identifier in '.localentry' directive"); 1799 1800 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name)); 1801 const MCExpr *Expr; 1802 1803 if (parseToken(AsmToken::Comma) || 1804 check(getParser().parseExpression(Expr), L, "expected expression") || 1805 parseToken(AsmToken::EndOfStatement)) 1806 return addErrorSuffix(" in '.localentry' directive"); 1807 1808 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>( 1809 getParser().getStreamer().getTargetStreamer()); 1810 if (TStreamer != nullptr) 1811 TStreamer->emitLocalEntry(Sym, Expr); 1812 1813 return false; 1814 } 1815 1816 1817 1818 /// Force static initialization. 1819 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCAsmParser() { 1820 RegisterMCAsmParser<PPCAsmParser> A(getThePPC32Target()); 1821 RegisterMCAsmParser<PPCAsmParser> B(getThePPC64Target()); 1822 RegisterMCAsmParser<PPCAsmParser> C(getThePPC64LETarget()); 1823 } 1824 1825 #define GET_REGISTER_MATCHER 1826 #define GET_MATCHER_IMPLEMENTATION 1827 #define GET_MNEMONIC_SPELL_CHECKER 1828 #include "PPCGenAsmMatcher.inc" 1829 1830 // Define this matcher function after the auto-generated include so we 1831 // have the match class enum definitions. 1832 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, 1833 unsigned Kind) { 1834 // If the kind is a token for a literal immediate, check if our asm 1835 // operand matches. This is for InstAliases which have a fixed-value 1836 // immediate in the syntax. 1837 int64_t ImmVal; 1838 switch (Kind) { 1839 case MCK_0: ImmVal = 0; break; 1840 case MCK_1: ImmVal = 1; break; 1841 case MCK_2: ImmVal = 2; break; 1842 case MCK_3: ImmVal = 3; break; 1843 case MCK_4: ImmVal = 4; break; 1844 case MCK_5: ImmVal = 5; break; 1845 case MCK_6: ImmVal = 6; break; 1846 case MCK_7: ImmVal = 7; break; 1847 default: return Match_InvalidOperand; 1848 } 1849 1850 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp); 1851 if (Op.isImm() && Op.getImm() == ImmVal) 1852 return Match_Success; 1853 1854 return Match_InvalidOperand; 1855 } 1856 1857 const MCExpr * 1858 PPCAsmParser::applyModifierToExpr(const MCExpr *E, 1859 MCSymbolRefExpr::VariantKind Variant, 1860 MCContext &Ctx) { 1861 switch (Variant) { 1862 case MCSymbolRefExpr::VK_PPC_LO: 1863 return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, Ctx); 1864 case MCSymbolRefExpr::VK_PPC_HI: 1865 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, Ctx); 1866 case MCSymbolRefExpr::VK_PPC_HA: 1867 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, Ctx); 1868 case MCSymbolRefExpr::VK_PPC_HIGH: 1869 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGH, E, Ctx); 1870 case MCSymbolRefExpr::VK_PPC_HIGHA: 1871 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHA, E, Ctx); 1872 case MCSymbolRefExpr::VK_PPC_HIGHER: 1873 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, Ctx); 1874 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1875 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, Ctx); 1876 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1877 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, Ctx); 1878 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1879 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, Ctx); 1880 default: 1881 return nullptr; 1882 } 1883 } 1884