xref: /llvm-project/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (revision 80722719eb42cb2d4d374abd507d05a49862049d) 
1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCExpr.h"
11 #include "MCTargetDesc/PPCMCTargetDesc.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/MC/MCSymbolELF.h"
30 #include "llvm/Support/SourceMgr.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Support/raw_ostream.h"
33 
34 using namespace llvm;
35 
36 static const MCPhysReg RRegs[32] = {
37   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
38   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
39   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
40   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
41   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
42   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
43   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
44   PPC::R28, PPC::R29, PPC::R30, PPC::R31
45 };
46 static const MCPhysReg RRegsNoR0[32] = {
47   PPC::ZERO,
48             PPC::R1,  PPC::R2,  PPC::R3,
49   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
50   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
51   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
52   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
53   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
54   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
55   PPC::R28, PPC::R29, PPC::R30, PPC::R31
56 };
57 static const MCPhysReg XRegs[32] = {
58   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
59   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
60   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
61   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
62   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
63   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
64   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
65   PPC::X28, PPC::X29, PPC::X30, PPC::X31
66 };
67 static const MCPhysReg XRegsNoX0[32] = {
68   PPC::ZERO8,
69             PPC::X1,  PPC::X2,  PPC::X3,
70   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
71   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
72   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
73   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
74   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
75   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
76   PPC::X28, PPC::X29, PPC::X30, PPC::X31
77 };
78 static const MCPhysReg FRegs[32] = {
79   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
80   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
81   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
82   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
83   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
84   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
85   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
86   PPC::F28, PPC::F29, PPC::F30, PPC::F31
87 };
88 static const MCPhysReg VRegs[32] = {
89   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
90   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
91   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
92   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
93   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
94   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
95   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
96   PPC::V28, PPC::V29, PPC::V30, PPC::V31
97 };
98 static const MCPhysReg VSRegs[64] = {
99   PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
100   PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
101   PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
102   PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
103   PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
104   PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
105   PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
106   PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
107 
108   PPC::VSH0,  PPC::VSH1,  PPC::VSH2,  PPC::VSH3,
109   PPC::VSH4,  PPC::VSH5,  PPC::VSH6,  PPC::VSH7,
110   PPC::VSH8,  PPC::VSH9,  PPC::VSH10, PPC::VSH11,
111   PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
112   PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
113   PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
114   PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
115   PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
116 };
117 static const MCPhysReg VSFRegs[64] = {
118   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
119   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
120   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
121   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
122   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
123   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
124   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
125   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
126 
127   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
128   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
129   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
130   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
131   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
132   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
133   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
134   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
135 };
136 static const MCPhysReg VSSRegs[64] = {
137   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
138   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
139   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
140   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
141   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
142   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
143   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
144   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
145 
146   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
147   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
148   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
149   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
150   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
151   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
152   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
153   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
154 };
155 static unsigned QFRegs[32] = {
156   PPC::QF0,  PPC::QF1,  PPC::QF2,  PPC::QF3,
157   PPC::QF4,  PPC::QF5,  PPC::QF6,  PPC::QF7,
158   PPC::QF8,  PPC::QF9,  PPC::QF10, PPC::QF11,
159   PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
160   PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
161   PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
162   PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
163   PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
164 };
165 static const MCPhysReg CRBITRegs[32] = {
166   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
167   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
168   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
169   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
170   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
171   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
172   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
173   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
174 };
175 static const MCPhysReg CRRegs[8] = {
176   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
177   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
178 };
179 
180 // Evaluate an expression containing condition register
181 // or condition register field symbols.  Returns positive
182 // value on success, or -1 on error.
183 static int64_t
184 EvaluateCRExpr(const MCExpr *E) {
185   switch (E->getKind()) {
186   case MCExpr::Target:
187     return -1;
188 
189   case MCExpr::Constant: {
190     int64_t Res = cast<MCConstantExpr>(E)->getValue();
191     return Res < 0 ? -1 : Res;
192   }
193 
194   case MCExpr::SymbolRef: {
195     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
196     StringRef Name = SRE->getSymbol().getName();
197 
198     if (Name == "lt") return 0;
199     if (Name == "gt") return 1;
200     if (Name == "eq") return 2;
201     if (Name == "so") return 3;
202     if (Name == "un") return 3;
203 
204     if (Name == "cr0") return 0;
205     if (Name == "cr1") return 1;
206     if (Name == "cr2") return 2;
207     if (Name == "cr3") return 3;
208     if (Name == "cr4") return 4;
209     if (Name == "cr5") return 5;
210     if (Name == "cr6") return 6;
211     if (Name == "cr7") return 7;
212 
213     return -1;
214   }
215 
216   case MCExpr::Unary:
217     return -1;
218 
219   case MCExpr::Binary: {
220     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
221     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
222     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
223     int64_t Res;
224 
225     if (LHSVal < 0 || RHSVal < 0)
226       return -1;
227 
228     switch (BE->getOpcode()) {
229     default: return -1;
230     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
231     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
232     }
233 
234     return Res < 0 ? -1 : Res;
235   }
236   }
237 
238   llvm_unreachable("Invalid expression kind!");
239 }
240 
241 namespace {
242 
243 struct PPCOperand;
244 
245 class PPCAsmParser : public MCTargetAsmParser {
246   const MCInstrInfo &MII;
247   bool IsPPC64;
248   bool IsDarwin;
249 
250   void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
251   bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
252 
253   bool isPPC64() const { return IsPPC64; }
254   bool isDarwin() const { return IsDarwin; }
255 
256   bool MatchRegisterName(const AsmToken &Tok,
257                          unsigned &RegNo, int64_t &IntVal);
258 
259   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
260 
261   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
262                                         PPCMCExpr::VariantKind &Variant);
263   const MCExpr *FixupVariantKind(const MCExpr *E);
264   bool ParseExpression(const MCExpr *&EVal);
265   bool ParseDarwinExpression(const MCExpr *&EVal);
266 
267   bool ParseOperand(OperandVector &Operands);
268 
269   bool ParseDirectiveWord(unsigned Size, SMLoc L);
270   bool ParseDirectiveTC(unsigned Size, SMLoc L);
271   bool ParseDirectiveMachine(SMLoc L);
272   bool ParseDarwinDirectiveMachine(SMLoc L);
273   bool ParseDirectiveAbiVersion(SMLoc L);
274   bool ParseDirectiveLocalEntry(SMLoc L);
275 
276   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
277                                OperandVector &Operands, MCStreamer &Out,
278                                uint64_t &ErrorInfo,
279                                bool MatchingInlineAsm) override;
280 
281   void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
282 
283   /// @name Auto-generated Match Functions
284   /// {
285 
286 #define GET_ASSEMBLER_HEADER
287 #include "PPCGenAsmMatcher.inc"
288 
289   /// }
290 
291 
292 public:
293   PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
294                const MCInstrInfo &MII, const MCTargetOptions &Options)
295     : MCTargetAsmParser(Options, STI), MII(MII) {
296     // Check for 64-bit vs. 32-bit pointer mode.
297     Triple TheTriple(STI.getTargetTriple());
298     IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
299                TheTriple.getArch() == Triple::ppc64le);
300     IsDarwin = TheTriple.isMacOSX();
301     // Initialize the set of available features.
302     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
303   }
304 
305   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
306                         SMLoc NameLoc, OperandVector &Operands) override;
307 
308   bool ParseDirective(AsmToken DirectiveID) override;
309 
310   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
311                                       unsigned Kind) override;
312 
313   const MCExpr *applyModifierToExpr(const MCExpr *E,
314                                     MCSymbolRefExpr::VariantKind,
315                                     MCContext &Ctx) override;
316 };
317 
318 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
319 /// instruction.
320 struct PPCOperand : public MCParsedAsmOperand {
321   enum KindTy {
322     Token,
323     Immediate,
324     ContextImmediate,
325     Expression,
326     TLSRegister
327   } Kind;
328 
329   SMLoc StartLoc, EndLoc;
330   bool IsPPC64;
331 
332   struct TokOp {
333     const char *Data;
334     unsigned Length;
335   };
336 
337   struct ImmOp {
338     int64_t Val;
339   };
340 
341   struct ExprOp {
342     const MCExpr *Val;
343     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
344   };
345 
346   struct TLSRegOp {
347     const MCSymbolRefExpr *Sym;
348   };
349 
350   union {
351     struct TokOp Tok;
352     struct ImmOp Imm;
353     struct ExprOp Expr;
354     struct TLSRegOp TLSReg;
355   };
356 
357   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
358 public:
359   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
360     Kind = o.Kind;
361     StartLoc = o.StartLoc;
362     EndLoc = o.EndLoc;
363     IsPPC64 = o.IsPPC64;
364     switch (Kind) {
365     case Token:
366       Tok = o.Tok;
367       break;
368     case Immediate:
369     case ContextImmediate:
370       Imm = o.Imm;
371       break;
372     case Expression:
373       Expr = o.Expr;
374       break;
375     case TLSRegister:
376       TLSReg = o.TLSReg;
377       break;
378     }
379   }
380 
381   // Disable use of sized deallocation due to overallocation of PPCOperand
382   // objects in CreateTokenWithStringCopy.
383   void operator delete(void *p) { ::operator delete(p); }
384 
385   /// getStartLoc - Get the location of the first token of this operand.
386   SMLoc getStartLoc() const override { return StartLoc; }
387 
388   /// getEndLoc - Get the location of the last token of this operand.
389   SMLoc getEndLoc() const override { return EndLoc; }
390 
391   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
392   bool isPPC64() const { return IsPPC64; }
393 
394   int64_t getImm() const {
395     assert(Kind == Immediate && "Invalid access!");
396     return Imm.Val;
397   }
398   int64_t getImmS16Context() const {
399     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
400     if (Kind == Immediate)
401       return Imm.Val;
402     return static_cast<int16_t>(Imm.Val);
403   }
404   int64_t getImmU16Context() const {
405     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
406     return Imm.Val;
407   }
408 
409   const MCExpr *getExpr() const {
410     assert(Kind == Expression && "Invalid access!");
411     return Expr.Val;
412   }
413 
414   int64_t getExprCRVal() const {
415     assert(Kind == Expression && "Invalid access!");
416     return Expr.CRVal;
417   }
418 
419   const MCExpr *getTLSReg() const {
420     assert(Kind == TLSRegister && "Invalid access!");
421     return TLSReg.Sym;
422   }
423 
424   unsigned getReg() const override {
425     assert(isRegNumber() && "Invalid access!");
426     return (unsigned) Imm.Val;
427   }
428 
429   unsigned getVSReg() const {
430     assert(isVSRegNumber() && "Invalid access!");
431     return (unsigned) Imm.Val;
432   }
433 
434   unsigned getCCReg() const {
435     assert(isCCRegNumber() && "Invalid access!");
436     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
437   }
438 
439   unsigned getCRBit() const {
440     assert(isCRBitNumber() && "Invalid access!");
441     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
442   }
443 
444   unsigned getCRBitMask() const {
445     assert(isCRBitMask() && "Invalid access!");
446     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
447   }
448 
449   bool isToken() const override { return Kind == Token; }
450   bool isImm() const override { return Kind == Immediate || Kind == Expression; }
451   bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
452   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
453   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
454   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
455   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
456   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
457   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
458   bool isU6ImmX2() const { return Kind == Immediate &&
459                                   isUInt<6>(getImm()) &&
460                                   (getImm() & 1) == 0; }
461   bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
462   bool isU7ImmX4() const { return Kind == Immediate &&
463                                   isUInt<7>(getImm()) &&
464                                   (getImm() & 3) == 0; }
465   bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
466   bool isU8ImmX8() const { return Kind == Immediate &&
467                                   isUInt<8>(getImm()) &&
468                                   (getImm() & 7) == 0; }
469 
470   bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
471   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
472   bool isU16Imm() const {
473     switch (Kind) {
474       case Expression:
475         return true;
476       case Immediate:
477       case ContextImmediate:
478         return isUInt<16>(getImmU16Context());
479       default:
480         return false;
481     }
482   }
483   bool isS16Imm() const {
484     switch (Kind) {
485       case Expression:
486         return true;
487       case Immediate:
488       case ContextImmediate:
489         return isInt<16>(getImmS16Context());
490       default:
491         return false;
492     }
493   }
494   bool isS16ImmX4() const { return Kind == Expression ||
495                                    (Kind == Immediate && isInt<16>(getImm()) &&
496                                     (getImm() & 3) == 0); }
497   bool isS16ImmX16() const { return Kind == Expression ||
498                                     (Kind == Immediate && isInt<16>(getImm()) &&
499                                      (getImm() & 15) == 0); }
500   bool isS17Imm() const {
501     switch (Kind) {
502       case Expression:
503         return true;
504       case Immediate:
505       case ContextImmediate:
506         return isInt<17>(getImmS16Context());
507       default:
508         return false;
509     }
510   }
511   bool isTLSReg() const { return Kind == TLSRegister; }
512   bool isDirectBr() const {
513     if (Kind == Expression)
514       return true;
515     if (Kind != Immediate)
516       return false;
517     // Operand must be 64-bit aligned, signed 27-bit immediate.
518     if ((getImm() & 3) != 0)
519       return false;
520     if (isInt<26>(getImm()))
521       return true;
522     if (!IsPPC64) {
523       // In 32-bit mode, large 32-bit quantities wrap around.
524       if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
525         return true;
526     }
527     return false;
528   }
529   bool isCondBr() const { return Kind == Expression ||
530                                  (Kind == Immediate && isInt<16>(getImm()) &&
531                                   (getImm() & 3) == 0); }
532   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
533   bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
534   bool isCCRegNumber() const { return (Kind == Expression
535                                        && isUInt<3>(getExprCRVal())) ||
536                                       (Kind == Immediate
537                                        && isUInt<3>(getImm())); }
538   bool isCRBitNumber() const { return (Kind == Expression
539                                        && isUInt<5>(getExprCRVal())) ||
540                                       (Kind == Immediate
541                                        && isUInt<5>(getImm())); }
542   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
543                                     isPowerOf2_32(getImm()); }
544   bool isMem() const override { return false; }
545   bool isReg() const override { return false; }
546 
547   void addRegOperands(MCInst &Inst, unsigned N) const {
548     llvm_unreachable("addRegOperands");
549   }
550 
551   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
552     assert(N == 1 && "Invalid number of operands!");
553     Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
554   }
555 
556   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
557     assert(N == 1 && "Invalid number of operands!");
558     Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
559   }
560 
561   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
562     assert(N == 1 && "Invalid number of operands!");
563     Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
564   }
565 
566   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
567     assert(N == 1 && "Invalid number of operands!");
568     Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
569   }
570 
571   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
572     if (isPPC64())
573       addRegG8RCOperands(Inst, N);
574     else
575       addRegGPRCOperands(Inst, N);
576   }
577 
578   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
579     if (isPPC64())
580       addRegG8RCNoX0Operands(Inst, N);
581     else
582       addRegGPRCNoR0Operands(Inst, N);
583   }
584 
585   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
586     assert(N == 1 && "Invalid number of operands!");
587     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
588   }
589 
590   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
591     assert(N == 1 && "Invalid number of operands!");
592     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
593   }
594 
595   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
596     assert(N == 1 && "Invalid number of operands!");
597     Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
598   }
599 
600   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
601     assert(N == 1 && "Invalid number of operands!");
602     Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
603   }
604 
605   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
606     assert(N == 1 && "Invalid number of operands!");
607     Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
608   }
609 
610   void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
611     assert(N == 1 && "Invalid number of operands!");
612     Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
613   }
614 
615   void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
616     assert(N == 1 && "Invalid number of operands!");
617     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
618   }
619 
620   void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
621     assert(N == 1 && "Invalid number of operands!");
622     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
623   }
624 
625   void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
626     assert(N == 1 && "Invalid number of operands!");
627     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
628   }
629 
630   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
631     assert(N == 1 && "Invalid number of operands!");
632     Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
633   }
634 
635   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
636     assert(N == 1 && "Invalid number of operands!");
637     Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
638   }
639 
640   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
641     assert(N == 1 && "Invalid number of operands!");
642     Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
643   }
644 
645   void addImmOperands(MCInst &Inst, unsigned N) const {
646     assert(N == 1 && "Invalid number of operands!");
647     if (Kind == Immediate)
648       Inst.addOperand(MCOperand::createImm(getImm()));
649     else
650       Inst.addOperand(MCOperand::createExpr(getExpr()));
651   }
652 
653   void addS16ImmOperands(MCInst &Inst, unsigned N) const {
654     assert(N == 1 && "Invalid number of operands!");
655     switch (Kind) {
656       case Immediate:
657         Inst.addOperand(MCOperand::createImm(getImm()));
658         break;
659       case ContextImmediate:
660         Inst.addOperand(MCOperand::createImm(getImmS16Context()));
661         break;
662       default:
663         Inst.addOperand(MCOperand::createExpr(getExpr()));
664         break;
665     }
666   }
667 
668   void addU16ImmOperands(MCInst &Inst, unsigned N) const {
669     assert(N == 1 && "Invalid number of operands!");
670     switch (Kind) {
671       case Immediate:
672         Inst.addOperand(MCOperand::createImm(getImm()));
673         break;
674       case ContextImmediate:
675         Inst.addOperand(MCOperand::createImm(getImmU16Context()));
676         break;
677       default:
678         Inst.addOperand(MCOperand::createExpr(getExpr()));
679         break;
680     }
681   }
682 
683   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
684     assert(N == 1 && "Invalid number of operands!");
685     if (Kind == Immediate)
686       Inst.addOperand(MCOperand::createImm(getImm() / 4));
687     else
688       Inst.addOperand(MCOperand::createExpr(getExpr()));
689   }
690 
691   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
692     assert(N == 1 && "Invalid number of operands!");
693     Inst.addOperand(MCOperand::createExpr(getTLSReg()));
694   }
695 
696   StringRef getToken() const {
697     assert(Kind == Token && "Invalid access!");
698     return StringRef(Tok.Data, Tok.Length);
699   }
700 
701   void print(raw_ostream &OS) const override;
702 
703   static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
704                                                  bool IsPPC64) {
705     auto Op = make_unique<PPCOperand>(Token);
706     Op->Tok.Data = Str.data();
707     Op->Tok.Length = Str.size();
708     Op->StartLoc = S;
709     Op->EndLoc = S;
710     Op->IsPPC64 = IsPPC64;
711     return Op;
712   }
713 
714   static std::unique_ptr<PPCOperand>
715   CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
716     // Allocate extra memory for the string and copy it.
717     // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
718     // deleter which will destroy them by simply using "delete", not correctly
719     // calling operator delete on this extra memory after calling the dtor
720     // explicitly.
721     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
722     std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
723     Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
724     Op->Tok.Length = Str.size();
725     std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
726     Op->StartLoc = S;
727     Op->EndLoc = S;
728     Op->IsPPC64 = IsPPC64;
729     return Op;
730   }
731 
732   static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
733                                                bool IsPPC64) {
734     auto Op = make_unique<PPCOperand>(Immediate);
735     Op->Imm.Val = Val;
736     Op->StartLoc = S;
737     Op->EndLoc = E;
738     Op->IsPPC64 = IsPPC64;
739     return Op;
740   }
741 
742   static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
743                                                 SMLoc E, bool IsPPC64) {
744     auto Op = make_unique<PPCOperand>(Expression);
745     Op->Expr.Val = Val;
746     Op->Expr.CRVal = EvaluateCRExpr(Val);
747     Op->StartLoc = S;
748     Op->EndLoc = E;
749     Op->IsPPC64 = IsPPC64;
750     return Op;
751   }
752 
753   static std::unique_ptr<PPCOperand>
754   CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
755     auto Op = make_unique<PPCOperand>(TLSRegister);
756     Op->TLSReg.Sym = Sym;
757     Op->StartLoc = S;
758     Op->EndLoc = E;
759     Op->IsPPC64 = IsPPC64;
760     return Op;
761   }
762 
763   static std::unique_ptr<PPCOperand>
764   CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
765     auto Op = make_unique<PPCOperand>(ContextImmediate);
766     Op->Imm.Val = Val;
767     Op->StartLoc = S;
768     Op->EndLoc = E;
769     Op->IsPPC64 = IsPPC64;
770     return Op;
771   }
772 
773   static std::unique_ptr<PPCOperand>
774   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
775     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
776       return CreateImm(CE->getValue(), S, E, IsPPC64);
777 
778     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
779       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
780         return CreateTLSReg(SRE, S, E, IsPPC64);
781 
782     if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
783       int64_t Res;
784       if (TE->evaluateAsConstant(Res))
785         return CreateContextImm(Res, S, E, IsPPC64);
786     }
787 
788     return CreateExpr(Val, S, E, IsPPC64);
789   }
790 };
791 
792 } // end anonymous namespace.
793 
794 void PPCOperand::print(raw_ostream &OS) const {
795   switch (Kind) {
796   case Token:
797     OS << "'" << getToken() << "'";
798     break;
799   case Immediate:
800   case ContextImmediate:
801     OS << getImm();
802     break;
803   case Expression:
804     OS << *getExpr();
805     break;
806   case TLSRegister:
807     OS << *getTLSReg();
808     break;
809   }
810 }
811 
812 static void
813 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
814   if (Op.isImm()) {
815     Inst.addOperand(MCOperand::createImm(-Op.getImm()));
816     return;
817   }
818   const MCExpr *Expr = Op.getExpr();
819   if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
820     if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
821       Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
822       return;
823     }
824   } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
825     if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
826       const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
827                                                  BinExpr->getLHS(), Ctx);
828       Inst.addOperand(MCOperand::createExpr(NE));
829       return;
830     }
831   }
832   Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx)));
833 }
834 
835 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
836                                       const OperandVector &Operands) {
837   int Opcode = Inst.getOpcode();
838   switch (Opcode) {
839   case PPC::DCBTx:
840   case PPC::DCBTT:
841   case PPC::DCBTSTx:
842   case PPC::DCBTSTT: {
843     MCInst TmpInst;
844     TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
845                       PPC::DCBT : PPC::DCBTST);
846     TmpInst.addOperand(MCOperand::createImm(
847       (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
848     TmpInst.addOperand(Inst.getOperand(0));
849     TmpInst.addOperand(Inst.getOperand(1));
850     Inst = TmpInst;
851     break;
852   }
853   case PPC::DCBTCT:
854   case PPC::DCBTDS: {
855     MCInst TmpInst;
856     TmpInst.setOpcode(PPC::DCBT);
857     TmpInst.addOperand(Inst.getOperand(2));
858     TmpInst.addOperand(Inst.getOperand(0));
859     TmpInst.addOperand(Inst.getOperand(1));
860     Inst = TmpInst;
861     break;
862   }
863   case PPC::DCBTSTCT:
864   case PPC::DCBTSTDS: {
865     MCInst TmpInst;
866     TmpInst.setOpcode(PPC::DCBTST);
867     TmpInst.addOperand(Inst.getOperand(2));
868     TmpInst.addOperand(Inst.getOperand(0));
869     TmpInst.addOperand(Inst.getOperand(1));
870     Inst = TmpInst;
871     break;
872   }
873   case PPC::LAx: {
874     MCInst TmpInst;
875     TmpInst.setOpcode(PPC::LA);
876     TmpInst.addOperand(Inst.getOperand(0));
877     TmpInst.addOperand(Inst.getOperand(2));
878     TmpInst.addOperand(Inst.getOperand(1));
879     Inst = TmpInst;
880     break;
881   }
882   case PPC::SUBI: {
883     MCInst TmpInst;
884     TmpInst.setOpcode(PPC::ADDI);
885     TmpInst.addOperand(Inst.getOperand(0));
886     TmpInst.addOperand(Inst.getOperand(1));
887     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
888     Inst = TmpInst;
889     break;
890   }
891   case PPC::SUBIS: {
892     MCInst TmpInst;
893     TmpInst.setOpcode(PPC::ADDIS);
894     TmpInst.addOperand(Inst.getOperand(0));
895     TmpInst.addOperand(Inst.getOperand(1));
896     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
897     Inst = TmpInst;
898     break;
899   }
900   case PPC::SUBIC: {
901     MCInst TmpInst;
902     TmpInst.setOpcode(PPC::ADDIC);
903     TmpInst.addOperand(Inst.getOperand(0));
904     TmpInst.addOperand(Inst.getOperand(1));
905     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
906     Inst = TmpInst;
907     break;
908   }
909   case PPC::SUBICo: {
910     MCInst TmpInst;
911     TmpInst.setOpcode(PPC::ADDICo);
912     TmpInst.addOperand(Inst.getOperand(0));
913     TmpInst.addOperand(Inst.getOperand(1));
914     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
915     Inst = TmpInst;
916     break;
917   }
918   case PPC::EXTLWI:
919   case PPC::EXTLWIo: {
920     MCInst TmpInst;
921     int64_t N = Inst.getOperand(2).getImm();
922     int64_t B = Inst.getOperand(3).getImm();
923     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
924     TmpInst.addOperand(Inst.getOperand(0));
925     TmpInst.addOperand(Inst.getOperand(1));
926     TmpInst.addOperand(MCOperand::createImm(B));
927     TmpInst.addOperand(MCOperand::createImm(0));
928     TmpInst.addOperand(MCOperand::createImm(N - 1));
929     Inst = TmpInst;
930     break;
931   }
932   case PPC::EXTRWI:
933   case PPC::EXTRWIo: {
934     MCInst TmpInst;
935     int64_t N = Inst.getOperand(2).getImm();
936     int64_t B = Inst.getOperand(3).getImm();
937     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
938     TmpInst.addOperand(Inst.getOperand(0));
939     TmpInst.addOperand(Inst.getOperand(1));
940     TmpInst.addOperand(MCOperand::createImm(B + N));
941     TmpInst.addOperand(MCOperand::createImm(32 - N));
942     TmpInst.addOperand(MCOperand::createImm(31));
943     Inst = TmpInst;
944     break;
945   }
946   case PPC::INSLWI:
947   case PPC::INSLWIo: {
948     MCInst TmpInst;
949     int64_t N = Inst.getOperand(2).getImm();
950     int64_t B = Inst.getOperand(3).getImm();
951     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
952     TmpInst.addOperand(Inst.getOperand(0));
953     TmpInst.addOperand(Inst.getOperand(0));
954     TmpInst.addOperand(Inst.getOperand(1));
955     TmpInst.addOperand(MCOperand::createImm(32 - B));
956     TmpInst.addOperand(MCOperand::createImm(B));
957     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
958     Inst = TmpInst;
959     break;
960   }
961   case PPC::INSRWI:
962   case PPC::INSRWIo: {
963     MCInst TmpInst;
964     int64_t N = Inst.getOperand(2).getImm();
965     int64_t B = Inst.getOperand(3).getImm();
966     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
967     TmpInst.addOperand(Inst.getOperand(0));
968     TmpInst.addOperand(Inst.getOperand(0));
969     TmpInst.addOperand(Inst.getOperand(1));
970     TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
971     TmpInst.addOperand(MCOperand::createImm(B));
972     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
973     Inst = TmpInst;
974     break;
975   }
976   case PPC::ROTRWI:
977   case PPC::ROTRWIo: {
978     MCInst TmpInst;
979     int64_t N = Inst.getOperand(2).getImm();
980     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
981     TmpInst.addOperand(Inst.getOperand(0));
982     TmpInst.addOperand(Inst.getOperand(1));
983     TmpInst.addOperand(MCOperand::createImm(32 - N));
984     TmpInst.addOperand(MCOperand::createImm(0));
985     TmpInst.addOperand(MCOperand::createImm(31));
986     Inst = TmpInst;
987     break;
988   }
989   case PPC::SLWI:
990   case PPC::SLWIo: {
991     MCInst TmpInst;
992     int64_t N = Inst.getOperand(2).getImm();
993     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
994     TmpInst.addOperand(Inst.getOperand(0));
995     TmpInst.addOperand(Inst.getOperand(1));
996     TmpInst.addOperand(MCOperand::createImm(N));
997     TmpInst.addOperand(MCOperand::createImm(0));
998     TmpInst.addOperand(MCOperand::createImm(31 - N));
999     Inst = TmpInst;
1000     break;
1001   }
1002   case PPC::SRWI:
1003   case PPC::SRWIo: {
1004     MCInst TmpInst;
1005     int64_t N = Inst.getOperand(2).getImm();
1006     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
1007     TmpInst.addOperand(Inst.getOperand(0));
1008     TmpInst.addOperand(Inst.getOperand(1));
1009     TmpInst.addOperand(MCOperand::createImm(32 - N));
1010     TmpInst.addOperand(MCOperand::createImm(N));
1011     TmpInst.addOperand(MCOperand::createImm(31));
1012     Inst = TmpInst;
1013     break;
1014   }
1015   case PPC::CLRRWI:
1016   case PPC::CLRRWIo: {
1017     MCInst TmpInst;
1018     int64_t N = Inst.getOperand(2).getImm();
1019     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
1020     TmpInst.addOperand(Inst.getOperand(0));
1021     TmpInst.addOperand(Inst.getOperand(1));
1022     TmpInst.addOperand(MCOperand::createImm(0));
1023     TmpInst.addOperand(MCOperand::createImm(0));
1024     TmpInst.addOperand(MCOperand::createImm(31 - N));
1025     Inst = TmpInst;
1026     break;
1027   }
1028   case PPC::CLRLSLWI:
1029   case PPC::CLRLSLWIo: {
1030     MCInst TmpInst;
1031     int64_t B = Inst.getOperand(2).getImm();
1032     int64_t N = Inst.getOperand(3).getImm();
1033     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
1034     TmpInst.addOperand(Inst.getOperand(0));
1035     TmpInst.addOperand(Inst.getOperand(1));
1036     TmpInst.addOperand(MCOperand::createImm(N));
1037     TmpInst.addOperand(MCOperand::createImm(B - N));
1038     TmpInst.addOperand(MCOperand::createImm(31 - N));
1039     Inst = TmpInst;
1040     break;
1041   }
1042   case PPC::EXTLDI:
1043   case PPC::EXTLDIo: {
1044     MCInst TmpInst;
1045     int64_t N = Inst.getOperand(2).getImm();
1046     int64_t B = Inst.getOperand(3).getImm();
1047     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1048     TmpInst.addOperand(Inst.getOperand(0));
1049     TmpInst.addOperand(Inst.getOperand(1));
1050     TmpInst.addOperand(MCOperand::createImm(B));
1051     TmpInst.addOperand(MCOperand::createImm(N - 1));
1052     Inst = TmpInst;
1053     break;
1054   }
1055   case PPC::EXTRDI:
1056   case PPC::EXTRDIo: {
1057     MCInst TmpInst;
1058     int64_t N = Inst.getOperand(2).getImm();
1059     int64_t B = Inst.getOperand(3).getImm();
1060     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1061     TmpInst.addOperand(Inst.getOperand(0));
1062     TmpInst.addOperand(Inst.getOperand(1));
1063     TmpInst.addOperand(MCOperand::createImm(B + N));
1064     TmpInst.addOperand(MCOperand::createImm(64 - N));
1065     Inst = TmpInst;
1066     break;
1067   }
1068   case PPC::INSRDI:
1069   case PPC::INSRDIo: {
1070     MCInst TmpInst;
1071     int64_t N = Inst.getOperand(2).getImm();
1072     int64_t B = Inst.getOperand(3).getImm();
1073     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1074     TmpInst.addOperand(Inst.getOperand(0));
1075     TmpInst.addOperand(Inst.getOperand(0));
1076     TmpInst.addOperand(Inst.getOperand(1));
1077     TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
1078     TmpInst.addOperand(MCOperand::createImm(B));
1079     Inst = TmpInst;
1080     break;
1081   }
1082   case PPC::ROTRDI:
1083   case PPC::ROTRDIo: {
1084     MCInst TmpInst;
1085     int64_t N = Inst.getOperand(2).getImm();
1086     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1087     TmpInst.addOperand(Inst.getOperand(0));
1088     TmpInst.addOperand(Inst.getOperand(1));
1089     TmpInst.addOperand(MCOperand::createImm(64 - N));
1090     TmpInst.addOperand(MCOperand::createImm(0));
1091     Inst = TmpInst;
1092     break;
1093   }
1094   case PPC::SLDI:
1095   case PPC::SLDIo: {
1096     MCInst TmpInst;
1097     int64_t N = Inst.getOperand(2).getImm();
1098     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1099     TmpInst.addOperand(Inst.getOperand(0));
1100     TmpInst.addOperand(Inst.getOperand(1));
1101     TmpInst.addOperand(MCOperand::createImm(N));
1102     TmpInst.addOperand(MCOperand::createImm(63 - N));
1103     Inst = TmpInst;
1104     break;
1105   }
1106   case PPC::SRDI:
1107   case PPC::SRDIo: {
1108     MCInst TmpInst;
1109     int64_t N = Inst.getOperand(2).getImm();
1110     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1111     TmpInst.addOperand(Inst.getOperand(0));
1112     TmpInst.addOperand(Inst.getOperand(1));
1113     TmpInst.addOperand(MCOperand::createImm(64 - N));
1114     TmpInst.addOperand(MCOperand::createImm(N));
1115     Inst = TmpInst;
1116     break;
1117   }
1118   case PPC::CLRRDI:
1119   case PPC::CLRRDIo: {
1120     MCInst TmpInst;
1121     int64_t N = Inst.getOperand(2).getImm();
1122     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1123     TmpInst.addOperand(Inst.getOperand(0));
1124     TmpInst.addOperand(Inst.getOperand(1));
1125     TmpInst.addOperand(MCOperand::createImm(0));
1126     TmpInst.addOperand(MCOperand::createImm(63 - N));
1127     Inst = TmpInst;
1128     break;
1129   }
1130   case PPC::CLRLSLDI:
1131   case PPC::CLRLSLDIo: {
1132     MCInst TmpInst;
1133     int64_t B = Inst.getOperand(2).getImm();
1134     int64_t N = Inst.getOperand(3).getImm();
1135     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1136     TmpInst.addOperand(Inst.getOperand(0));
1137     TmpInst.addOperand(Inst.getOperand(1));
1138     TmpInst.addOperand(MCOperand::createImm(N));
1139     TmpInst.addOperand(MCOperand::createImm(B - N));
1140     Inst = TmpInst;
1141     break;
1142   }
1143   case PPC::RLWINMbm:
1144   case PPC::RLWINMobm: {
1145     unsigned MB, ME;
1146     int64_t BM = Inst.getOperand(3).getImm();
1147     if (!isRunOfOnes(BM, MB, ME))
1148       break;
1149 
1150     MCInst TmpInst;
1151     TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1152     TmpInst.addOperand(Inst.getOperand(0));
1153     TmpInst.addOperand(Inst.getOperand(1));
1154     TmpInst.addOperand(Inst.getOperand(2));
1155     TmpInst.addOperand(MCOperand::createImm(MB));
1156     TmpInst.addOperand(MCOperand::createImm(ME));
1157     Inst = TmpInst;
1158     break;
1159   }
1160   case PPC::RLWIMIbm:
1161   case PPC::RLWIMIobm: {
1162     unsigned MB, ME;
1163     int64_t BM = Inst.getOperand(3).getImm();
1164     if (!isRunOfOnes(BM, MB, ME))
1165       break;
1166 
1167     MCInst TmpInst;
1168     TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1169     TmpInst.addOperand(Inst.getOperand(0));
1170     TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1171     TmpInst.addOperand(Inst.getOperand(1));
1172     TmpInst.addOperand(Inst.getOperand(2));
1173     TmpInst.addOperand(MCOperand::createImm(MB));
1174     TmpInst.addOperand(MCOperand::createImm(ME));
1175     Inst = TmpInst;
1176     break;
1177   }
1178   case PPC::RLWNMbm:
1179   case PPC::RLWNMobm: {
1180     unsigned MB, ME;
1181     int64_t BM = Inst.getOperand(3).getImm();
1182     if (!isRunOfOnes(BM, MB, ME))
1183       break;
1184 
1185     MCInst TmpInst;
1186     TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1187     TmpInst.addOperand(Inst.getOperand(0));
1188     TmpInst.addOperand(Inst.getOperand(1));
1189     TmpInst.addOperand(Inst.getOperand(2));
1190     TmpInst.addOperand(MCOperand::createImm(MB));
1191     TmpInst.addOperand(MCOperand::createImm(ME));
1192     Inst = TmpInst;
1193     break;
1194   }
1195   case PPC::MFTB: {
1196     if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1197       assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1198       Inst.setOpcode(PPC::MFSPR);
1199     }
1200     break;
1201   }
1202   }
1203 }
1204 
1205 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1206                                            OperandVector &Operands,
1207                                            MCStreamer &Out, uint64_t &ErrorInfo,
1208                                            bool MatchingInlineAsm) {
1209   MCInst Inst;
1210 
1211   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1212   case Match_Success:
1213     // Post-process instructions (typically extended mnemonics)
1214     ProcessInstruction(Inst, Operands);
1215     Inst.setLoc(IDLoc);
1216     Out.EmitInstruction(Inst, getSTI());
1217     return false;
1218   case Match_MissingFeature:
1219     return Error(IDLoc, "instruction use requires an option to be enabled");
1220   case Match_MnemonicFail:
1221     return Error(IDLoc, "unrecognized instruction mnemonic");
1222   case Match_InvalidOperand: {
1223     SMLoc ErrorLoc = IDLoc;
1224     if (ErrorInfo != ~0ULL) {
1225       if (ErrorInfo >= Operands.size())
1226         return Error(IDLoc, "too few operands for instruction");
1227 
1228       ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1229       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1230     }
1231 
1232     return Error(ErrorLoc, "invalid operand for instruction");
1233   }
1234   }
1235 
1236   llvm_unreachable("Implement any new match types added!");
1237 }
1238 
1239 bool PPCAsmParser::
1240 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1241   if (Tok.is(AsmToken::Identifier)) {
1242     StringRef Name = Tok.getString();
1243 
1244     if (Name.equals_lower("lr")) {
1245       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1246       IntVal = 8;
1247       return false;
1248     } else if (Name.equals_lower("ctr")) {
1249       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1250       IntVal = 9;
1251       return false;
1252     } else if (Name.equals_lower("vrsave")) {
1253       RegNo = PPC::VRSAVE;
1254       IntVal = 256;
1255       return false;
1256     } else if (Name.startswith_lower("r") &&
1257                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1258       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1259       return false;
1260     } else if (Name.startswith_lower("f") &&
1261                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1262       RegNo = FRegs[IntVal];
1263       return false;
1264     } else if (Name.startswith_lower("vs") &&
1265                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1266       RegNo = VSRegs[IntVal];
1267       return false;
1268     } else if (Name.startswith_lower("v") &&
1269                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1270       RegNo = VRegs[IntVal];
1271       return false;
1272     } else if (Name.startswith_lower("q") &&
1273                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1274       RegNo = QFRegs[IntVal];
1275       return false;
1276     } else if (Name.startswith_lower("cr") &&
1277                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1278       RegNo = CRRegs[IntVal];
1279       return false;
1280     }
1281   }
1282 
1283   return true;
1284 }
1285 
1286 bool PPCAsmParser::
1287 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1288   MCAsmParser &Parser = getParser();
1289   const AsmToken &Tok = Parser.getTok();
1290   StartLoc = Tok.getLoc();
1291   EndLoc = Tok.getEndLoc();
1292   RegNo = 0;
1293   int64_t IntVal;
1294 
1295   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1296     Parser.Lex(); // Eat identifier token.
1297     return false;
1298   }
1299 
1300   return Error(StartLoc, "invalid register name");
1301 }
1302 
1303 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1304 /// the expression and check for VK_PPC_LO/HI/HA
1305 /// symbol variants.  If all symbols with modifier use the same
1306 /// variant, return the corresponding PPCMCExpr::VariantKind,
1307 /// and a modified expression using the default symbol variant.
1308 /// Otherwise, return NULL.
1309 const MCExpr *PPCAsmParser::
1310 ExtractModifierFromExpr(const MCExpr *E,
1311                         PPCMCExpr::VariantKind &Variant) {
1312   MCContext &Context = getParser().getContext();
1313   Variant = PPCMCExpr::VK_PPC_None;
1314 
1315   switch (E->getKind()) {
1316   case MCExpr::Target:
1317   case MCExpr::Constant:
1318     return nullptr;
1319 
1320   case MCExpr::SymbolRef: {
1321     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1322 
1323     switch (SRE->getKind()) {
1324     case MCSymbolRefExpr::VK_PPC_LO:
1325       Variant = PPCMCExpr::VK_PPC_LO;
1326       break;
1327     case MCSymbolRefExpr::VK_PPC_HI:
1328       Variant = PPCMCExpr::VK_PPC_HI;
1329       break;
1330     case MCSymbolRefExpr::VK_PPC_HA:
1331       Variant = PPCMCExpr::VK_PPC_HA;
1332       break;
1333     case MCSymbolRefExpr::VK_PPC_HIGHER:
1334       Variant = PPCMCExpr::VK_PPC_HIGHER;
1335       break;
1336     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1337       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1338       break;
1339     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1340       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1341       break;
1342     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1343       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1344       break;
1345     default:
1346       return nullptr;
1347     }
1348 
1349     return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1350   }
1351 
1352   case MCExpr::Unary: {
1353     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1354     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1355     if (!Sub)
1356       return nullptr;
1357     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1358   }
1359 
1360   case MCExpr::Binary: {
1361     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1362     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1363     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1364     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1365 
1366     if (!LHS && !RHS)
1367       return nullptr;
1368 
1369     if (!LHS) LHS = BE->getLHS();
1370     if (!RHS) RHS = BE->getRHS();
1371 
1372     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1373       Variant = RHSVariant;
1374     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1375       Variant = LHSVariant;
1376     else if (LHSVariant == RHSVariant)
1377       Variant = LHSVariant;
1378     else
1379       return nullptr;
1380 
1381     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1382   }
1383   }
1384 
1385   llvm_unreachable("Invalid expression kind!");
1386 }
1387 
1388 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1389 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1390 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1391 /// FIXME: This is a hack.
1392 const MCExpr *PPCAsmParser::
1393 FixupVariantKind(const MCExpr *E) {
1394   MCContext &Context = getParser().getContext();
1395 
1396   switch (E->getKind()) {
1397   case MCExpr::Target:
1398   case MCExpr::Constant:
1399     return E;
1400 
1401   case MCExpr::SymbolRef: {
1402     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1403     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1404 
1405     switch (SRE->getKind()) {
1406     case MCSymbolRefExpr::VK_TLSGD:
1407       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1408       break;
1409     case MCSymbolRefExpr::VK_TLSLD:
1410       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1411       break;
1412     default:
1413       return E;
1414     }
1415     return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1416   }
1417 
1418   case MCExpr::Unary: {
1419     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1420     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1421     if (Sub == UE->getSubExpr())
1422       return E;
1423     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1424   }
1425 
1426   case MCExpr::Binary: {
1427     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1428     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1429     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1430     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1431       return E;
1432     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1433   }
1434   }
1435 
1436   llvm_unreachable("Invalid expression kind!");
1437 }
1438 
1439 /// ParseExpression.  This differs from the default "parseExpression" in that
1440 /// it handles modifiers.
1441 bool PPCAsmParser::
1442 ParseExpression(const MCExpr *&EVal) {
1443 
1444   if (isDarwin())
1445     return ParseDarwinExpression(EVal);
1446 
1447   // (ELF Platforms)
1448   // Handle \code @l/@ha \endcode
1449   if (getParser().parseExpression(EVal))
1450     return true;
1451 
1452   EVal = FixupVariantKind(EVal);
1453 
1454   PPCMCExpr::VariantKind Variant;
1455   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1456   if (E)
1457     EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext());
1458 
1459   return false;
1460 }
1461 
1462 /// ParseDarwinExpression.  (MachO Platforms)
1463 /// This differs from the default "parseExpression" in that it handles detection
1464 /// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1465 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1466 /// syntax form so it is done here.  TODO: Determine if there is merit in arranging
1467 /// for this to be done at a higher level.
1468 bool PPCAsmParser::
1469 ParseDarwinExpression(const MCExpr *&EVal) {
1470   MCAsmParser &Parser = getParser();
1471   PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1472   switch (getLexer().getKind()) {
1473   default:
1474     break;
1475   case AsmToken::Identifier:
1476     // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1477     // something starting with any other char should be part of the
1478     // asm syntax.  If handwritten asm includes an identifier like lo16,
1479     // then all bets are off - but no-one would do that, right?
1480     StringRef poss = Parser.getTok().getString();
1481     if (poss.equals_lower("lo16")) {
1482       Variant = PPCMCExpr::VK_PPC_LO;
1483     } else if (poss.equals_lower("hi16")) {
1484       Variant = PPCMCExpr::VK_PPC_HI;
1485     } else if (poss.equals_lower("ha16")) {
1486       Variant = PPCMCExpr::VK_PPC_HA;
1487     }
1488     if (Variant != PPCMCExpr::VK_PPC_None) {
1489       Parser.Lex(); // Eat the xx16
1490       if (getLexer().isNot(AsmToken::LParen))
1491         return Error(Parser.getTok().getLoc(), "expected '('");
1492       Parser.Lex(); // Eat the '('
1493     }
1494     break;
1495   }
1496 
1497   if (getParser().parseExpression(EVal))
1498     return true;
1499 
1500   if (Variant != PPCMCExpr::VK_PPC_None) {
1501     if (getLexer().isNot(AsmToken::RParen))
1502       return Error(Parser.getTok().getLoc(), "expected ')'");
1503     Parser.Lex(); // Eat the ')'
1504     EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext());
1505   }
1506   return false;
1507 }
1508 
1509 /// ParseOperand
1510 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1511 /// rNN for MachO.
1512 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1513   MCAsmParser &Parser = getParser();
1514   SMLoc S = Parser.getTok().getLoc();
1515   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1516   const MCExpr *EVal;
1517 
1518   // Attempt to parse the next token as an immediate
1519   switch (getLexer().getKind()) {
1520   // Special handling for register names.  These are interpreted
1521   // as immediates corresponding to the register number.
1522   case AsmToken::Percent:
1523     Parser.Lex(); // Eat the '%'.
1524     unsigned RegNo;
1525     int64_t IntVal;
1526     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1527       Parser.Lex(); // Eat the identifier token.
1528       Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1529       return false;
1530     }
1531     return Error(S, "invalid register name");
1532 
1533   case AsmToken::Identifier:
1534     // Note that non-register-name identifiers from the compiler will begin
1535     // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1536     // identifiers like r31foo - so we fall through in the event that parsing
1537     // a register name fails.
1538     if (isDarwin()) {
1539       unsigned RegNo;
1540       int64_t IntVal;
1541       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1542         Parser.Lex(); // Eat the identifier token.
1543         Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1544         return false;
1545       }
1546     }
1547   // Fall-through to process non-register-name identifiers as expression.
1548   // All other expressions
1549   case AsmToken::LParen:
1550   case AsmToken::Plus:
1551   case AsmToken::Minus:
1552   case AsmToken::Integer:
1553   case AsmToken::Dot:
1554   case AsmToken::Dollar:
1555   case AsmToken::Exclaim:
1556   case AsmToken::Tilde:
1557     if (!ParseExpression(EVal))
1558       break;
1559     /* fall through */
1560   default:
1561     return Error(S, "unknown operand");
1562   }
1563 
1564   // Push the parsed operand into the list of operands
1565   Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1566 
1567   // Check whether this is a TLS call expression
1568   bool TLSCall = false;
1569   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1570     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1571 
1572   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1573     const MCExpr *TLSSym;
1574 
1575     Parser.Lex(); // Eat the '('.
1576     S = Parser.getTok().getLoc();
1577     if (ParseExpression(TLSSym))
1578       return Error(S, "invalid TLS call expression");
1579     if (getLexer().isNot(AsmToken::RParen))
1580       return Error(Parser.getTok().getLoc(), "missing ')'");
1581     E = Parser.getTok().getLoc();
1582     Parser.Lex(); // Eat the ')'.
1583 
1584     Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1585   }
1586 
1587   // Otherwise, check for D-form memory operands
1588   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1589     Parser.Lex(); // Eat the '('.
1590     S = Parser.getTok().getLoc();
1591 
1592     int64_t IntVal;
1593     switch (getLexer().getKind()) {
1594     case AsmToken::Percent:
1595       Parser.Lex(); // Eat the '%'.
1596       unsigned RegNo;
1597       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1598         return Error(S, "invalid register name");
1599       Parser.Lex(); // Eat the identifier token.
1600       break;
1601 
1602     case AsmToken::Integer:
1603       if (!isDarwin()) {
1604         if (getParser().parseAbsoluteExpression(IntVal) ||
1605           IntVal < 0 || IntVal > 31)
1606         return Error(S, "invalid register number");
1607       } else {
1608         return Error(S, "unexpected integer value");
1609       }
1610       break;
1611 
1612    case AsmToken::Identifier:
1613     if (isDarwin()) {
1614       unsigned RegNo;
1615       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1616         Parser.Lex(); // Eat the identifier token.
1617         break;
1618       }
1619     }
1620     // Fall-through..
1621 
1622     default:
1623       return Error(S, "invalid memory operand");
1624     }
1625 
1626     if (getLexer().isNot(AsmToken::RParen))
1627       return Error(Parser.getTok().getLoc(), "missing ')'");
1628     E = Parser.getTok().getLoc();
1629     Parser.Lex(); // Eat the ')'.
1630 
1631     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1632   }
1633 
1634   return false;
1635 }
1636 
1637 /// Parse an instruction mnemonic followed by its operands.
1638 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1639                                     SMLoc NameLoc, OperandVector &Operands) {
1640   // The first operand is the token for the instruction name.
1641   // If the next character is a '+' or '-', we need to add it to the
1642   // instruction name, to match what TableGen is doing.
1643   std::string NewOpcode;
1644   if (getLexer().is(AsmToken::Plus)) {
1645     getLexer().Lex();
1646     NewOpcode = Name;
1647     NewOpcode += '+';
1648     Name = NewOpcode;
1649   }
1650   if (getLexer().is(AsmToken::Minus)) {
1651     getLexer().Lex();
1652     NewOpcode = Name;
1653     NewOpcode += '-';
1654     Name = NewOpcode;
1655   }
1656   // If the instruction ends in a '.', we need to create a separate
1657   // token for it, to match what TableGen is doing.
1658   size_t Dot = Name.find('.');
1659   StringRef Mnemonic = Name.slice(0, Dot);
1660   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1661     Operands.push_back(
1662         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1663   else
1664     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1665   if (Dot != StringRef::npos) {
1666     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1667     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1668     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1669       Operands.push_back(
1670           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1671     else
1672       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1673   }
1674 
1675   // If there are no more operands then finish
1676   if (getLexer().is(AsmToken::EndOfStatement))
1677     return false;
1678 
1679   // Parse the first operand
1680   if (ParseOperand(Operands))
1681     return true;
1682 
1683   while (getLexer().isNot(AsmToken::EndOfStatement) &&
1684          getLexer().is(AsmToken::Comma)) {
1685     // Consume the comma token
1686     getLexer().Lex();
1687 
1688     // Parse the next operand
1689     if (ParseOperand(Operands))
1690       return true;
1691   }
1692 
1693   // We'll now deal with an unfortunate special case: the syntax for the dcbt
1694   // and dcbtst instructions differs for server vs. embedded cores.
1695   //  The syntax for dcbt is:
1696   //    dcbt ra, rb, th [server]
1697   //    dcbt th, ra, rb [embedded]
1698   //  where th can be omitted when it is 0. dcbtst is the same. We take the
1699   //  server form to be the default, so swap the operands if we're parsing for
1700   //  an embedded core (they'll be swapped again upon printing).
1701   if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1702       Operands.size() == 4 &&
1703       (Name == "dcbt" || Name == "dcbtst")) {
1704     std::swap(Operands[1], Operands[3]);
1705     std::swap(Operands[2], Operands[1]);
1706   }
1707 
1708   return false;
1709 }
1710 
1711 /// ParseDirective parses the PPC specific directives
1712 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1713   StringRef IDVal = DirectiveID.getIdentifier();
1714   if (!isDarwin()) {
1715     if (IDVal == ".word")
1716       return ParseDirectiveWord(2, DirectiveID.getLoc());
1717     if (IDVal == ".llong")
1718       return ParseDirectiveWord(8, DirectiveID.getLoc());
1719     if (IDVal == ".tc")
1720       return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1721     if (IDVal == ".machine")
1722       return ParseDirectiveMachine(DirectiveID.getLoc());
1723     if (IDVal == ".abiversion")
1724       return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1725     if (IDVal == ".localentry")
1726       return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1727   } else {
1728     if (IDVal == ".machine")
1729       return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1730   }
1731   return true;
1732 }
1733 
1734 /// ParseDirectiveWord
1735 ///  ::= .word [ expression (, expression)* ]
1736 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1737   MCAsmParser &Parser = getParser();
1738   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1739     for (;;) {
1740       const MCExpr *Value;
1741       SMLoc ExprLoc = getLexer().getLoc();
1742       if (getParser().parseExpression(Value))
1743         return false;
1744 
1745       if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1746         assert(Size <= 8 && "Invalid size");
1747         uint64_t IntValue = MCE->getValue();
1748         if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
1749           return Error(ExprLoc, "literal value out of range for directive");
1750         getStreamer().EmitIntValue(IntValue, Size);
1751       } else {
1752         getStreamer().EmitValue(Value, Size, ExprLoc);
1753       }
1754 
1755       if (getLexer().is(AsmToken::EndOfStatement))
1756         break;
1757 
1758       if (getLexer().isNot(AsmToken::Comma))
1759         return Error(L, "unexpected token in directive");
1760       Parser.Lex();
1761     }
1762   }
1763 
1764   Parser.Lex();
1765   return false;
1766 }
1767 
1768 /// ParseDirectiveTC
1769 ///  ::= .tc [ symbol (, expression)* ]
1770 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1771   MCAsmParser &Parser = getParser();
1772   // Skip TC symbol, which is only used with XCOFF.
1773   while (getLexer().isNot(AsmToken::EndOfStatement)
1774          && getLexer().isNot(AsmToken::Comma))
1775     Parser.Lex();
1776   if (getLexer().isNot(AsmToken::Comma)) {
1777     Error(L, "unexpected token in directive");
1778     return false;
1779   }
1780   Parser.Lex();
1781 
1782   // Align to word size.
1783   getParser().getStreamer().EmitValueToAlignment(Size);
1784 
1785   // Emit expressions.
1786   return ParseDirectiveWord(Size, L);
1787 }
1788 
1789 /// ParseDirectiveMachine (ELF platforms)
1790 ///  ::= .machine [ cpu | "push" | "pop" ]
1791 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1792   MCAsmParser &Parser = getParser();
1793   if (getLexer().isNot(AsmToken::Identifier) &&
1794       getLexer().isNot(AsmToken::String)) {
1795     Error(L, "unexpected token in directive");
1796     return false;
1797   }
1798 
1799   StringRef CPU = Parser.getTok().getIdentifier();
1800   Parser.Lex();
1801 
1802   // FIXME: Right now, the parser always allows any available
1803   // instruction, so the .machine directive is not useful.
1804   // Implement ".machine any" (by doing nothing) for the benefit
1805   // of existing assembler code.  Likewise, we can then implement
1806   // ".machine push" and ".machine pop" as no-op.
1807   if (CPU != "any" && CPU != "push" && CPU != "pop") {
1808     Error(L, "unrecognized machine type");
1809     return false;
1810   }
1811 
1812   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1813     Error(L, "unexpected token in directive");
1814     return false;
1815   }
1816   PPCTargetStreamer &TStreamer =
1817       *static_cast<PPCTargetStreamer *>(
1818            getParser().getStreamer().getTargetStreamer());
1819   TStreamer.emitMachine(CPU);
1820 
1821   return false;
1822 }
1823 
1824 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1825 ///  ::= .machine cpu-identifier
1826 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1827   MCAsmParser &Parser = getParser();
1828   if (getLexer().isNot(AsmToken::Identifier) &&
1829       getLexer().isNot(AsmToken::String)) {
1830     Error(L, "unexpected token in directive");
1831     return false;
1832   }
1833 
1834   StringRef CPU = Parser.getTok().getIdentifier();
1835   Parser.Lex();
1836 
1837   // FIXME: this is only the 'default' set of cpu variants.
1838   // However we don't act on this information at present, this is simply
1839   // allowing parsing to proceed with minimal sanity checking.
1840   if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1841     Error(L, "unrecognized cpu type");
1842     return false;
1843   }
1844 
1845   if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1846     Error(L, "wrong cpu type specified for 64bit");
1847     return false;
1848   }
1849   if (!isPPC64() && CPU == "ppc64") {
1850     Error(L, "wrong cpu type specified for 32bit");
1851     return false;
1852   }
1853 
1854   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1855     Error(L, "unexpected token in directive");
1856     return false;
1857   }
1858 
1859   return false;
1860 }
1861 
1862 /// ParseDirectiveAbiVersion
1863 ///  ::= .abiversion constant-expression
1864 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1865   int64_t AbiVersion;
1866   if (getParser().parseAbsoluteExpression(AbiVersion)){
1867     Error(L, "expected constant expression");
1868     return false;
1869   }
1870   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1871     Error(L, "unexpected token in directive");
1872     return false;
1873   }
1874 
1875   PPCTargetStreamer &TStreamer =
1876       *static_cast<PPCTargetStreamer *>(
1877            getParser().getStreamer().getTargetStreamer());
1878   TStreamer.emitAbiVersion(AbiVersion);
1879 
1880   return false;
1881 }
1882 
1883 /// ParseDirectiveLocalEntry
1884 ///  ::= .localentry symbol, expression
1885 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1886   StringRef Name;
1887   if (getParser().parseIdentifier(Name)) {
1888     Error(L, "expected identifier in directive");
1889     return false;
1890   }
1891   MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1892 
1893   if (getLexer().isNot(AsmToken::Comma)) {
1894     Error(L, "unexpected token in directive");
1895     return false;
1896   }
1897   Lex();
1898 
1899   const MCExpr *Expr;
1900   if (getParser().parseExpression(Expr)) {
1901     Error(L, "expected expression");
1902     return false;
1903   }
1904 
1905   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1906     Error(L, "unexpected token in directive");
1907     return false;
1908   }
1909 
1910   PPCTargetStreamer &TStreamer =
1911       *static_cast<PPCTargetStreamer *>(
1912            getParser().getStreamer().getTargetStreamer());
1913   TStreamer.emitLocalEntry(Sym, Expr);
1914 
1915   return false;
1916 }
1917 
1918 
1919 
1920 /// Force static initialization.
1921 extern "C" void LLVMInitializePowerPCAsmParser() {
1922   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1923   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1924   RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1925 }
1926 
1927 #define GET_REGISTER_MATCHER
1928 #define GET_MATCHER_IMPLEMENTATION
1929 #include "PPCGenAsmMatcher.inc"
1930 
1931 // Define this matcher function after the auto-generated include so we
1932 // have the match class enum definitions.
1933 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1934                                                   unsigned Kind) {
1935   // If the kind is a token for a literal immediate, check if our asm
1936   // operand matches. This is for InstAliases which have a fixed-value
1937   // immediate in the syntax.
1938   int64_t ImmVal;
1939   switch (Kind) {
1940     case MCK_0: ImmVal = 0; break;
1941     case MCK_1: ImmVal = 1; break;
1942     case MCK_2: ImmVal = 2; break;
1943     case MCK_3: ImmVal = 3; break;
1944     case MCK_4: ImmVal = 4; break;
1945     case MCK_5: ImmVal = 5; break;
1946     case MCK_6: ImmVal = 6; break;
1947     case MCK_7: ImmVal = 7; break;
1948     default: return Match_InvalidOperand;
1949   }
1950 
1951   PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1952   if (Op.isImm() && Op.getImm() == ImmVal)
1953     return Match_Success;
1954 
1955   return Match_InvalidOperand;
1956 }
1957 
1958 const MCExpr *
1959 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1960                                   MCSymbolRefExpr::VariantKind Variant,
1961                                   MCContext &Ctx) {
1962   switch (Variant) {
1963   case MCSymbolRefExpr::VK_PPC_LO:
1964     return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1965   case MCSymbolRefExpr::VK_PPC_HI:
1966     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1967   case MCSymbolRefExpr::VK_PPC_HA:
1968     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1969   case MCSymbolRefExpr::VK_PPC_HIGHER:
1970     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1971   case MCSymbolRefExpr::VK_PPC_HIGHERA:
1972     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1973   case MCSymbolRefExpr::VK_PPC_HIGHEST:
1974     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1975   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1976     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1977   default:
1978     return nullptr;
1979   }
1980 }
1981