xref: /llvm-project/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (revision 6e9110abe923569e8abdf17f63658851e2f46ae3) 
1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCTargetAsmParser.h"
29 #include "llvm/Support/SourceMgr.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
32 
33 using namespace llvm;
34 
35 static const MCPhysReg RRegs[32] = {
36   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
37   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
38   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
39   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
40   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
41   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
42   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
43   PPC::R28, PPC::R29, PPC::R30, PPC::R31
44 };
45 static const MCPhysReg RRegsNoR0[32] = {
46   PPC::ZERO,
47             PPC::R1,  PPC::R2,  PPC::R3,
48   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
49   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
50   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
51   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
52   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
53   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
54   PPC::R28, PPC::R29, PPC::R30, PPC::R31
55 };
56 static const MCPhysReg XRegs[32] = {
57   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
58   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
59   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
60   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
61   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
62   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
63   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
64   PPC::X28, PPC::X29, PPC::X30, PPC::X31
65 };
66 static const MCPhysReg XRegsNoX0[32] = {
67   PPC::ZERO8,
68             PPC::X1,  PPC::X2,  PPC::X3,
69   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
70   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
71   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
72   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
73   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
74   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
75   PPC::X28, PPC::X29, PPC::X30, PPC::X31
76 };
77 static const MCPhysReg FRegs[32] = {
78   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
79   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
80   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
81   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
82   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
83   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
84   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
85   PPC::F28, PPC::F29, PPC::F30, PPC::F31
86 };
87 static const MCPhysReg VRegs[32] = {
88   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
89   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
90   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
91   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
92   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
93   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
94   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
95   PPC::V28, PPC::V29, PPC::V30, PPC::V31
96 };
97 static const MCPhysReg VSRegs[64] = {
98   PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
99   PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
100   PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
101   PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
102   PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
103   PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
104   PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
105   PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
106 
107   PPC::VSH0,  PPC::VSH1,  PPC::VSH2,  PPC::VSH3,
108   PPC::VSH4,  PPC::VSH5,  PPC::VSH6,  PPC::VSH7,
109   PPC::VSH8,  PPC::VSH9,  PPC::VSH10, PPC::VSH11,
110   PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
111   PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
112   PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
113   PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
114   PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
115 };
116 static const MCPhysReg VSFRegs[64] = {
117   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
118   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
119   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
120   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
121   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
122   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
123   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
124   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
125 
126   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
127   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
128   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
129   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
130   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
131   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
132   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
133   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
134 };
135 static unsigned QFRegs[32] = {
136   PPC::QF0,  PPC::QF1,  PPC::QF2,  PPC::QF3,
137   PPC::QF4,  PPC::QF5,  PPC::QF6,  PPC::QF7,
138   PPC::QF8,  PPC::QF9,  PPC::QF10, PPC::QF11,
139   PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
140   PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
141   PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
142   PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
143   PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
144 };
145 static const MCPhysReg CRBITRegs[32] = {
146   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
147   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
148   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
149   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
150   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
151   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
152   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
153   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
154 };
155 static const MCPhysReg CRRegs[8] = {
156   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
157   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
158 };
159 
160 // Evaluate an expression containing condition register
161 // or condition register field symbols.  Returns positive
162 // value on success, or -1 on error.
163 static int64_t
164 EvaluateCRExpr(const MCExpr *E) {
165   switch (E->getKind()) {
166   case MCExpr::Target:
167     return -1;
168 
169   case MCExpr::Constant: {
170     int64_t Res = cast<MCConstantExpr>(E)->getValue();
171     return Res < 0 ? -1 : Res;
172   }
173 
174   case MCExpr::SymbolRef: {
175     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
176     StringRef Name = SRE->getSymbol().getName();
177 
178     if (Name == "lt") return 0;
179     if (Name == "gt") return 1;
180     if (Name == "eq") return 2;
181     if (Name == "so") return 3;
182     if (Name == "un") return 3;
183 
184     if (Name == "cr0") return 0;
185     if (Name == "cr1") return 1;
186     if (Name == "cr2") return 2;
187     if (Name == "cr3") return 3;
188     if (Name == "cr4") return 4;
189     if (Name == "cr5") return 5;
190     if (Name == "cr6") return 6;
191     if (Name == "cr7") return 7;
192 
193     return -1;
194   }
195 
196   case MCExpr::Unary:
197     return -1;
198 
199   case MCExpr::Binary: {
200     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
201     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
202     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
203     int64_t Res;
204 
205     if (LHSVal < 0 || RHSVal < 0)
206       return -1;
207 
208     switch (BE->getOpcode()) {
209     default: return -1;
210     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
211     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
212     }
213 
214     return Res < 0 ? -1 : Res;
215   }
216   }
217 
218   llvm_unreachable("Invalid expression kind!");
219 }
220 
221 namespace {
222 
223 struct PPCOperand;
224 
225 class PPCAsmParser : public MCTargetAsmParser {
226   MCSubtargetInfo &STI;
227   const MCInstrInfo &MII;
228   bool IsPPC64;
229   bool IsDarwin;
230 
231   void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
232   bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
233 
234   bool isPPC64() const { return IsPPC64; }
235   bool isDarwin() const { return IsDarwin; }
236 
237   bool MatchRegisterName(const AsmToken &Tok,
238                          unsigned &RegNo, int64_t &IntVal);
239 
240   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
241 
242   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
243                                         PPCMCExpr::VariantKind &Variant);
244   const MCExpr *FixupVariantKind(const MCExpr *E);
245   bool ParseExpression(const MCExpr *&EVal);
246   bool ParseDarwinExpression(const MCExpr *&EVal);
247 
248   bool ParseOperand(OperandVector &Operands);
249 
250   bool ParseDirectiveWord(unsigned Size, SMLoc L);
251   bool ParseDirectiveTC(unsigned Size, SMLoc L);
252   bool ParseDirectiveMachine(SMLoc L);
253   bool ParseDarwinDirectiveMachine(SMLoc L);
254   bool ParseDirectiveAbiVersion(SMLoc L);
255   bool ParseDirectiveLocalEntry(SMLoc L);
256 
257   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
258                                OperandVector &Operands, MCStreamer &Out,
259                                uint64_t &ErrorInfo,
260                                bool MatchingInlineAsm) override;
261 
262   void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
263 
264   /// @name Auto-generated Match Functions
265   /// {
266 
267 #define GET_ASSEMBLER_HEADER
268 #include "PPCGenAsmMatcher.inc"
269 
270   /// }
271 
272 
273 public:
274   PPCAsmParser(MCSubtargetInfo &STI, MCAsmParser &, const MCInstrInfo &MII,
275                const MCTargetOptions &Options)
276       : MCTargetAsmParser(), STI(STI), MII(MII) {
277     // Check for 64-bit vs. 32-bit pointer mode.
278     Triple TheTriple(STI.getTargetTriple());
279     IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
280                TheTriple.getArch() == Triple::ppc64le);
281     IsDarwin = TheTriple.isMacOSX();
282     // Initialize the set of available features.
283     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
284   }
285 
286   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
287                         SMLoc NameLoc, OperandVector &Operands) override;
288 
289   bool ParseDirective(AsmToken DirectiveID) override;
290 
291   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
292                                       unsigned Kind) override;
293 
294   const MCExpr *applyModifierToExpr(const MCExpr *E,
295                                     MCSymbolRefExpr::VariantKind,
296                                     MCContext &Ctx) override;
297 };
298 
299 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
300 /// instruction.
301 struct PPCOperand : public MCParsedAsmOperand {
302   enum KindTy {
303     Token,
304     Immediate,
305     ContextImmediate,
306     Expression,
307     TLSRegister
308   } Kind;
309 
310   SMLoc StartLoc, EndLoc;
311   bool IsPPC64;
312 
313   struct TokOp {
314     const char *Data;
315     unsigned Length;
316   };
317 
318   struct ImmOp {
319     int64_t Val;
320   };
321 
322   struct ExprOp {
323     const MCExpr *Val;
324     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
325   };
326 
327   struct TLSRegOp {
328     const MCSymbolRefExpr *Sym;
329   };
330 
331   union {
332     struct TokOp Tok;
333     struct ImmOp Imm;
334     struct ExprOp Expr;
335     struct TLSRegOp TLSReg;
336   };
337 
338   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
339 public:
340   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
341     Kind = o.Kind;
342     StartLoc = o.StartLoc;
343     EndLoc = o.EndLoc;
344     IsPPC64 = o.IsPPC64;
345     switch (Kind) {
346     case Token:
347       Tok = o.Tok;
348       break;
349     case Immediate:
350     case ContextImmediate:
351       Imm = o.Imm;
352       break;
353     case Expression:
354       Expr = o.Expr;
355       break;
356     case TLSRegister:
357       TLSReg = o.TLSReg;
358       break;
359     }
360   }
361 
362   /// getStartLoc - Get the location of the first token of this operand.
363   SMLoc getStartLoc() const override { return StartLoc; }
364 
365   /// getEndLoc - Get the location of the last token of this operand.
366   SMLoc getEndLoc() const override { return EndLoc; }
367 
368   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
369   bool isPPC64() const { return IsPPC64; }
370 
371   int64_t getImm() const {
372     assert(Kind == Immediate && "Invalid access!");
373     return Imm.Val;
374   }
375   int64_t getImmS16Context() const {
376     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
377     if (Kind == Immediate)
378       return Imm.Val;
379     return static_cast<int16_t>(Imm.Val);
380   }
381   int64_t getImmU16Context() const {
382     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
383     return Imm.Val;
384   }
385 
386   const MCExpr *getExpr() const {
387     assert(Kind == Expression && "Invalid access!");
388     return Expr.Val;
389   }
390 
391   int64_t getExprCRVal() const {
392     assert(Kind == Expression && "Invalid access!");
393     return Expr.CRVal;
394   }
395 
396   const MCExpr *getTLSReg() const {
397     assert(Kind == TLSRegister && "Invalid access!");
398     return TLSReg.Sym;
399   }
400 
401   unsigned getReg() const override {
402     assert(isRegNumber() && "Invalid access!");
403     return (unsigned) Imm.Val;
404   }
405 
406   unsigned getVSReg() const {
407     assert(isVSRegNumber() && "Invalid access!");
408     return (unsigned) Imm.Val;
409   }
410 
411   unsigned getCCReg() const {
412     assert(isCCRegNumber() && "Invalid access!");
413     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
414   }
415 
416   unsigned getCRBit() const {
417     assert(isCRBitNumber() && "Invalid access!");
418     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
419   }
420 
421   unsigned getCRBitMask() const {
422     assert(isCRBitMask() && "Invalid access!");
423     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
424   }
425 
426   bool isToken() const override { return Kind == Token; }
427   bool isImm() const override { return Kind == Immediate || Kind == Expression; }
428   bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
429   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
430   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
431   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
432   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
433   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
434   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
435   bool isU6ImmX2() const { return Kind == Immediate &&
436                                   isUInt<6>(getImm()) &&
437                                   (getImm() & 1) == 0; }
438   bool isU7ImmX4() const { return Kind == Immediate &&
439                                   isUInt<7>(getImm()) &&
440                                   (getImm() & 3) == 0; }
441   bool isU8ImmX8() const { return Kind == Immediate &&
442                                   isUInt<8>(getImm()) &&
443                                   (getImm() & 7) == 0; }
444   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
445   bool isU16Imm() const {
446     switch (Kind) {
447       case Expression:
448         return true;
449       case Immediate:
450       case ContextImmediate:
451         return isUInt<16>(getImmU16Context());
452       default:
453         return false;
454     }
455   }
456   bool isS16Imm() const {
457     switch (Kind) {
458       case Expression:
459         return true;
460       case Immediate:
461       case ContextImmediate:
462         return isInt<16>(getImmS16Context());
463       default:
464         return false;
465     }
466   }
467   bool isS16ImmX4() const { return Kind == Expression ||
468                                    (Kind == Immediate && isInt<16>(getImm()) &&
469                                     (getImm() & 3) == 0); }
470   bool isS17Imm() const {
471     switch (Kind) {
472       case Expression:
473         return true;
474       case Immediate:
475       case ContextImmediate:
476         return isInt<17>(getImmS16Context());
477       default:
478         return false;
479     }
480   }
481   bool isTLSReg() const { return Kind == TLSRegister; }
482   bool isDirectBr() const {
483     if (Kind == Expression)
484       return true;
485     if (Kind != Immediate)
486       return false;
487     // Operand must be 64-bit aligned, signed 27-bit immediate.
488     if ((getImm() & 3) != 0)
489       return false;
490     if (isInt<26>(getImm()))
491       return true;
492     if (!IsPPC64) {
493       // In 32-bit mode, large 32-bit quantities wrap around.
494       if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
495         return true;
496     }
497     return false;
498   }
499   bool isCondBr() const { return Kind == Expression ||
500                                  (Kind == Immediate && isInt<16>(getImm()) &&
501                                   (getImm() & 3) == 0); }
502   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
503   bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
504   bool isCCRegNumber() const { return (Kind == Expression
505                                        && isUInt<3>(getExprCRVal())) ||
506                                       (Kind == Immediate
507                                        && isUInt<3>(getImm())); }
508   bool isCRBitNumber() const { return (Kind == Expression
509                                        && isUInt<5>(getExprCRVal())) ||
510                                       (Kind == Immediate
511                                        && isUInt<5>(getImm())); }
512   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
513                                     isPowerOf2_32(getImm()); }
514   bool isMem() const override { return false; }
515   bool isReg() const override { return false; }
516 
517   void addRegOperands(MCInst &Inst, unsigned N) const {
518     llvm_unreachable("addRegOperands");
519   }
520 
521   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
522     assert(N == 1 && "Invalid number of operands!");
523     Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
524   }
525 
526   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
527     assert(N == 1 && "Invalid number of operands!");
528     Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
529   }
530 
531   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
532     assert(N == 1 && "Invalid number of operands!");
533     Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
534   }
535 
536   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
537     assert(N == 1 && "Invalid number of operands!");
538     Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
539   }
540 
541   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
542     if (isPPC64())
543       addRegG8RCOperands(Inst, N);
544     else
545       addRegGPRCOperands(Inst, N);
546   }
547 
548   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
549     if (isPPC64())
550       addRegG8RCNoX0Operands(Inst, N);
551     else
552       addRegGPRCNoR0Operands(Inst, N);
553   }
554 
555   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
556     assert(N == 1 && "Invalid number of operands!");
557     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
558   }
559 
560   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
561     assert(N == 1 && "Invalid number of operands!");
562     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
563   }
564 
565   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
566     assert(N == 1 && "Invalid number of operands!");
567     Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
568   }
569 
570   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
571     assert(N == 1 && "Invalid number of operands!");
572     Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
573   }
574 
575   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
576     assert(N == 1 && "Invalid number of operands!");
577     Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
578   }
579 
580   void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
581     assert(N == 1 && "Invalid number of operands!");
582     Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
583   }
584 
585   void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
586     assert(N == 1 && "Invalid number of operands!");
587     Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
588   }
589 
590   void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
591     assert(N == 1 && "Invalid number of operands!");
592     Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
593   }
594 
595   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
596     assert(N == 1 && "Invalid number of operands!");
597     Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
598   }
599 
600   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
601     assert(N == 1 && "Invalid number of operands!");
602     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
603   }
604 
605   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
606     assert(N == 1 && "Invalid number of operands!");
607     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
608   }
609 
610   void addImmOperands(MCInst &Inst, unsigned N) const {
611     assert(N == 1 && "Invalid number of operands!");
612     if (Kind == Immediate)
613       Inst.addOperand(MCOperand::CreateImm(getImm()));
614     else
615       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
616   }
617 
618   void addS16ImmOperands(MCInst &Inst, unsigned N) const {
619     assert(N == 1 && "Invalid number of operands!");
620     switch (Kind) {
621       case Immediate:
622         Inst.addOperand(MCOperand::CreateImm(getImm()));
623         break;
624       case ContextImmediate:
625         Inst.addOperand(MCOperand::CreateImm(getImmS16Context()));
626         break;
627       default:
628         Inst.addOperand(MCOperand::CreateExpr(getExpr()));
629         break;
630     }
631   }
632 
633   void addU16ImmOperands(MCInst &Inst, unsigned N) const {
634     assert(N == 1 && "Invalid number of operands!");
635     switch (Kind) {
636       case Immediate:
637         Inst.addOperand(MCOperand::CreateImm(getImm()));
638         break;
639       case ContextImmediate:
640         Inst.addOperand(MCOperand::CreateImm(getImmU16Context()));
641         break;
642       default:
643         Inst.addOperand(MCOperand::CreateExpr(getExpr()));
644         break;
645     }
646   }
647 
648   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
649     assert(N == 1 && "Invalid number of operands!");
650     if (Kind == Immediate)
651       Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
652     else
653       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
654   }
655 
656   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
657     assert(N == 1 && "Invalid number of operands!");
658     Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
659   }
660 
661   StringRef getToken() const {
662     assert(Kind == Token && "Invalid access!");
663     return StringRef(Tok.Data, Tok.Length);
664   }
665 
666   void print(raw_ostream &OS) const override;
667 
668   static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
669                                                  bool IsPPC64) {
670     auto Op = make_unique<PPCOperand>(Token);
671     Op->Tok.Data = Str.data();
672     Op->Tok.Length = Str.size();
673     Op->StartLoc = S;
674     Op->EndLoc = S;
675     Op->IsPPC64 = IsPPC64;
676     return Op;
677   }
678 
679   static std::unique_ptr<PPCOperand>
680   CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
681     // Allocate extra memory for the string and copy it.
682     // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
683     // deleter which will destroy them by simply using "delete", not correctly
684     // calling operator delete on this extra memory after calling the dtor
685     // explicitly.
686     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
687     std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
688     Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
689     Op->Tok.Length = Str.size();
690     std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
691     Op->StartLoc = S;
692     Op->EndLoc = S;
693     Op->IsPPC64 = IsPPC64;
694     return Op;
695   }
696 
697   static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
698                                                bool IsPPC64) {
699     auto Op = make_unique<PPCOperand>(Immediate);
700     Op->Imm.Val = Val;
701     Op->StartLoc = S;
702     Op->EndLoc = E;
703     Op->IsPPC64 = IsPPC64;
704     return Op;
705   }
706 
707   static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
708                                                 SMLoc E, bool IsPPC64) {
709     auto Op = make_unique<PPCOperand>(Expression);
710     Op->Expr.Val = Val;
711     Op->Expr.CRVal = EvaluateCRExpr(Val);
712     Op->StartLoc = S;
713     Op->EndLoc = E;
714     Op->IsPPC64 = IsPPC64;
715     return Op;
716   }
717 
718   static std::unique_ptr<PPCOperand>
719   CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
720     auto Op = make_unique<PPCOperand>(TLSRegister);
721     Op->TLSReg.Sym = Sym;
722     Op->StartLoc = S;
723     Op->EndLoc = E;
724     Op->IsPPC64 = IsPPC64;
725     return Op;
726   }
727 
728   static std::unique_ptr<PPCOperand>
729   CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
730     auto Op = make_unique<PPCOperand>(ContextImmediate);
731     Op->Imm.Val = Val;
732     Op->StartLoc = S;
733     Op->EndLoc = E;
734     Op->IsPPC64 = IsPPC64;
735     return Op;
736   }
737 
738   static std::unique_ptr<PPCOperand>
739   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
740     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
741       return CreateImm(CE->getValue(), S, E, IsPPC64);
742 
743     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
744       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
745         return CreateTLSReg(SRE, S, E, IsPPC64);
746 
747     if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
748       int64_t Res;
749       if (TE->EvaluateAsConstant(Res))
750         return CreateContextImm(Res, S, E, IsPPC64);
751     }
752 
753     return CreateExpr(Val, S, E, IsPPC64);
754   }
755 };
756 
757 } // end anonymous namespace.
758 
759 void PPCOperand::print(raw_ostream &OS) const {
760   switch (Kind) {
761   case Token:
762     OS << "'" << getToken() << "'";
763     break;
764   case Immediate:
765   case ContextImmediate:
766     OS << getImm();
767     break;
768   case Expression:
769     getExpr()->print(OS);
770     break;
771   case TLSRegister:
772     getTLSReg()->print(OS);
773     break;
774   }
775 }
776 
777 static void
778 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
779   if (Op.isImm()) {
780     Inst.addOperand(MCOperand::CreateImm(-Op.getImm()));
781     return;
782   }
783   const MCExpr *Expr = Op.getExpr();
784   if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
785     if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
786       Inst.addOperand(MCOperand::CreateExpr(UnExpr->getSubExpr()));
787       return;
788     }
789   } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
790     if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
791       const MCExpr *NE = MCBinaryExpr::CreateSub(BinExpr->getRHS(),
792                                                  BinExpr->getLHS(), Ctx);
793       Inst.addOperand(MCOperand::CreateExpr(NE));
794       return;
795     }
796   }
797   Inst.addOperand(MCOperand::CreateExpr(MCUnaryExpr::CreateMinus(Expr, Ctx)));
798 }
799 
800 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
801                                       const OperandVector &Operands) {
802   int Opcode = Inst.getOpcode();
803   switch (Opcode) {
804   case PPC::LAx: {
805     MCInst TmpInst;
806     TmpInst.setOpcode(PPC::LA);
807     TmpInst.addOperand(Inst.getOperand(0));
808     TmpInst.addOperand(Inst.getOperand(2));
809     TmpInst.addOperand(Inst.getOperand(1));
810     Inst = TmpInst;
811     break;
812   }
813   case PPC::SUBI: {
814     MCInst TmpInst;
815     TmpInst.setOpcode(PPC::ADDI);
816     TmpInst.addOperand(Inst.getOperand(0));
817     TmpInst.addOperand(Inst.getOperand(1));
818     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
819     Inst = TmpInst;
820     break;
821   }
822   case PPC::SUBIS: {
823     MCInst TmpInst;
824     TmpInst.setOpcode(PPC::ADDIS);
825     TmpInst.addOperand(Inst.getOperand(0));
826     TmpInst.addOperand(Inst.getOperand(1));
827     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
828     Inst = TmpInst;
829     break;
830   }
831   case PPC::SUBIC: {
832     MCInst TmpInst;
833     TmpInst.setOpcode(PPC::ADDIC);
834     TmpInst.addOperand(Inst.getOperand(0));
835     TmpInst.addOperand(Inst.getOperand(1));
836     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
837     Inst = TmpInst;
838     break;
839   }
840   case PPC::SUBICo: {
841     MCInst TmpInst;
842     TmpInst.setOpcode(PPC::ADDICo);
843     TmpInst.addOperand(Inst.getOperand(0));
844     TmpInst.addOperand(Inst.getOperand(1));
845     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
846     Inst = TmpInst;
847     break;
848   }
849   case PPC::EXTLWI:
850   case PPC::EXTLWIo: {
851     MCInst TmpInst;
852     int64_t N = Inst.getOperand(2).getImm();
853     int64_t B = Inst.getOperand(3).getImm();
854     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
855     TmpInst.addOperand(Inst.getOperand(0));
856     TmpInst.addOperand(Inst.getOperand(1));
857     TmpInst.addOperand(MCOperand::CreateImm(B));
858     TmpInst.addOperand(MCOperand::CreateImm(0));
859     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
860     Inst = TmpInst;
861     break;
862   }
863   case PPC::EXTRWI:
864   case PPC::EXTRWIo: {
865     MCInst TmpInst;
866     int64_t N = Inst.getOperand(2).getImm();
867     int64_t B = Inst.getOperand(3).getImm();
868     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
869     TmpInst.addOperand(Inst.getOperand(0));
870     TmpInst.addOperand(Inst.getOperand(1));
871     TmpInst.addOperand(MCOperand::CreateImm(B + N));
872     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
873     TmpInst.addOperand(MCOperand::CreateImm(31));
874     Inst = TmpInst;
875     break;
876   }
877   case PPC::INSLWI:
878   case PPC::INSLWIo: {
879     MCInst TmpInst;
880     int64_t N = Inst.getOperand(2).getImm();
881     int64_t B = Inst.getOperand(3).getImm();
882     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
883     TmpInst.addOperand(Inst.getOperand(0));
884     TmpInst.addOperand(Inst.getOperand(0));
885     TmpInst.addOperand(Inst.getOperand(1));
886     TmpInst.addOperand(MCOperand::CreateImm(32 - B));
887     TmpInst.addOperand(MCOperand::CreateImm(B));
888     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
889     Inst = TmpInst;
890     break;
891   }
892   case PPC::INSRWI:
893   case PPC::INSRWIo: {
894     MCInst TmpInst;
895     int64_t N = Inst.getOperand(2).getImm();
896     int64_t B = Inst.getOperand(3).getImm();
897     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
898     TmpInst.addOperand(Inst.getOperand(0));
899     TmpInst.addOperand(Inst.getOperand(0));
900     TmpInst.addOperand(Inst.getOperand(1));
901     TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
902     TmpInst.addOperand(MCOperand::CreateImm(B));
903     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
904     Inst = TmpInst;
905     break;
906   }
907   case PPC::ROTRWI:
908   case PPC::ROTRWIo: {
909     MCInst TmpInst;
910     int64_t N = Inst.getOperand(2).getImm();
911     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
912     TmpInst.addOperand(Inst.getOperand(0));
913     TmpInst.addOperand(Inst.getOperand(1));
914     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
915     TmpInst.addOperand(MCOperand::CreateImm(0));
916     TmpInst.addOperand(MCOperand::CreateImm(31));
917     Inst = TmpInst;
918     break;
919   }
920   case PPC::SLWI:
921   case PPC::SLWIo: {
922     MCInst TmpInst;
923     int64_t N = Inst.getOperand(2).getImm();
924     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
925     TmpInst.addOperand(Inst.getOperand(0));
926     TmpInst.addOperand(Inst.getOperand(1));
927     TmpInst.addOperand(MCOperand::CreateImm(N));
928     TmpInst.addOperand(MCOperand::CreateImm(0));
929     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
930     Inst = TmpInst;
931     break;
932   }
933   case PPC::SRWI:
934   case PPC::SRWIo: {
935     MCInst TmpInst;
936     int64_t N = Inst.getOperand(2).getImm();
937     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
938     TmpInst.addOperand(Inst.getOperand(0));
939     TmpInst.addOperand(Inst.getOperand(1));
940     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
941     TmpInst.addOperand(MCOperand::CreateImm(N));
942     TmpInst.addOperand(MCOperand::CreateImm(31));
943     Inst = TmpInst;
944     break;
945   }
946   case PPC::CLRRWI:
947   case PPC::CLRRWIo: {
948     MCInst TmpInst;
949     int64_t N = Inst.getOperand(2).getImm();
950     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
951     TmpInst.addOperand(Inst.getOperand(0));
952     TmpInst.addOperand(Inst.getOperand(1));
953     TmpInst.addOperand(MCOperand::CreateImm(0));
954     TmpInst.addOperand(MCOperand::CreateImm(0));
955     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
956     Inst = TmpInst;
957     break;
958   }
959   case PPC::CLRLSLWI:
960   case PPC::CLRLSLWIo: {
961     MCInst TmpInst;
962     int64_t B = Inst.getOperand(2).getImm();
963     int64_t N = Inst.getOperand(3).getImm();
964     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
965     TmpInst.addOperand(Inst.getOperand(0));
966     TmpInst.addOperand(Inst.getOperand(1));
967     TmpInst.addOperand(MCOperand::CreateImm(N));
968     TmpInst.addOperand(MCOperand::CreateImm(B - N));
969     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
970     Inst = TmpInst;
971     break;
972   }
973   case PPC::EXTLDI:
974   case PPC::EXTLDIo: {
975     MCInst TmpInst;
976     int64_t N = Inst.getOperand(2).getImm();
977     int64_t B = Inst.getOperand(3).getImm();
978     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
979     TmpInst.addOperand(Inst.getOperand(0));
980     TmpInst.addOperand(Inst.getOperand(1));
981     TmpInst.addOperand(MCOperand::CreateImm(B));
982     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
983     Inst = TmpInst;
984     break;
985   }
986   case PPC::EXTRDI:
987   case PPC::EXTRDIo: {
988     MCInst TmpInst;
989     int64_t N = Inst.getOperand(2).getImm();
990     int64_t B = Inst.getOperand(3).getImm();
991     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
992     TmpInst.addOperand(Inst.getOperand(0));
993     TmpInst.addOperand(Inst.getOperand(1));
994     TmpInst.addOperand(MCOperand::CreateImm(B + N));
995     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
996     Inst = TmpInst;
997     break;
998   }
999   case PPC::INSRDI:
1000   case PPC::INSRDIo: {
1001     MCInst TmpInst;
1002     int64_t N = Inst.getOperand(2).getImm();
1003     int64_t B = Inst.getOperand(3).getImm();
1004     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1005     TmpInst.addOperand(Inst.getOperand(0));
1006     TmpInst.addOperand(Inst.getOperand(0));
1007     TmpInst.addOperand(Inst.getOperand(1));
1008     TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
1009     TmpInst.addOperand(MCOperand::CreateImm(B));
1010     Inst = TmpInst;
1011     break;
1012   }
1013   case PPC::ROTRDI:
1014   case PPC::ROTRDIo: {
1015     MCInst TmpInst;
1016     int64_t N = Inst.getOperand(2).getImm();
1017     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1018     TmpInst.addOperand(Inst.getOperand(0));
1019     TmpInst.addOperand(Inst.getOperand(1));
1020     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1021     TmpInst.addOperand(MCOperand::CreateImm(0));
1022     Inst = TmpInst;
1023     break;
1024   }
1025   case PPC::SLDI:
1026   case PPC::SLDIo: {
1027     MCInst TmpInst;
1028     int64_t N = Inst.getOperand(2).getImm();
1029     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1030     TmpInst.addOperand(Inst.getOperand(0));
1031     TmpInst.addOperand(Inst.getOperand(1));
1032     TmpInst.addOperand(MCOperand::CreateImm(N));
1033     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1034     Inst = TmpInst;
1035     break;
1036   }
1037   case PPC::SRDI:
1038   case PPC::SRDIo: {
1039     MCInst TmpInst;
1040     int64_t N = Inst.getOperand(2).getImm();
1041     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1042     TmpInst.addOperand(Inst.getOperand(0));
1043     TmpInst.addOperand(Inst.getOperand(1));
1044     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1045     TmpInst.addOperand(MCOperand::CreateImm(N));
1046     Inst = TmpInst;
1047     break;
1048   }
1049   case PPC::CLRRDI:
1050   case PPC::CLRRDIo: {
1051     MCInst TmpInst;
1052     int64_t N = Inst.getOperand(2).getImm();
1053     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1054     TmpInst.addOperand(Inst.getOperand(0));
1055     TmpInst.addOperand(Inst.getOperand(1));
1056     TmpInst.addOperand(MCOperand::CreateImm(0));
1057     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1058     Inst = TmpInst;
1059     break;
1060   }
1061   case PPC::CLRLSLDI:
1062   case PPC::CLRLSLDIo: {
1063     MCInst TmpInst;
1064     int64_t B = Inst.getOperand(2).getImm();
1065     int64_t N = Inst.getOperand(3).getImm();
1066     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1067     TmpInst.addOperand(Inst.getOperand(0));
1068     TmpInst.addOperand(Inst.getOperand(1));
1069     TmpInst.addOperand(MCOperand::CreateImm(N));
1070     TmpInst.addOperand(MCOperand::CreateImm(B - N));
1071     Inst = TmpInst;
1072     break;
1073   }
1074   case PPC::RLWINMbm:
1075   case PPC::RLWINMobm: {
1076     unsigned MB, ME;
1077     int64_t BM = Inst.getOperand(3).getImm();
1078     if (!isRunOfOnes(BM, MB, ME))
1079       break;
1080 
1081     MCInst TmpInst;
1082     TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1083     TmpInst.addOperand(Inst.getOperand(0));
1084     TmpInst.addOperand(Inst.getOperand(1));
1085     TmpInst.addOperand(Inst.getOperand(2));
1086     TmpInst.addOperand(MCOperand::CreateImm(MB));
1087     TmpInst.addOperand(MCOperand::CreateImm(ME));
1088     Inst = TmpInst;
1089     break;
1090   }
1091   case PPC::RLWIMIbm:
1092   case PPC::RLWIMIobm: {
1093     unsigned MB, ME;
1094     int64_t BM = Inst.getOperand(3).getImm();
1095     if (!isRunOfOnes(BM, MB, ME))
1096       break;
1097 
1098     MCInst TmpInst;
1099     TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1100     TmpInst.addOperand(Inst.getOperand(0));
1101     TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1102     TmpInst.addOperand(Inst.getOperand(1));
1103     TmpInst.addOperand(Inst.getOperand(2));
1104     TmpInst.addOperand(MCOperand::CreateImm(MB));
1105     TmpInst.addOperand(MCOperand::CreateImm(ME));
1106     Inst = TmpInst;
1107     break;
1108   }
1109   case PPC::RLWNMbm:
1110   case PPC::RLWNMobm: {
1111     unsigned MB, ME;
1112     int64_t BM = Inst.getOperand(3).getImm();
1113     if (!isRunOfOnes(BM, MB, ME))
1114       break;
1115 
1116     MCInst TmpInst;
1117     TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1118     TmpInst.addOperand(Inst.getOperand(0));
1119     TmpInst.addOperand(Inst.getOperand(1));
1120     TmpInst.addOperand(Inst.getOperand(2));
1121     TmpInst.addOperand(MCOperand::CreateImm(MB));
1122     TmpInst.addOperand(MCOperand::CreateImm(ME));
1123     Inst = TmpInst;
1124     break;
1125   }
1126   }
1127 }
1128 
1129 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1130                                            OperandVector &Operands,
1131                                            MCStreamer &Out, uint64_t &ErrorInfo,
1132                                            bool MatchingInlineAsm) {
1133   MCInst Inst;
1134 
1135   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1136   case Match_Success:
1137     // Post-process instructions (typically extended mnemonics)
1138     ProcessInstruction(Inst, Operands);
1139     Inst.setLoc(IDLoc);
1140     Out.EmitInstruction(Inst, STI);
1141     return false;
1142   case Match_MissingFeature:
1143     return Error(IDLoc, "instruction use requires an option to be enabled");
1144   case Match_MnemonicFail:
1145     return Error(IDLoc, "unrecognized instruction mnemonic");
1146   case Match_InvalidOperand: {
1147     SMLoc ErrorLoc = IDLoc;
1148     if (ErrorInfo != ~0ULL) {
1149       if (ErrorInfo >= Operands.size())
1150         return Error(IDLoc, "too few operands for instruction");
1151 
1152       ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1153       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1154     }
1155 
1156     return Error(ErrorLoc, "invalid operand for instruction");
1157   }
1158   }
1159 
1160   llvm_unreachable("Implement any new match types added!");
1161 }
1162 
1163 bool PPCAsmParser::
1164 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1165   if (Tok.is(AsmToken::Identifier)) {
1166     StringRef Name = Tok.getString();
1167 
1168     if (Name.equals_lower("lr")) {
1169       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1170       IntVal = 8;
1171       return false;
1172     } else if (Name.equals_lower("ctr")) {
1173       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1174       IntVal = 9;
1175       return false;
1176     } else if (Name.equals_lower("vrsave")) {
1177       RegNo = PPC::VRSAVE;
1178       IntVal = 256;
1179       return false;
1180     } else if (Name.startswith_lower("r") &&
1181                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1182       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1183       return false;
1184     } else if (Name.startswith_lower("f") &&
1185                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1186       RegNo = FRegs[IntVal];
1187       return false;
1188     } else if (Name.startswith_lower("v") &&
1189                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1190       RegNo = VRegs[IntVal];
1191       return false;
1192     } else if (Name.startswith_lower("cr") &&
1193                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1194       RegNo = CRRegs[IntVal];
1195       return false;
1196     }
1197   }
1198 
1199   return true;
1200 }
1201 
1202 bool PPCAsmParser::
1203 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1204   MCAsmParser &Parser = getParser();
1205   const AsmToken &Tok = Parser.getTok();
1206   StartLoc = Tok.getLoc();
1207   EndLoc = Tok.getEndLoc();
1208   RegNo = 0;
1209   int64_t IntVal;
1210 
1211   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1212     Parser.Lex(); // Eat identifier token.
1213     return false;
1214   }
1215 
1216   return Error(StartLoc, "invalid register name");
1217 }
1218 
1219 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1220 /// the expression and check for VK_PPC_LO/HI/HA
1221 /// symbol variants.  If all symbols with modifier use the same
1222 /// variant, return the corresponding PPCMCExpr::VariantKind,
1223 /// and a modified expression using the default symbol variant.
1224 /// Otherwise, return NULL.
1225 const MCExpr *PPCAsmParser::
1226 ExtractModifierFromExpr(const MCExpr *E,
1227                         PPCMCExpr::VariantKind &Variant) {
1228   MCContext &Context = getParser().getContext();
1229   Variant = PPCMCExpr::VK_PPC_None;
1230 
1231   switch (E->getKind()) {
1232   case MCExpr::Target:
1233   case MCExpr::Constant:
1234     return nullptr;
1235 
1236   case MCExpr::SymbolRef: {
1237     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1238 
1239     switch (SRE->getKind()) {
1240     case MCSymbolRefExpr::VK_PPC_LO:
1241       Variant = PPCMCExpr::VK_PPC_LO;
1242       break;
1243     case MCSymbolRefExpr::VK_PPC_HI:
1244       Variant = PPCMCExpr::VK_PPC_HI;
1245       break;
1246     case MCSymbolRefExpr::VK_PPC_HA:
1247       Variant = PPCMCExpr::VK_PPC_HA;
1248       break;
1249     case MCSymbolRefExpr::VK_PPC_HIGHER:
1250       Variant = PPCMCExpr::VK_PPC_HIGHER;
1251       break;
1252     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1253       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1254       break;
1255     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1256       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1257       break;
1258     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1259       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1260       break;
1261     default:
1262       return nullptr;
1263     }
1264 
1265     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1266   }
1267 
1268   case MCExpr::Unary: {
1269     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1270     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1271     if (!Sub)
1272       return nullptr;
1273     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1274   }
1275 
1276   case MCExpr::Binary: {
1277     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1278     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1279     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1280     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1281 
1282     if (!LHS && !RHS)
1283       return nullptr;
1284 
1285     if (!LHS) LHS = BE->getLHS();
1286     if (!RHS) RHS = BE->getRHS();
1287 
1288     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1289       Variant = RHSVariant;
1290     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1291       Variant = LHSVariant;
1292     else if (LHSVariant == RHSVariant)
1293       Variant = LHSVariant;
1294     else
1295       return nullptr;
1296 
1297     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1298   }
1299   }
1300 
1301   llvm_unreachable("Invalid expression kind!");
1302 }
1303 
1304 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1305 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1306 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1307 /// FIXME: This is a hack.
1308 const MCExpr *PPCAsmParser::
1309 FixupVariantKind(const MCExpr *E) {
1310   MCContext &Context = getParser().getContext();
1311 
1312   switch (E->getKind()) {
1313   case MCExpr::Target:
1314   case MCExpr::Constant:
1315     return E;
1316 
1317   case MCExpr::SymbolRef: {
1318     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1319     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1320 
1321     switch (SRE->getKind()) {
1322     case MCSymbolRefExpr::VK_TLSGD:
1323       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1324       break;
1325     case MCSymbolRefExpr::VK_TLSLD:
1326       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1327       break;
1328     default:
1329       return E;
1330     }
1331     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1332   }
1333 
1334   case MCExpr::Unary: {
1335     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1336     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1337     if (Sub == UE->getSubExpr())
1338       return E;
1339     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1340   }
1341 
1342   case MCExpr::Binary: {
1343     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1344     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1345     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1346     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1347       return E;
1348     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1349   }
1350   }
1351 
1352   llvm_unreachable("Invalid expression kind!");
1353 }
1354 
1355 /// ParseExpression.  This differs from the default "parseExpression" in that
1356 /// it handles modifiers.
1357 bool PPCAsmParser::
1358 ParseExpression(const MCExpr *&EVal) {
1359 
1360   if (isDarwin())
1361     return ParseDarwinExpression(EVal);
1362 
1363   // (ELF Platforms)
1364   // Handle \code @l/@ha \endcode
1365   if (getParser().parseExpression(EVal))
1366     return true;
1367 
1368   EVal = FixupVariantKind(EVal);
1369 
1370   PPCMCExpr::VariantKind Variant;
1371   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1372   if (E)
1373     EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1374 
1375   return false;
1376 }
1377 
1378 /// ParseDarwinExpression.  (MachO Platforms)
1379 /// This differs from the default "parseExpression" in that it handles detection
1380 /// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1381 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1382 /// syntax form so it is done here.  TODO: Determine if there is merit in arranging
1383 /// for this to be done at a higher level.
1384 bool PPCAsmParser::
1385 ParseDarwinExpression(const MCExpr *&EVal) {
1386   MCAsmParser &Parser = getParser();
1387   PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1388   switch (getLexer().getKind()) {
1389   default:
1390     break;
1391   case AsmToken::Identifier:
1392     // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1393     // something starting with any other char should be part of the
1394     // asm syntax.  If handwritten asm includes an identifier like lo16,
1395     // then all bets are off - but no-one would do that, right?
1396     StringRef poss = Parser.getTok().getString();
1397     if (poss.equals_lower("lo16")) {
1398       Variant = PPCMCExpr::VK_PPC_LO;
1399     } else if (poss.equals_lower("hi16")) {
1400       Variant = PPCMCExpr::VK_PPC_HI;
1401     } else if (poss.equals_lower("ha16")) {
1402       Variant = PPCMCExpr::VK_PPC_HA;
1403     }
1404     if (Variant != PPCMCExpr::VK_PPC_None) {
1405       Parser.Lex(); // Eat the xx16
1406       if (getLexer().isNot(AsmToken::LParen))
1407         return Error(Parser.getTok().getLoc(), "expected '('");
1408       Parser.Lex(); // Eat the '('
1409     }
1410     break;
1411   }
1412 
1413   if (getParser().parseExpression(EVal))
1414     return true;
1415 
1416   if (Variant != PPCMCExpr::VK_PPC_None) {
1417     if (getLexer().isNot(AsmToken::RParen))
1418       return Error(Parser.getTok().getLoc(), "expected ')'");
1419     Parser.Lex(); // Eat the ')'
1420     EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1421   }
1422   return false;
1423 }
1424 
1425 /// ParseOperand
1426 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1427 /// rNN for MachO.
1428 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1429   MCAsmParser &Parser = getParser();
1430   SMLoc S = Parser.getTok().getLoc();
1431   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1432   const MCExpr *EVal;
1433 
1434   // Attempt to parse the next token as an immediate
1435   switch (getLexer().getKind()) {
1436   // Special handling for register names.  These are interpreted
1437   // as immediates corresponding to the register number.
1438   case AsmToken::Percent:
1439     Parser.Lex(); // Eat the '%'.
1440     unsigned RegNo;
1441     int64_t IntVal;
1442     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1443       Parser.Lex(); // Eat the identifier token.
1444       Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1445       return false;
1446     }
1447     return Error(S, "invalid register name");
1448 
1449   case AsmToken::Identifier:
1450     // Note that non-register-name identifiers from the compiler will begin
1451     // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1452     // identifiers like r31foo - so we fall through in the event that parsing
1453     // a register name fails.
1454     if (isDarwin()) {
1455       unsigned RegNo;
1456       int64_t IntVal;
1457       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1458         Parser.Lex(); // Eat the identifier token.
1459         Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1460         return false;
1461       }
1462     }
1463   // Fall-through to process non-register-name identifiers as expression.
1464   // All other expressions
1465   case AsmToken::LParen:
1466   case AsmToken::Plus:
1467   case AsmToken::Minus:
1468   case AsmToken::Integer:
1469   case AsmToken::Dot:
1470   case AsmToken::Dollar:
1471   case AsmToken::Exclaim:
1472   case AsmToken::Tilde:
1473     if (!ParseExpression(EVal))
1474       break;
1475     /* fall through */
1476   default:
1477     return Error(S, "unknown operand");
1478   }
1479 
1480   // Push the parsed operand into the list of operands
1481   Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1482 
1483   // Check whether this is a TLS call expression
1484   bool TLSCall = false;
1485   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1486     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1487 
1488   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1489     const MCExpr *TLSSym;
1490 
1491     Parser.Lex(); // Eat the '('.
1492     S = Parser.getTok().getLoc();
1493     if (ParseExpression(TLSSym))
1494       return Error(S, "invalid TLS call expression");
1495     if (getLexer().isNot(AsmToken::RParen))
1496       return Error(Parser.getTok().getLoc(), "missing ')'");
1497     E = Parser.getTok().getLoc();
1498     Parser.Lex(); // Eat the ')'.
1499 
1500     Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1501   }
1502 
1503   // Otherwise, check for D-form memory operands
1504   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1505     Parser.Lex(); // Eat the '('.
1506     S = Parser.getTok().getLoc();
1507 
1508     int64_t IntVal;
1509     switch (getLexer().getKind()) {
1510     case AsmToken::Percent:
1511       Parser.Lex(); // Eat the '%'.
1512       unsigned RegNo;
1513       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1514         return Error(S, "invalid register name");
1515       Parser.Lex(); // Eat the identifier token.
1516       break;
1517 
1518     case AsmToken::Integer:
1519       if (!isDarwin()) {
1520         if (getParser().parseAbsoluteExpression(IntVal) ||
1521           IntVal < 0 || IntVal > 31)
1522         return Error(S, "invalid register number");
1523       } else {
1524         return Error(S, "unexpected integer value");
1525       }
1526       break;
1527 
1528    case AsmToken::Identifier:
1529     if (isDarwin()) {
1530       unsigned RegNo;
1531       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1532         Parser.Lex(); // Eat the identifier token.
1533         break;
1534       }
1535     }
1536     // Fall-through..
1537 
1538     default:
1539       return Error(S, "invalid memory operand");
1540     }
1541 
1542     if (getLexer().isNot(AsmToken::RParen))
1543       return Error(Parser.getTok().getLoc(), "missing ')'");
1544     E = Parser.getTok().getLoc();
1545     Parser.Lex(); // Eat the ')'.
1546 
1547     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1548   }
1549 
1550   return false;
1551 }
1552 
1553 /// Parse an instruction mnemonic followed by its operands.
1554 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1555                                     SMLoc NameLoc, OperandVector &Operands) {
1556   // The first operand is the token for the instruction name.
1557   // If the next character is a '+' or '-', we need to add it to the
1558   // instruction name, to match what TableGen is doing.
1559   std::string NewOpcode;
1560   if (getLexer().is(AsmToken::Plus)) {
1561     getLexer().Lex();
1562     NewOpcode = Name;
1563     NewOpcode += '+';
1564     Name = NewOpcode;
1565   }
1566   if (getLexer().is(AsmToken::Minus)) {
1567     getLexer().Lex();
1568     NewOpcode = Name;
1569     NewOpcode += '-';
1570     Name = NewOpcode;
1571   }
1572   // If the instruction ends in a '.', we need to create a separate
1573   // token for it, to match what TableGen is doing.
1574   size_t Dot = Name.find('.');
1575   StringRef Mnemonic = Name.slice(0, Dot);
1576   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1577     Operands.push_back(
1578         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1579   else
1580     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1581   if (Dot != StringRef::npos) {
1582     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1583     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1584     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1585       Operands.push_back(
1586           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1587     else
1588       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1589   }
1590 
1591   // If there are no more operands then finish
1592   if (getLexer().is(AsmToken::EndOfStatement))
1593     return false;
1594 
1595   // Parse the first operand
1596   if (ParseOperand(Operands))
1597     return true;
1598 
1599   while (getLexer().isNot(AsmToken::EndOfStatement) &&
1600          getLexer().is(AsmToken::Comma)) {
1601     // Consume the comma token
1602     getLexer().Lex();
1603 
1604     // Parse the next operand
1605     if (ParseOperand(Operands))
1606       return true;
1607   }
1608 
1609   return false;
1610 }
1611 
1612 /// ParseDirective parses the PPC specific directives
1613 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1614   StringRef IDVal = DirectiveID.getIdentifier();
1615   if (!isDarwin()) {
1616     if (IDVal == ".word")
1617       return ParseDirectiveWord(2, DirectiveID.getLoc());
1618     if (IDVal == ".llong")
1619       return ParseDirectiveWord(8, DirectiveID.getLoc());
1620     if (IDVal == ".tc")
1621       return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1622     if (IDVal == ".machine")
1623       return ParseDirectiveMachine(DirectiveID.getLoc());
1624     if (IDVal == ".abiversion")
1625       return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1626     if (IDVal == ".localentry")
1627       return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1628   } else {
1629     if (IDVal == ".machine")
1630       return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1631   }
1632   return true;
1633 }
1634 
1635 /// ParseDirectiveWord
1636 ///  ::= .word [ expression (, expression)* ]
1637 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1638   MCAsmParser &Parser = getParser();
1639   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1640     for (;;) {
1641       const MCExpr *Value;
1642       if (getParser().parseExpression(Value))
1643         return false;
1644 
1645       getParser().getStreamer().EmitValue(Value, Size);
1646 
1647       if (getLexer().is(AsmToken::EndOfStatement))
1648         break;
1649 
1650       if (getLexer().isNot(AsmToken::Comma))
1651         return Error(L, "unexpected token in directive");
1652       Parser.Lex();
1653     }
1654   }
1655 
1656   Parser.Lex();
1657   return false;
1658 }
1659 
1660 /// ParseDirectiveTC
1661 ///  ::= .tc [ symbol (, expression)* ]
1662 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1663   MCAsmParser &Parser = getParser();
1664   // Skip TC symbol, which is only used with XCOFF.
1665   while (getLexer().isNot(AsmToken::EndOfStatement)
1666          && getLexer().isNot(AsmToken::Comma))
1667     Parser.Lex();
1668   if (getLexer().isNot(AsmToken::Comma)) {
1669     Error(L, "unexpected token in directive");
1670     return false;
1671   }
1672   Parser.Lex();
1673 
1674   // Align to word size.
1675   getParser().getStreamer().EmitValueToAlignment(Size);
1676 
1677   // Emit expressions.
1678   return ParseDirectiveWord(Size, L);
1679 }
1680 
1681 /// ParseDirectiveMachine (ELF platforms)
1682 ///  ::= .machine [ cpu | "push" | "pop" ]
1683 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1684   MCAsmParser &Parser = getParser();
1685   if (getLexer().isNot(AsmToken::Identifier) &&
1686       getLexer().isNot(AsmToken::String)) {
1687     Error(L, "unexpected token in directive");
1688     return false;
1689   }
1690 
1691   StringRef CPU = Parser.getTok().getIdentifier();
1692   Parser.Lex();
1693 
1694   // FIXME: Right now, the parser always allows any available
1695   // instruction, so the .machine directive is not useful.
1696   // Implement ".machine any" (by doing nothing) for the benefit
1697   // of existing assembler code.  Likewise, we can then implement
1698   // ".machine push" and ".machine pop" as no-op.
1699   if (CPU != "any" && CPU != "push" && CPU != "pop") {
1700     Error(L, "unrecognized machine type");
1701     return false;
1702   }
1703 
1704   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1705     Error(L, "unexpected token in directive");
1706     return false;
1707   }
1708   PPCTargetStreamer &TStreamer =
1709       *static_cast<PPCTargetStreamer *>(
1710            getParser().getStreamer().getTargetStreamer());
1711   TStreamer.emitMachine(CPU);
1712 
1713   return false;
1714 }
1715 
1716 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1717 ///  ::= .machine cpu-identifier
1718 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1719   MCAsmParser &Parser = getParser();
1720   if (getLexer().isNot(AsmToken::Identifier) &&
1721       getLexer().isNot(AsmToken::String)) {
1722     Error(L, "unexpected token in directive");
1723     return false;
1724   }
1725 
1726   StringRef CPU = Parser.getTok().getIdentifier();
1727   Parser.Lex();
1728 
1729   // FIXME: this is only the 'default' set of cpu variants.
1730   // However we don't act on this information at present, this is simply
1731   // allowing parsing to proceed with minimal sanity checking.
1732   if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1733     Error(L, "unrecognized cpu type");
1734     return false;
1735   }
1736 
1737   if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1738     Error(L, "wrong cpu type specified for 64bit");
1739     return false;
1740   }
1741   if (!isPPC64() && CPU == "ppc64") {
1742     Error(L, "wrong cpu type specified for 32bit");
1743     return false;
1744   }
1745 
1746   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1747     Error(L, "unexpected token in directive");
1748     return false;
1749   }
1750 
1751   return false;
1752 }
1753 
1754 /// ParseDirectiveAbiVersion
1755 ///  ::= .abiversion constant-expression
1756 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1757   int64_t AbiVersion;
1758   if (getParser().parseAbsoluteExpression(AbiVersion)){
1759     Error(L, "expected constant expression");
1760     return false;
1761   }
1762   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1763     Error(L, "unexpected token in directive");
1764     return false;
1765   }
1766 
1767   PPCTargetStreamer &TStreamer =
1768       *static_cast<PPCTargetStreamer *>(
1769            getParser().getStreamer().getTargetStreamer());
1770   TStreamer.emitAbiVersion(AbiVersion);
1771 
1772   return false;
1773 }
1774 
1775 /// ParseDirectiveLocalEntry
1776 ///  ::= .localentry symbol, expression
1777 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1778   StringRef Name;
1779   if (getParser().parseIdentifier(Name)) {
1780     Error(L, "expected identifier in directive");
1781     return false;
1782   }
1783   MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
1784 
1785   if (getLexer().isNot(AsmToken::Comma)) {
1786     Error(L, "unexpected token in directive");
1787     return false;
1788   }
1789   Lex();
1790 
1791   const MCExpr *Expr;
1792   if (getParser().parseExpression(Expr)) {
1793     Error(L, "expected expression");
1794     return false;
1795   }
1796 
1797   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1798     Error(L, "unexpected token in directive");
1799     return false;
1800   }
1801 
1802   PPCTargetStreamer &TStreamer =
1803       *static_cast<PPCTargetStreamer *>(
1804            getParser().getStreamer().getTargetStreamer());
1805   TStreamer.emitLocalEntry(Sym, Expr);
1806 
1807   return false;
1808 }
1809 
1810 
1811 
1812 /// Force static initialization.
1813 extern "C" void LLVMInitializePowerPCAsmParser() {
1814   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1815   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1816   RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1817 }
1818 
1819 #define GET_REGISTER_MATCHER
1820 #define GET_MATCHER_IMPLEMENTATION
1821 #include "PPCGenAsmMatcher.inc"
1822 
1823 // Define this matcher function after the auto-generated include so we
1824 // have the match class enum definitions.
1825 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1826                                                   unsigned Kind) {
1827   // If the kind is a token for a literal immediate, check if our asm
1828   // operand matches. This is for InstAliases which have a fixed-value
1829   // immediate in the syntax.
1830   int64_t ImmVal;
1831   switch (Kind) {
1832     case MCK_0: ImmVal = 0; break;
1833     case MCK_1: ImmVal = 1; break;
1834     case MCK_2: ImmVal = 2; break;
1835     case MCK_3: ImmVal = 3; break;
1836     case MCK_4: ImmVal = 4; break;
1837     case MCK_5: ImmVal = 5; break;
1838     case MCK_6: ImmVal = 6; break;
1839     case MCK_7: ImmVal = 7; break;
1840     default: return Match_InvalidOperand;
1841   }
1842 
1843   PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1844   if (Op.isImm() && Op.getImm() == ImmVal)
1845     return Match_Success;
1846 
1847   return Match_InvalidOperand;
1848 }
1849 
1850 const MCExpr *
1851 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1852                                   MCSymbolRefExpr::VariantKind Variant,
1853                                   MCContext &Ctx) {
1854   switch (Variant) {
1855   case MCSymbolRefExpr::VK_PPC_LO:
1856     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1857   case MCSymbolRefExpr::VK_PPC_HI:
1858     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1859   case MCSymbolRefExpr::VK_PPC_HA:
1860     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1861   case MCSymbolRefExpr::VK_PPC_HIGHER:
1862     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1863   case MCSymbolRefExpr::VK_PPC_HIGHERA:
1864     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1865   case MCSymbolRefExpr::VK_PPC_HIGHEST:
1866     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1867   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1868     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1869   default:
1870     return nullptr;
1871   }
1872 }
1873