1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/PPCMCTargetDesc.h" 11 #include "MCTargetDesc/PPCMCExpr.h" 12 #include "PPCTargetStreamer.h" 13 #include "llvm/ADT/STLExtras.h" 14 #include "llvm/ADT/SmallString.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringSwitch.h" 17 #include "llvm/ADT/Twine.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrInfo.h" 21 #include "llvm/MC/MCParser/MCAsmLexer.h" 22 #include "llvm/MC/MCParser/MCAsmParser.h" 23 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/MC/MCStreamer.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/MC/MCTargetAsmParser.h" 28 #include "llvm/Support/SourceMgr.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include "llvm/Support/raw_ostream.h" 31 32 using namespace llvm; 33 34 namespace { 35 36 static unsigned RRegs[32] = { 37 PPC::R0, PPC::R1, PPC::R2, PPC::R3, 38 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 39 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 40 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 41 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 42 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 43 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 44 PPC::R28, PPC::R29, PPC::R30, PPC::R31 45 }; 46 static unsigned RRegsNoR0[32] = { 47 PPC::ZERO, 48 PPC::R1, PPC::R2, PPC::R3, 49 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 50 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 51 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 52 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 53 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 54 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 55 PPC::R28, PPC::R29, PPC::R30, PPC::R31 56 }; 57 static unsigned XRegs[32] = { 58 PPC::X0, PPC::X1, PPC::X2, PPC::X3, 59 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 60 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 61 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 62 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 63 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 64 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 65 PPC::X28, PPC::X29, PPC::X30, PPC::X31 66 }; 67 static unsigned XRegsNoX0[32] = { 68 PPC::ZERO8, 69 PPC::X1, PPC::X2, PPC::X3, 70 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 71 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 72 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 73 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 74 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 75 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 76 PPC::X28, PPC::X29, PPC::X30, PPC::X31 77 }; 78 static unsigned FRegs[32] = { 79 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 80 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 81 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 82 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 83 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 84 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 85 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 86 PPC::F28, PPC::F29, PPC::F30, PPC::F31 87 }; 88 static unsigned VRegs[32] = { 89 PPC::V0, PPC::V1, PPC::V2, PPC::V3, 90 PPC::V4, PPC::V5, PPC::V6, PPC::V7, 91 PPC::V8, PPC::V9, PPC::V10, PPC::V11, 92 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 93 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 94 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 95 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 96 PPC::V28, PPC::V29, PPC::V30, PPC::V31 97 }; 98 static unsigned CRBITRegs[32] = { 99 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, 100 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, 101 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 102 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 103 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 104 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, 105 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, 106 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN 107 }; 108 static unsigned CRRegs[8] = { 109 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, 110 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7 111 }; 112 113 // Evaluate an expression containing condition register 114 // or condition register field symbols. Returns positive 115 // value on success, or -1 on error. 116 static int64_t 117 EvaluateCRExpr(const MCExpr *E) { 118 switch (E->getKind()) { 119 case MCExpr::Target: 120 return -1; 121 122 case MCExpr::Constant: { 123 int64_t Res = cast<MCConstantExpr>(E)->getValue(); 124 return Res < 0 ? -1 : Res; 125 } 126 127 case MCExpr::SymbolRef: { 128 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 129 StringRef Name = SRE->getSymbol().getName(); 130 131 if (Name == "lt") return 0; 132 if (Name == "gt") return 1; 133 if (Name == "eq") return 2; 134 if (Name == "so") return 3; 135 if (Name == "un") return 3; 136 137 if (Name == "cr0") return 0; 138 if (Name == "cr1") return 1; 139 if (Name == "cr2") return 2; 140 if (Name == "cr3") return 3; 141 if (Name == "cr4") return 4; 142 if (Name == "cr5") return 5; 143 if (Name == "cr6") return 6; 144 if (Name == "cr7") return 7; 145 146 return -1; 147 } 148 149 case MCExpr::Unary: 150 return -1; 151 152 case MCExpr::Binary: { 153 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 154 int64_t LHSVal = EvaluateCRExpr(BE->getLHS()); 155 int64_t RHSVal = EvaluateCRExpr(BE->getRHS()); 156 int64_t Res; 157 158 if (LHSVal < 0 || RHSVal < 0) 159 return -1; 160 161 switch (BE->getOpcode()) { 162 default: return -1; 163 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break; 164 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break; 165 } 166 167 return Res < 0 ? -1 : Res; 168 } 169 } 170 171 llvm_unreachable("Invalid expression kind!"); 172 } 173 174 struct PPCOperand; 175 176 class PPCAsmParser : public MCTargetAsmParser { 177 MCSubtargetInfo &STI; 178 MCAsmParser &Parser; 179 const MCInstrInfo &MII; 180 bool IsPPC64; 181 bool IsDarwin; 182 183 MCAsmParser &getParser() const { return Parser; } 184 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 185 186 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 187 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 188 189 bool isPPC64() const { return IsPPC64; } 190 bool isDarwin() const { return IsDarwin; } 191 192 bool MatchRegisterName(const AsmToken &Tok, 193 unsigned &RegNo, int64_t &IntVal); 194 195 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 196 197 const MCExpr *ExtractModifierFromExpr(const MCExpr *E, 198 PPCMCExpr::VariantKind &Variant); 199 const MCExpr *FixupVariantKind(const MCExpr *E); 200 bool ParseExpression(const MCExpr *&EVal); 201 bool ParseDarwinExpression(const MCExpr *&EVal); 202 203 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 204 205 bool ParseDirectiveWord(unsigned Size, SMLoc L); 206 bool ParseDirectiveTC(unsigned Size, SMLoc L); 207 bool ParseDirectiveMachine(SMLoc L); 208 bool ParseDarwinDirectiveMachine(SMLoc L); 209 210 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 211 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 212 MCStreamer &Out, unsigned &ErrorInfo, 213 bool MatchingInlineAsm); 214 215 void ProcessInstruction(MCInst &Inst, 216 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 217 218 /// @name Auto-generated Match Functions 219 /// { 220 221 #define GET_ASSEMBLER_HEADER 222 #include "PPCGenAsmMatcher.inc" 223 224 /// } 225 226 227 public: 228 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser, 229 const MCInstrInfo &_MII) 230 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) { 231 // Check for 64-bit vs. 32-bit pointer mode. 232 Triple TheTriple(STI.getTargetTriple()); 233 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 || 234 TheTriple.getArch() == Triple::ppc64le); 235 IsDarwin = TheTriple.isMacOSX(); 236 // Initialize the set of available features. 237 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 238 } 239 240 virtual bool ParseInstruction(ParseInstructionInfo &Info, 241 StringRef Name, SMLoc NameLoc, 242 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 243 244 virtual bool ParseDirective(AsmToken DirectiveID); 245 246 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind); 247 248 virtual const MCExpr *applyModifierToExpr(const MCExpr *E, 249 MCSymbolRefExpr::VariantKind, 250 MCContext &Ctx); 251 }; 252 253 /// PPCOperand - Instances of this class represent a parsed PowerPC machine 254 /// instruction. 255 struct PPCOperand : public MCParsedAsmOperand { 256 enum KindTy { 257 Token, 258 Immediate, 259 Expression, 260 TLSRegister 261 } Kind; 262 263 SMLoc StartLoc, EndLoc; 264 bool IsPPC64; 265 266 struct TokOp { 267 const char *Data; 268 unsigned Length; 269 }; 270 271 struct ImmOp { 272 int64_t Val; 273 }; 274 275 struct ExprOp { 276 const MCExpr *Val; 277 int64_t CRVal; // Cached result of EvaluateCRExpr(Val) 278 }; 279 280 struct TLSRegOp { 281 const MCSymbolRefExpr *Sym; 282 }; 283 284 union { 285 struct TokOp Tok; 286 struct ImmOp Imm; 287 struct ExprOp Expr; 288 struct TLSRegOp TLSReg; 289 }; 290 291 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 292 public: 293 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() { 294 Kind = o.Kind; 295 StartLoc = o.StartLoc; 296 EndLoc = o.EndLoc; 297 IsPPC64 = o.IsPPC64; 298 switch (Kind) { 299 case Token: 300 Tok = o.Tok; 301 break; 302 case Immediate: 303 Imm = o.Imm; 304 break; 305 case Expression: 306 Expr = o.Expr; 307 break; 308 case TLSRegister: 309 TLSReg = o.TLSReg; 310 break; 311 } 312 } 313 314 /// getStartLoc - Get the location of the first token of this operand. 315 SMLoc getStartLoc() const { return StartLoc; } 316 317 /// getEndLoc - Get the location of the last token of this operand. 318 SMLoc getEndLoc() const { return EndLoc; } 319 320 /// isPPC64 - True if this operand is for an instruction in 64-bit mode. 321 bool isPPC64() const { return IsPPC64; } 322 323 int64_t getImm() const { 324 assert(Kind == Immediate && "Invalid access!"); 325 return Imm.Val; 326 } 327 328 const MCExpr *getExpr() const { 329 assert(Kind == Expression && "Invalid access!"); 330 return Expr.Val; 331 } 332 333 int64_t getExprCRVal() const { 334 assert(Kind == Expression && "Invalid access!"); 335 return Expr.CRVal; 336 } 337 338 const MCExpr *getTLSReg() const { 339 assert(Kind == TLSRegister && "Invalid access!"); 340 return TLSReg.Sym; 341 } 342 343 unsigned getReg() const { 344 assert(isRegNumber() && "Invalid access!"); 345 return (unsigned) Imm.Val; 346 } 347 348 unsigned getCCReg() const { 349 assert(isCCRegNumber() && "Invalid access!"); 350 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 351 } 352 353 unsigned getCRBit() const { 354 assert(isCRBitNumber() && "Invalid access!"); 355 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 356 } 357 358 unsigned getCRBitMask() const { 359 assert(isCRBitMask() && "Invalid access!"); 360 return 7 - countTrailingZeros<uint64_t>(Imm.Val); 361 } 362 363 bool isToken() const { return Kind == Token; } 364 bool isImm() const { return Kind == Immediate || Kind == Expression; } 365 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } 366 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } 367 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } 368 bool isU16Imm() const { return Kind == Expression || 369 (Kind == Immediate && isUInt<16>(getImm())); } 370 bool isS16Imm() const { return Kind == Expression || 371 (Kind == Immediate && isInt<16>(getImm())); } 372 bool isS16ImmX4() const { return Kind == Expression || 373 (Kind == Immediate && isInt<16>(getImm()) && 374 (getImm() & 3) == 0); } 375 bool isS17Imm() const { return Kind == Expression || 376 (Kind == Immediate && isInt<17>(getImm())); } 377 bool isTLSReg() const { return Kind == TLSRegister; } 378 bool isDirectBr() const { return Kind == Expression || 379 (Kind == Immediate && isInt<26>(getImm()) && 380 (getImm() & 3) == 0); } 381 bool isCondBr() const { return Kind == Expression || 382 (Kind == Immediate && isInt<16>(getImm()) && 383 (getImm() & 3) == 0); } 384 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } 385 bool isCCRegNumber() const { return (Kind == Expression 386 && isUInt<3>(getExprCRVal())) || 387 (Kind == Immediate 388 && isUInt<3>(getImm())); } 389 bool isCRBitNumber() const { return (Kind == Expression 390 && isUInt<5>(getExprCRVal())) || 391 (Kind == Immediate 392 && isUInt<5>(getImm())); } 393 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) && 394 isPowerOf2_32(getImm()); } 395 bool isMem() const { return false; } 396 bool isReg() const { return false; } 397 398 void addRegOperands(MCInst &Inst, unsigned N) const { 399 llvm_unreachable("addRegOperands"); 400 } 401 402 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { 403 assert(N == 1 && "Invalid number of operands!"); 404 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()])); 405 } 406 407 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { 408 assert(N == 1 && "Invalid number of operands!"); 409 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()])); 410 } 411 412 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { 413 assert(N == 1 && "Invalid number of operands!"); 414 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()])); 415 } 416 417 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { 418 assert(N == 1 && "Invalid number of operands!"); 419 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()])); 420 } 421 422 void addRegGxRCOperands(MCInst &Inst, unsigned N) const { 423 if (isPPC64()) 424 addRegG8RCOperands(Inst, N); 425 else 426 addRegGPRCOperands(Inst, N); 427 } 428 429 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const { 430 if (isPPC64()) 431 addRegG8RCNoX0Operands(Inst, N); 432 else 433 addRegGPRCNoR0Operands(Inst, N); 434 } 435 436 void addRegF4RCOperands(MCInst &Inst, unsigned N) const { 437 assert(N == 1 && "Invalid number of operands!"); 438 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); 439 } 440 441 void addRegF8RCOperands(MCInst &Inst, unsigned N) const { 442 assert(N == 1 && "Invalid number of operands!"); 443 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); 444 } 445 446 void addRegVRRCOperands(MCInst &Inst, unsigned N) const { 447 assert(N == 1 && "Invalid number of operands!"); 448 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()])); 449 } 450 451 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const { 452 assert(N == 1 && "Invalid number of operands!"); 453 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()])); 454 } 455 456 void addRegCRRCOperands(MCInst &Inst, unsigned N) const { 457 assert(N == 1 && "Invalid number of operands!"); 458 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()])); 459 } 460 461 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const { 462 assert(N == 1 && "Invalid number of operands!"); 463 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()])); 464 } 465 466 void addImmOperands(MCInst &Inst, unsigned N) const { 467 assert(N == 1 && "Invalid number of operands!"); 468 if (Kind == Immediate) 469 Inst.addOperand(MCOperand::CreateImm(getImm())); 470 else 471 Inst.addOperand(MCOperand::CreateExpr(getExpr())); 472 } 473 474 void addBranchTargetOperands(MCInst &Inst, unsigned N) const { 475 assert(N == 1 && "Invalid number of operands!"); 476 if (Kind == Immediate) 477 Inst.addOperand(MCOperand::CreateImm(getImm() / 4)); 478 else 479 Inst.addOperand(MCOperand::CreateExpr(getExpr())); 480 } 481 482 void addTLSRegOperands(MCInst &Inst, unsigned N) const { 483 assert(N == 1 && "Invalid number of operands!"); 484 Inst.addOperand(MCOperand::CreateExpr(getTLSReg())); 485 } 486 487 StringRef getToken() const { 488 assert(Kind == Token && "Invalid access!"); 489 return StringRef(Tok.Data, Tok.Length); 490 } 491 492 virtual void print(raw_ostream &OS) const; 493 494 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) { 495 PPCOperand *Op = new PPCOperand(Token); 496 Op->Tok.Data = Str.data(); 497 Op->Tok.Length = Str.size(); 498 Op->StartLoc = S; 499 Op->EndLoc = S; 500 Op->IsPPC64 = IsPPC64; 501 return Op; 502 } 503 504 static PPCOperand *CreateTokenWithStringCopy(StringRef Str, SMLoc S, 505 bool IsPPC64) { 506 // Allocate extra memory for the string and copy it. 507 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size()); 508 PPCOperand *Op = new (Mem) PPCOperand(Token); 509 Op->Tok.Data = (const char *)(Op + 1); 510 Op->Tok.Length = Str.size(); 511 std::memcpy((char *)(Op + 1), Str.data(), Str.size()); 512 Op->StartLoc = S; 513 Op->EndLoc = S; 514 Op->IsPPC64 = IsPPC64; 515 return Op; 516 } 517 518 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) { 519 PPCOperand *Op = new PPCOperand(Immediate); 520 Op->Imm.Val = Val; 521 Op->StartLoc = S; 522 Op->EndLoc = E; 523 Op->IsPPC64 = IsPPC64; 524 return Op; 525 } 526 527 static PPCOperand *CreateExpr(const MCExpr *Val, 528 SMLoc S, SMLoc E, bool IsPPC64) { 529 PPCOperand *Op = new PPCOperand(Expression); 530 Op->Expr.Val = Val; 531 Op->Expr.CRVal = EvaluateCRExpr(Val); 532 Op->StartLoc = S; 533 Op->EndLoc = E; 534 Op->IsPPC64 = IsPPC64; 535 return Op; 536 } 537 538 static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym, 539 SMLoc S, SMLoc E, bool IsPPC64) { 540 PPCOperand *Op = new PPCOperand(TLSRegister); 541 Op->TLSReg.Sym = Sym; 542 Op->StartLoc = S; 543 Op->EndLoc = E; 544 Op->IsPPC64 = IsPPC64; 545 return Op; 546 } 547 548 static PPCOperand *CreateFromMCExpr(const MCExpr *Val, 549 SMLoc S, SMLoc E, bool IsPPC64) { 550 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val)) 551 return CreateImm(CE->getValue(), S, E, IsPPC64); 552 553 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val)) 554 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS) 555 return CreateTLSReg(SRE, S, E, IsPPC64); 556 557 return CreateExpr(Val, S, E, IsPPC64); 558 } 559 }; 560 561 } // end anonymous namespace. 562 563 void PPCOperand::print(raw_ostream &OS) const { 564 switch (Kind) { 565 case Token: 566 OS << "'" << getToken() << "'"; 567 break; 568 case Immediate: 569 OS << getImm(); 570 break; 571 case Expression: 572 getExpr()->print(OS); 573 break; 574 case TLSRegister: 575 getTLSReg()->print(OS); 576 break; 577 } 578 } 579 580 581 void PPCAsmParser:: 582 ProcessInstruction(MCInst &Inst, 583 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 584 int Opcode = Inst.getOpcode(); 585 switch (Opcode) { 586 case PPC::LAx: { 587 MCInst TmpInst; 588 TmpInst.setOpcode(PPC::LA); 589 TmpInst.addOperand(Inst.getOperand(0)); 590 TmpInst.addOperand(Inst.getOperand(2)); 591 TmpInst.addOperand(Inst.getOperand(1)); 592 Inst = TmpInst; 593 break; 594 } 595 case PPC::SUBI: { 596 MCInst TmpInst; 597 int64_t N = Inst.getOperand(2).getImm(); 598 TmpInst.setOpcode(PPC::ADDI); 599 TmpInst.addOperand(Inst.getOperand(0)); 600 TmpInst.addOperand(Inst.getOperand(1)); 601 TmpInst.addOperand(MCOperand::CreateImm(-N)); 602 Inst = TmpInst; 603 break; 604 } 605 case PPC::SUBIS: { 606 MCInst TmpInst; 607 int64_t N = Inst.getOperand(2).getImm(); 608 TmpInst.setOpcode(PPC::ADDIS); 609 TmpInst.addOperand(Inst.getOperand(0)); 610 TmpInst.addOperand(Inst.getOperand(1)); 611 TmpInst.addOperand(MCOperand::CreateImm(-N)); 612 Inst = TmpInst; 613 break; 614 } 615 case PPC::SUBIC: { 616 MCInst TmpInst; 617 int64_t N = Inst.getOperand(2).getImm(); 618 TmpInst.setOpcode(PPC::ADDIC); 619 TmpInst.addOperand(Inst.getOperand(0)); 620 TmpInst.addOperand(Inst.getOperand(1)); 621 TmpInst.addOperand(MCOperand::CreateImm(-N)); 622 Inst = TmpInst; 623 break; 624 } 625 case PPC::SUBICo: { 626 MCInst TmpInst; 627 int64_t N = Inst.getOperand(2).getImm(); 628 TmpInst.setOpcode(PPC::ADDICo); 629 TmpInst.addOperand(Inst.getOperand(0)); 630 TmpInst.addOperand(Inst.getOperand(1)); 631 TmpInst.addOperand(MCOperand::CreateImm(-N)); 632 Inst = TmpInst; 633 break; 634 } 635 case PPC::EXTLWI: 636 case PPC::EXTLWIo: { 637 MCInst TmpInst; 638 int64_t N = Inst.getOperand(2).getImm(); 639 int64_t B = Inst.getOperand(3).getImm(); 640 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo); 641 TmpInst.addOperand(Inst.getOperand(0)); 642 TmpInst.addOperand(Inst.getOperand(1)); 643 TmpInst.addOperand(MCOperand::CreateImm(B)); 644 TmpInst.addOperand(MCOperand::CreateImm(0)); 645 TmpInst.addOperand(MCOperand::CreateImm(N - 1)); 646 Inst = TmpInst; 647 break; 648 } 649 case PPC::EXTRWI: 650 case PPC::EXTRWIo: { 651 MCInst TmpInst; 652 int64_t N = Inst.getOperand(2).getImm(); 653 int64_t B = Inst.getOperand(3).getImm(); 654 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo); 655 TmpInst.addOperand(Inst.getOperand(0)); 656 TmpInst.addOperand(Inst.getOperand(1)); 657 TmpInst.addOperand(MCOperand::CreateImm(B + N)); 658 TmpInst.addOperand(MCOperand::CreateImm(32 - N)); 659 TmpInst.addOperand(MCOperand::CreateImm(31)); 660 Inst = TmpInst; 661 break; 662 } 663 case PPC::INSLWI: 664 case PPC::INSLWIo: { 665 MCInst TmpInst; 666 int64_t N = Inst.getOperand(2).getImm(); 667 int64_t B = Inst.getOperand(3).getImm(); 668 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo); 669 TmpInst.addOperand(Inst.getOperand(0)); 670 TmpInst.addOperand(Inst.getOperand(0)); 671 TmpInst.addOperand(Inst.getOperand(1)); 672 TmpInst.addOperand(MCOperand::CreateImm(32 - B)); 673 TmpInst.addOperand(MCOperand::CreateImm(B)); 674 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1)); 675 Inst = TmpInst; 676 break; 677 } 678 case PPC::INSRWI: 679 case PPC::INSRWIo: { 680 MCInst TmpInst; 681 int64_t N = Inst.getOperand(2).getImm(); 682 int64_t B = Inst.getOperand(3).getImm(); 683 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo); 684 TmpInst.addOperand(Inst.getOperand(0)); 685 TmpInst.addOperand(Inst.getOperand(0)); 686 TmpInst.addOperand(Inst.getOperand(1)); 687 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N))); 688 TmpInst.addOperand(MCOperand::CreateImm(B)); 689 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1)); 690 Inst = TmpInst; 691 break; 692 } 693 case PPC::ROTRWI: 694 case PPC::ROTRWIo: { 695 MCInst TmpInst; 696 int64_t N = Inst.getOperand(2).getImm(); 697 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo); 698 TmpInst.addOperand(Inst.getOperand(0)); 699 TmpInst.addOperand(Inst.getOperand(1)); 700 TmpInst.addOperand(MCOperand::CreateImm(32 - N)); 701 TmpInst.addOperand(MCOperand::CreateImm(0)); 702 TmpInst.addOperand(MCOperand::CreateImm(31)); 703 Inst = TmpInst; 704 break; 705 } 706 case PPC::SLWI: 707 case PPC::SLWIo: { 708 MCInst TmpInst; 709 int64_t N = Inst.getOperand(2).getImm(); 710 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo); 711 TmpInst.addOperand(Inst.getOperand(0)); 712 TmpInst.addOperand(Inst.getOperand(1)); 713 TmpInst.addOperand(MCOperand::CreateImm(N)); 714 TmpInst.addOperand(MCOperand::CreateImm(0)); 715 TmpInst.addOperand(MCOperand::CreateImm(31 - N)); 716 Inst = TmpInst; 717 break; 718 } 719 case PPC::SRWI: 720 case PPC::SRWIo: { 721 MCInst TmpInst; 722 int64_t N = Inst.getOperand(2).getImm(); 723 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo); 724 TmpInst.addOperand(Inst.getOperand(0)); 725 TmpInst.addOperand(Inst.getOperand(1)); 726 TmpInst.addOperand(MCOperand::CreateImm(32 - N)); 727 TmpInst.addOperand(MCOperand::CreateImm(N)); 728 TmpInst.addOperand(MCOperand::CreateImm(31)); 729 Inst = TmpInst; 730 break; 731 } 732 case PPC::CLRRWI: 733 case PPC::CLRRWIo: { 734 MCInst TmpInst; 735 int64_t N = Inst.getOperand(2).getImm(); 736 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo); 737 TmpInst.addOperand(Inst.getOperand(0)); 738 TmpInst.addOperand(Inst.getOperand(1)); 739 TmpInst.addOperand(MCOperand::CreateImm(0)); 740 TmpInst.addOperand(MCOperand::CreateImm(0)); 741 TmpInst.addOperand(MCOperand::CreateImm(31 - N)); 742 Inst = TmpInst; 743 break; 744 } 745 case PPC::CLRLSLWI: 746 case PPC::CLRLSLWIo: { 747 MCInst TmpInst; 748 int64_t B = Inst.getOperand(2).getImm(); 749 int64_t N = Inst.getOperand(3).getImm(); 750 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo); 751 TmpInst.addOperand(Inst.getOperand(0)); 752 TmpInst.addOperand(Inst.getOperand(1)); 753 TmpInst.addOperand(MCOperand::CreateImm(N)); 754 TmpInst.addOperand(MCOperand::CreateImm(B - N)); 755 TmpInst.addOperand(MCOperand::CreateImm(31 - N)); 756 Inst = TmpInst; 757 break; 758 } 759 case PPC::EXTLDI: 760 case PPC::EXTLDIo: { 761 MCInst TmpInst; 762 int64_t N = Inst.getOperand(2).getImm(); 763 int64_t B = Inst.getOperand(3).getImm(); 764 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo); 765 TmpInst.addOperand(Inst.getOperand(0)); 766 TmpInst.addOperand(Inst.getOperand(1)); 767 TmpInst.addOperand(MCOperand::CreateImm(B)); 768 TmpInst.addOperand(MCOperand::CreateImm(N - 1)); 769 Inst = TmpInst; 770 break; 771 } 772 case PPC::EXTRDI: 773 case PPC::EXTRDIo: { 774 MCInst TmpInst; 775 int64_t N = Inst.getOperand(2).getImm(); 776 int64_t B = Inst.getOperand(3).getImm(); 777 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo); 778 TmpInst.addOperand(Inst.getOperand(0)); 779 TmpInst.addOperand(Inst.getOperand(1)); 780 TmpInst.addOperand(MCOperand::CreateImm(B + N)); 781 TmpInst.addOperand(MCOperand::CreateImm(64 - N)); 782 Inst = TmpInst; 783 break; 784 } 785 case PPC::INSRDI: 786 case PPC::INSRDIo: { 787 MCInst TmpInst; 788 int64_t N = Inst.getOperand(2).getImm(); 789 int64_t B = Inst.getOperand(3).getImm(); 790 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo); 791 TmpInst.addOperand(Inst.getOperand(0)); 792 TmpInst.addOperand(Inst.getOperand(0)); 793 TmpInst.addOperand(Inst.getOperand(1)); 794 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N))); 795 TmpInst.addOperand(MCOperand::CreateImm(B)); 796 Inst = TmpInst; 797 break; 798 } 799 case PPC::ROTRDI: 800 case PPC::ROTRDIo: { 801 MCInst TmpInst; 802 int64_t N = Inst.getOperand(2).getImm(); 803 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo); 804 TmpInst.addOperand(Inst.getOperand(0)); 805 TmpInst.addOperand(Inst.getOperand(1)); 806 TmpInst.addOperand(MCOperand::CreateImm(64 - N)); 807 TmpInst.addOperand(MCOperand::CreateImm(0)); 808 Inst = TmpInst; 809 break; 810 } 811 case PPC::SLDI: 812 case PPC::SLDIo: { 813 MCInst TmpInst; 814 int64_t N = Inst.getOperand(2).getImm(); 815 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo); 816 TmpInst.addOperand(Inst.getOperand(0)); 817 TmpInst.addOperand(Inst.getOperand(1)); 818 TmpInst.addOperand(MCOperand::CreateImm(N)); 819 TmpInst.addOperand(MCOperand::CreateImm(63 - N)); 820 Inst = TmpInst; 821 break; 822 } 823 case PPC::SRDI: 824 case PPC::SRDIo: { 825 MCInst TmpInst; 826 int64_t N = Inst.getOperand(2).getImm(); 827 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo); 828 TmpInst.addOperand(Inst.getOperand(0)); 829 TmpInst.addOperand(Inst.getOperand(1)); 830 TmpInst.addOperand(MCOperand::CreateImm(64 - N)); 831 TmpInst.addOperand(MCOperand::CreateImm(N)); 832 Inst = TmpInst; 833 break; 834 } 835 case PPC::CLRRDI: 836 case PPC::CLRRDIo: { 837 MCInst TmpInst; 838 int64_t N = Inst.getOperand(2).getImm(); 839 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo); 840 TmpInst.addOperand(Inst.getOperand(0)); 841 TmpInst.addOperand(Inst.getOperand(1)); 842 TmpInst.addOperand(MCOperand::CreateImm(0)); 843 TmpInst.addOperand(MCOperand::CreateImm(63 - N)); 844 Inst = TmpInst; 845 break; 846 } 847 case PPC::CLRLSLDI: 848 case PPC::CLRLSLDIo: { 849 MCInst TmpInst; 850 int64_t B = Inst.getOperand(2).getImm(); 851 int64_t N = Inst.getOperand(3).getImm(); 852 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo); 853 TmpInst.addOperand(Inst.getOperand(0)); 854 TmpInst.addOperand(Inst.getOperand(1)); 855 TmpInst.addOperand(MCOperand::CreateImm(N)); 856 TmpInst.addOperand(MCOperand::CreateImm(B - N)); 857 Inst = TmpInst; 858 break; 859 } 860 } 861 } 862 863 bool PPCAsmParser:: 864 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 865 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 866 MCStreamer &Out, unsigned &ErrorInfo, 867 bool MatchingInlineAsm) { 868 MCInst Inst; 869 870 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { 871 default: break; 872 case Match_Success: 873 // Post-process instructions (typically extended mnemonics) 874 ProcessInstruction(Inst, Operands); 875 Inst.setLoc(IDLoc); 876 Out.EmitInstruction(Inst); 877 return false; 878 case Match_MissingFeature: 879 return Error(IDLoc, "instruction use requires an option to be enabled"); 880 case Match_MnemonicFail: 881 return Error(IDLoc, "unrecognized instruction mnemonic"); 882 case Match_InvalidOperand: { 883 SMLoc ErrorLoc = IDLoc; 884 if (ErrorInfo != ~0U) { 885 if (ErrorInfo >= Operands.size()) 886 return Error(IDLoc, "too few operands for instruction"); 887 888 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc(); 889 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 890 } 891 892 return Error(ErrorLoc, "invalid operand for instruction"); 893 } 894 } 895 896 llvm_unreachable("Implement any new match types added!"); 897 } 898 899 bool PPCAsmParser:: 900 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) { 901 if (Tok.is(AsmToken::Identifier)) { 902 StringRef Name = Tok.getString(); 903 904 if (Name.equals_lower("lr")) { 905 RegNo = isPPC64()? PPC::LR8 : PPC::LR; 906 IntVal = 8; 907 return false; 908 } else if (Name.equals_lower("ctr")) { 909 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR; 910 IntVal = 9; 911 return false; 912 } else if (Name.equals_lower("vrsave")) { 913 RegNo = PPC::VRSAVE; 914 IntVal = 256; 915 return false; 916 } else if (Name.startswith_lower("r") && 917 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 918 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal]; 919 return false; 920 } else if (Name.startswith_lower("f") && 921 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 922 RegNo = FRegs[IntVal]; 923 return false; 924 } else if (Name.startswith_lower("v") && 925 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 926 RegNo = VRegs[IntVal]; 927 return false; 928 } else if (Name.startswith_lower("cr") && 929 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { 930 RegNo = CRRegs[IntVal]; 931 return false; 932 } 933 } 934 935 return true; 936 } 937 938 bool PPCAsmParser:: 939 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 940 const AsmToken &Tok = Parser.getTok(); 941 StartLoc = Tok.getLoc(); 942 EndLoc = Tok.getEndLoc(); 943 RegNo = 0; 944 int64_t IntVal; 945 946 if (!MatchRegisterName(Tok, RegNo, IntVal)) { 947 Parser.Lex(); // Eat identifier token. 948 return false; 949 } 950 951 return Error(StartLoc, "invalid register name"); 952 } 953 954 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan 955 /// the expression and check for VK_PPC_LO/HI/HA 956 /// symbol variants. If all symbols with modifier use the same 957 /// variant, return the corresponding PPCMCExpr::VariantKind, 958 /// and a modified expression using the default symbol variant. 959 /// Otherwise, return NULL. 960 const MCExpr *PPCAsmParser:: 961 ExtractModifierFromExpr(const MCExpr *E, 962 PPCMCExpr::VariantKind &Variant) { 963 MCContext &Context = getParser().getContext(); 964 Variant = PPCMCExpr::VK_PPC_None; 965 966 switch (E->getKind()) { 967 case MCExpr::Target: 968 case MCExpr::Constant: 969 return 0; 970 971 case MCExpr::SymbolRef: { 972 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 973 974 switch (SRE->getKind()) { 975 case MCSymbolRefExpr::VK_PPC_LO: 976 Variant = PPCMCExpr::VK_PPC_LO; 977 break; 978 case MCSymbolRefExpr::VK_PPC_HI: 979 Variant = PPCMCExpr::VK_PPC_HI; 980 break; 981 case MCSymbolRefExpr::VK_PPC_HA: 982 Variant = PPCMCExpr::VK_PPC_HA; 983 break; 984 case MCSymbolRefExpr::VK_PPC_HIGHER: 985 Variant = PPCMCExpr::VK_PPC_HIGHER; 986 break; 987 case MCSymbolRefExpr::VK_PPC_HIGHERA: 988 Variant = PPCMCExpr::VK_PPC_HIGHERA; 989 break; 990 case MCSymbolRefExpr::VK_PPC_HIGHEST: 991 Variant = PPCMCExpr::VK_PPC_HIGHEST; 992 break; 993 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 994 Variant = PPCMCExpr::VK_PPC_HIGHESTA; 995 break; 996 default: 997 return 0; 998 } 999 1000 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context); 1001 } 1002 1003 case MCExpr::Unary: { 1004 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1005 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant); 1006 if (!Sub) 1007 return 0; 1008 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context); 1009 } 1010 1011 case MCExpr::Binary: { 1012 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1013 PPCMCExpr::VariantKind LHSVariant, RHSVariant; 1014 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant); 1015 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant); 1016 1017 if (!LHS && !RHS) 1018 return 0; 1019 1020 if (!LHS) LHS = BE->getLHS(); 1021 if (!RHS) RHS = BE->getRHS(); 1022 1023 if (LHSVariant == PPCMCExpr::VK_PPC_None) 1024 Variant = RHSVariant; 1025 else if (RHSVariant == PPCMCExpr::VK_PPC_None) 1026 Variant = LHSVariant; 1027 else if (LHSVariant == RHSVariant) 1028 Variant = LHSVariant; 1029 else 1030 return 0; 1031 1032 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context); 1033 } 1034 } 1035 1036 llvm_unreachable("Invalid expression kind!"); 1037 } 1038 1039 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace 1040 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having 1041 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT. 1042 /// FIXME: This is a hack. 1043 const MCExpr *PPCAsmParser:: 1044 FixupVariantKind(const MCExpr *E) { 1045 MCContext &Context = getParser().getContext(); 1046 1047 switch (E->getKind()) { 1048 case MCExpr::Target: 1049 case MCExpr::Constant: 1050 return E; 1051 1052 case MCExpr::SymbolRef: { 1053 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1054 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; 1055 1056 switch (SRE->getKind()) { 1057 case MCSymbolRefExpr::VK_TLSGD: 1058 Variant = MCSymbolRefExpr::VK_PPC_TLSGD; 1059 break; 1060 case MCSymbolRefExpr::VK_TLSLD: 1061 Variant = MCSymbolRefExpr::VK_PPC_TLSLD; 1062 break; 1063 default: 1064 return E; 1065 } 1066 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context); 1067 } 1068 1069 case MCExpr::Unary: { 1070 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1071 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr()); 1072 if (Sub == UE->getSubExpr()) 1073 return E; 1074 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context); 1075 } 1076 1077 case MCExpr::Binary: { 1078 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1079 const MCExpr *LHS = FixupVariantKind(BE->getLHS()); 1080 const MCExpr *RHS = FixupVariantKind(BE->getRHS()); 1081 if (LHS == BE->getLHS() && RHS == BE->getRHS()) 1082 return E; 1083 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context); 1084 } 1085 } 1086 1087 llvm_unreachable("Invalid expression kind!"); 1088 } 1089 1090 /// ParseExpression. This differs from the default "parseExpression" in that 1091 /// it handles modifiers. 1092 bool PPCAsmParser:: 1093 ParseExpression(const MCExpr *&EVal) { 1094 1095 if (isDarwin()) 1096 return ParseDarwinExpression(EVal); 1097 1098 // (ELF Platforms) 1099 // Handle \code @l/@ha \endcode 1100 if (getParser().parseExpression(EVal)) 1101 return true; 1102 1103 EVal = FixupVariantKind(EVal); 1104 1105 PPCMCExpr::VariantKind Variant; 1106 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant); 1107 if (E) 1108 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext()); 1109 1110 return false; 1111 } 1112 1113 /// ParseDarwinExpression. (MachO Platforms) 1114 /// This differs from the default "parseExpression" in that it handles detection 1115 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present, 1116 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO 1117 /// syntax form so it is done here. TODO: Determine if there is merit in arranging 1118 /// for this to be done at a higher level. 1119 bool PPCAsmParser:: 1120 ParseDarwinExpression(const MCExpr *&EVal) { 1121 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None; 1122 switch (getLexer().getKind()) { 1123 default: 1124 break; 1125 case AsmToken::Identifier: 1126 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus 1127 // something starting with any other char should be part of the 1128 // asm syntax. If handwritten asm includes an identifier like lo16, 1129 // then all bets are off - but no-one would do that, right? 1130 StringRef poss = Parser.getTok().getString(); 1131 if (poss.equals_lower("lo16")) { 1132 Variant = PPCMCExpr::VK_PPC_LO; 1133 } else if (poss.equals_lower("hi16")) { 1134 Variant = PPCMCExpr::VK_PPC_HI; 1135 } else if (poss.equals_lower("ha16")) { 1136 Variant = PPCMCExpr::VK_PPC_HA; 1137 } 1138 if (Variant != PPCMCExpr::VK_PPC_None) { 1139 Parser.Lex(); // Eat the xx16 1140 if (getLexer().isNot(AsmToken::LParen)) 1141 return Error(Parser.getTok().getLoc(), "expected '('"); 1142 Parser.Lex(); // Eat the '(' 1143 } 1144 break; 1145 } 1146 1147 if (getParser().parseExpression(EVal)) 1148 return true; 1149 1150 if (Variant != PPCMCExpr::VK_PPC_None) { 1151 if (getLexer().isNot(AsmToken::RParen)) 1152 return Error(Parser.getTok().getLoc(), "expected ')'"); 1153 Parser.Lex(); // Eat the ')' 1154 EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext()); 1155 } 1156 return false; 1157 } 1158 1159 /// ParseOperand 1160 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and 1161 /// rNN for MachO. 1162 bool PPCAsmParser:: 1163 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1164 SMLoc S = Parser.getTok().getLoc(); 1165 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1166 const MCExpr *EVal; 1167 PPCOperand *Op; 1168 1169 // Attempt to parse the next token as an immediate 1170 switch (getLexer().getKind()) { 1171 // Special handling for register names. These are interpreted 1172 // as immediates corresponding to the register number. 1173 case AsmToken::Percent: 1174 Parser.Lex(); // Eat the '%'. 1175 unsigned RegNo; 1176 int64_t IntVal; 1177 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) { 1178 Parser.Lex(); // Eat the identifier token. 1179 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64()); 1180 Operands.push_back(Op); 1181 return false; 1182 } 1183 return Error(S, "invalid register name"); 1184 1185 case AsmToken::Identifier: 1186 // Note that non-register-name identifiers from the compiler will begin 1187 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include 1188 // identifiers like r31foo - so we fall through in the event that parsing 1189 // a register name fails. 1190 if (isDarwin()) { 1191 unsigned RegNo; 1192 int64_t IntVal; 1193 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) { 1194 Parser.Lex(); // Eat the identifier token. 1195 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64()); 1196 Operands.push_back(Op); 1197 return false; 1198 } 1199 } 1200 // Fall-through to process non-register-name identifiers as expression. 1201 // All other expressions 1202 case AsmToken::LParen: 1203 case AsmToken::Plus: 1204 case AsmToken::Minus: 1205 case AsmToken::Integer: 1206 case AsmToken::Dot: 1207 case AsmToken::Dollar: 1208 if (!ParseExpression(EVal)) 1209 break; 1210 /* fall through */ 1211 default: 1212 return Error(S, "unknown operand"); 1213 } 1214 1215 // Push the parsed operand into the list of operands 1216 Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()); 1217 Operands.push_back(Op); 1218 1219 // Check whether this is a TLS call expression 1220 bool TLSCall = false; 1221 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal)) 1222 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr"; 1223 1224 if (TLSCall && getLexer().is(AsmToken::LParen)) { 1225 const MCExpr *TLSSym; 1226 1227 Parser.Lex(); // Eat the '('. 1228 S = Parser.getTok().getLoc(); 1229 if (ParseExpression(TLSSym)) 1230 return Error(S, "invalid TLS call expression"); 1231 if (getLexer().isNot(AsmToken::RParen)) 1232 return Error(Parser.getTok().getLoc(), "missing ')'"); 1233 E = Parser.getTok().getLoc(); 1234 Parser.Lex(); // Eat the ')'. 1235 1236 Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()); 1237 Operands.push_back(Op); 1238 } 1239 1240 // Otherwise, check for D-form memory operands 1241 if (!TLSCall && getLexer().is(AsmToken::LParen)) { 1242 Parser.Lex(); // Eat the '('. 1243 S = Parser.getTok().getLoc(); 1244 1245 int64_t IntVal; 1246 switch (getLexer().getKind()) { 1247 case AsmToken::Percent: 1248 Parser.Lex(); // Eat the '%'. 1249 unsigned RegNo; 1250 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal)) 1251 return Error(S, "invalid register name"); 1252 Parser.Lex(); // Eat the identifier token. 1253 break; 1254 1255 case AsmToken::Integer: 1256 if (!isDarwin()) { 1257 if (getParser().parseAbsoluteExpression(IntVal) || 1258 IntVal < 0 || IntVal > 31) 1259 return Error(S, "invalid register number"); 1260 } else { 1261 return Error(S, "unexpected integer value"); 1262 } 1263 break; 1264 1265 case AsmToken::Identifier: 1266 if (isDarwin()) { 1267 unsigned RegNo; 1268 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) { 1269 Parser.Lex(); // Eat the identifier token. 1270 break; 1271 } 1272 } 1273 // Fall-through.. 1274 1275 default: 1276 return Error(S, "invalid memory operand"); 1277 } 1278 1279 if (getLexer().isNot(AsmToken::RParen)) 1280 return Error(Parser.getTok().getLoc(), "missing ')'"); 1281 E = Parser.getTok().getLoc(); 1282 Parser.Lex(); // Eat the ')'. 1283 1284 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64()); 1285 Operands.push_back(Op); 1286 } 1287 1288 return false; 1289 } 1290 1291 /// Parse an instruction mnemonic followed by its operands. 1292 bool PPCAsmParser:: 1293 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, 1294 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1295 // The first operand is the token for the instruction name. 1296 // If the next character is a '+' or '-', we need to add it to the 1297 // instruction name, to match what TableGen is doing. 1298 std::string NewOpcode; 1299 if (getLexer().is(AsmToken::Plus)) { 1300 getLexer().Lex(); 1301 NewOpcode = Name; 1302 NewOpcode += '+'; 1303 Name = NewOpcode; 1304 } 1305 if (getLexer().is(AsmToken::Minus)) { 1306 getLexer().Lex(); 1307 NewOpcode = Name; 1308 NewOpcode += '-'; 1309 Name = NewOpcode; 1310 } 1311 // If the instruction ends in a '.', we need to create a separate 1312 // token for it, to match what TableGen is doing. 1313 size_t Dot = Name.find('.'); 1314 StringRef Mnemonic = Name.slice(0, Dot); 1315 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1316 Operands.push_back( 1317 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64())); 1318 else 1319 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64())); 1320 if (Dot != StringRef::npos) { 1321 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot); 1322 StringRef DotStr = Name.slice(Dot, StringRef::npos); 1323 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1324 Operands.push_back( 1325 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64())); 1326 else 1327 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64())); 1328 } 1329 1330 // If there are no more operands then finish 1331 if (getLexer().is(AsmToken::EndOfStatement)) 1332 return false; 1333 1334 // Parse the first operand 1335 if (ParseOperand(Operands)) 1336 return true; 1337 1338 while (getLexer().isNot(AsmToken::EndOfStatement) && 1339 getLexer().is(AsmToken::Comma)) { 1340 // Consume the comma token 1341 getLexer().Lex(); 1342 1343 // Parse the next operand 1344 if (ParseOperand(Operands)) 1345 return true; 1346 } 1347 1348 return false; 1349 } 1350 1351 /// ParseDirective parses the PPC specific directives 1352 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) { 1353 StringRef IDVal = DirectiveID.getIdentifier(); 1354 if (!isDarwin()) { 1355 if (IDVal == ".word") 1356 return ParseDirectiveWord(2, DirectiveID.getLoc()); 1357 if (IDVal == ".llong") 1358 return ParseDirectiveWord(8, DirectiveID.getLoc()); 1359 if (IDVal == ".tc") 1360 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc()); 1361 if (IDVal == ".machine") 1362 return ParseDirectiveMachine(DirectiveID.getLoc()); 1363 } else { 1364 if (IDVal == ".machine") 1365 return ParseDarwinDirectiveMachine(DirectiveID.getLoc()); 1366 } 1367 return true; 1368 } 1369 1370 /// ParseDirectiveWord 1371 /// ::= .word [ expression (, expression)* ] 1372 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) { 1373 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1374 for (;;) { 1375 const MCExpr *Value; 1376 if (getParser().parseExpression(Value)) 1377 return false; 1378 1379 getParser().getStreamer().EmitValue(Value, Size); 1380 1381 if (getLexer().is(AsmToken::EndOfStatement)) 1382 break; 1383 1384 if (getLexer().isNot(AsmToken::Comma)) 1385 return Error(L, "unexpected token in directive"); 1386 Parser.Lex(); 1387 } 1388 } 1389 1390 Parser.Lex(); 1391 return false; 1392 } 1393 1394 /// ParseDirectiveTC 1395 /// ::= .tc [ symbol (, expression)* ] 1396 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) { 1397 // Skip TC symbol, which is only used with XCOFF. 1398 while (getLexer().isNot(AsmToken::EndOfStatement) 1399 && getLexer().isNot(AsmToken::Comma)) 1400 Parser.Lex(); 1401 if (getLexer().isNot(AsmToken::Comma)) { 1402 Error(L, "unexpected token in directive"); 1403 return false; 1404 } 1405 Parser.Lex(); 1406 1407 // Align to word size. 1408 getParser().getStreamer().EmitValueToAlignment(Size); 1409 1410 // Emit expressions. 1411 return ParseDirectiveWord(Size, L); 1412 } 1413 1414 /// ParseDirectiveMachine (ELF platforms) 1415 /// ::= .machine [ cpu | "push" | "pop" ] 1416 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) { 1417 if (getLexer().isNot(AsmToken::Identifier) && 1418 getLexer().isNot(AsmToken::String)) { 1419 Error(L, "unexpected token in directive"); 1420 return false; 1421 } 1422 1423 StringRef CPU = Parser.getTok().getIdentifier(); 1424 Parser.Lex(); 1425 1426 // FIXME: Right now, the parser always allows any available 1427 // instruction, so the .machine directive is not useful. 1428 // Implement ".machine any" (by doing nothing) for the benefit 1429 // of existing assembler code. Likewise, we can then implement 1430 // ".machine push" and ".machine pop" as no-op. 1431 if (CPU != "any" && CPU != "push" && CPU != "pop") { 1432 Error(L, "unrecognized machine type"); 1433 return false; 1434 } 1435 1436 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1437 Error(L, "unexpected token in directive"); 1438 return false; 1439 } 1440 PPCTargetStreamer &TStreamer = 1441 *static_cast<PPCTargetStreamer *>( 1442 getParser().getStreamer().getTargetStreamer()); 1443 TStreamer.emitMachine(CPU); 1444 1445 return false; 1446 } 1447 1448 /// ParseDarwinDirectiveMachine (Mach-o platforms) 1449 /// ::= .machine cpu-identifier 1450 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) { 1451 if (getLexer().isNot(AsmToken::Identifier) && 1452 getLexer().isNot(AsmToken::String)) { 1453 Error(L, "unexpected token in directive"); 1454 return false; 1455 } 1456 1457 StringRef CPU = Parser.getTok().getIdentifier(); 1458 Parser.Lex(); 1459 1460 // FIXME: this is only the 'default' set of cpu variants. 1461 // However we don't act on this information at present, this is simply 1462 // allowing parsing to proceed with minimal sanity checking. 1463 if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") { 1464 Error(L, "unrecognized cpu type"); 1465 return false; 1466 } 1467 1468 if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) { 1469 Error(L, "wrong cpu type specified for 64bit"); 1470 return false; 1471 } 1472 if (!isPPC64() && CPU == "ppc64") { 1473 Error(L, "wrong cpu type specified for 32bit"); 1474 return false; 1475 } 1476 1477 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1478 Error(L, "unexpected token in directive"); 1479 return false; 1480 } 1481 1482 return false; 1483 } 1484 1485 /// Force static initialization. 1486 extern "C" void LLVMInitializePowerPCAsmParser() { 1487 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target); 1488 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target); 1489 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget); 1490 } 1491 1492 #define GET_REGISTER_MATCHER 1493 #define GET_MATCHER_IMPLEMENTATION 1494 #include "PPCGenAsmMatcher.inc" 1495 1496 // Define this matcher function after the auto-generated include so we 1497 // have the match class enum definitions. 1498 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp, 1499 unsigned Kind) { 1500 // If the kind is a token for a literal immediate, check if our asm 1501 // operand matches. This is for InstAliases which have a fixed-value 1502 // immediate in the syntax. 1503 int64_t ImmVal; 1504 switch (Kind) { 1505 case MCK_0: ImmVal = 0; break; 1506 case MCK_1: ImmVal = 1; break; 1507 case MCK_2: ImmVal = 2; break; 1508 case MCK_3: ImmVal = 3; break; 1509 default: return Match_InvalidOperand; 1510 } 1511 1512 PPCOperand *Op = static_cast<PPCOperand*>(AsmOp); 1513 if (Op->isImm() && Op->getImm() == ImmVal) 1514 return Match_Success; 1515 1516 return Match_InvalidOperand; 1517 } 1518 1519 const MCExpr * 1520 PPCAsmParser::applyModifierToExpr(const MCExpr *E, 1521 MCSymbolRefExpr::VariantKind Variant, 1522 MCContext &Ctx) { 1523 switch (Variant) { 1524 case MCSymbolRefExpr::VK_PPC_LO: 1525 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx); 1526 case MCSymbolRefExpr::VK_PPC_HI: 1527 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx); 1528 case MCSymbolRefExpr::VK_PPC_HA: 1529 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx); 1530 case MCSymbolRefExpr::VK_PPC_HIGHER: 1531 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx); 1532 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1533 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx); 1534 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1535 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx); 1536 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1537 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx); 1538 default: 1539 return 0; 1540 } 1541 } 1542