1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCExpr.h" 10 #include "MCTargetDesc/PPCMCTargetDesc.h" 11 #include "PPCTargetStreamer.h" 12 #include "TargetInfo/PowerPCTargetInfo.h" 13 #include "llvm/ADT/STLExtras.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Twine.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCParser/MCAsmLexer.h" 21 #include "llvm/MC/MCParser/MCAsmParser.h" 22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 23 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 24 #include "llvm/MC/MCStreamer.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/MC/MCSymbolELF.h" 27 #include "llvm/Support/SourceMgr.h" 28 #include "llvm/Support/TargetRegistry.h" 29 #include "llvm/Support/raw_ostream.h" 30 31 using namespace llvm; 32 33 DEFINE_PPC_REGCLASSES; 34 35 // Evaluate an expression containing condition register 36 // or condition register field symbols. Returns positive 37 // value on success, or -1 on error. 38 static int64_t 39 EvaluateCRExpr(const MCExpr *E) { 40 switch (E->getKind()) { 41 case MCExpr::Target: 42 return -1; 43 44 case MCExpr::Constant: { 45 int64_t Res = cast<MCConstantExpr>(E)->getValue(); 46 return Res < 0 ? -1 : Res; 47 } 48 49 case MCExpr::SymbolRef: { 50 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 51 StringRef Name = SRE->getSymbol().getName(); 52 53 if (Name == "lt") return 0; 54 if (Name == "gt") return 1; 55 if (Name == "eq") return 2; 56 if (Name == "so") return 3; 57 if (Name == "un") return 3; 58 59 if (Name == "cr0") return 0; 60 if (Name == "cr1") return 1; 61 if (Name == "cr2") return 2; 62 if (Name == "cr3") return 3; 63 if (Name == "cr4") return 4; 64 if (Name == "cr5") return 5; 65 if (Name == "cr6") return 6; 66 if (Name == "cr7") return 7; 67 68 return -1; 69 } 70 71 case MCExpr::Unary: 72 return -1; 73 74 case MCExpr::Binary: { 75 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 76 int64_t LHSVal = EvaluateCRExpr(BE->getLHS()); 77 int64_t RHSVal = EvaluateCRExpr(BE->getRHS()); 78 int64_t Res; 79 80 if (LHSVal < 0 || RHSVal < 0) 81 return -1; 82 83 switch (BE->getOpcode()) { 84 default: return -1; 85 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break; 86 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break; 87 } 88 89 return Res < 0 ? -1 : Res; 90 } 91 } 92 93 llvm_unreachable("Invalid expression kind!"); 94 } 95 96 namespace { 97 98 struct PPCOperand; 99 100 class PPCAsmParser : public MCTargetAsmParser { 101 bool IsPPC64; 102 bool IsDarwin; 103 104 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); } 105 106 bool isPPC64() const { return IsPPC64; } 107 bool isDarwin() const { return IsDarwin; } 108 109 bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal); 110 111 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 112 113 const MCExpr *ExtractModifierFromExpr(const MCExpr *E, 114 PPCMCExpr::VariantKind &Variant); 115 const MCExpr *FixupVariantKind(const MCExpr *E); 116 bool ParseExpression(const MCExpr *&EVal); 117 bool ParseDarwinExpression(const MCExpr *&EVal); 118 119 bool ParseOperand(OperandVector &Operands); 120 121 bool ParseDirectiveWord(unsigned Size, AsmToken ID); 122 bool ParseDirectiveTC(unsigned Size, AsmToken ID); 123 bool ParseDirectiveMachine(SMLoc L); 124 bool ParseDarwinDirectiveMachine(SMLoc L); 125 bool ParseDirectiveAbiVersion(SMLoc L); 126 bool ParseDirectiveLocalEntry(SMLoc L); 127 128 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 129 OperandVector &Operands, MCStreamer &Out, 130 uint64_t &ErrorInfo, 131 bool MatchingInlineAsm) override; 132 133 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops); 134 135 /// @name Auto-generated Match Functions 136 /// { 137 138 #define GET_ASSEMBLER_HEADER 139 #include "PPCGenAsmMatcher.inc" 140 141 /// } 142 143 144 public: 145 PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &, 146 const MCInstrInfo &MII, const MCTargetOptions &Options) 147 : MCTargetAsmParser(Options, STI, MII) { 148 // Check for 64-bit vs. 32-bit pointer mode. 149 const Triple &TheTriple = STI.getTargetTriple(); 150 IsPPC64 = TheTriple.isPPC64(); 151 IsDarwin = TheTriple.isMacOSX(); 152 // Initialize the set of available features. 153 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 154 } 155 156 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 157 SMLoc NameLoc, OperandVector &Operands) override; 158 159 bool ParseDirective(AsmToken DirectiveID) override; 160 161 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 162 unsigned Kind) override; 163 164 const MCExpr *applyModifierToExpr(const MCExpr *E, 165 MCSymbolRefExpr::VariantKind, 166 MCContext &Ctx) override; 167 }; 168 169 /// PPCOperand - Instances of this class represent a parsed PowerPC machine 170 /// instruction. 171 struct PPCOperand : public MCParsedAsmOperand { 172 enum KindTy { 173 Token, 174 Immediate, 175 ContextImmediate, 176 Expression, 177 TLSRegister 178 } Kind; 179 180 SMLoc StartLoc, EndLoc; 181 bool IsPPC64; 182 183 struct TokOp { 184 const char *Data; 185 unsigned Length; 186 }; 187 188 struct ImmOp { 189 int64_t Val; 190 }; 191 192 struct ExprOp { 193 const MCExpr *Val; 194 int64_t CRVal; // Cached result of EvaluateCRExpr(Val) 195 }; 196 197 struct TLSRegOp { 198 const MCSymbolRefExpr *Sym; 199 }; 200 201 union { 202 struct TokOp Tok; 203 struct ImmOp Imm; 204 struct ExprOp Expr; 205 struct TLSRegOp TLSReg; 206 }; 207 208 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 209 public: 210 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() { 211 Kind = o.Kind; 212 StartLoc = o.StartLoc; 213 EndLoc = o.EndLoc; 214 IsPPC64 = o.IsPPC64; 215 switch (Kind) { 216 case Token: 217 Tok = o.Tok; 218 break; 219 case Immediate: 220 case ContextImmediate: 221 Imm = o.Imm; 222 break; 223 case Expression: 224 Expr = o.Expr; 225 break; 226 case TLSRegister: 227 TLSReg = o.TLSReg; 228 break; 229 } 230 } 231 232 // Disable use of sized deallocation due to overallocation of PPCOperand 233 // objects in CreateTokenWithStringCopy. 234 void operator delete(void *p) { ::operator delete(p); } 235 236 /// getStartLoc - Get the location of the first token of this operand. 237 SMLoc getStartLoc() const override { return StartLoc; } 238 239 /// getEndLoc - Get the location of the last token of this operand. 240 SMLoc getEndLoc() const override { return EndLoc; } 241 242 /// getLocRange - Get the range between the first and last token of this 243 /// operand. 244 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 245 246 /// isPPC64 - True if this operand is for an instruction in 64-bit mode. 247 bool isPPC64() const { return IsPPC64; } 248 249 int64_t getImm() const { 250 assert(Kind == Immediate && "Invalid access!"); 251 return Imm.Val; 252 } 253 int64_t getImmS16Context() const { 254 assert((Kind == Immediate || Kind == ContextImmediate) && 255 "Invalid access!"); 256 if (Kind == Immediate) 257 return Imm.Val; 258 return static_cast<int16_t>(Imm.Val); 259 } 260 int64_t getImmU16Context() const { 261 assert((Kind == Immediate || Kind == ContextImmediate) && 262 "Invalid access!"); 263 return Imm.Val; 264 } 265 266 const MCExpr *getExpr() const { 267 assert(Kind == Expression && "Invalid access!"); 268 return Expr.Val; 269 } 270 271 int64_t getExprCRVal() const { 272 assert(Kind == Expression && "Invalid access!"); 273 return Expr.CRVal; 274 } 275 276 const MCExpr *getTLSReg() const { 277 assert(Kind == TLSRegister && "Invalid access!"); 278 return TLSReg.Sym; 279 } 280 281 unsigned getReg() const override { 282 assert(isRegNumber() && "Invalid access!"); 283 return (unsigned) Imm.Val; 284 } 285 286 unsigned getVSReg() const { 287 assert(isVSRegNumber() && "Invalid access!"); 288 return (unsigned) Imm.Val; 289 } 290 291 unsigned getCCReg() const { 292 assert(isCCRegNumber() && "Invalid access!"); 293 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 294 } 295 296 unsigned getCRBit() const { 297 assert(isCRBitNumber() && "Invalid access!"); 298 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 299 } 300 301 unsigned getCRBitMask() const { 302 assert(isCRBitMask() && "Invalid access!"); 303 return 7 - countTrailingZeros<uint64_t>(Imm.Val); 304 } 305 306 bool isToken() const override { return Kind == Token; } 307 bool isImm() const override { 308 return Kind == Immediate || Kind == Expression; 309 } 310 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } 311 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } 312 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } 313 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } 314 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } 315 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } 316 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } 317 bool isU6ImmX2() const { return Kind == Immediate && 318 isUInt<6>(getImm()) && 319 (getImm() & 1) == 0; } 320 bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); } 321 bool isU7ImmX4() const { return Kind == Immediate && 322 isUInt<7>(getImm()) && 323 (getImm() & 3) == 0; } 324 bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); } 325 bool isU8ImmX8() const { return Kind == Immediate && 326 isUInt<8>(getImm()) && 327 (getImm() & 7) == 0; } 328 329 bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); } 330 bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); } 331 bool isU16Imm() const { 332 switch (Kind) { 333 case Expression: 334 return true; 335 case Immediate: 336 case ContextImmediate: 337 return isUInt<16>(getImmU16Context()); 338 default: 339 return false; 340 } 341 } 342 bool isS16Imm() const { 343 switch (Kind) { 344 case Expression: 345 return true; 346 case Immediate: 347 case ContextImmediate: 348 return isInt<16>(getImmS16Context()); 349 default: 350 return false; 351 } 352 } 353 bool isS16ImmX4() const { return Kind == Expression || 354 (Kind == Immediate && isInt<16>(getImm()) && 355 (getImm() & 3) == 0); } 356 bool isS16ImmX16() const { return Kind == Expression || 357 (Kind == Immediate && isInt<16>(getImm()) && 358 (getImm() & 15) == 0); } 359 bool isS34Imm() const { 360 // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit 361 // ContextImmediate is needed. 362 return Kind == Expression || (Kind == Immediate && isInt<34>(getImm())); 363 } 364 365 bool isS17Imm() const { 366 switch (Kind) { 367 case Expression: 368 return true; 369 case Immediate: 370 case ContextImmediate: 371 return isInt<17>(getImmS16Context()); 372 default: 373 return false; 374 } 375 } 376 bool isTLSReg() const { return Kind == TLSRegister; } 377 bool isDirectBr() const { 378 if (Kind == Expression) 379 return true; 380 if (Kind != Immediate) 381 return false; 382 // Operand must be 64-bit aligned, signed 27-bit immediate. 383 if ((getImm() & 3) != 0) 384 return false; 385 if (isInt<26>(getImm())) 386 return true; 387 if (!IsPPC64) { 388 // In 32-bit mode, large 32-bit quantities wrap around. 389 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm()))) 390 return true; 391 } 392 return false; 393 } 394 bool isCondBr() const { return Kind == Expression || 395 (Kind == Immediate && isInt<16>(getImm()) && 396 (getImm() & 3) == 0); } 397 bool isImmZero() const { return Kind == Immediate && getImm() == 0; } 398 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } 399 bool isVSRegNumber() const { 400 return Kind == Immediate && isUInt<6>(getImm()); 401 } 402 bool isCCRegNumber() const { return (Kind == Expression 403 && isUInt<3>(getExprCRVal())) || 404 (Kind == Immediate 405 && isUInt<3>(getImm())); } 406 bool isCRBitNumber() const { return (Kind == Expression 407 && isUInt<5>(getExprCRVal())) || 408 (Kind == Immediate 409 && isUInt<5>(getImm())); } 410 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) && 411 isPowerOf2_32(getImm()); } 412 bool isATBitsAsHint() const { return false; } 413 bool isMem() const override { return false; } 414 bool isReg() const override { return false; } 415 416 void addRegOperands(MCInst &Inst, unsigned N) const { 417 llvm_unreachable("addRegOperands"); 418 } 419 420 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { 421 assert(N == 1 && "Invalid number of operands!"); 422 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 423 } 424 425 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { 426 assert(N == 1 && "Invalid number of operands!"); 427 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); 428 } 429 430 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { 431 assert(N == 1 && "Invalid number of operands!"); 432 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); 433 } 434 435 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { 436 assert(N == 1 && "Invalid number of operands!"); 437 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); 438 } 439 440 void addRegGxRCOperands(MCInst &Inst, unsigned N) const { 441 if (isPPC64()) 442 addRegG8RCOperands(Inst, N); 443 else 444 addRegGPRCOperands(Inst, N); 445 } 446 447 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const { 448 if (isPPC64()) 449 addRegG8RCNoX0Operands(Inst, N); 450 else 451 addRegGPRCNoR0Operands(Inst, N); 452 } 453 454 void addRegF4RCOperands(MCInst &Inst, unsigned N) const { 455 assert(N == 1 && "Invalid number of operands!"); 456 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 457 } 458 459 void addRegF8RCOperands(MCInst &Inst, unsigned N) const { 460 assert(N == 1 && "Invalid number of operands!"); 461 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 462 } 463 464 void addRegVFRCOperands(MCInst &Inst, unsigned N) const { 465 assert(N == 1 && "Invalid number of operands!"); 466 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); 467 } 468 469 void addRegVRRCOperands(MCInst &Inst, unsigned N) const { 470 assert(N == 1 && "Invalid number of operands!"); 471 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); 472 } 473 474 void addRegVSRCOperands(MCInst &Inst, unsigned N) const { 475 assert(N == 1 && "Invalid number of operands!"); 476 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); 477 } 478 479 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const { 480 assert(N == 1 && "Invalid number of operands!"); 481 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); 482 } 483 484 void addRegVSSRCOperands(MCInst &Inst, unsigned N) const { 485 assert(N == 1 && "Invalid number of operands!"); 486 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); 487 } 488 489 void addRegQFRCOperands(MCInst &Inst, unsigned N) const { 490 assert(N == 1 && "Invalid number of operands!"); 491 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()])); 492 } 493 494 void addRegQSRCOperands(MCInst &Inst, unsigned N) const { 495 assert(N == 1 && "Invalid number of operands!"); 496 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()])); 497 } 498 499 void addRegQBRCOperands(MCInst &Inst, unsigned N) const { 500 assert(N == 1 && "Invalid number of operands!"); 501 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()])); 502 } 503 504 void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const { 505 assert(N == 1 && "Invalid number of operands!"); 506 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 507 } 508 509 void addRegSPERCOperands(MCInst &Inst, unsigned N) const { 510 assert(N == 1 && "Invalid number of operands!"); 511 Inst.addOperand(MCOperand::createReg(SPERegs[getReg()])); 512 } 513 514 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const { 515 assert(N == 1 && "Invalid number of operands!"); 516 Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()])); 517 } 518 519 void addRegCRRCOperands(MCInst &Inst, unsigned N) const { 520 assert(N == 1 && "Invalid number of operands!"); 521 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()])); 522 } 523 524 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const { 525 assert(N == 1 && "Invalid number of operands!"); 526 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()])); 527 } 528 529 void addImmOperands(MCInst &Inst, unsigned N) const { 530 assert(N == 1 && "Invalid number of operands!"); 531 if (Kind == Immediate) 532 Inst.addOperand(MCOperand::createImm(getImm())); 533 else 534 Inst.addOperand(MCOperand::createExpr(getExpr())); 535 } 536 537 void addS16ImmOperands(MCInst &Inst, unsigned N) const { 538 assert(N == 1 && "Invalid number of operands!"); 539 switch (Kind) { 540 case Immediate: 541 Inst.addOperand(MCOperand::createImm(getImm())); 542 break; 543 case ContextImmediate: 544 Inst.addOperand(MCOperand::createImm(getImmS16Context())); 545 break; 546 default: 547 Inst.addOperand(MCOperand::createExpr(getExpr())); 548 break; 549 } 550 } 551 552 void addU16ImmOperands(MCInst &Inst, unsigned N) const { 553 assert(N == 1 && "Invalid number of operands!"); 554 switch (Kind) { 555 case Immediate: 556 Inst.addOperand(MCOperand::createImm(getImm())); 557 break; 558 case ContextImmediate: 559 Inst.addOperand(MCOperand::createImm(getImmU16Context())); 560 break; 561 default: 562 Inst.addOperand(MCOperand::createExpr(getExpr())); 563 break; 564 } 565 } 566 567 void addBranchTargetOperands(MCInst &Inst, unsigned N) const { 568 assert(N == 1 && "Invalid number of operands!"); 569 if (Kind == Immediate) 570 Inst.addOperand(MCOperand::createImm(getImm() / 4)); 571 else 572 Inst.addOperand(MCOperand::createExpr(getExpr())); 573 } 574 575 void addTLSRegOperands(MCInst &Inst, unsigned N) const { 576 assert(N == 1 && "Invalid number of operands!"); 577 Inst.addOperand(MCOperand::createExpr(getTLSReg())); 578 } 579 580 StringRef getToken() const { 581 assert(Kind == Token && "Invalid access!"); 582 return StringRef(Tok.Data, Tok.Length); 583 } 584 585 void print(raw_ostream &OS) const override; 586 587 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S, 588 bool IsPPC64) { 589 auto Op = std::make_unique<PPCOperand>(Token); 590 Op->Tok.Data = Str.data(); 591 Op->Tok.Length = Str.size(); 592 Op->StartLoc = S; 593 Op->EndLoc = S; 594 Op->IsPPC64 = IsPPC64; 595 return Op; 596 } 597 598 static std::unique_ptr<PPCOperand> 599 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) { 600 // Allocate extra memory for the string and copy it. 601 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default 602 // deleter which will destroy them by simply using "delete", not correctly 603 // calling operator delete on this extra memory after calling the dtor 604 // explicitly. 605 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size()); 606 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token)); 607 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1); 608 Op->Tok.Length = Str.size(); 609 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size()); 610 Op->StartLoc = S; 611 Op->EndLoc = S; 612 Op->IsPPC64 = IsPPC64; 613 return Op; 614 } 615 616 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E, 617 bool IsPPC64) { 618 auto Op = std::make_unique<PPCOperand>(Immediate); 619 Op->Imm.Val = Val; 620 Op->StartLoc = S; 621 Op->EndLoc = E; 622 Op->IsPPC64 = IsPPC64; 623 return Op; 624 } 625 626 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S, 627 SMLoc E, bool IsPPC64) { 628 auto Op = std::make_unique<PPCOperand>(Expression); 629 Op->Expr.Val = Val; 630 Op->Expr.CRVal = EvaluateCRExpr(Val); 631 Op->StartLoc = S; 632 Op->EndLoc = E; 633 Op->IsPPC64 = IsPPC64; 634 return Op; 635 } 636 637 static std::unique_ptr<PPCOperand> 638 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) { 639 auto Op = std::make_unique<PPCOperand>(TLSRegister); 640 Op->TLSReg.Sym = Sym; 641 Op->StartLoc = S; 642 Op->EndLoc = E; 643 Op->IsPPC64 = IsPPC64; 644 return Op; 645 } 646 647 static std::unique_ptr<PPCOperand> 648 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) { 649 auto Op = std::make_unique<PPCOperand>(ContextImmediate); 650 Op->Imm.Val = Val; 651 Op->StartLoc = S; 652 Op->EndLoc = E; 653 Op->IsPPC64 = IsPPC64; 654 return Op; 655 } 656 657 static std::unique_ptr<PPCOperand> 658 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) { 659 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val)) 660 return CreateImm(CE->getValue(), S, E, IsPPC64); 661 662 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val)) 663 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS) 664 return CreateTLSReg(SRE, S, E, IsPPC64); 665 666 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) { 667 int64_t Res; 668 if (TE->evaluateAsConstant(Res)) 669 return CreateContextImm(Res, S, E, IsPPC64); 670 } 671 672 return CreateExpr(Val, S, E, IsPPC64); 673 } 674 }; 675 676 } // end anonymous namespace. 677 678 void PPCOperand::print(raw_ostream &OS) const { 679 switch (Kind) { 680 case Token: 681 OS << "'" << getToken() << "'"; 682 break; 683 case Immediate: 684 case ContextImmediate: 685 OS << getImm(); 686 break; 687 case Expression: 688 OS << *getExpr(); 689 break; 690 case TLSRegister: 691 OS << *getTLSReg(); 692 break; 693 } 694 } 695 696 static void 697 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) { 698 if (Op.isImm()) { 699 Inst.addOperand(MCOperand::createImm(-Op.getImm())); 700 return; 701 } 702 const MCExpr *Expr = Op.getExpr(); 703 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) { 704 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) { 705 Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr())); 706 return; 707 } 708 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) { 709 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) { 710 const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(), 711 BinExpr->getLHS(), Ctx); 712 Inst.addOperand(MCOperand::createExpr(NE)); 713 return; 714 } 715 } 716 Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx))); 717 } 718 719 void PPCAsmParser::ProcessInstruction(MCInst &Inst, 720 const OperandVector &Operands) { 721 int Opcode = Inst.getOpcode(); 722 switch (Opcode) { 723 case PPC::DCBTx: 724 case PPC::DCBTT: 725 case PPC::DCBTSTx: 726 case PPC::DCBTSTT: { 727 MCInst TmpInst; 728 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? 729 PPC::DCBT : PPC::DCBTST); 730 TmpInst.addOperand(MCOperand::createImm( 731 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16)); 732 TmpInst.addOperand(Inst.getOperand(0)); 733 TmpInst.addOperand(Inst.getOperand(1)); 734 Inst = TmpInst; 735 break; 736 } 737 case PPC::DCBTCT: 738 case PPC::DCBTDS: { 739 MCInst TmpInst; 740 TmpInst.setOpcode(PPC::DCBT); 741 TmpInst.addOperand(Inst.getOperand(2)); 742 TmpInst.addOperand(Inst.getOperand(0)); 743 TmpInst.addOperand(Inst.getOperand(1)); 744 Inst = TmpInst; 745 break; 746 } 747 case PPC::DCBTSTCT: 748 case PPC::DCBTSTDS: { 749 MCInst TmpInst; 750 TmpInst.setOpcode(PPC::DCBTST); 751 TmpInst.addOperand(Inst.getOperand(2)); 752 TmpInst.addOperand(Inst.getOperand(0)); 753 TmpInst.addOperand(Inst.getOperand(1)); 754 Inst = TmpInst; 755 break; 756 } 757 case PPC::DCBFx: 758 case PPC::DCBFL: 759 case PPC::DCBFLP: { 760 int L = 0; 761 if (Opcode == PPC::DCBFL) 762 L = 1; 763 else if (Opcode == PPC::DCBFLP) 764 L = 3; 765 766 MCInst TmpInst; 767 TmpInst.setOpcode(PPC::DCBF); 768 TmpInst.addOperand(MCOperand::createImm(L)); 769 TmpInst.addOperand(Inst.getOperand(0)); 770 TmpInst.addOperand(Inst.getOperand(1)); 771 Inst = TmpInst; 772 break; 773 } 774 case PPC::LAx: { 775 MCInst TmpInst; 776 TmpInst.setOpcode(PPC::LA); 777 TmpInst.addOperand(Inst.getOperand(0)); 778 TmpInst.addOperand(Inst.getOperand(2)); 779 TmpInst.addOperand(Inst.getOperand(1)); 780 Inst = TmpInst; 781 break; 782 } 783 case PPC::SUBI: { 784 MCInst TmpInst; 785 TmpInst.setOpcode(PPC::ADDI); 786 TmpInst.addOperand(Inst.getOperand(0)); 787 TmpInst.addOperand(Inst.getOperand(1)); 788 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 789 Inst = TmpInst; 790 break; 791 } 792 case PPC::SUBIS: { 793 MCInst TmpInst; 794 TmpInst.setOpcode(PPC::ADDIS); 795 TmpInst.addOperand(Inst.getOperand(0)); 796 TmpInst.addOperand(Inst.getOperand(1)); 797 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 798 Inst = TmpInst; 799 break; 800 } 801 case PPC::SUBIC: { 802 MCInst TmpInst; 803 TmpInst.setOpcode(PPC::ADDIC); 804 TmpInst.addOperand(Inst.getOperand(0)); 805 TmpInst.addOperand(Inst.getOperand(1)); 806 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 807 Inst = TmpInst; 808 break; 809 } 810 case PPC::SUBIC_rec: { 811 MCInst TmpInst; 812 TmpInst.setOpcode(PPC::ADDIC_rec); 813 TmpInst.addOperand(Inst.getOperand(0)); 814 TmpInst.addOperand(Inst.getOperand(1)); 815 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 816 Inst = TmpInst; 817 break; 818 } 819 case PPC::EXTLWI: 820 case PPC::EXTLWI_rec: { 821 MCInst TmpInst; 822 int64_t N = Inst.getOperand(2).getImm(); 823 int64_t B = Inst.getOperand(3).getImm(); 824 TmpInst.setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec); 825 TmpInst.addOperand(Inst.getOperand(0)); 826 TmpInst.addOperand(Inst.getOperand(1)); 827 TmpInst.addOperand(MCOperand::createImm(B)); 828 TmpInst.addOperand(MCOperand::createImm(0)); 829 TmpInst.addOperand(MCOperand::createImm(N - 1)); 830 Inst = TmpInst; 831 break; 832 } 833 case PPC::EXTRWI: 834 case PPC::EXTRWI_rec: { 835 MCInst TmpInst; 836 int64_t N = Inst.getOperand(2).getImm(); 837 int64_t B = Inst.getOperand(3).getImm(); 838 TmpInst.setOpcode(Opcode == PPC::EXTRWI ? PPC::RLWINM : PPC::RLWINM_rec); 839 TmpInst.addOperand(Inst.getOperand(0)); 840 TmpInst.addOperand(Inst.getOperand(1)); 841 TmpInst.addOperand(MCOperand::createImm(B + N)); 842 TmpInst.addOperand(MCOperand::createImm(32 - N)); 843 TmpInst.addOperand(MCOperand::createImm(31)); 844 Inst = TmpInst; 845 break; 846 } 847 case PPC::INSLWI: 848 case PPC::INSLWI_rec: { 849 MCInst TmpInst; 850 int64_t N = Inst.getOperand(2).getImm(); 851 int64_t B = Inst.getOperand(3).getImm(); 852 TmpInst.setOpcode(Opcode == PPC::INSLWI ? PPC::RLWIMI : PPC::RLWIMI_rec); 853 TmpInst.addOperand(Inst.getOperand(0)); 854 TmpInst.addOperand(Inst.getOperand(0)); 855 TmpInst.addOperand(Inst.getOperand(1)); 856 TmpInst.addOperand(MCOperand::createImm(32 - B)); 857 TmpInst.addOperand(MCOperand::createImm(B)); 858 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 859 Inst = TmpInst; 860 break; 861 } 862 case PPC::INSRWI: 863 case PPC::INSRWI_rec: { 864 MCInst TmpInst; 865 int64_t N = Inst.getOperand(2).getImm(); 866 int64_t B = Inst.getOperand(3).getImm(); 867 TmpInst.setOpcode(Opcode == PPC::INSRWI ? PPC::RLWIMI : PPC::RLWIMI_rec); 868 TmpInst.addOperand(Inst.getOperand(0)); 869 TmpInst.addOperand(Inst.getOperand(0)); 870 TmpInst.addOperand(Inst.getOperand(1)); 871 TmpInst.addOperand(MCOperand::createImm(32 - (B + N))); 872 TmpInst.addOperand(MCOperand::createImm(B)); 873 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 874 Inst = TmpInst; 875 break; 876 } 877 case PPC::ROTRWI: 878 case PPC::ROTRWI_rec: { 879 MCInst TmpInst; 880 int64_t N = Inst.getOperand(2).getImm(); 881 TmpInst.setOpcode(Opcode == PPC::ROTRWI ? PPC::RLWINM : PPC::RLWINM_rec); 882 TmpInst.addOperand(Inst.getOperand(0)); 883 TmpInst.addOperand(Inst.getOperand(1)); 884 TmpInst.addOperand(MCOperand::createImm(32 - N)); 885 TmpInst.addOperand(MCOperand::createImm(0)); 886 TmpInst.addOperand(MCOperand::createImm(31)); 887 Inst = TmpInst; 888 break; 889 } 890 case PPC::SLWI: 891 case PPC::SLWI_rec: { 892 MCInst TmpInst; 893 int64_t N = Inst.getOperand(2).getImm(); 894 TmpInst.setOpcode(Opcode == PPC::SLWI ? PPC::RLWINM : PPC::RLWINM_rec); 895 TmpInst.addOperand(Inst.getOperand(0)); 896 TmpInst.addOperand(Inst.getOperand(1)); 897 TmpInst.addOperand(MCOperand::createImm(N)); 898 TmpInst.addOperand(MCOperand::createImm(0)); 899 TmpInst.addOperand(MCOperand::createImm(31 - N)); 900 Inst = TmpInst; 901 break; 902 } 903 case PPC::SRWI: 904 case PPC::SRWI_rec: { 905 MCInst TmpInst; 906 int64_t N = Inst.getOperand(2).getImm(); 907 TmpInst.setOpcode(Opcode == PPC::SRWI ? PPC::RLWINM : PPC::RLWINM_rec); 908 TmpInst.addOperand(Inst.getOperand(0)); 909 TmpInst.addOperand(Inst.getOperand(1)); 910 TmpInst.addOperand(MCOperand::createImm(32 - N)); 911 TmpInst.addOperand(MCOperand::createImm(N)); 912 TmpInst.addOperand(MCOperand::createImm(31)); 913 Inst = TmpInst; 914 break; 915 } 916 case PPC::CLRRWI: 917 case PPC::CLRRWI_rec: { 918 MCInst TmpInst; 919 int64_t N = Inst.getOperand(2).getImm(); 920 TmpInst.setOpcode(Opcode == PPC::CLRRWI ? PPC::RLWINM : PPC::RLWINM_rec); 921 TmpInst.addOperand(Inst.getOperand(0)); 922 TmpInst.addOperand(Inst.getOperand(1)); 923 TmpInst.addOperand(MCOperand::createImm(0)); 924 TmpInst.addOperand(MCOperand::createImm(0)); 925 TmpInst.addOperand(MCOperand::createImm(31 - N)); 926 Inst = TmpInst; 927 break; 928 } 929 case PPC::CLRLSLWI: 930 case PPC::CLRLSLWI_rec: { 931 MCInst TmpInst; 932 int64_t B = Inst.getOperand(2).getImm(); 933 int64_t N = Inst.getOperand(3).getImm(); 934 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI ? PPC::RLWINM : PPC::RLWINM_rec); 935 TmpInst.addOperand(Inst.getOperand(0)); 936 TmpInst.addOperand(Inst.getOperand(1)); 937 TmpInst.addOperand(MCOperand::createImm(N)); 938 TmpInst.addOperand(MCOperand::createImm(B - N)); 939 TmpInst.addOperand(MCOperand::createImm(31 - N)); 940 Inst = TmpInst; 941 break; 942 } 943 case PPC::EXTLDI: 944 case PPC::EXTLDI_rec: { 945 MCInst TmpInst; 946 int64_t N = Inst.getOperand(2).getImm(); 947 int64_t B = Inst.getOperand(3).getImm(); 948 TmpInst.setOpcode(Opcode == PPC::EXTLDI ? PPC::RLDICR : PPC::RLDICR_rec); 949 TmpInst.addOperand(Inst.getOperand(0)); 950 TmpInst.addOperand(Inst.getOperand(1)); 951 TmpInst.addOperand(MCOperand::createImm(B)); 952 TmpInst.addOperand(MCOperand::createImm(N - 1)); 953 Inst = TmpInst; 954 break; 955 } 956 case PPC::EXTRDI: 957 case PPC::EXTRDI_rec: { 958 MCInst TmpInst; 959 int64_t N = Inst.getOperand(2).getImm(); 960 int64_t B = Inst.getOperand(3).getImm(); 961 TmpInst.setOpcode(Opcode == PPC::EXTRDI ? PPC::RLDICL : PPC::RLDICL_rec); 962 TmpInst.addOperand(Inst.getOperand(0)); 963 TmpInst.addOperand(Inst.getOperand(1)); 964 TmpInst.addOperand(MCOperand::createImm(B + N)); 965 TmpInst.addOperand(MCOperand::createImm(64 - N)); 966 Inst = TmpInst; 967 break; 968 } 969 case PPC::INSRDI: 970 case PPC::INSRDI_rec: { 971 MCInst TmpInst; 972 int64_t N = Inst.getOperand(2).getImm(); 973 int64_t B = Inst.getOperand(3).getImm(); 974 TmpInst.setOpcode(Opcode == PPC::INSRDI ? PPC::RLDIMI : PPC::RLDIMI_rec); 975 TmpInst.addOperand(Inst.getOperand(0)); 976 TmpInst.addOperand(Inst.getOperand(0)); 977 TmpInst.addOperand(Inst.getOperand(1)); 978 TmpInst.addOperand(MCOperand::createImm(64 - (B + N))); 979 TmpInst.addOperand(MCOperand::createImm(B)); 980 Inst = TmpInst; 981 break; 982 } 983 case PPC::ROTRDI: 984 case PPC::ROTRDI_rec: { 985 MCInst TmpInst; 986 int64_t N = Inst.getOperand(2).getImm(); 987 TmpInst.setOpcode(Opcode == PPC::ROTRDI ? PPC::RLDICL : PPC::RLDICL_rec); 988 TmpInst.addOperand(Inst.getOperand(0)); 989 TmpInst.addOperand(Inst.getOperand(1)); 990 TmpInst.addOperand(MCOperand::createImm(64 - N)); 991 TmpInst.addOperand(MCOperand::createImm(0)); 992 Inst = TmpInst; 993 break; 994 } 995 case PPC::SLDI: 996 case PPC::SLDI_rec: { 997 MCInst TmpInst; 998 int64_t N = Inst.getOperand(2).getImm(); 999 TmpInst.setOpcode(Opcode == PPC::SLDI ? PPC::RLDICR : PPC::RLDICR_rec); 1000 TmpInst.addOperand(Inst.getOperand(0)); 1001 TmpInst.addOperand(Inst.getOperand(1)); 1002 TmpInst.addOperand(MCOperand::createImm(N)); 1003 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1004 Inst = TmpInst; 1005 break; 1006 } 1007 case PPC::SUBPCIS: { 1008 MCInst TmpInst; 1009 int64_t N = Inst.getOperand(1).getImm(); 1010 TmpInst.setOpcode(PPC::ADDPCIS); 1011 TmpInst.addOperand(Inst.getOperand(0)); 1012 TmpInst.addOperand(MCOperand::createImm(-N)); 1013 Inst = TmpInst; 1014 break; 1015 } 1016 case PPC::SRDI: 1017 case PPC::SRDI_rec: { 1018 MCInst TmpInst; 1019 int64_t N = Inst.getOperand(2).getImm(); 1020 TmpInst.setOpcode(Opcode == PPC::SRDI ? PPC::RLDICL : PPC::RLDICL_rec); 1021 TmpInst.addOperand(Inst.getOperand(0)); 1022 TmpInst.addOperand(Inst.getOperand(1)); 1023 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1024 TmpInst.addOperand(MCOperand::createImm(N)); 1025 Inst = TmpInst; 1026 break; 1027 } 1028 case PPC::CLRRDI: 1029 case PPC::CLRRDI_rec: { 1030 MCInst TmpInst; 1031 int64_t N = Inst.getOperand(2).getImm(); 1032 TmpInst.setOpcode(Opcode == PPC::CLRRDI ? PPC::RLDICR : PPC::RLDICR_rec); 1033 TmpInst.addOperand(Inst.getOperand(0)); 1034 TmpInst.addOperand(Inst.getOperand(1)); 1035 TmpInst.addOperand(MCOperand::createImm(0)); 1036 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1037 Inst = TmpInst; 1038 break; 1039 } 1040 case PPC::CLRLSLDI: 1041 case PPC::CLRLSLDI_rec: { 1042 MCInst TmpInst; 1043 int64_t B = Inst.getOperand(2).getImm(); 1044 int64_t N = Inst.getOperand(3).getImm(); 1045 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI ? PPC::RLDIC : PPC::RLDIC_rec); 1046 TmpInst.addOperand(Inst.getOperand(0)); 1047 TmpInst.addOperand(Inst.getOperand(1)); 1048 TmpInst.addOperand(MCOperand::createImm(N)); 1049 TmpInst.addOperand(MCOperand::createImm(B - N)); 1050 Inst = TmpInst; 1051 break; 1052 } 1053 case PPC::RLWINMbm: 1054 case PPC::RLWINMbm_rec: { 1055 unsigned MB, ME; 1056 int64_t BM = Inst.getOperand(3).getImm(); 1057 if (!isRunOfOnes(BM, MB, ME)) 1058 break; 1059 1060 MCInst TmpInst; 1061 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINM_rec); 1062 TmpInst.addOperand(Inst.getOperand(0)); 1063 TmpInst.addOperand(Inst.getOperand(1)); 1064 TmpInst.addOperand(Inst.getOperand(2)); 1065 TmpInst.addOperand(MCOperand::createImm(MB)); 1066 TmpInst.addOperand(MCOperand::createImm(ME)); 1067 Inst = TmpInst; 1068 break; 1069 } 1070 case PPC::RLWIMIbm: 1071 case PPC::RLWIMIbm_rec: { 1072 unsigned MB, ME; 1073 int64_t BM = Inst.getOperand(3).getImm(); 1074 if (!isRunOfOnes(BM, MB, ME)) 1075 break; 1076 1077 MCInst TmpInst; 1078 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMI_rec); 1079 TmpInst.addOperand(Inst.getOperand(0)); 1080 TmpInst.addOperand(Inst.getOperand(0)); // The tied operand. 1081 TmpInst.addOperand(Inst.getOperand(1)); 1082 TmpInst.addOperand(Inst.getOperand(2)); 1083 TmpInst.addOperand(MCOperand::createImm(MB)); 1084 TmpInst.addOperand(MCOperand::createImm(ME)); 1085 Inst = TmpInst; 1086 break; 1087 } 1088 case PPC::RLWNMbm: 1089 case PPC::RLWNMbm_rec: { 1090 unsigned MB, ME; 1091 int64_t BM = Inst.getOperand(3).getImm(); 1092 if (!isRunOfOnes(BM, MB, ME)) 1093 break; 1094 1095 MCInst TmpInst; 1096 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNM_rec); 1097 TmpInst.addOperand(Inst.getOperand(0)); 1098 TmpInst.addOperand(Inst.getOperand(1)); 1099 TmpInst.addOperand(Inst.getOperand(2)); 1100 TmpInst.addOperand(MCOperand::createImm(MB)); 1101 TmpInst.addOperand(MCOperand::createImm(ME)); 1102 Inst = TmpInst; 1103 break; 1104 } 1105 case PPC::MFTB: { 1106 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) { 1107 assert(Inst.getNumOperands() == 2 && "Expecting two operands"); 1108 Inst.setOpcode(PPC::MFSPR); 1109 } 1110 break; 1111 } 1112 case PPC::CP_COPYx: 1113 case PPC::CP_COPY_FIRST: { 1114 MCInst TmpInst; 1115 TmpInst.setOpcode(PPC::CP_COPY); 1116 TmpInst.addOperand(Inst.getOperand(0)); 1117 TmpInst.addOperand(Inst.getOperand(1)); 1118 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1)); 1119 1120 Inst = TmpInst; 1121 break; 1122 } 1123 case PPC::CP_PASTEx : 1124 case PPC::CP_PASTE_LAST: { 1125 MCInst TmpInst; 1126 TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ? PPC::CP_PASTE 1127 : PPC::CP_PASTE_rec); 1128 TmpInst.addOperand(Inst.getOperand(0)); 1129 TmpInst.addOperand(Inst.getOperand(1)); 1130 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1)); 1131 1132 Inst = TmpInst; 1133 break; 1134 } 1135 } 1136 } 1137 1138 static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, 1139 unsigned VariantID = 0); 1140 1141 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 1142 OperandVector &Operands, 1143 MCStreamer &Out, uint64_t &ErrorInfo, 1144 bool MatchingInlineAsm) { 1145 MCInst Inst; 1146 1147 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { 1148 case Match_Success: 1149 // Post-process instructions (typically extended mnemonics) 1150 ProcessInstruction(Inst, Operands); 1151 Inst.setLoc(IDLoc); 1152 Out.EmitInstruction(Inst, getSTI()); 1153 return false; 1154 case Match_MissingFeature: 1155 return Error(IDLoc, "instruction use requires an option to be enabled"); 1156 case Match_MnemonicFail: { 1157 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); 1158 std::string Suggestion = PPCMnemonicSpellCheck( 1159 ((PPCOperand &)*Operands[0]).getToken(), FBS); 1160 return Error(IDLoc, "invalid instruction" + Suggestion, 1161 ((PPCOperand &)*Operands[0]).getLocRange()); 1162 } 1163 case Match_InvalidOperand: { 1164 SMLoc ErrorLoc = IDLoc; 1165 if (ErrorInfo != ~0ULL) { 1166 if (ErrorInfo >= Operands.size()) 1167 return Error(IDLoc, "too few operands for instruction"); 1168 1169 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc(); 1170 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 1171 } 1172 1173 return Error(ErrorLoc, "invalid operand for instruction"); 1174 } 1175 } 1176 1177 llvm_unreachable("Implement any new match types added!"); 1178 } 1179 1180 bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) { 1181 if (getParser().getTok().is(AsmToken::Identifier)) { 1182 StringRef Name = getParser().getTok().getString(); 1183 if (Name.equals_lower("lr")) { 1184 RegNo = isPPC64()? PPC::LR8 : PPC::LR; 1185 IntVal = 8; 1186 } else if (Name.equals_lower("ctr")) { 1187 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR; 1188 IntVal = 9; 1189 } else if (Name.equals_lower("vrsave")) { 1190 RegNo = PPC::VRSAVE; 1191 IntVal = 256; 1192 } else if (Name.startswith_lower("r") && 1193 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1194 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal]; 1195 } else if (Name.startswith_lower("f") && 1196 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1197 RegNo = FRegs[IntVal]; 1198 } else if (Name.startswith_lower("vs") && 1199 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) { 1200 RegNo = VSRegs[IntVal]; 1201 } else if (Name.startswith_lower("v") && 1202 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1203 RegNo = VRegs[IntVal]; 1204 } else if (Name.startswith_lower("q") && 1205 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1206 RegNo = QFRegs[IntVal]; 1207 } else if (Name.startswith_lower("cr") && 1208 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { 1209 RegNo = CRRegs[IntVal]; 1210 } else 1211 return true; 1212 getParser().Lex(); 1213 return false; 1214 } 1215 return true; 1216 } 1217 1218 bool PPCAsmParser:: 1219 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 1220 const AsmToken &Tok = getParser().getTok(); 1221 StartLoc = Tok.getLoc(); 1222 EndLoc = Tok.getEndLoc(); 1223 RegNo = 0; 1224 int64_t IntVal; 1225 if (MatchRegisterName(RegNo, IntVal)) 1226 return TokError("invalid register name"); 1227 return false; 1228 } 1229 1230 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan 1231 /// the expression and check for VK_PPC_LO/HI/HA 1232 /// symbol variants. If all symbols with modifier use the same 1233 /// variant, return the corresponding PPCMCExpr::VariantKind, 1234 /// and a modified expression using the default symbol variant. 1235 /// Otherwise, return NULL. 1236 const MCExpr *PPCAsmParser:: 1237 ExtractModifierFromExpr(const MCExpr *E, 1238 PPCMCExpr::VariantKind &Variant) { 1239 MCContext &Context = getParser().getContext(); 1240 Variant = PPCMCExpr::VK_PPC_None; 1241 1242 switch (E->getKind()) { 1243 case MCExpr::Target: 1244 case MCExpr::Constant: 1245 return nullptr; 1246 1247 case MCExpr::SymbolRef: { 1248 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1249 1250 switch (SRE->getKind()) { 1251 case MCSymbolRefExpr::VK_PPC_LO: 1252 Variant = PPCMCExpr::VK_PPC_LO; 1253 break; 1254 case MCSymbolRefExpr::VK_PPC_HI: 1255 Variant = PPCMCExpr::VK_PPC_HI; 1256 break; 1257 case MCSymbolRefExpr::VK_PPC_HA: 1258 Variant = PPCMCExpr::VK_PPC_HA; 1259 break; 1260 case MCSymbolRefExpr::VK_PPC_HIGH: 1261 Variant = PPCMCExpr::VK_PPC_HIGH; 1262 break; 1263 case MCSymbolRefExpr::VK_PPC_HIGHA: 1264 Variant = PPCMCExpr::VK_PPC_HIGHA; 1265 break; 1266 case MCSymbolRefExpr::VK_PPC_HIGHER: 1267 Variant = PPCMCExpr::VK_PPC_HIGHER; 1268 break; 1269 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1270 Variant = PPCMCExpr::VK_PPC_HIGHERA; 1271 break; 1272 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1273 Variant = PPCMCExpr::VK_PPC_HIGHEST; 1274 break; 1275 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1276 Variant = PPCMCExpr::VK_PPC_HIGHESTA; 1277 break; 1278 default: 1279 return nullptr; 1280 } 1281 1282 return MCSymbolRefExpr::create(&SRE->getSymbol(), Context); 1283 } 1284 1285 case MCExpr::Unary: { 1286 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1287 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant); 1288 if (!Sub) 1289 return nullptr; 1290 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1291 } 1292 1293 case MCExpr::Binary: { 1294 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1295 PPCMCExpr::VariantKind LHSVariant, RHSVariant; 1296 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant); 1297 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant); 1298 1299 if (!LHS && !RHS) 1300 return nullptr; 1301 1302 if (!LHS) LHS = BE->getLHS(); 1303 if (!RHS) RHS = BE->getRHS(); 1304 1305 if (LHSVariant == PPCMCExpr::VK_PPC_None) 1306 Variant = RHSVariant; 1307 else if (RHSVariant == PPCMCExpr::VK_PPC_None) 1308 Variant = LHSVariant; 1309 else if (LHSVariant == RHSVariant) 1310 Variant = LHSVariant; 1311 else 1312 return nullptr; 1313 1314 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1315 } 1316 } 1317 1318 llvm_unreachable("Invalid expression kind!"); 1319 } 1320 1321 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace 1322 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having 1323 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT. 1324 /// FIXME: This is a hack. 1325 const MCExpr *PPCAsmParser:: 1326 FixupVariantKind(const MCExpr *E) { 1327 MCContext &Context = getParser().getContext(); 1328 1329 switch (E->getKind()) { 1330 case MCExpr::Target: 1331 case MCExpr::Constant: 1332 return E; 1333 1334 case MCExpr::SymbolRef: { 1335 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1336 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; 1337 1338 switch (SRE->getKind()) { 1339 case MCSymbolRefExpr::VK_TLSGD: 1340 Variant = MCSymbolRefExpr::VK_PPC_TLSGD; 1341 break; 1342 case MCSymbolRefExpr::VK_TLSLD: 1343 Variant = MCSymbolRefExpr::VK_PPC_TLSLD; 1344 break; 1345 default: 1346 return E; 1347 } 1348 return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context); 1349 } 1350 1351 case MCExpr::Unary: { 1352 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1353 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr()); 1354 if (Sub == UE->getSubExpr()) 1355 return E; 1356 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1357 } 1358 1359 case MCExpr::Binary: { 1360 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1361 const MCExpr *LHS = FixupVariantKind(BE->getLHS()); 1362 const MCExpr *RHS = FixupVariantKind(BE->getRHS()); 1363 if (LHS == BE->getLHS() && RHS == BE->getRHS()) 1364 return E; 1365 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1366 } 1367 } 1368 1369 llvm_unreachable("Invalid expression kind!"); 1370 } 1371 1372 /// ParseExpression. This differs from the default "parseExpression" in that 1373 /// it handles modifiers. 1374 bool PPCAsmParser:: 1375 ParseExpression(const MCExpr *&EVal) { 1376 1377 if (isDarwin()) 1378 return ParseDarwinExpression(EVal); 1379 1380 // (ELF Platforms) 1381 // Handle \code @l/@ha \endcode 1382 if (getParser().parseExpression(EVal)) 1383 return true; 1384 1385 EVal = FixupVariantKind(EVal); 1386 1387 PPCMCExpr::VariantKind Variant; 1388 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant); 1389 if (E) 1390 EVal = PPCMCExpr::create(Variant, E, getParser().getContext()); 1391 1392 return false; 1393 } 1394 1395 /// ParseDarwinExpression. (MachO Platforms) 1396 /// This differs from the default "parseExpression" in that it handles detection 1397 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present, 1398 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO 1399 /// syntax form so it is done here. TODO: Determine if there is merit in 1400 /// arranging for this to be done at a higher level. 1401 bool PPCAsmParser:: 1402 ParseDarwinExpression(const MCExpr *&EVal) { 1403 MCAsmParser &Parser = getParser(); 1404 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None; 1405 switch (getLexer().getKind()) { 1406 default: 1407 break; 1408 case AsmToken::Identifier: 1409 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus 1410 // something starting with any other char should be part of the 1411 // asm syntax. If handwritten asm includes an identifier like lo16, 1412 // then all bets are off - but no-one would do that, right? 1413 StringRef poss = Parser.getTok().getString(); 1414 if (poss.equals_lower("lo16")) { 1415 Variant = PPCMCExpr::VK_PPC_LO; 1416 } else if (poss.equals_lower("hi16")) { 1417 Variant = PPCMCExpr::VK_PPC_HI; 1418 } else if (poss.equals_lower("ha16")) { 1419 Variant = PPCMCExpr::VK_PPC_HA; 1420 } 1421 if (Variant != PPCMCExpr::VK_PPC_None) { 1422 Parser.Lex(); // Eat the xx16 1423 if (getLexer().isNot(AsmToken::LParen)) 1424 return Error(Parser.getTok().getLoc(), "expected '('"); 1425 Parser.Lex(); // Eat the '(' 1426 } 1427 break; 1428 } 1429 1430 if (getParser().parseExpression(EVal)) 1431 return true; 1432 1433 if (Variant != PPCMCExpr::VK_PPC_None) { 1434 if (getLexer().isNot(AsmToken::RParen)) 1435 return Error(Parser.getTok().getLoc(), "expected ')'"); 1436 Parser.Lex(); // Eat the ')' 1437 EVal = PPCMCExpr::create(Variant, EVal, getParser().getContext()); 1438 } 1439 return false; 1440 } 1441 1442 /// ParseOperand 1443 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and 1444 /// rNN for MachO. 1445 bool PPCAsmParser::ParseOperand(OperandVector &Operands) { 1446 MCAsmParser &Parser = getParser(); 1447 SMLoc S = Parser.getTok().getLoc(); 1448 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1449 const MCExpr *EVal; 1450 1451 // Attempt to parse the next token as an immediate 1452 switch (getLexer().getKind()) { 1453 // Special handling for register names. These are interpreted 1454 // as immediates corresponding to the register number. 1455 case AsmToken::Percent: 1456 Parser.Lex(); // Eat the '%'. 1457 unsigned RegNo; 1458 int64_t IntVal; 1459 if (MatchRegisterName(RegNo, IntVal)) 1460 return Error(S, "invalid register name"); 1461 1462 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1463 return false; 1464 1465 case AsmToken::Identifier: 1466 case AsmToken::LParen: 1467 case AsmToken::Plus: 1468 case AsmToken::Minus: 1469 case AsmToken::Integer: 1470 case AsmToken::Dot: 1471 case AsmToken::Dollar: 1472 case AsmToken::Exclaim: 1473 case AsmToken::Tilde: 1474 // Note that non-register-name identifiers from the compiler will begin 1475 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include 1476 // identifiers like r31foo - so we fall through in the event that parsing 1477 // a register name fails. 1478 if (isDarwin()) { 1479 unsigned RegNo; 1480 int64_t IntVal; 1481 if (!MatchRegisterName(RegNo, IntVal)) { 1482 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1483 return false; 1484 } 1485 } 1486 // All other expressions 1487 1488 if (!ParseExpression(EVal)) 1489 break; 1490 // Fall-through 1491 LLVM_FALLTHROUGH; 1492 default: 1493 return Error(S, "unknown operand"); 1494 } 1495 1496 // Push the parsed operand into the list of operands 1497 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64())); 1498 1499 // Check whether this is a TLS call expression 1500 bool TLSCall = false; 1501 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal)) 1502 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr"; 1503 1504 if (TLSCall && getLexer().is(AsmToken::LParen)) { 1505 const MCExpr *TLSSym; 1506 1507 Parser.Lex(); // Eat the '('. 1508 S = Parser.getTok().getLoc(); 1509 if (ParseExpression(TLSSym)) 1510 return Error(S, "invalid TLS call expression"); 1511 if (getLexer().isNot(AsmToken::RParen)) 1512 return Error(Parser.getTok().getLoc(), "missing ')'"); 1513 E = Parser.getTok().getLoc(); 1514 Parser.Lex(); // Eat the ')'. 1515 1516 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64())); 1517 } 1518 1519 // Otherwise, check for D-form memory operands 1520 if (!TLSCall && getLexer().is(AsmToken::LParen)) { 1521 Parser.Lex(); // Eat the '('. 1522 S = Parser.getTok().getLoc(); 1523 1524 int64_t IntVal; 1525 switch (getLexer().getKind()) { 1526 case AsmToken::Percent: 1527 Parser.Lex(); // Eat the '%'. 1528 unsigned RegNo; 1529 if (MatchRegisterName(RegNo, IntVal)) 1530 return Error(S, "invalid register name"); 1531 break; 1532 1533 case AsmToken::Integer: 1534 if (isDarwin()) 1535 return Error(S, "unexpected integer value"); 1536 else if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 || 1537 IntVal > 31) 1538 return Error(S, "invalid register number"); 1539 break; 1540 case AsmToken::Identifier: 1541 if (isDarwin()) { 1542 unsigned RegNo; 1543 if (!MatchRegisterName(RegNo, IntVal)) { 1544 break; 1545 } 1546 } 1547 LLVM_FALLTHROUGH; 1548 1549 default: 1550 return Error(S, "invalid memory operand"); 1551 } 1552 1553 E = Parser.getTok().getLoc(); 1554 if (parseToken(AsmToken::RParen, "missing ')'")) 1555 return true; 1556 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1557 } 1558 1559 return false; 1560 } 1561 1562 /// Parse an instruction mnemonic followed by its operands. 1563 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 1564 SMLoc NameLoc, OperandVector &Operands) { 1565 // The first operand is the token for the instruction name. 1566 // If the next character is a '+' or '-', we need to add it to the 1567 // instruction name, to match what TableGen is doing. 1568 std::string NewOpcode; 1569 if (parseOptionalToken(AsmToken::Plus)) { 1570 NewOpcode = Name; 1571 NewOpcode += '+'; 1572 Name = NewOpcode; 1573 } 1574 if (parseOptionalToken(AsmToken::Minus)) { 1575 NewOpcode = Name; 1576 NewOpcode += '-'; 1577 Name = NewOpcode; 1578 } 1579 // If the instruction ends in a '.', we need to create a separate 1580 // token for it, to match what TableGen is doing. 1581 size_t Dot = Name.find('.'); 1582 StringRef Mnemonic = Name.slice(0, Dot); 1583 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1584 Operands.push_back( 1585 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64())); 1586 else 1587 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64())); 1588 if (Dot != StringRef::npos) { 1589 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot); 1590 StringRef DotStr = Name.slice(Dot, StringRef::npos); 1591 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1592 Operands.push_back( 1593 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64())); 1594 else 1595 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64())); 1596 } 1597 1598 // If there are no more operands then finish 1599 if (parseOptionalToken(AsmToken::EndOfStatement)) 1600 return false; 1601 1602 // Parse the first operand 1603 if (ParseOperand(Operands)) 1604 return true; 1605 1606 while (!parseOptionalToken(AsmToken::EndOfStatement)) { 1607 if (parseToken(AsmToken::Comma) || ParseOperand(Operands)) 1608 return true; 1609 } 1610 1611 // We'll now deal with an unfortunate special case: the syntax for the dcbt 1612 // and dcbtst instructions differs for server vs. embedded cores. 1613 // The syntax for dcbt is: 1614 // dcbt ra, rb, th [server] 1615 // dcbt th, ra, rb [embedded] 1616 // where th can be omitted when it is 0. dcbtst is the same. We take the 1617 // server form to be the default, so swap the operands if we're parsing for 1618 // an embedded core (they'll be swapped again upon printing). 1619 if (getSTI().getFeatureBits()[PPC::FeatureBookE] && 1620 Operands.size() == 4 && 1621 (Name == "dcbt" || Name == "dcbtst")) { 1622 std::swap(Operands[1], Operands[3]); 1623 std::swap(Operands[2], Operands[1]); 1624 } 1625 1626 return false; 1627 } 1628 1629 /// ParseDirective parses the PPC specific directives 1630 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) { 1631 StringRef IDVal = DirectiveID.getIdentifier(); 1632 if (isDarwin()) { 1633 if (IDVal == ".machine") 1634 ParseDarwinDirectiveMachine(DirectiveID.getLoc()); 1635 else 1636 return true; 1637 } else if (IDVal == ".word") 1638 ParseDirectiveWord(2, DirectiveID); 1639 else if (IDVal == ".llong") 1640 ParseDirectiveWord(8, DirectiveID); 1641 else if (IDVal == ".tc") 1642 ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID); 1643 else if (IDVal == ".machine") 1644 ParseDirectiveMachine(DirectiveID.getLoc()); 1645 else if (IDVal == ".abiversion") 1646 ParseDirectiveAbiVersion(DirectiveID.getLoc()); 1647 else if (IDVal == ".localentry") 1648 ParseDirectiveLocalEntry(DirectiveID.getLoc()); 1649 else 1650 return true; 1651 return false; 1652 } 1653 1654 /// ParseDirectiveWord 1655 /// ::= .word [ expression (, expression)* ] 1656 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) { 1657 auto parseOp = [&]() -> bool { 1658 const MCExpr *Value; 1659 SMLoc ExprLoc = getParser().getTok().getLoc(); 1660 if (getParser().parseExpression(Value)) 1661 return true; 1662 if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) { 1663 assert(Size <= 8 && "Invalid size"); 1664 uint64_t IntValue = MCE->getValue(); 1665 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue)) 1666 return Error(ExprLoc, "literal value out of range for '" + 1667 ID.getIdentifier() + "' directive"); 1668 getStreamer().EmitIntValue(IntValue, Size); 1669 } else 1670 getStreamer().EmitValue(Value, Size, ExprLoc); 1671 return false; 1672 }; 1673 1674 if (parseMany(parseOp)) 1675 return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive"); 1676 return false; 1677 } 1678 1679 /// ParseDirectiveTC 1680 /// ::= .tc [ symbol (, expression)* ] 1681 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) { 1682 MCAsmParser &Parser = getParser(); 1683 // Skip TC symbol, which is only used with XCOFF. 1684 while (getLexer().isNot(AsmToken::EndOfStatement) 1685 && getLexer().isNot(AsmToken::Comma)) 1686 Parser.Lex(); 1687 if (parseToken(AsmToken::Comma)) 1688 return addErrorSuffix(" in '.tc' directive"); 1689 1690 // Align to word size. 1691 getParser().getStreamer().EmitValueToAlignment(Size); 1692 1693 // Emit expressions. 1694 return ParseDirectiveWord(Size, ID); 1695 } 1696 1697 /// ParseDirectiveMachine (ELF platforms) 1698 /// ::= .machine [ cpu | "push" | "pop" ] 1699 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) { 1700 MCAsmParser &Parser = getParser(); 1701 if (Parser.getTok().isNot(AsmToken::Identifier) && 1702 Parser.getTok().isNot(AsmToken::String)) 1703 return Error(L, "unexpected token in '.machine' directive"); 1704 1705 StringRef CPU = Parser.getTok().getIdentifier(); 1706 1707 // FIXME: Right now, the parser always allows any available 1708 // instruction, so the .machine directive is not useful. 1709 // Implement ".machine any" (by doing nothing) for the benefit 1710 // of existing assembler code. Likewise, we can then implement 1711 // ".machine push" and ".machine pop" as no-op. 1712 if (CPU != "any" && CPU != "push" && CPU != "pop") 1713 return TokError("unrecognized machine type"); 1714 1715 Parser.Lex(); 1716 1717 if (parseToken(AsmToken::EndOfStatement)) 1718 return addErrorSuffix(" in '.machine' directive"); 1719 1720 PPCTargetStreamer &TStreamer = 1721 *static_cast<PPCTargetStreamer *>( 1722 getParser().getStreamer().getTargetStreamer()); 1723 TStreamer.emitMachine(CPU); 1724 1725 return false; 1726 } 1727 1728 /// ParseDarwinDirectiveMachine (Mach-o platforms) 1729 /// ::= .machine cpu-identifier 1730 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) { 1731 MCAsmParser &Parser = getParser(); 1732 if (Parser.getTok().isNot(AsmToken::Identifier) && 1733 Parser.getTok().isNot(AsmToken::String)) 1734 return Error(L, "unexpected token in directive"); 1735 1736 StringRef CPU = Parser.getTok().getIdentifier(); 1737 Parser.Lex(); 1738 1739 // FIXME: this is only the 'default' set of cpu variants. 1740 // However we don't act on this information at present, this is simply 1741 // allowing parsing to proceed with minimal sanity checking. 1742 if (check(CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64", L, 1743 "unrecognized cpu type") || 1744 check(isPPC64() && (CPU == "ppc7400" || CPU == "ppc"), L, 1745 "wrong cpu type specified for 64bit") || 1746 check(!isPPC64() && CPU == "ppc64", L, 1747 "wrong cpu type specified for 32bit") || 1748 parseToken(AsmToken::EndOfStatement)) 1749 return addErrorSuffix(" in '.machine' directive"); 1750 return false; 1751 } 1752 1753 /// ParseDirectiveAbiVersion 1754 /// ::= .abiversion constant-expression 1755 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) { 1756 int64_t AbiVersion; 1757 if (check(getParser().parseAbsoluteExpression(AbiVersion), L, 1758 "expected constant expression") || 1759 parseToken(AsmToken::EndOfStatement)) 1760 return addErrorSuffix(" in '.abiversion' directive"); 1761 1762 PPCTargetStreamer &TStreamer = 1763 *static_cast<PPCTargetStreamer *>( 1764 getParser().getStreamer().getTargetStreamer()); 1765 TStreamer.emitAbiVersion(AbiVersion); 1766 1767 return false; 1768 } 1769 1770 /// ParseDirectiveLocalEntry 1771 /// ::= .localentry symbol, expression 1772 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) { 1773 StringRef Name; 1774 if (getParser().parseIdentifier(Name)) 1775 return Error(L, "expected identifier in '.localentry' directive"); 1776 1777 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name)); 1778 const MCExpr *Expr; 1779 1780 if (parseToken(AsmToken::Comma) || 1781 check(getParser().parseExpression(Expr), L, "expected expression") || 1782 parseToken(AsmToken::EndOfStatement)) 1783 return addErrorSuffix(" in '.localentry' directive"); 1784 1785 PPCTargetStreamer &TStreamer = 1786 *static_cast<PPCTargetStreamer *>( 1787 getParser().getStreamer().getTargetStreamer()); 1788 TStreamer.emitLocalEntry(Sym, Expr); 1789 1790 return false; 1791 } 1792 1793 1794 1795 /// Force static initialization. 1796 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCAsmParser() { 1797 RegisterMCAsmParser<PPCAsmParser> A(getThePPC32Target()); 1798 RegisterMCAsmParser<PPCAsmParser> B(getThePPC64Target()); 1799 RegisterMCAsmParser<PPCAsmParser> C(getThePPC64LETarget()); 1800 } 1801 1802 #define GET_REGISTER_MATCHER 1803 #define GET_MATCHER_IMPLEMENTATION 1804 #define GET_MNEMONIC_SPELL_CHECKER 1805 #include "PPCGenAsmMatcher.inc" 1806 1807 // Define this matcher function after the auto-generated include so we 1808 // have the match class enum definitions. 1809 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, 1810 unsigned Kind) { 1811 // If the kind is a token for a literal immediate, check if our asm 1812 // operand matches. This is for InstAliases which have a fixed-value 1813 // immediate in the syntax. 1814 int64_t ImmVal; 1815 switch (Kind) { 1816 case MCK_0: ImmVal = 0; break; 1817 case MCK_1: ImmVal = 1; break; 1818 case MCK_2: ImmVal = 2; break; 1819 case MCK_3: ImmVal = 3; break; 1820 case MCK_4: ImmVal = 4; break; 1821 case MCK_5: ImmVal = 5; break; 1822 case MCK_6: ImmVal = 6; break; 1823 case MCK_7: ImmVal = 7; break; 1824 default: return Match_InvalidOperand; 1825 } 1826 1827 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp); 1828 if (Op.isImm() && Op.getImm() == ImmVal) 1829 return Match_Success; 1830 1831 return Match_InvalidOperand; 1832 } 1833 1834 const MCExpr * 1835 PPCAsmParser::applyModifierToExpr(const MCExpr *E, 1836 MCSymbolRefExpr::VariantKind Variant, 1837 MCContext &Ctx) { 1838 switch (Variant) { 1839 case MCSymbolRefExpr::VK_PPC_LO: 1840 return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, Ctx); 1841 case MCSymbolRefExpr::VK_PPC_HI: 1842 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, Ctx); 1843 case MCSymbolRefExpr::VK_PPC_HA: 1844 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, Ctx); 1845 case MCSymbolRefExpr::VK_PPC_HIGH: 1846 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGH, E, Ctx); 1847 case MCSymbolRefExpr::VK_PPC_HIGHA: 1848 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHA, E, Ctx); 1849 case MCSymbolRefExpr::VK_PPC_HIGHER: 1850 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, Ctx); 1851 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1852 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, Ctx); 1853 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1854 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, Ctx); 1855 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1856 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, Ctx); 1857 default: 1858 return nullptr; 1859 } 1860 } 1861