xref: /llvm-project/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (revision 5aab5afcd2d2edc16fbe37096aebbeb1495b98f0) 
1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCTargetAsmParser.h"
29 #include "llvm/Support/SourceMgr.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
32 
33 using namespace llvm;
34 
35 namespace {
36 
37 static unsigned RRegs[32] = {
38   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
39   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
40   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
41   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
42   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
43   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
44   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
45   PPC::R28, PPC::R29, PPC::R30, PPC::R31
46 };
47 static unsigned RRegsNoR0[32] = {
48   PPC::ZERO,
49             PPC::R1,  PPC::R2,  PPC::R3,
50   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
51   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
52   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
53   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
54   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
55   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
56   PPC::R28, PPC::R29, PPC::R30, PPC::R31
57 };
58 static unsigned XRegs[32] = {
59   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
60   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
61   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
62   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
63   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
64   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
65   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
66   PPC::X28, PPC::X29, PPC::X30, PPC::X31
67 };
68 static unsigned XRegsNoX0[32] = {
69   PPC::ZERO8,
70             PPC::X1,  PPC::X2,  PPC::X3,
71   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
72   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
73   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
74   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
75   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
76   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
77   PPC::X28, PPC::X29, PPC::X30, PPC::X31
78 };
79 static unsigned FRegs[32] = {
80   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
81   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
82   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
83   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
84   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
85   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
86   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
87   PPC::F28, PPC::F29, PPC::F30, PPC::F31
88 };
89 static unsigned VRegs[32] = {
90   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
91   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
92   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
93   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
94   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
95   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
96   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
97   PPC::V28, PPC::V29, PPC::V30, PPC::V31
98 };
99 static unsigned VSRegs[64] = {
100   PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
101   PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
102   PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
103   PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
104   PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
105   PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
106   PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
107   PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
108 
109   PPC::VSH0,  PPC::VSH1,  PPC::VSH2,  PPC::VSH3,
110   PPC::VSH4,  PPC::VSH5,  PPC::VSH6,  PPC::VSH7,
111   PPC::VSH8,  PPC::VSH9,  PPC::VSH10, PPC::VSH11,
112   PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
113   PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
114   PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
115   PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
116   PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
117 };
118 static unsigned VSFRegs[64] = {
119   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
120   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
121   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
122   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
123   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
124   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
125   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
126   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
127 
128   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
129   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
130   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
131   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
132   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
133   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
134   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
135   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
136 };
137 static unsigned CRBITRegs[32] = {
138   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
139   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
140   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
141   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
142   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
143   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
144   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
145   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
146 };
147 static unsigned CRRegs[8] = {
148   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
149   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
150 };
151 
152 // Evaluate an expression containing condition register
153 // or condition register field symbols.  Returns positive
154 // value on success, or -1 on error.
155 static int64_t
156 EvaluateCRExpr(const MCExpr *E) {
157   switch (E->getKind()) {
158   case MCExpr::Target:
159     return -1;
160 
161   case MCExpr::Constant: {
162     int64_t Res = cast<MCConstantExpr>(E)->getValue();
163     return Res < 0 ? -1 : Res;
164   }
165 
166   case MCExpr::SymbolRef: {
167     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
168     StringRef Name = SRE->getSymbol().getName();
169 
170     if (Name == "lt") return 0;
171     if (Name == "gt") return 1;
172     if (Name == "eq") return 2;
173     if (Name == "so") return 3;
174     if (Name == "un") return 3;
175 
176     if (Name == "cr0") return 0;
177     if (Name == "cr1") return 1;
178     if (Name == "cr2") return 2;
179     if (Name == "cr3") return 3;
180     if (Name == "cr4") return 4;
181     if (Name == "cr5") return 5;
182     if (Name == "cr6") return 6;
183     if (Name == "cr7") return 7;
184 
185     return -1;
186   }
187 
188   case MCExpr::Unary:
189     return -1;
190 
191   case MCExpr::Binary: {
192     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
193     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
194     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
195     int64_t Res;
196 
197     if (LHSVal < 0 || RHSVal < 0)
198       return -1;
199 
200     switch (BE->getOpcode()) {
201     default: return -1;
202     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
203     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
204     }
205 
206     return Res < 0 ? -1 : Res;
207   }
208   }
209 
210   llvm_unreachable("Invalid expression kind!");
211 }
212 
213 struct PPCOperand;
214 
215 class PPCAsmParser : public MCTargetAsmParser {
216   MCSubtargetInfo &STI;
217   MCAsmParser &Parser;
218   const MCInstrInfo &MII;
219   bool IsPPC64;
220   bool IsDarwin;
221 
222   MCAsmParser &getParser() const { return Parser; }
223   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
224 
225   void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
226   bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
227 
228   bool isPPC64() const { return IsPPC64; }
229   bool isDarwin() const { return IsDarwin; }
230 
231   bool MatchRegisterName(const AsmToken &Tok,
232                          unsigned &RegNo, int64_t &IntVal);
233 
234   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
235 
236   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
237                                         PPCMCExpr::VariantKind &Variant);
238   const MCExpr *FixupVariantKind(const MCExpr *E);
239   bool ParseExpression(const MCExpr *&EVal);
240   bool ParseDarwinExpression(const MCExpr *&EVal);
241 
242   bool ParseOperand(OperandVector &Operands);
243 
244   bool ParseDirectiveWord(unsigned Size, SMLoc L);
245   bool ParseDirectiveTC(unsigned Size, SMLoc L);
246   bool ParseDirectiveMachine(SMLoc L);
247   bool ParseDarwinDirectiveMachine(SMLoc L);
248   bool ParseDirectiveAbiVersion(SMLoc L);
249   bool ParseDirectiveLocalEntry(SMLoc L);
250 
251   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
252                                OperandVector &Operands, MCStreamer &Out,
253                                unsigned &ErrorInfo,
254                                bool MatchingInlineAsm) override;
255 
256   void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
257 
258   /// @name Auto-generated Match Functions
259   /// {
260 
261 #define GET_ASSEMBLER_HEADER
262 #include "PPCGenAsmMatcher.inc"
263 
264   /// }
265 
266 
267 public:
268   PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
269                const MCInstrInfo &_MII,
270                const MCTargetOptions &Options)
271       : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) {
272     // Check for 64-bit vs. 32-bit pointer mode.
273     Triple TheTriple(STI.getTargetTriple());
274     IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
275                TheTriple.getArch() == Triple::ppc64le);
276     IsDarwin = TheTriple.isMacOSX();
277     // Initialize the set of available features.
278     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
279   }
280 
281   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
282                         SMLoc NameLoc, OperandVector &Operands) override;
283 
284   bool ParseDirective(AsmToken DirectiveID) override;
285 
286   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
287                                       unsigned Kind) override;
288 
289   const MCExpr *applyModifierToExpr(const MCExpr *E,
290                                     MCSymbolRefExpr::VariantKind,
291                                     MCContext &Ctx) override;
292 };
293 
294 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
295 /// instruction.
296 struct PPCOperand : public MCParsedAsmOperand {
297   enum KindTy {
298     Token,
299     Immediate,
300     Expression,
301     TLSRegister
302   } Kind;
303 
304   SMLoc StartLoc, EndLoc;
305   bool IsPPC64;
306 
307   struct TokOp {
308     const char *Data;
309     unsigned Length;
310   };
311 
312   struct ImmOp {
313     int64_t Val;
314   };
315 
316   struct ExprOp {
317     const MCExpr *Val;
318     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
319   };
320 
321   struct TLSRegOp {
322     const MCSymbolRefExpr *Sym;
323   };
324 
325   union {
326     struct TokOp Tok;
327     struct ImmOp Imm;
328     struct ExprOp Expr;
329     struct TLSRegOp TLSReg;
330   };
331 
332   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
333 public:
334   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
335     Kind = o.Kind;
336     StartLoc = o.StartLoc;
337     EndLoc = o.EndLoc;
338     IsPPC64 = o.IsPPC64;
339     switch (Kind) {
340     case Token:
341       Tok = o.Tok;
342       break;
343     case Immediate:
344       Imm = o.Imm;
345       break;
346     case Expression:
347       Expr = o.Expr;
348       break;
349     case TLSRegister:
350       TLSReg = o.TLSReg;
351       break;
352     }
353   }
354 
355   /// getStartLoc - Get the location of the first token of this operand.
356   SMLoc getStartLoc() const override { return StartLoc; }
357 
358   /// getEndLoc - Get the location of the last token of this operand.
359   SMLoc getEndLoc() const override { return EndLoc; }
360 
361   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
362   bool isPPC64() const { return IsPPC64; }
363 
364   int64_t getImm() const {
365     assert(Kind == Immediate && "Invalid access!");
366     return Imm.Val;
367   }
368 
369   const MCExpr *getExpr() const {
370     assert(Kind == Expression && "Invalid access!");
371     return Expr.Val;
372   }
373 
374   int64_t getExprCRVal() const {
375     assert(Kind == Expression && "Invalid access!");
376     return Expr.CRVal;
377   }
378 
379   const MCExpr *getTLSReg() const {
380     assert(Kind == TLSRegister && "Invalid access!");
381     return TLSReg.Sym;
382   }
383 
384   unsigned getReg() const override {
385     assert(isRegNumber() && "Invalid access!");
386     return (unsigned) Imm.Val;
387   }
388 
389   unsigned getVSReg() const {
390     assert(isVSRegNumber() && "Invalid access!");
391     return (unsigned) Imm.Val;
392   }
393 
394   unsigned getCCReg() const {
395     assert(isCCRegNumber() && "Invalid access!");
396     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
397   }
398 
399   unsigned getCRBit() const {
400     assert(isCRBitNumber() && "Invalid access!");
401     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
402   }
403 
404   unsigned getCRBitMask() const {
405     assert(isCRBitMask() && "Invalid access!");
406     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
407   }
408 
409   bool isToken() const override { return Kind == Token; }
410   bool isImm() const override { return Kind == Immediate || Kind == Expression; }
411   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
412   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
413   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
414   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
415   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
416   bool isU6ImmX2() const { return Kind == Immediate &&
417                                   isUInt<6>(getImm()) &&
418                                   (getImm() & 1) == 0; }
419   bool isU7ImmX4() const { return Kind == Immediate &&
420                                   isUInt<7>(getImm()) &&
421                                   (getImm() & 3) == 0; }
422   bool isU8ImmX8() const { return Kind == Immediate &&
423                                   isUInt<8>(getImm()) &&
424                                   (getImm() & 7) == 0; }
425   bool isU16Imm() const { return Kind == Expression ||
426                                  (Kind == Immediate && isUInt<16>(getImm())); }
427   bool isS16Imm() const { return Kind == Expression ||
428                                  (Kind == Immediate && isInt<16>(getImm())); }
429   bool isS16ImmX4() const { return Kind == Expression ||
430                                    (Kind == Immediate && isInt<16>(getImm()) &&
431                                     (getImm() & 3) == 0); }
432   bool isS17Imm() const { return Kind == Expression ||
433                                  (Kind == Immediate && isInt<17>(getImm())); }
434   bool isTLSReg() const { return Kind == TLSRegister; }
435   bool isDirectBr() const {
436     if (Kind == Expression)
437       return true;
438     if (Kind != Immediate)
439       return false;
440     // Operand must be 64-bit aligned, signed 27-bit immediate.
441     if ((getImm() & 3) != 0)
442       return false;
443     if (isInt<26>(getImm()))
444       return true;
445     if (!IsPPC64) {
446       // In 32-bit mode, large 32-bit quantities wrap around.
447       if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
448         return true;
449     }
450     return false;
451   }
452   bool isCondBr() const { return Kind == Expression ||
453                                  (Kind == Immediate && isInt<16>(getImm()) &&
454                                   (getImm() & 3) == 0); }
455   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
456   bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
457   bool isCCRegNumber() const { return (Kind == Expression
458                                        && isUInt<3>(getExprCRVal())) ||
459                                       (Kind == Immediate
460                                        && isUInt<3>(getImm())); }
461   bool isCRBitNumber() const { return (Kind == Expression
462                                        && isUInt<5>(getExprCRVal())) ||
463                                       (Kind == Immediate
464                                        && isUInt<5>(getImm())); }
465   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
466                                     isPowerOf2_32(getImm()); }
467   bool isMem() const override { return false; }
468   bool isReg() const override { return false; }
469 
470   void addRegOperands(MCInst &Inst, unsigned N) const {
471     llvm_unreachable("addRegOperands");
472   }
473 
474   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
475     assert(N == 1 && "Invalid number of operands!");
476     Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
477   }
478 
479   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
480     assert(N == 1 && "Invalid number of operands!");
481     Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
482   }
483 
484   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
485     assert(N == 1 && "Invalid number of operands!");
486     Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
487   }
488 
489   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
490     assert(N == 1 && "Invalid number of operands!");
491     Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
492   }
493 
494   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
495     if (isPPC64())
496       addRegG8RCOperands(Inst, N);
497     else
498       addRegGPRCOperands(Inst, N);
499   }
500 
501   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
502     if (isPPC64())
503       addRegG8RCNoX0Operands(Inst, N);
504     else
505       addRegGPRCNoR0Operands(Inst, N);
506   }
507 
508   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
509     assert(N == 1 && "Invalid number of operands!");
510     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
511   }
512 
513   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
514     assert(N == 1 && "Invalid number of operands!");
515     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
516   }
517 
518   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
519     assert(N == 1 && "Invalid number of operands!");
520     Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
521   }
522 
523   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
524     assert(N == 1 && "Invalid number of operands!");
525     Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
526   }
527 
528   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
529     assert(N == 1 && "Invalid number of operands!");
530     Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
531   }
532 
533   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
534     assert(N == 1 && "Invalid number of operands!");
535     Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
536   }
537 
538   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
539     assert(N == 1 && "Invalid number of operands!");
540     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
541   }
542 
543   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
544     assert(N == 1 && "Invalid number of operands!");
545     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
546   }
547 
548   void addImmOperands(MCInst &Inst, unsigned N) const {
549     assert(N == 1 && "Invalid number of operands!");
550     if (Kind == Immediate)
551       Inst.addOperand(MCOperand::CreateImm(getImm()));
552     else
553       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
554   }
555 
556   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
557     assert(N == 1 && "Invalid number of operands!");
558     if (Kind == Immediate)
559       Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
560     else
561       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
562   }
563 
564   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
565     assert(N == 1 && "Invalid number of operands!");
566     Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
567   }
568 
569   StringRef getToken() const {
570     assert(Kind == Token && "Invalid access!");
571     return StringRef(Tok.Data, Tok.Length);
572   }
573 
574   void print(raw_ostream &OS) const override;
575 
576   static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
577                                                  bool IsPPC64) {
578     auto Op = make_unique<PPCOperand>(Token);
579     Op->Tok.Data = Str.data();
580     Op->Tok.Length = Str.size();
581     Op->StartLoc = S;
582     Op->EndLoc = S;
583     Op->IsPPC64 = IsPPC64;
584     return Op;
585   }
586 
587   static std::unique_ptr<PPCOperand>
588   CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
589     // Allocate extra memory for the string and copy it.
590     // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
591     // deleter which will destroy them by simply using "delete", not correctly
592     // calling operator delete on this extra memory after calling the dtor
593     // explicitly.
594     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
595     std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
596     Op->Tok.Data = (const char *)(Op.get() + 1);
597     Op->Tok.Length = Str.size();
598     std::memcpy((void *)Op->Tok.Data, Str.data(), Str.size());
599     Op->StartLoc = S;
600     Op->EndLoc = S;
601     Op->IsPPC64 = IsPPC64;
602     return Op;
603   }
604 
605   static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
606                                                bool IsPPC64) {
607     auto Op = make_unique<PPCOperand>(Immediate);
608     Op->Imm.Val = Val;
609     Op->StartLoc = S;
610     Op->EndLoc = E;
611     Op->IsPPC64 = IsPPC64;
612     return Op;
613   }
614 
615   static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
616                                                 SMLoc E, bool IsPPC64) {
617     auto Op = make_unique<PPCOperand>(Expression);
618     Op->Expr.Val = Val;
619     Op->Expr.CRVal = EvaluateCRExpr(Val);
620     Op->StartLoc = S;
621     Op->EndLoc = E;
622     Op->IsPPC64 = IsPPC64;
623     return Op;
624   }
625 
626   static std::unique_ptr<PPCOperand>
627   CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
628     auto Op = make_unique<PPCOperand>(TLSRegister);
629     Op->TLSReg.Sym = Sym;
630     Op->StartLoc = S;
631     Op->EndLoc = E;
632     Op->IsPPC64 = IsPPC64;
633     return Op;
634   }
635 
636   static std::unique_ptr<PPCOperand>
637   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
638     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
639       return CreateImm(CE->getValue(), S, E, IsPPC64);
640 
641     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
642       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
643         return CreateTLSReg(SRE, S, E, IsPPC64);
644 
645     return CreateExpr(Val, S, E, IsPPC64);
646   }
647 };
648 
649 } // end anonymous namespace.
650 
651 void PPCOperand::print(raw_ostream &OS) const {
652   switch (Kind) {
653   case Token:
654     OS << "'" << getToken() << "'";
655     break;
656   case Immediate:
657     OS << getImm();
658     break;
659   case Expression:
660     getExpr()->print(OS);
661     break;
662   case TLSRegister:
663     getTLSReg()->print(OS);
664     break;
665   }
666 }
667 
668 static void
669 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
670   if (Op.isImm()) {
671     Inst.addOperand(MCOperand::CreateImm(-Op.getImm()));
672     return;
673   }
674   const MCExpr *Expr = Op.getExpr();
675   if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
676     if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
677       Inst.addOperand(MCOperand::CreateExpr(UnExpr->getSubExpr()));
678       return;
679     }
680   } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
681     if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
682       const MCExpr *NE = MCBinaryExpr::CreateSub(BinExpr->getRHS(),
683                                                  BinExpr->getLHS(), Ctx);
684       Inst.addOperand(MCOperand::CreateExpr(NE));
685       return;
686     }
687   }
688   Inst.addOperand(MCOperand::CreateExpr(MCUnaryExpr::CreateMinus(Expr, Ctx)));
689 }
690 
691 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
692                                       const OperandVector &Operands) {
693   int Opcode = Inst.getOpcode();
694   switch (Opcode) {
695   case PPC::LAx: {
696     MCInst TmpInst;
697     TmpInst.setOpcode(PPC::LA);
698     TmpInst.addOperand(Inst.getOperand(0));
699     TmpInst.addOperand(Inst.getOperand(2));
700     TmpInst.addOperand(Inst.getOperand(1));
701     Inst = TmpInst;
702     break;
703   }
704   case PPC::SUBI: {
705     MCInst TmpInst;
706     TmpInst.setOpcode(PPC::ADDI);
707     TmpInst.addOperand(Inst.getOperand(0));
708     TmpInst.addOperand(Inst.getOperand(1));
709     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
710     Inst = TmpInst;
711     break;
712   }
713   case PPC::SUBIS: {
714     MCInst TmpInst;
715     TmpInst.setOpcode(PPC::ADDIS);
716     TmpInst.addOperand(Inst.getOperand(0));
717     TmpInst.addOperand(Inst.getOperand(1));
718     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
719     Inst = TmpInst;
720     break;
721   }
722   case PPC::SUBIC: {
723     MCInst TmpInst;
724     TmpInst.setOpcode(PPC::ADDIC);
725     TmpInst.addOperand(Inst.getOperand(0));
726     TmpInst.addOperand(Inst.getOperand(1));
727     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
728     Inst = TmpInst;
729     break;
730   }
731   case PPC::SUBICo: {
732     MCInst TmpInst;
733     TmpInst.setOpcode(PPC::ADDICo);
734     TmpInst.addOperand(Inst.getOperand(0));
735     TmpInst.addOperand(Inst.getOperand(1));
736     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
737     Inst = TmpInst;
738     break;
739   }
740   case PPC::EXTLWI:
741   case PPC::EXTLWIo: {
742     MCInst TmpInst;
743     int64_t N = Inst.getOperand(2).getImm();
744     int64_t B = Inst.getOperand(3).getImm();
745     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
746     TmpInst.addOperand(Inst.getOperand(0));
747     TmpInst.addOperand(Inst.getOperand(1));
748     TmpInst.addOperand(MCOperand::CreateImm(B));
749     TmpInst.addOperand(MCOperand::CreateImm(0));
750     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
751     Inst = TmpInst;
752     break;
753   }
754   case PPC::EXTRWI:
755   case PPC::EXTRWIo: {
756     MCInst TmpInst;
757     int64_t N = Inst.getOperand(2).getImm();
758     int64_t B = Inst.getOperand(3).getImm();
759     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
760     TmpInst.addOperand(Inst.getOperand(0));
761     TmpInst.addOperand(Inst.getOperand(1));
762     TmpInst.addOperand(MCOperand::CreateImm(B + N));
763     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
764     TmpInst.addOperand(MCOperand::CreateImm(31));
765     Inst = TmpInst;
766     break;
767   }
768   case PPC::INSLWI:
769   case PPC::INSLWIo: {
770     MCInst TmpInst;
771     int64_t N = Inst.getOperand(2).getImm();
772     int64_t B = Inst.getOperand(3).getImm();
773     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
774     TmpInst.addOperand(Inst.getOperand(0));
775     TmpInst.addOperand(Inst.getOperand(0));
776     TmpInst.addOperand(Inst.getOperand(1));
777     TmpInst.addOperand(MCOperand::CreateImm(32 - B));
778     TmpInst.addOperand(MCOperand::CreateImm(B));
779     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
780     Inst = TmpInst;
781     break;
782   }
783   case PPC::INSRWI:
784   case PPC::INSRWIo: {
785     MCInst TmpInst;
786     int64_t N = Inst.getOperand(2).getImm();
787     int64_t B = Inst.getOperand(3).getImm();
788     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
789     TmpInst.addOperand(Inst.getOperand(0));
790     TmpInst.addOperand(Inst.getOperand(0));
791     TmpInst.addOperand(Inst.getOperand(1));
792     TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
793     TmpInst.addOperand(MCOperand::CreateImm(B));
794     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
795     Inst = TmpInst;
796     break;
797   }
798   case PPC::ROTRWI:
799   case PPC::ROTRWIo: {
800     MCInst TmpInst;
801     int64_t N = Inst.getOperand(2).getImm();
802     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
803     TmpInst.addOperand(Inst.getOperand(0));
804     TmpInst.addOperand(Inst.getOperand(1));
805     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
806     TmpInst.addOperand(MCOperand::CreateImm(0));
807     TmpInst.addOperand(MCOperand::CreateImm(31));
808     Inst = TmpInst;
809     break;
810   }
811   case PPC::SLWI:
812   case PPC::SLWIo: {
813     MCInst TmpInst;
814     int64_t N = Inst.getOperand(2).getImm();
815     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
816     TmpInst.addOperand(Inst.getOperand(0));
817     TmpInst.addOperand(Inst.getOperand(1));
818     TmpInst.addOperand(MCOperand::CreateImm(N));
819     TmpInst.addOperand(MCOperand::CreateImm(0));
820     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
821     Inst = TmpInst;
822     break;
823   }
824   case PPC::SRWI:
825   case PPC::SRWIo: {
826     MCInst TmpInst;
827     int64_t N = Inst.getOperand(2).getImm();
828     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
829     TmpInst.addOperand(Inst.getOperand(0));
830     TmpInst.addOperand(Inst.getOperand(1));
831     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
832     TmpInst.addOperand(MCOperand::CreateImm(N));
833     TmpInst.addOperand(MCOperand::CreateImm(31));
834     Inst = TmpInst;
835     break;
836   }
837   case PPC::CLRRWI:
838   case PPC::CLRRWIo: {
839     MCInst TmpInst;
840     int64_t N = Inst.getOperand(2).getImm();
841     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
842     TmpInst.addOperand(Inst.getOperand(0));
843     TmpInst.addOperand(Inst.getOperand(1));
844     TmpInst.addOperand(MCOperand::CreateImm(0));
845     TmpInst.addOperand(MCOperand::CreateImm(0));
846     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
847     Inst = TmpInst;
848     break;
849   }
850   case PPC::CLRLSLWI:
851   case PPC::CLRLSLWIo: {
852     MCInst TmpInst;
853     int64_t B = Inst.getOperand(2).getImm();
854     int64_t N = Inst.getOperand(3).getImm();
855     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
856     TmpInst.addOperand(Inst.getOperand(0));
857     TmpInst.addOperand(Inst.getOperand(1));
858     TmpInst.addOperand(MCOperand::CreateImm(N));
859     TmpInst.addOperand(MCOperand::CreateImm(B - N));
860     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
861     Inst = TmpInst;
862     break;
863   }
864   case PPC::EXTLDI:
865   case PPC::EXTLDIo: {
866     MCInst TmpInst;
867     int64_t N = Inst.getOperand(2).getImm();
868     int64_t B = Inst.getOperand(3).getImm();
869     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
870     TmpInst.addOperand(Inst.getOperand(0));
871     TmpInst.addOperand(Inst.getOperand(1));
872     TmpInst.addOperand(MCOperand::CreateImm(B));
873     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
874     Inst = TmpInst;
875     break;
876   }
877   case PPC::EXTRDI:
878   case PPC::EXTRDIo: {
879     MCInst TmpInst;
880     int64_t N = Inst.getOperand(2).getImm();
881     int64_t B = Inst.getOperand(3).getImm();
882     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
883     TmpInst.addOperand(Inst.getOperand(0));
884     TmpInst.addOperand(Inst.getOperand(1));
885     TmpInst.addOperand(MCOperand::CreateImm(B + N));
886     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
887     Inst = TmpInst;
888     break;
889   }
890   case PPC::INSRDI:
891   case PPC::INSRDIo: {
892     MCInst TmpInst;
893     int64_t N = Inst.getOperand(2).getImm();
894     int64_t B = Inst.getOperand(3).getImm();
895     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
896     TmpInst.addOperand(Inst.getOperand(0));
897     TmpInst.addOperand(Inst.getOperand(0));
898     TmpInst.addOperand(Inst.getOperand(1));
899     TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
900     TmpInst.addOperand(MCOperand::CreateImm(B));
901     Inst = TmpInst;
902     break;
903   }
904   case PPC::ROTRDI:
905   case PPC::ROTRDIo: {
906     MCInst TmpInst;
907     int64_t N = Inst.getOperand(2).getImm();
908     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
909     TmpInst.addOperand(Inst.getOperand(0));
910     TmpInst.addOperand(Inst.getOperand(1));
911     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
912     TmpInst.addOperand(MCOperand::CreateImm(0));
913     Inst = TmpInst;
914     break;
915   }
916   case PPC::SLDI:
917   case PPC::SLDIo: {
918     MCInst TmpInst;
919     int64_t N = Inst.getOperand(2).getImm();
920     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
921     TmpInst.addOperand(Inst.getOperand(0));
922     TmpInst.addOperand(Inst.getOperand(1));
923     TmpInst.addOperand(MCOperand::CreateImm(N));
924     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
925     Inst = TmpInst;
926     break;
927   }
928   case PPC::SRDI:
929   case PPC::SRDIo: {
930     MCInst TmpInst;
931     int64_t N = Inst.getOperand(2).getImm();
932     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
933     TmpInst.addOperand(Inst.getOperand(0));
934     TmpInst.addOperand(Inst.getOperand(1));
935     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
936     TmpInst.addOperand(MCOperand::CreateImm(N));
937     Inst = TmpInst;
938     break;
939   }
940   case PPC::CLRRDI:
941   case PPC::CLRRDIo: {
942     MCInst TmpInst;
943     int64_t N = Inst.getOperand(2).getImm();
944     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
945     TmpInst.addOperand(Inst.getOperand(0));
946     TmpInst.addOperand(Inst.getOperand(1));
947     TmpInst.addOperand(MCOperand::CreateImm(0));
948     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
949     Inst = TmpInst;
950     break;
951   }
952   case PPC::CLRLSLDI:
953   case PPC::CLRLSLDIo: {
954     MCInst TmpInst;
955     int64_t B = Inst.getOperand(2).getImm();
956     int64_t N = Inst.getOperand(3).getImm();
957     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
958     TmpInst.addOperand(Inst.getOperand(0));
959     TmpInst.addOperand(Inst.getOperand(1));
960     TmpInst.addOperand(MCOperand::CreateImm(N));
961     TmpInst.addOperand(MCOperand::CreateImm(B - N));
962     Inst = TmpInst;
963     break;
964   }
965   }
966 }
967 
968 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
969                                            OperandVector &Operands,
970                                            MCStreamer &Out, unsigned &ErrorInfo,
971                                            bool MatchingInlineAsm) {
972   MCInst Inst;
973 
974   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
975   default: break;
976   case Match_Success:
977     // Post-process instructions (typically extended mnemonics)
978     ProcessInstruction(Inst, Operands);
979     Inst.setLoc(IDLoc);
980     Out.EmitInstruction(Inst, STI);
981     return false;
982   case Match_MissingFeature:
983     return Error(IDLoc, "instruction use requires an option to be enabled");
984   case Match_MnemonicFail:
985       return Error(IDLoc, "unrecognized instruction mnemonic");
986   case Match_InvalidOperand: {
987     SMLoc ErrorLoc = IDLoc;
988     if (ErrorInfo != ~0U) {
989       if (ErrorInfo >= Operands.size())
990         return Error(IDLoc, "too few operands for instruction");
991 
992       ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
993       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
994     }
995 
996     return Error(ErrorLoc, "invalid operand for instruction");
997   }
998   }
999 
1000   llvm_unreachable("Implement any new match types added!");
1001 }
1002 
1003 bool PPCAsmParser::
1004 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1005   if (Tok.is(AsmToken::Identifier)) {
1006     StringRef Name = Tok.getString();
1007 
1008     if (Name.equals_lower("lr")) {
1009       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1010       IntVal = 8;
1011       return false;
1012     } else if (Name.equals_lower("ctr")) {
1013       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1014       IntVal = 9;
1015       return false;
1016     } else if (Name.equals_lower("vrsave")) {
1017       RegNo = PPC::VRSAVE;
1018       IntVal = 256;
1019       return false;
1020     } else if (Name.startswith_lower("r") &&
1021                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1022       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1023       return false;
1024     } else if (Name.startswith_lower("f") &&
1025                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1026       RegNo = FRegs[IntVal];
1027       return false;
1028     } else if (Name.startswith_lower("v") &&
1029                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1030       RegNo = VRegs[IntVal];
1031       return false;
1032     } else if (Name.startswith_lower("cr") &&
1033                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1034       RegNo = CRRegs[IntVal];
1035       return false;
1036     }
1037   }
1038 
1039   return true;
1040 }
1041 
1042 bool PPCAsmParser::
1043 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1044   const AsmToken &Tok = Parser.getTok();
1045   StartLoc = Tok.getLoc();
1046   EndLoc = Tok.getEndLoc();
1047   RegNo = 0;
1048   int64_t IntVal;
1049 
1050   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1051     Parser.Lex(); // Eat identifier token.
1052     return false;
1053   }
1054 
1055   return Error(StartLoc, "invalid register name");
1056 }
1057 
1058 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1059 /// the expression and check for VK_PPC_LO/HI/HA
1060 /// symbol variants.  If all symbols with modifier use the same
1061 /// variant, return the corresponding PPCMCExpr::VariantKind,
1062 /// and a modified expression using the default symbol variant.
1063 /// Otherwise, return NULL.
1064 const MCExpr *PPCAsmParser::
1065 ExtractModifierFromExpr(const MCExpr *E,
1066                         PPCMCExpr::VariantKind &Variant) {
1067   MCContext &Context = getParser().getContext();
1068   Variant = PPCMCExpr::VK_PPC_None;
1069 
1070   switch (E->getKind()) {
1071   case MCExpr::Target:
1072   case MCExpr::Constant:
1073     return nullptr;
1074 
1075   case MCExpr::SymbolRef: {
1076     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1077 
1078     switch (SRE->getKind()) {
1079     case MCSymbolRefExpr::VK_PPC_LO:
1080       Variant = PPCMCExpr::VK_PPC_LO;
1081       break;
1082     case MCSymbolRefExpr::VK_PPC_HI:
1083       Variant = PPCMCExpr::VK_PPC_HI;
1084       break;
1085     case MCSymbolRefExpr::VK_PPC_HA:
1086       Variant = PPCMCExpr::VK_PPC_HA;
1087       break;
1088     case MCSymbolRefExpr::VK_PPC_HIGHER:
1089       Variant = PPCMCExpr::VK_PPC_HIGHER;
1090       break;
1091     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1092       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1093       break;
1094     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1095       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1096       break;
1097     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1098       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1099       break;
1100     default:
1101       return nullptr;
1102     }
1103 
1104     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1105   }
1106 
1107   case MCExpr::Unary: {
1108     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1109     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1110     if (!Sub)
1111       return nullptr;
1112     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1113   }
1114 
1115   case MCExpr::Binary: {
1116     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1117     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1118     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1119     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1120 
1121     if (!LHS && !RHS)
1122       return nullptr;
1123 
1124     if (!LHS) LHS = BE->getLHS();
1125     if (!RHS) RHS = BE->getRHS();
1126 
1127     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1128       Variant = RHSVariant;
1129     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1130       Variant = LHSVariant;
1131     else if (LHSVariant == RHSVariant)
1132       Variant = LHSVariant;
1133     else
1134       return nullptr;
1135 
1136     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1137   }
1138   }
1139 
1140   llvm_unreachable("Invalid expression kind!");
1141 }
1142 
1143 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1144 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1145 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1146 /// FIXME: This is a hack.
1147 const MCExpr *PPCAsmParser::
1148 FixupVariantKind(const MCExpr *E) {
1149   MCContext &Context = getParser().getContext();
1150 
1151   switch (E->getKind()) {
1152   case MCExpr::Target:
1153   case MCExpr::Constant:
1154     return E;
1155 
1156   case MCExpr::SymbolRef: {
1157     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1158     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1159 
1160     switch (SRE->getKind()) {
1161     case MCSymbolRefExpr::VK_TLSGD:
1162       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1163       break;
1164     case MCSymbolRefExpr::VK_TLSLD:
1165       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1166       break;
1167     default:
1168       return E;
1169     }
1170     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1171   }
1172 
1173   case MCExpr::Unary: {
1174     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1175     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1176     if (Sub == UE->getSubExpr())
1177       return E;
1178     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1179   }
1180 
1181   case MCExpr::Binary: {
1182     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1183     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1184     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1185     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1186       return E;
1187     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1188   }
1189   }
1190 
1191   llvm_unreachable("Invalid expression kind!");
1192 }
1193 
1194 /// ParseExpression.  This differs from the default "parseExpression" in that
1195 /// it handles modifiers.
1196 bool PPCAsmParser::
1197 ParseExpression(const MCExpr *&EVal) {
1198 
1199   if (isDarwin())
1200     return ParseDarwinExpression(EVal);
1201 
1202   // (ELF Platforms)
1203   // Handle \code @l/@ha \endcode
1204   if (getParser().parseExpression(EVal))
1205     return true;
1206 
1207   EVal = FixupVariantKind(EVal);
1208 
1209   PPCMCExpr::VariantKind Variant;
1210   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1211   if (E)
1212     EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1213 
1214   return false;
1215 }
1216 
1217 /// ParseDarwinExpression.  (MachO Platforms)
1218 /// This differs from the default "parseExpression" in that it handles detection
1219 /// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1220 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1221 /// syntax form so it is done here.  TODO: Determine if there is merit in arranging
1222 /// for this to be done at a higher level.
1223 bool PPCAsmParser::
1224 ParseDarwinExpression(const MCExpr *&EVal) {
1225   PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1226   switch (getLexer().getKind()) {
1227   default:
1228     break;
1229   case AsmToken::Identifier:
1230     // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1231     // something starting with any other char should be part of the
1232     // asm syntax.  If handwritten asm includes an identifier like lo16,
1233     // then all bets are off - but no-one would do that, right?
1234     StringRef poss = Parser.getTok().getString();
1235     if (poss.equals_lower("lo16")) {
1236       Variant = PPCMCExpr::VK_PPC_LO;
1237     } else if (poss.equals_lower("hi16")) {
1238       Variant = PPCMCExpr::VK_PPC_HI;
1239     } else if (poss.equals_lower("ha16")) {
1240       Variant = PPCMCExpr::VK_PPC_HA;
1241     }
1242     if (Variant != PPCMCExpr::VK_PPC_None) {
1243       Parser.Lex(); // Eat the xx16
1244       if (getLexer().isNot(AsmToken::LParen))
1245         return Error(Parser.getTok().getLoc(), "expected '('");
1246       Parser.Lex(); // Eat the '('
1247     }
1248     break;
1249   }
1250 
1251   if (getParser().parseExpression(EVal))
1252     return true;
1253 
1254   if (Variant != PPCMCExpr::VK_PPC_None) {
1255     if (getLexer().isNot(AsmToken::RParen))
1256       return Error(Parser.getTok().getLoc(), "expected ')'");
1257     Parser.Lex(); // Eat the ')'
1258     EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1259   }
1260   return false;
1261 }
1262 
1263 /// ParseOperand
1264 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1265 /// rNN for MachO.
1266 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1267   SMLoc S = Parser.getTok().getLoc();
1268   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1269   const MCExpr *EVal;
1270 
1271   // Attempt to parse the next token as an immediate
1272   switch (getLexer().getKind()) {
1273   // Special handling for register names.  These are interpreted
1274   // as immediates corresponding to the register number.
1275   case AsmToken::Percent:
1276     Parser.Lex(); // Eat the '%'.
1277     unsigned RegNo;
1278     int64_t IntVal;
1279     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1280       Parser.Lex(); // Eat the identifier token.
1281       Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1282       return false;
1283     }
1284     return Error(S, "invalid register name");
1285 
1286   case AsmToken::Identifier:
1287     // Note that non-register-name identifiers from the compiler will begin
1288     // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1289     // identifiers like r31foo - so we fall through in the event that parsing
1290     // a register name fails.
1291     if (isDarwin()) {
1292       unsigned RegNo;
1293       int64_t IntVal;
1294       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1295         Parser.Lex(); // Eat the identifier token.
1296         Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1297         return false;
1298       }
1299     }
1300   // Fall-through to process non-register-name identifiers as expression.
1301   // All other expressions
1302   case AsmToken::LParen:
1303   case AsmToken::Plus:
1304   case AsmToken::Minus:
1305   case AsmToken::Integer:
1306   case AsmToken::Dot:
1307   case AsmToken::Dollar:
1308   case AsmToken::Exclaim:
1309   case AsmToken::Tilde:
1310     if (!ParseExpression(EVal))
1311       break;
1312     /* fall through */
1313   default:
1314     return Error(S, "unknown operand");
1315   }
1316 
1317   // Push the parsed operand into the list of operands
1318   Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1319 
1320   // Check whether this is a TLS call expression
1321   bool TLSCall = false;
1322   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1323     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1324 
1325   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1326     const MCExpr *TLSSym;
1327 
1328     Parser.Lex(); // Eat the '('.
1329     S = Parser.getTok().getLoc();
1330     if (ParseExpression(TLSSym))
1331       return Error(S, "invalid TLS call expression");
1332     if (getLexer().isNot(AsmToken::RParen))
1333       return Error(Parser.getTok().getLoc(), "missing ')'");
1334     E = Parser.getTok().getLoc();
1335     Parser.Lex(); // Eat the ')'.
1336 
1337     Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1338   }
1339 
1340   // Otherwise, check for D-form memory operands
1341   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1342     Parser.Lex(); // Eat the '('.
1343     S = Parser.getTok().getLoc();
1344 
1345     int64_t IntVal;
1346     switch (getLexer().getKind()) {
1347     case AsmToken::Percent:
1348       Parser.Lex(); // Eat the '%'.
1349       unsigned RegNo;
1350       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1351         return Error(S, "invalid register name");
1352       Parser.Lex(); // Eat the identifier token.
1353       break;
1354 
1355     case AsmToken::Integer:
1356       if (!isDarwin()) {
1357         if (getParser().parseAbsoluteExpression(IntVal) ||
1358           IntVal < 0 || IntVal > 31)
1359         return Error(S, "invalid register number");
1360       } else {
1361         return Error(S, "unexpected integer value");
1362       }
1363       break;
1364 
1365    case AsmToken::Identifier:
1366     if (isDarwin()) {
1367       unsigned RegNo;
1368       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1369         Parser.Lex(); // Eat the identifier token.
1370         break;
1371       }
1372     }
1373     // Fall-through..
1374 
1375     default:
1376       return Error(S, "invalid memory operand");
1377     }
1378 
1379     if (getLexer().isNot(AsmToken::RParen))
1380       return Error(Parser.getTok().getLoc(), "missing ')'");
1381     E = Parser.getTok().getLoc();
1382     Parser.Lex(); // Eat the ')'.
1383 
1384     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1385   }
1386 
1387   return false;
1388 }
1389 
1390 /// Parse an instruction mnemonic followed by its operands.
1391 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1392                                     SMLoc NameLoc, OperandVector &Operands) {
1393   // The first operand is the token for the instruction name.
1394   // If the next character is a '+' or '-', we need to add it to the
1395   // instruction name, to match what TableGen is doing.
1396   std::string NewOpcode;
1397   if (getLexer().is(AsmToken::Plus)) {
1398     getLexer().Lex();
1399     NewOpcode = Name;
1400     NewOpcode += '+';
1401     Name = NewOpcode;
1402   }
1403   if (getLexer().is(AsmToken::Minus)) {
1404     getLexer().Lex();
1405     NewOpcode = Name;
1406     NewOpcode += '-';
1407     Name = NewOpcode;
1408   }
1409   // If the instruction ends in a '.', we need to create a separate
1410   // token for it, to match what TableGen is doing.
1411   size_t Dot = Name.find('.');
1412   StringRef Mnemonic = Name.slice(0, Dot);
1413   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1414     Operands.push_back(
1415         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1416   else
1417     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1418   if (Dot != StringRef::npos) {
1419     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1420     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1421     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1422       Operands.push_back(
1423           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1424     else
1425       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1426   }
1427 
1428   // If there are no more operands then finish
1429   if (getLexer().is(AsmToken::EndOfStatement))
1430     return false;
1431 
1432   // Parse the first operand
1433   if (ParseOperand(Operands))
1434     return true;
1435 
1436   while (getLexer().isNot(AsmToken::EndOfStatement) &&
1437          getLexer().is(AsmToken::Comma)) {
1438     // Consume the comma token
1439     getLexer().Lex();
1440 
1441     // Parse the next operand
1442     if (ParseOperand(Operands))
1443       return true;
1444   }
1445 
1446   return false;
1447 }
1448 
1449 /// ParseDirective parses the PPC specific directives
1450 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1451   StringRef IDVal = DirectiveID.getIdentifier();
1452   if (!isDarwin()) {
1453     if (IDVal == ".word")
1454       return ParseDirectiveWord(2, DirectiveID.getLoc());
1455     if (IDVal == ".llong")
1456       return ParseDirectiveWord(8, DirectiveID.getLoc());
1457     if (IDVal == ".tc")
1458       return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1459     if (IDVal == ".machine")
1460       return ParseDirectiveMachine(DirectiveID.getLoc());
1461     if (IDVal == ".abiversion")
1462       return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1463     if (IDVal == ".localentry")
1464       return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1465   } else {
1466     if (IDVal == ".machine")
1467       return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1468   }
1469   return true;
1470 }
1471 
1472 /// ParseDirectiveWord
1473 ///  ::= .word [ expression (, expression)* ]
1474 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1475   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1476     for (;;) {
1477       const MCExpr *Value;
1478       if (getParser().parseExpression(Value))
1479         return false;
1480 
1481       getParser().getStreamer().EmitValue(Value, Size);
1482 
1483       if (getLexer().is(AsmToken::EndOfStatement))
1484         break;
1485 
1486       if (getLexer().isNot(AsmToken::Comma))
1487         return Error(L, "unexpected token in directive");
1488       Parser.Lex();
1489     }
1490   }
1491 
1492   Parser.Lex();
1493   return false;
1494 }
1495 
1496 /// ParseDirectiveTC
1497 ///  ::= .tc [ symbol (, expression)* ]
1498 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1499   // Skip TC symbol, which is only used with XCOFF.
1500   while (getLexer().isNot(AsmToken::EndOfStatement)
1501          && getLexer().isNot(AsmToken::Comma))
1502     Parser.Lex();
1503   if (getLexer().isNot(AsmToken::Comma)) {
1504     Error(L, "unexpected token in directive");
1505     return false;
1506   }
1507   Parser.Lex();
1508 
1509   // Align to word size.
1510   getParser().getStreamer().EmitValueToAlignment(Size);
1511 
1512   // Emit expressions.
1513   return ParseDirectiveWord(Size, L);
1514 }
1515 
1516 /// ParseDirectiveMachine (ELF platforms)
1517 ///  ::= .machine [ cpu | "push" | "pop" ]
1518 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1519   if (getLexer().isNot(AsmToken::Identifier) &&
1520       getLexer().isNot(AsmToken::String)) {
1521     Error(L, "unexpected token in directive");
1522     return false;
1523   }
1524 
1525   StringRef CPU = Parser.getTok().getIdentifier();
1526   Parser.Lex();
1527 
1528   // FIXME: Right now, the parser always allows any available
1529   // instruction, so the .machine directive is not useful.
1530   // Implement ".machine any" (by doing nothing) for the benefit
1531   // of existing assembler code.  Likewise, we can then implement
1532   // ".machine push" and ".machine pop" as no-op.
1533   if (CPU != "any" && CPU != "push" && CPU != "pop") {
1534     Error(L, "unrecognized machine type");
1535     return false;
1536   }
1537 
1538   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1539     Error(L, "unexpected token in directive");
1540     return false;
1541   }
1542   PPCTargetStreamer &TStreamer =
1543       *static_cast<PPCTargetStreamer *>(
1544            getParser().getStreamer().getTargetStreamer());
1545   TStreamer.emitMachine(CPU);
1546 
1547   return false;
1548 }
1549 
1550 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1551 ///  ::= .machine cpu-identifier
1552 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1553   if (getLexer().isNot(AsmToken::Identifier) &&
1554       getLexer().isNot(AsmToken::String)) {
1555     Error(L, "unexpected token in directive");
1556     return false;
1557   }
1558 
1559   StringRef CPU = Parser.getTok().getIdentifier();
1560   Parser.Lex();
1561 
1562   // FIXME: this is only the 'default' set of cpu variants.
1563   // However we don't act on this information at present, this is simply
1564   // allowing parsing to proceed with minimal sanity checking.
1565   if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1566     Error(L, "unrecognized cpu type");
1567     return false;
1568   }
1569 
1570   if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1571     Error(L, "wrong cpu type specified for 64bit");
1572     return false;
1573   }
1574   if (!isPPC64() && CPU == "ppc64") {
1575     Error(L, "wrong cpu type specified for 32bit");
1576     return false;
1577   }
1578 
1579   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1580     Error(L, "unexpected token in directive");
1581     return false;
1582   }
1583 
1584   return false;
1585 }
1586 
1587 /// ParseDirectiveAbiVersion
1588 ///  ::= .abiversion constant-expression
1589 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1590   int64_t AbiVersion;
1591   if (getParser().parseAbsoluteExpression(AbiVersion)){
1592     Error(L, "expected constant expression");
1593     return false;
1594   }
1595   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1596     Error(L, "unexpected token in directive");
1597     return false;
1598   }
1599 
1600   PPCTargetStreamer &TStreamer =
1601       *static_cast<PPCTargetStreamer *>(
1602            getParser().getStreamer().getTargetStreamer());
1603   TStreamer.emitAbiVersion(AbiVersion);
1604 
1605   return false;
1606 }
1607 
1608 /// ParseDirectiveLocalEntry
1609 ///  ::= .localentry symbol, expression
1610 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1611   StringRef Name;
1612   if (getParser().parseIdentifier(Name)) {
1613     Error(L, "expected identifier in directive");
1614     return false;
1615   }
1616   MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
1617 
1618   if (getLexer().isNot(AsmToken::Comma)) {
1619     Error(L, "unexpected token in directive");
1620     return false;
1621   }
1622   Lex();
1623 
1624   const MCExpr *Expr;
1625   if (getParser().parseExpression(Expr)) {
1626     Error(L, "expected expression");
1627     return false;
1628   }
1629 
1630   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1631     Error(L, "unexpected token in directive");
1632     return false;
1633   }
1634 
1635   PPCTargetStreamer &TStreamer =
1636       *static_cast<PPCTargetStreamer *>(
1637            getParser().getStreamer().getTargetStreamer());
1638   TStreamer.emitLocalEntry(Sym, Expr);
1639 
1640   return false;
1641 }
1642 
1643 
1644 
1645 /// Force static initialization.
1646 extern "C" void LLVMInitializePowerPCAsmParser() {
1647   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1648   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1649   RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1650 }
1651 
1652 #define GET_REGISTER_MATCHER
1653 #define GET_MATCHER_IMPLEMENTATION
1654 #include "PPCGenAsmMatcher.inc"
1655 
1656 // Define this matcher function after the auto-generated include so we
1657 // have the match class enum definitions.
1658 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1659                                                   unsigned Kind) {
1660   // If the kind is a token for a literal immediate, check if our asm
1661   // operand matches. This is for InstAliases which have a fixed-value
1662   // immediate in the syntax.
1663   int64_t ImmVal;
1664   switch (Kind) {
1665     case MCK_0: ImmVal = 0; break;
1666     case MCK_1: ImmVal = 1; break;
1667     case MCK_2: ImmVal = 2; break;
1668     case MCK_3: ImmVal = 3; break;
1669     case MCK_4: ImmVal = 4; break;
1670     case MCK_5: ImmVal = 5; break;
1671     case MCK_6: ImmVal = 6; break;
1672     case MCK_7: ImmVal = 7; break;
1673     default: return Match_InvalidOperand;
1674   }
1675 
1676   PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1677   if (Op.isImm() && Op.getImm() == ImmVal)
1678     return Match_Success;
1679 
1680   return Match_InvalidOperand;
1681 }
1682 
1683 const MCExpr *
1684 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1685                                   MCSymbolRefExpr::VariantKind Variant,
1686                                   MCContext &Ctx) {
1687   switch (Variant) {
1688   case MCSymbolRefExpr::VK_PPC_LO:
1689     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1690   case MCSymbolRefExpr::VK_PPC_HI:
1691     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1692   case MCSymbolRefExpr::VK_PPC_HA:
1693     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1694   case MCSymbolRefExpr::VK_PPC_HIGHER:
1695     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1696   case MCSymbolRefExpr::VK_PPC_HIGHERA:
1697     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1698   case MCSymbolRefExpr::VK_PPC_HIGHEST:
1699     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1700   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1701     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1702   default:
1703     return nullptr;
1704   }
1705 }
1706