1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCExpr.h" 10 #include "MCTargetDesc/PPCMCTargetDesc.h" 11 #include "PPCTargetStreamer.h" 12 #include "TargetInfo/PowerPCTargetInfo.h" 13 #include "llvm/ADT/STLExtras.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Twine.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCParser/MCAsmLexer.h" 21 #include "llvm/MC/MCParser/MCAsmParser.h" 22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 23 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 24 #include "llvm/MC/MCStreamer.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/MC/MCSymbolELF.h" 27 #include "llvm/Support/SourceMgr.h" 28 #include "llvm/Support/TargetRegistry.h" 29 #include "llvm/Support/raw_ostream.h" 30 31 using namespace llvm; 32 33 DEFINE_PPC_REGCLASSES; 34 35 // Evaluate an expression containing condition register 36 // or condition register field symbols. Returns positive 37 // value on success, or -1 on error. 38 static int64_t 39 EvaluateCRExpr(const MCExpr *E) { 40 switch (E->getKind()) { 41 case MCExpr::Target: 42 return -1; 43 44 case MCExpr::Constant: { 45 int64_t Res = cast<MCConstantExpr>(E)->getValue(); 46 return Res < 0 ? -1 : Res; 47 } 48 49 case MCExpr::SymbolRef: { 50 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 51 StringRef Name = SRE->getSymbol().getName(); 52 53 if (Name == "lt") return 0; 54 if (Name == "gt") return 1; 55 if (Name == "eq") return 2; 56 if (Name == "so") return 3; 57 if (Name == "un") return 3; 58 59 if (Name == "cr0") return 0; 60 if (Name == "cr1") return 1; 61 if (Name == "cr2") return 2; 62 if (Name == "cr3") return 3; 63 if (Name == "cr4") return 4; 64 if (Name == "cr5") return 5; 65 if (Name == "cr6") return 6; 66 if (Name == "cr7") return 7; 67 68 return -1; 69 } 70 71 case MCExpr::Unary: 72 return -1; 73 74 case MCExpr::Binary: { 75 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 76 int64_t LHSVal = EvaluateCRExpr(BE->getLHS()); 77 int64_t RHSVal = EvaluateCRExpr(BE->getRHS()); 78 int64_t Res; 79 80 if (LHSVal < 0 || RHSVal < 0) 81 return -1; 82 83 switch (BE->getOpcode()) { 84 default: return -1; 85 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break; 86 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break; 87 } 88 89 return Res < 0 ? -1 : Res; 90 } 91 } 92 93 llvm_unreachable("Invalid expression kind!"); 94 } 95 96 namespace { 97 98 struct PPCOperand; 99 100 class PPCAsmParser : public MCTargetAsmParser { 101 bool IsPPC64; 102 bool IsDarwin; 103 104 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); } 105 106 bool isPPC64() const { return IsPPC64; } 107 bool isDarwin() const { return IsDarwin; } 108 109 bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal); 110 111 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 112 113 const MCExpr *ExtractModifierFromExpr(const MCExpr *E, 114 PPCMCExpr::VariantKind &Variant); 115 const MCExpr *FixupVariantKind(const MCExpr *E); 116 bool ParseExpression(const MCExpr *&EVal); 117 bool ParseDarwinExpression(const MCExpr *&EVal); 118 119 bool ParseOperand(OperandVector &Operands); 120 121 bool ParseDirectiveWord(unsigned Size, AsmToken ID); 122 bool ParseDirectiveTC(unsigned Size, AsmToken ID); 123 bool ParseDirectiveMachine(SMLoc L); 124 bool ParseDarwinDirectiveMachine(SMLoc L); 125 bool ParseDirectiveAbiVersion(SMLoc L); 126 bool ParseDirectiveLocalEntry(SMLoc L); 127 128 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 129 OperandVector &Operands, MCStreamer &Out, 130 uint64_t &ErrorInfo, 131 bool MatchingInlineAsm) override; 132 133 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops); 134 135 /// @name Auto-generated Match Functions 136 /// { 137 138 #define GET_ASSEMBLER_HEADER 139 #include "PPCGenAsmMatcher.inc" 140 141 /// } 142 143 144 public: 145 PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &, 146 const MCInstrInfo &MII, const MCTargetOptions &Options) 147 : MCTargetAsmParser(Options, STI, MII) { 148 // Check for 64-bit vs. 32-bit pointer mode. 149 const Triple &TheTriple = STI.getTargetTriple(); 150 IsPPC64 = TheTriple.isPPC64(); 151 IsDarwin = TheTriple.isMacOSX(); 152 // Initialize the set of available features. 153 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 154 } 155 156 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 157 SMLoc NameLoc, OperandVector &Operands) override; 158 159 bool ParseDirective(AsmToken DirectiveID) override; 160 161 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 162 unsigned Kind) override; 163 164 const MCExpr *applyModifierToExpr(const MCExpr *E, 165 MCSymbolRefExpr::VariantKind, 166 MCContext &Ctx) override; 167 }; 168 169 /// PPCOperand - Instances of this class represent a parsed PowerPC machine 170 /// instruction. 171 struct PPCOperand : public MCParsedAsmOperand { 172 enum KindTy { 173 Token, 174 Immediate, 175 ContextImmediate, 176 Expression, 177 TLSRegister 178 } Kind; 179 180 SMLoc StartLoc, EndLoc; 181 bool IsPPC64; 182 183 struct TokOp { 184 const char *Data; 185 unsigned Length; 186 }; 187 188 struct ImmOp { 189 int64_t Val; 190 }; 191 192 struct ExprOp { 193 const MCExpr *Val; 194 int64_t CRVal; // Cached result of EvaluateCRExpr(Val) 195 }; 196 197 struct TLSRegOp { 198 const MCSymbolRefExpr *Sym; 199 }; 200 201 union { 202 struct TokOp Tok; 203 struct ImmOp Imm; 204 struct ExprOp Expr; 205 struct TLSRegOp TLSReg; 206 }; 207 208 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 209 public: 210 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() { 211 Kind = o.Kind; 212 StartLoc = o.StartLoc; 213 EndLoc = o.EndLoc; 214 IsPPC64 = o.IsPPC64; 215 switch (Kind) { 216 case Token: 217 Tok = o.Tok; 218 break; 219 case Immediate: 220 case ContextImmediate: 221 Imm = o.Imm; 222 break; 223 case Expression: 224 Expr = o.Expr; 225 break; 226 case TLSRegister: 227 TLSReg = o.TLSReg; 228 break; 229 } 230 } 231 232 // Disable use of sized deallocation due to overallocation of PPCOperand 233 // objects in CreateTokenWithStringCopy. 234 void operator delete(void *p) { ::operator delete(p); } 235 236 /// getStartLoc - Get the location of the first token of this operand. 237 SMLoc getStartLoc() const override { return StartLoc; } 238 239 /// getEndLoc - Get the location of the last token of this operand. 240 SMLoc getEndLoc() const override { return EndLoc; } 241 242 /// getLocRange - Get the range between the first and last token of this 243 /// operand. 244 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 245 246 /// isPPC64 - True if this operand is for an instruction in 64-bit mode. 247 bool isPPC64() const { return IsPPC64; } 248 249 int64_t getImm() const { 250 assert(Kind == Immediate && "Invalid access!"); 251 return Imm.Val; 252 } 253 int64_t getImmS16Context() const { 254 assert((Kind == Immediate || Kind == ContextImmediate) && 255 "Invalid access!"); 256 if (Kind == Immediate) 257 return Imm.Val; 258 return static_cast<int16_t>(Imm.Val); 259 } 260 int64_t getImmU16Context() const { 261 assert((Kind == Immediate || Kind == ContextImmediate) && 262 "Invalid access!"); 263 return Imm.Val; 264 } 265 266 const MCExpr *getExpr() const { 267 assert(Kind == Expression && "Invalid access!"); 268 return Expr.Val; 269 } 270 271 int64_t getExprCRVal() const { 272 assert(Kind == Expression && "Invalid access!"); 273 return Expr.CRVal; 274 } 275 276 const MCExpr *getTLSReg() const { 277 assert(Kind == TLSRegister && "Invalid access!"); 278 return TLSReg.Sym; 279 } 280 281 unsigned getReg() const override { 282 assert(isRegNumber() && "Invalid access!"); 283 return (unsigned) Imm.Val; 284 } 285 286 unsigned getVSReg() const { 287 assert(isVSRegNumber() && "Invalid access!"); 288 return (unsigned) Imm.Val; 289 } 290 291 unsigned getCCReg() const { 292 assert(isCCRegNumber() && "Invalid access!"); 293 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 294 } 295 296 unsigned getCRBit() const { 297 assert(isCRBitNumber() && "Invalid access!"); 298 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 299 } 300 301 unsigned getCRBitMask() const { 302 assert(isCRBitMask() && "Invalid access!"); 303 return 7 - countTrailingZeros<uint64_t>(Imm.Val); 304 } 305 306 bool isToken() const override { return Kind == Token; } 307 bool isImm() const override { 308 return Kind == Immediate || Kind == Expression; 309 } 310 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } 311 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } 312 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } 313 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } 314 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } 315 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } 316 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } 317 bool isU6ImmX2() const { return Kind == Immediate && 318 isUInt<6>(getImm()) && 319 (getImm() & 1) == 0; } 320 bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); } 321 bool isU7ImmX4() const { return Kind == Immediate && 322 isUInt<7>(getImm()) && 323 (getImm() & 3) == 0; } 324 bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); } 325 bool isU8ImmX8() const { return Kind == Immediate && 326 isUInt<8>(getImm()) && 327 (getImm() & 7) == 0; } 328 329 bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); } 330 bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); } 331 bool isU16Imm() const { 332 switch (Kind) { 333 case Expression: 334 return true; 335 case Immediate: 336 case ContextImmediate: 337 return isUInt<16>(getImmU16Context()); 338 default: 339 return false; 340 } 341 } 342 bool isS16Imm() const { 343 switch (Kind) { 344 case Expression: 345 return true; 346 case Immediate: 347 case ContextImmediate: 348 return isInt<16>(getImmS16Context()); 349 default: 350 return false; 351 } 352 } 353 bool isS16ImmX4() const { return Kind == Expression || 354 (Kind == Immediate && isInt<16>(getImm()) && 355 (getImm() & 3) == 0); } 356 bool isS16ImmX16() const { return Kind == Expression || 357 (Kind == Immediate && isInt<16>(getImm()) && 358 (getImm() & 15) == 0); } 359 bool isS34ImmX16() const { return Kind == Expression || 360 (Kind == Immediate && isInt<34>(getImm()) && 361 (getImm() & 15) == 0); } 362 bool isS34Imm() const { 363 // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit 364 // ContextImmediate is needed. 365 return Kind == Expression || (Kind == Immediate && isInt<34>(getImm())); 366 } 367 368 bool isS17Imm() const { 369 switch (Kind) { 370 case Expression: 371 return true; 372 case Immediate: 373 case ContextImmediate: 374 return isInt<17>(getImmS16Context()); 375 default: 376 return false; 377 } 378 } 379 bool isTLSReg() const { return Kind == TLSRegister; } 380 bool isDirectBr() const { 381 if (Kind == Expression) 382 return true; 383 if (Kind != Immediate) 384 return false; 385 // Operand must be 64-bit aligned, signed 27-bit immediate. 386 if ((getImm() & 3) != 0) 387 return false; 388 if (isInt<26>(getImm())) 389 return true; 390 if (!IsPPC64) { 391 // In 32-bit mode, large 32-bit quantities wrap around. 392 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm()))) 393 return true; 394 } 395 return false; 396 } 397 bool isCondBr() const { return Kind == Expression || 398 (Kind == Immediate && isInt<16>(getImm()) && 399 (getImm() & 3) == 0); } 400 bool isImmZero() const { return Kind == Immediate && getImm() == 0; } 401 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } 402 bool isVSRegNumber() const { 403 return Kind == Immediate && isUInt<6>(getImm()); 404 } 405 bool isCCRegNumber() const { return (Kind == Expression 406 && isUInt<3>(getExprCRVal())) || 407 (Kind == Immediate 408 && isUInt<3>(getImm())); } 409 bool isCRBitNumber() const { return (Kind == Expression 410 && isUInt<5>(getExprCRVal())) || 411 (Kind == Immediate 412 && isUInt<5>(getImm())); } 413 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) && 414 isPowerOf2_32(getImm()); } 415 bool isATBitsAsHint() const { return false; } 416 bool isMem() const override { return false; } 417 bool isReg() const override { return false; } 418 419 void addRegOperands(MCInst &Inst, unsigned N) const { 420 llvm_unreachable("addRegOperands"); 421 } 422 423 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { 424 assert(N == 1 && "Invalid number of operands!"); 425 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 426 } 427 428 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { 429 assert(N == 1 && "Invalid number of operands!"); 430 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); 431 } 432 433 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { 434 assert(N == 1 && "Invalid number of operands!"); 435 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); 436 } 437 438 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { 439 assert(N == 1 && "Invalid number of operands!"); 440 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); 441 } 442 443 void addRegGxRCOperands(MCInst &Inst, unsigned N) const { 444 if (isPPC64()) 445 addRegG8RCOperands(Inst, N); 446 else 447 addRegGPRCOperands(Inst, N); 448 } 449 450 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const { 451 if (isPPC64()) 452 addRegG8RCNoX0Operands(Inst, N); 453 else 454 addRegGPRCNoR0Operands(Inst, N); 455 } 456 457 void addRegF4RCOperands(MCInst &Inst, unsigned N) const { 458 assert(N == 1 && "Invalid number of operands!"); 459 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 460 } 461 462 void addRegF8RCOperands(MCInst &Inst, unsigned N) const { 463 assert(N == 1 && "Invalid number of operands!"); 464 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 465 } 466 467 void addRegVFRCOperands(MCInst &Inst, unsigned N) const { 468 assert(N == 1 && "Invalid number of operands!"); 469 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); 470 } 471 472 void addRegVRRCOperands(MCInst &Inst, unsigned N) const { 473 assert(N == 1 && "Invalid number of operands!"); 474 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); 475 } 476 477 void addRegVSRCOperands(MCInst &Inst, unsigned N) const { 478 assert(N == 1 && "Invalid number of operands!"); 479 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); 480 } 481 482 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const { 483 assert(N == 1 && "Invalid number of operands!"); 484 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); 485 } 486 487 void addRegVSSRCOperands(MCInst &Inst, unsigned N) const { 488 assert(N == 1 && "Invalid number of operands!"); 489 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); 490 } 491 492 void addRegQFRCOperands(MCInst &Inst, unsigned N) const { 493 assert(N == 1 && "Invalid number of operands!"); 494 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()])); 495 } 496 497 void addRegQSRCOperands(MCInst &Inst, unsigned N) const { 498 assert(N == 1 && "Invalid number of operands!"); 499 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()])); 500 } 501 502 void addRegQBRCOperands(MCInst &Inst, unsigned N) const { 503 assert(N == 1 && "Invalid number of operands!"); 504 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()])); 505 } 506 507 void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const { 508 assert(N == 1 && "Invalid number of operands!"); 509 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 510 } 511 512 void addRegSPERCOperands(MCInst &Inst, unsigned N) const { 513 assert(N == 1 && "Invalid number of operands!"); 514 Inst.addOperand(MCOperand::createReg(SPERegs[getReg()])); 515 } 516 517 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const { 518 assert(N == 1 && "Invalid number of operands!"); 519 Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()])); 520 } 521 522 void addRegCRRCOperands(MCInst &Inst, unsigned N) const { 523 assert(N == 1 && "Invalid number of operands!"); 524 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()])); 525 } 526 527 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const { 528 assert(N == 1 && "Invalid number of operands!"); 529 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()])); 530 } 531 532 void addImmOperands(MCInst &Inst, unsigned N) const { 533 assert(N == 1 && "Invalid number of operands!"); 534 if (Kind == Immediate) 535 Inst.addOperand(MCOperand::createImm(getImm())); 536 else 537 Inst.addOperand(MCOperand::createExpr(getExpr())); 538 } 539 540 void addS16ImmOperands(MCInst &Inst, unsigned N) const { 541 assert(N == 1 && "Invalid number of operands!"); 542 switch (Kind) { 543 case Immediate: 544 Inst.addOperand(MCOperand::createImm(getImm())); 545 break; 546 case ContextImmediate: 547 Inst.addOperand(MCOperand::createImm(getImmS16Context())); 548 break; 549 default: 550 Inst.addOperand(MCOperand::createExpr(getExpr())); 551 break; 552 } 553 } 554 555 void addU16ImmOperands(MCInst &Inst, unsigned N) const { 556 assert(N == 1 && "Invalid number of operands!"); 557 switch (Kind) { 558 case Immediate: 559 Inst.addOperand(MCOperand::createImm(getImm())); 560 break; 561 case ContextImmediate: 562 Inst.addOperand(MCOperand::createImm(getImmU16Context())); 563 break; 564 default: 565 Inst.addOperand(MCOperand::createExpr(getExpr())); 566 break; 567 } 568 } 569 570 void addBranchTargetOperands(MCInst &Inst, unsigned N) const { 571 assert(N == 1 && "Invalid number of operands!"); 572 if (Kind == Immediate) 573 Inst.addOperand(MCOperand::createImm(getImm() / 4)); 574 else 575 Inst.addOperand(MCOperand::createExpr(getExpr())); 576 } 577 578 void addTLSRegOperands(MCInst &Inst, unsigned N) const { 579 assert(N == 1 && "Invalid number of operands!"); 580 Inst.addOperand(MCOperand::createExpr(getTLSReg())); 581 } 582 583 StringRef getToken() const { 584 assert(Kind == Token && "Invalid access!"); 585 return StringRef(Tok.Data, Tok.Length); 586 } 587 588 void print(raw_ostream &OS) const override; 589 590 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S, 591 bool IsPPC64) { 592 auto Op = std::make_unique<PPCOperand>(Token); 593 Op->Tok.Data = Str.data(); 594 Op->Tok.Length = Str.size(); 595 Op->StartLoc = S; 596 Op->EndLoc = S; 597 Op->IsPPC64 = IsPPC64; 598 return Op; 599 } 600 601 static std::unique_ptr<PPCOperand> 602 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) { 603 // Allocate extra memory for the string and copy it. 604 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default 605 // deleter which will destroy them by simply using "delete", not correctly 606 // calling operator delete on this extra memory after calling the dtor 607 // explicitly. 608 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size()); 609 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token)); 610 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1); 611 Op->Tok.Length = Str.size(); 612 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size()); 613 Op->StartLoc = S; 614 Op->EndLoc = S; 615 Op->IsPPC64 = IsPPC64; 616 return Op; 617 } 618 619 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E, 620 bool IsPPC64) { 621 auto Op = std::make_unique<PPCOperand>(Immediate); 622 Op->Imm.Val = Val; 623 Op->StartLoc = S; 624 Op->EndLoc = E; 625 Op->IsPPC64 = IsPPC64; 626 return Op; 627 } 628 629 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S, 630 SMLoc E, bool IsPPC64) { 631 auto Op = std::make_unique<PPCOperand>(Expression); 632 Op->Expr.Val = Val; 633 Op->Expr.CRVal = EvaluateCRExpr(Val); 634 Op->StartLoc = S; 635 Op->EndLoc = E; 636 Op->IsPPC64 = IsPPC64; 637 return Op; 638 } 639 640 static std::unique_ptr<PPCOperand> 641 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) { 642 auto Op = std::make_unique<PPCOperand>(TLSRegister); 643 Op->TLSReg.Sym = Sym; 644 Op->StartLoc = S; 645 Op->EndLoc = E; 646 Op->IsPPC64 = IsPPC64; 647 return Op; 648 } 649 650 static std::unique_ptr<PPCOperand> 651 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) { 652 auto Op = std::make_unique<PPCOperand>(ContextImmediate); 653 Op->Imm.Val = Val; 654 Op->StartLoc = S; 655 Op->EndLoc = E; 656 Op->IsPPC64 = IsPPC64; 657 return Op; 658 } 659 660 static std::unique_ptr<PPCOperand> 661 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) { 662 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val)) 663 return CreateImm(CE->getValue(), S, E, IsPPC64); 664 665 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val)) 666 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS) 667 return CreateTLSReg(SRE, S, E, IsPPC64); 668 669 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) { 670 int64_t Res; 671 if (TE->evaluateAsConstant(Res)) 672 return CreateContextImm(Res, S, E, IsPPC64); 673 } 674 675 return CreateExpr(Val, S, E, IsPPC64); 676 } 677 }; 678 679 } // end anonymous namespace. 680 681 void PPCOperand::print(raw_ostream &OS) const { 682 switch (Kind) { 683 case Token: 684 OS << "'" << getToken() << "'"; 685 break; 686 case Immediate: 687 case ContextImmediate: 688 OS << getImm(); 689 break; 690 case Expression: 691 OS << *getExpr(); 692 break; 693 case TLSRegister: 694 OS << *getTLSReg(); 695 break; 696 } 697 } 698 699 static void 700 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) { 701 if (Op.isImm()) { 702 Inst.addOperand(MCOperand::createImm(-Op.getImm())); 703 return; 704 } 705 const MCExpr *Expr = Op.getExpr(); 706 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) { 707 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) { 708 Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr())); 709 return; 710 } 711 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) { 712 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) { 713 const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(), 714 BinExpr->getLHS(), Ctx); 715 Inst.addOperand(MCOperand::createExpr(NE)); 716 return; 717 } 718 } 719 Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx))); 720 } 721 722 void PPCAsmParser::ProcessInstruction(MCInst &Inst, 723 const OperandVector &Operands) { 724 int Opcode = Inst.getOpcode(); 725 switch (Opcode) { 726 case PPC::DCBTx: 727 case PPC::DCBTT: 728 case PPC::DCBTSTx: 729 case PPC::DCBTSTT: { 730 MCInst TmpInst; 731 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? 732 PPC::DCBT : PPC::DCBTST); 733 TmpInst.addOperand(MCOperand::createImm( 734 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16)); 735 TmpInst.addOperand(Inst.getOperand(0)); 736 TmpInst.addOperand(Inst.getOperand(1)); 737 Inst = TmpInst; 738 break; 739 } 740 case PPC::DCBTCT: 741 case PPC::DCBTDS: { 742 MCInst TmpInst; 743 TmpInst.setOpcode(PPC::DCBT); 744 TmpInst.addOperand(Inst.getOperand(2)); 745 TmpInst.addOperand(Inst.getOperand(0)); 746 TmpInst.addOperand(Inst.getOperand(1)); 747 Inst = TmpInst; 748 break; 749 } 750 case PPC::DCBTSTCT: 751 case PPC::DCBTSTDS: { 752 MCInst TmpInst; 753 TmpInst.setOpcode(PPC::DCBTST); 754 TmpInst.addOperand(Inst.getOperand(2)); 755 TmpInst.addOperand(Inst.getOperand(0)); 756 TmpInst.addOperand(Inst.getOperand(1)); 757 Inst = TmpInst; 758 break; 759 } 760 case PPC::DCBFx: 761 case PPC::DCBFL: 762 case PPC::DCBFLP: { 763 int L = 0; 764 if (Opcode == PPC::DCBFL) 765 L = 1; 766 else if (Opcode == PPC::DCBFLP) 767 L = 3; 768 769 MCInst TmpInst; 770 TmpInst.setOpcode(PPC::DCBF); 771 TmpInst.addOperand(MCOperand::createImm(L)); 772 TmpInst.addOperand(Inst.getOperand(0)); 773 TmpInst.addOperand(Inst.getOperand(1)); 774 Inst = TmpInst; 775 break; 776 } 777 case PPC::LAx: { 778 MCInst TmpInst; 779 TmpInst.setOpcode(PPC::LA); 780 TmpInst.addOperand(Inst.getOperand(0)); 781 TmpInst.addOperand(Inst.getOperand(2)); 782 TmpInst.addOperand(Inst.getOperand(1)); 783 Inst = TmpInst; 784 break; 785 } 786 case PPC::SUBI: { 787 MCInst TmpInst; 788 TmpInst.setOpcode(PPC::ADDI); 789 TmpInst.addOperand(Inst.getOperand(0)); 790 TmpInst.addOperand(Inst.getOperand(1)); 791 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 792 Inst = TmpInst; 793 break; 794 } 795 case PPC::SUBIS: { 796 MCInst TmpInst; 797 TmpInst.setOpcode(PPC::ADDIS); 798 TmpInst.addOperand(Inst.getOperand(0)); 799 TmpInst.addOperand(Inst.getOperand(1)); 800 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 801 Inst = TmpInst; 802 break; 803 } 804 case PPC::SUBIC: { 805 MCInst TmpInst; 806 TmpInst.setOpcode(PPC::ADDIC); 807 TmpInst.addOperand(Inst.getOperand(0)); 808 TmpInst.addOperand(Inst.getOperand(1)); 809 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 810 Inst = TmpInst; 811 break; 812 } 813 case PPC::SUBIC_rec: { 814 MCInst TmpInst; 815 TmpInst.setOpcode(PPC::ADDIC_rec); 816 TmpInst.addOperand(Inst.getOperand(0)); 817 TmpInst.addOperand(Inst.getOperand(1)); 818 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 819 Inst = TmpInst; 820 break; 821 } 822 case PPC::EXTLWI: 823 case PPC::EXTLWI_rec: { 824 MCInst TmpInst; 825 int64_t N = Inst.getOperand(2).getImm(); 826 int64_t B = Inst.getOperand(3).getImm(); 827 TmpInst.setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec); 828 TmpInst.addOperand(Inst.getOperand(0)); 829 TmpInst.addOperand(Inst.getOperand(1)); 830 TmpInst.addOperand(MCOperand::createImm(B)); 831 TmpInst.addOperand(MCOperand::createImm(0)); 832 TmpInst.addOperand(MCOperand::createImm(N - 1)); 833 Inst = TmpInst; 834 break; 835 } 836 case PPC::EXTRWI: 837 case PPC::EXTRWI_rec: { 838 MCInst TmpInst; 839 int64_t N = Inst.getOperand(2).getImm(); 840 int64_t B = Inst.getOperand(3).getImm(); 841 TmpInst.setOpcode(Opcode == PPC::EXTRWI ? PPC::RLWINM : PPC::RLWINM_rec); 842 TmpInst.addOperand(Inst.getOperand(0)); 843 TmpInst.addOperand(Inst.getOperand(1)); 844 TmpInst.addOperand(MCOperand::createImm(B + N)); 845 TmpInst.addOperand(MCOperand::createImm(32 - N)); 846 TmpInst.addOperand(MCOperand::createImm(31)); 847 Inst = TmpInst; 848 break; 849 } 850 case PPC::INSLWI: 851 case PPC::INSLWI_rec: { 852 MCInst TmpInst; 853 int64_t N = Inst.getOperand(2).getImm(); 854 int64_t B = Inst.getOperand(3).getImm(); 855 TmpInst.setOpcode(Opcode == PPC::INSLWI ? PPC::RLWIMI : PPC::RLWIMI_rec); 856 TmpInst.addOperand(Inst.getOperand(0)); 857 TmpInst.addOperand(Inst.getOperand(0)); 858 TmpInst.addOperand(Inst.getOperand(1)); 859 TmpInst.addOperand(MCOperand::createImm(32 - B)); 860 TmpInst.addOperand(MCOperand::createImm(B)); 861 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 862 Inst = TmpInst; 863 break; 864 } 865 case PPC::INSRWI: 866 case PPC::INSRWI_rec: { 867 MCInst TmpInst; 868 int64_t N = Inst.getOperand(2).getImm(); 869 int64_t B = Inst.getOperand(3).getImm(); 870 TmpInst.setOpcode(Opcode == PPC::INSRWI ? PPC::RLWIMI : PPC::RLWIMI_rec); 871 TmpInst.addOperand(Inst.getOperand(0)); 872 TmpInst.addOperand(Inst.getOperand(0)); 873 TmpInst.addOperand(Inst.getOperand(1)); 874 TmpInst.addOperand(MCOperand::createImm(32 - (B + N))); 875 TmpInst.addOperand(MCOperand::createImm(B)); 876 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 877 Inst = TmpInst; 878 break; 879 } 880 case PPC::ROTRWI: 881 case PPC::ROTRWI_rec: { 882 MCInst TmpInst; 883 int64_t N = Inst.getOperand(2).getImm(); 884 TmpInst.setOpcode(Opcode == PPC::ROTRWI ? PPC::RLWINM : PPC::RLWINM_rec); 885 TmpInst.addOperand(Inst.getOperand(0)); 886 TmpInst.addOperand(Inst.getOperand(1)); 887 TmpInst.addOperand(MCOperand::createImm(32 - N)); 888 TmpInst.addOperand(MCOperand::createImm(0)); 889 TmpInst.addOperand(MCOperand::createImm(31)); 890 Inst = TmpInst; 891 break; 892 } 893 case PPC::SLWI: 894 case PPC::SLWI_rec: { 895 MCInst TmpInst; 896 int64_t N = Inst.getOperand(2).getImm(); 897 TmpInst.setOpcode(Opcode == PPC::SLWI ? PPC::RLWINM : PPC::RLWINM_rec); 898 TmpInst.addOperand(Inst.getOperand(0)); 899 TmpInst.addOperand(Inst.getOperand(1)); 900 TmpInst.addOperand(MCOperand::createImm(N)); 901 TmpInst.addOperand(MCOperand::createImm(0)); 902 TmpInst.addOperand(MCOperand::createImm(31 - N)); 903 Inst = TmpInst; 904 break; 905 } 906 case PPC::SRWI: 907 case PPC::SRWI_rec: { 908 MCInst TmpInst; 909 int64_t N = Inst.getOperand(2).getImm(); 910 TmpInst.setOpcode(Opcode == PPC::SRWI ? PPC::RLWINM : PPC::RLWINM_rec); 911 TmpInst.addOperand(Inst.getOperand(0)); 912 TmpInst.addOperand(Inst.getOperand(1)); 913 TmpInst.addOperand(MCOperand::createImm(32 - N)); 914 TmpInst.addOperand(MCOperand::createImm(N)); 915 TmpInst.addOperand(MCOperand::createImm(31)); 916 Inst = TmpInst; 917 break; 918 } 919 case PPC::CLRRWI: 920 case PPC::CLRRWI_rec: { 921 MCInst TmpInst; 922 int64_t N = Inst.getOperand(2).getImm(); 923 TmpInst.setOpcode(Opcode == PPC::CLRRWI ? PPC::RLWINM : PPC::RLWINM_rec); 924 TmpInst.addOperand(Inst.getOperand(0)); 925 TmpInst.addOperand(Inst.getOperand(1)); 926 TmpInst.addOperand(MCOperand::createImm(0)); 927 TmpInst.addOperand(MCOperand::createImm(0)); 928 TmpInst.addOperand(MCOperand::createImm(31 - N)); 929 Inst = TmpInst; 930 break; 931 } 932 case PPC::CLRLSLWI: 933 case PPC::CLRLSLWI_rec: { 934 MCInst TmpInst; 935 int64_t B = Inst.getOperand(2).getImm(); 936 int64_t N = Inst.getOperand(3).getImm(); 937 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI ? PPC::RLWINM : PPC::RLWINM_rec); 938 TmpInst.addOperand(Inst.getOperand(0)); 939 TmpInst.addOperand(Inst.getOperand(1)); 940 TmpInst.addOperand(MCOperand::createImm(N)); 941 TmpInst.addOperand(MCOperand::createImm(B - N)); 942 TmpInst.addOperand(MCOperand::createImm(31 - N)); 943 Inst = TmpInst; 944 break; 945 } 946 case PPC::EXTLDI: 947 case PPC::EXTLDI_rec: { 948 MCInst TmpInst; 949 int64_t N = Inst.getOperand(2).getImm(); 950 int64_t B = Inst.getOperand(3).getImm(); 951 TmpInst.setOpcode(Opcode == PPC::EXTLDI ? PPC::RLDICR : PPC::RLDICR_rec); 952 TmpInst.addOperand(Inst.getOperand(0)); 953 TmpInst.addOperand(Inst.getOperand(1)); 954 TmpInst.addOperand(MCOperand::createImm(B)); 955 TmpInst.addOperand(MCOperand::createImm(N - 1)); 956 Inst = TmpInst; 957 break; 958 } 959 case PPC::EXTRDI: 960 case PPC::EXTRDI_rec: { 961 MCInst TmpInst; 962 int64_t N = Inst.getOperand(2).getImm(); 963 int64_t B = Inst.getOperand(3).getImm(); 964 TmpInst.setOpcode(Opcode == PPC::EXTRDI ? PPC::RLDICL : PPC::RLDICL_rec); 965 TmpInst.addOperand(Inst.getOperand(0)); 966 TmpInst.addOperand(Inst.getOperand(1)); 967 TmpInst.addOperand(MCOperand::createImm(B + N)); 968 TmpInst.addOperand(MCOperand::createImm(64 - N)); 969 Inst = TmpInst; 970 break; 971 } 972 case PPC::INSRDI: 973 case PPC::INSRDI_rec: { 974 MCInst TmpInst; 975 int64_t N = Inst.getOperand(2).getImm(); 976 int64_t B = Inst.getOperand(3).getImm(); 977 TmpInst.setOpcode(Opcode == PPC::INSRDI ? PPC::RLDIMI : PPC::RLDIMI_rec); 978 TmpInst.addOperand(Inst.getOperand(0)); 979 TmpInst.addOperand(Inst.getOperand(0)); 980 TmpInst.addOperand(Inst.getOperand(1)); 981 TmpInst.addOperand(MCOperand::createImm(64 - (B + N))); 982 TmpInst.addOperand(MCOperand::createImm(B)); 983 Inst = TmpInst; 984 break; 985 } 986 case PPC::ROTRDI: 987 case PPC::ROTRDI_rec: { 988 MCInst TmpInst; 989 int64_t N = Inst.getOperand(2).getImm(); 990 TmpInst.setOpcode(Opcode == PPC::ROTRDI ? PPC::RLDICL : PPC::RLDICL_rec); 991 TmpInst.addOperand(Inst.getOperand(0)); 992 TmpInst.addOperand(Inst.getOperand(1)); 993 TmpInst.addOperand(MCOperand::createImm(64 - N)); 994 TmpInst.addOperand(MCOperand::createImm(0)); 995 Inst = TmpInst; 996 break; 997 } 998 case PPC::SLDI: 999 case PPC::SLDI_rec: { 1000 MCInst TmpInst; 1001 int64_t N = Inst.getOperand(2).getImm(); 1002 TmpInst.setOpcode(Opcode == PPC::SLDI ? PPC::RLDICR : PPC::RLDICR_rec); 1003 TmpInst.addOperand(Inst.getOperand(0)); 1004 TmpInst.addOperand(Inst.getOperand(1)); 1005 TmpInst.addOperand(MCOperand::createImm(N)); 1006 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1007 Inst = TmpInst; 1008 break; 1009 } 1010 case PPC::SUBPCIS: { 1011 MCInst TmpInst; 1012 int64_t N = Inst.getOperand(1).getImm(); 1013 TmpInst.setOpcode(PPC::ADDPCIS); 1014 TmpInst.addOperand(Inst.getOperand(0)); 1015 TmpInst.addOperand(MCOperand::createImm(-N)); 1016 Inst = TmpInst; 1017 break; 1018 } 1019 case PPC::SRDI: 1020 case PPC::SRDI_rec: { 1021 MCInst TmpInst; 1022 int64_t N = Inst.getOperand(2).getImm(); 1023 TmpInst.setOpcode(Opcode == PPC::SRDI ? PPC::RLDICL : PPC::RLDICL_rec); 1024 TmpInst.addOperand(Inst.getOperand(0)); 1025 TmpInst.addOperand(Inst.getOperand(1)); 1026 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1027 TmpInst.addOperand(MCOperand::createImm(N)); 1028 Inst = TmpInst; 1029 break; 1030 } 1031 case PPC::CLRRDI: 1032 case PPC::CLRRDI_rec: { 1033 MCInst TmpInst; 1034 int64_t N = Inst.getOperand(2).getImm(); 1035 TmpInst.setOpcode(Opcode == PPC::CLRRDI ? PPC::RLDICR : PPC::RLDICR_rec); 1036 TmpInst.addOperand(Inst.getOperand(0)); 1037 TmpInst.addOperand(Inst.getOperand(1)); 1038 TmpInst.addOperand(MCOperand::createImm(0)); 1039 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1040 Inst = TmpInst; 1041 break; 1042 } 1043 case PPC::CLRLSLDI: 1044 case PPC::CLRLSLDI_rec: { 1045 MCInst TmpInst; 1046 int64_t B = Inst.getOperand(2).getImm(); 1047 int64_t N = Inst.getOperand(3).getImm(); 1048 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI ? PPC::RLDIC : PPC::RLDIC_rec); 1049 TmpInst.addOperand(Inst.getOperand(0)); 1050 TmpInst.addOperand(Inst.getOperand(1)); 1051 TmpInst.addOperand(MCOperand::createImm(N)); 1052 TmpInst.addOperand(MCOperand::createImm(B - N)); 1053 Inst = TmpInst; 1054 break; 1055 } 1056 case PPC::RLWINMbm: 1057 case PPC::RLWINMbm_rec: { 1058 unsigned MB, ME; 1059 int64_t BM = Inst.getOperand(3).getImm(); 1060 if (!isRunOfOnes(BM, MB, ME)) 1061 break; 1062 1063 MCInst TmpInst; 1064 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINM_rec); 1065 TmpInst.addOperand(Inst.getOperand(0)); 1066 TmpInst.addOperand(Inst.getOperand(1)); 1067 TmpInst.addOperand(Inst.getOperand(2)); 1068 TmpInst.addOperand(MCOperand::createImm(MB)); 1069 TmpInst.addOperand(MCOperand::createImm(ME)); 1070 Inst = TmpInst; 1071 break; 1072 } 1073 case PPC::RLWIMIbm: 1074 case PPC::RLWIMIbm_rec: { 1075 unsigned MB, ME; 1076 int64_t BM = Inst.getOperand(3).getImm(); 1077 if (!isRunOfOnes(BM, MB, ME)) 1078 break; 1079 1080 MCInst TmpInst; 1081 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMI_rec); 1082 TmpInst.addOperand(Inst.getOperand(0)); 1083 TmpInst.addOperand(Inst.getOperand(0)); // The tied operand. 1084 TmpInst.addOperand(Inst.getOperand(1)); 1085 TmpInst.addOperand(Inst.getOperand(2)); 1086 TmpInst.addOperand(MCOperand::createImm(MB)); 1087 TmpInst.addOperand(MCOperand::createImm(ME)); 1088 Inst = TmpInst; 1089 break; 1090 } 1091 case PPC::RLWNMbm: 1092 case PPC::RLWNMbm_rec: { 1093 unsigned MB, ME; 1094 int64_t BM = Inst.getOperand(3).getImm(); 1095 if (!isRunOfOnes(BM, MB, ME)) 1096 break; 1097 1098 MCInst TmpInst; 1099 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNM_rec); 1100 TmpInst.addOperand(Inst.getOperand(0)); 1101 TmpInst.addOperand(Inst.getOperand(1)); 1102 TmpInst.addOperand(Inst.getOperand(2)); 1103 TmpInst.addOperand(MCOperand::createImm(MB)); 1104 TmpInst.addOperand(MCOperand::createImm(ME)); 1105 Inst = TmpInst; 1106 break; 1107 } 1108 case PPC::MFTB: { 1109 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) { 1110 assert(Inst.getNumOperands() == 2 && "Expecting two operands"); 1111 Inst.setOpcode(PPC::MFSPR); 1112 } 1113 break; 1114 } 1115 case PPC::CP_COPYx: 1116 case PPC::CP_COPY_FIRST: { 1117 MCInst TmpInst; 1118 TmpInst.setOpcode(PPC::CP_COPY); 1119 TmpInst.addOperand(Inst.getOperand(0)); 1120 TmpInst.addOperand(Inst.getOperand(1)); 1121 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1)); 1122 1123 Inst = TmpInst; 1124 break; 1125 } 1126 case PPC::CP_PASTEx : 1127 case PPC::CP_PASTE_LAST: { 1128 MCInst TmpInst; 1129 TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ? PPC::CP_PASTE 1130 : PPC::CP_PASTE_rec); 1131 TmpInst.addOperand(Inst.getOperand(0)); 1132 TmpInst.addOperand(Inst.getOperand(1)); 1133 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1)); 1134 1135 Inst = TmpInst; 1136 break; 1137 } 1138 } 1139 } 1140 1141 static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, 1142 unsigned VariantID = 0); 1143 1144 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 1145 OperandVector &Operands, 1146 MCStreamer &Out, uint64_t &ErrorInfo, 1147 bool MatchingInlineAsm) { 1148 MCInst Inst; 1149 1150 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { 1151 case Match_Success: 1152 // Post-process instructions (typically extended mnemonics) 1153 ProcessInstruction(Inst, Operands); 1154 Inst.setLoc(IDLoc); 1155 Out.EmitInstruction(Inst, getSTI()); 1156 return false; 1157 case Match_MissingFeature: 1158 return Error(IDLoc, "instruction use requires an option to be enabled"); 1159 case Match_MnemonicFail: { 1160 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); 1161 std::string Suggestion = PPCMnemonicSpellCheck( 1162 ((PPCOperand &)*Operands[0]).getToken(), FBS); 1163 return Error(IDLoc, "invalid instruction" + Suggestion, 1164 ((PPCOperand &)*Operands[0]).getLocRange()); 1165 } 1166 case Match_InvalidOperand: { 1167 SMLoc ErrorLoc = IDLoc; 1168 if (ErrorInfo != ~0ULL) { 1169 if (ErrorInfo >= Operands.size()) 1170 return Error(IDLoc, "too few operands for instruction"); 1171 1172 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc(); 1173 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 1174 } 1175 1176 return Error(ErrorLoc, "invalid operand for instruction"); 1177 } 1178 } 1179 1180 llvm_unreachable("Implement any new match types added!"); 1181 } 1182 1183 bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) { 1184 if (getParser().getTok().is(AsmToken::Identifier)) { 1185 StringRef Name = getParser().getTok().getString(); 1186 if (Name.equals_lower("lr")) { 1187 RegNo = isPPC64()? PPC::LR8 : PPC::LR; 1188 IntVal = 8; 1189 } else if (Name.equals_lower("ctr")) { 1190 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR; 1191 IntVal = 9; 1192 } else if (Name.equals_lower("vrsave")) { 1193 RegNo = PPC::VRSAVE; 1194 IntVal = 256; 1195 } else if (Name.startswith_lower("r") && 1196 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1197 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal]; 1198 } else if (Name.startswith_lower("f") && 1199 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1200 RegNo = FRegs[IntVal]; 1201 } else if (Name.startswith_lower("vs") && 1202 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) { 1203 RegNo = VSRegs[IntVal]; 1204 } else if (Name.startswith_lower("v") && 1205 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1206 RegNo = VRegs[IntVal]; 1207 } else if (Name.startswith_lower("q") && 1208 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1209 RegNo = QFRegs[IntVal]; 1210 } else if (Name.startswith_lower("cr") && 1211 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { 1212 RegNo = CRRegs[IntVal]; 1213 } else 1214 return true; 1215 getParser().Lex(); 1216 return false; 1217 } 1218 return true; 1219 } 1220 1221 bool PPCAsmParser:: 1222 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 1223 const AsmToken &Tok = getParser().getTok(); 1224 StartLoc = Tok.getLoc(); 1225 EndLoc = Tok.getEndLoc(); 1226 RegNo = 0; 1227 int64_t IntVal; 1228 if (MatchRegisterName(RegNo, IntVal)) 1229 return TokError("invalid register name"); 1230 return false; 1231 } 1232 1233 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan 1234 /// the expression and check for VK_PPC_LO/HI/HA 1235 /// symbol variants. If all symbols with modifier use the same 1236 /// variant, return the corresponding PPCMCExpr::VariantKind, 1237 /// and a modified expression using the default symbol variant. 1238 /// Otherwise, return NULL. 1239 const MCExpr *PPCAsmParser:: 1240 ExtractModifierFromExpr(const MCExpr *E, 1241 PPCMCExpr::VariantKind &Variant) { 1242 MCContext &Context = getParser().getContext(); 1243 Variant = PPCMCExpr::VK_PPC_None; 1244 1245 switch (E->getKind()) { 1246 case MCExpr::Target: 1247 case MCExpr::Constant: 1248 return nullptr; 1249 1250 case MCExpr::SymbolRef: { 1251 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1252 1253 switch (SRE->getKind()) { 1254 case MCSymbolRefExpr::VK_PPC_LO: 1255 Variant = PPCMCExpr::VK_PPC_LO; 1256 break; 1257 case MCSymbolRefExpr::VK_PPC_HI: 1258 Variant = PPCMCExpr::VK_PPC_HI; 1259 break; 1260 case MCSymbolRefExpr::VK_PPC_HA: 1261 Variant = PPCMCExpr::VK_PPC_HA; 1262 break; 1263 case MCSymbolRefExpr::VK_PPC_HIGH: 1264 Variant = PPCMCExpr::VK_PPC_HIGH; 1265 break; 1266 case MCSymbolRefExpr::VK_PPC_HIGHA: 1267 Variant = PPCMCExpr::VK_PPC_HIGHA; 1268 break; 1269 case MCSymbolRefExpr::VK_PPC_HIGHER: 1270 Variant = PPCMCExpr::VK_PPC_HIGHER; 1271 break; 1272 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1273 Variant = PPCMCExpr::VK_PPC_HIGHERA; 1274 break; 1275 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1276 Variant = PPCMCExpr::VK_PPC_HIGHEST; 1277 break; 1278 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1279 Variant = PPCMCExpr::VK_PPC_HIGHESTA; 1280 break; 1281 default: 1282 return nullptr; 1283 } 1284 1285 return MCSymbolRefExpr::create(&SRE->getSymbol(), Context); 1286 } 1287 1288 case MCExpr::Unary: { 1289 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1290 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant); 1291 if (!Sub) 1292 return nullptr; 1293 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1294 } 1295 1296 case MCExpr::Binary: { 1297 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1298 PPCMCExpr::VariantKind LHSVariant, RHSVariant; 1299 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant); 1300 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant); 1301 1302 if (!LHS && !RHS) 1303 return nullptr; 1304 1305 if (!LHS) LHS = BE->getLHS(); 1306 if (!RHS) RHS = BE->getRHS(); 1307 1308 if (LHSVariant == PPCMCExpr::VK_PPC_None) 1309 Variant = RHSVariant; 1310 else if (RHSVariant == PPCMCExpr::VK_PPC_None) 1311 Variant = LHSVariant; 1312 else if (LHSVariant == RHSVariant) 1313 Variant = LHSVariant; 1314 else 1315 return nullptr; 1316 1317 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1318 } 1319 } 1320 1321 llvm_unreachable("Invalid expression kind!"); 1322 } 1323 1324 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace 1325 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having 1326 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT. 1327 /// FIXME: This is a hack. 1328 const MCExpr *PPCAsmParser:: 1329 FixupVariantKind(const MCExpr *E) { 1330 MCContext &Context = getParser().getContext(); 1331 1332 switch (E->getKind()) { 1333 case MCExpr::Target: 1334 case MCExpr::Constant: 1335 return E; 1336 1337 case MCExpr::SymbolRef: { 1338 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1339 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; 1340 1341 switch (SRE->getKind()) { 1342 case MCSymbolRefExpr::VK_TLSGD: 1343 Variant = MCSymbolRefExpr::VK_PPC_TLSGD; 1344 break; 1345 case MCSymbolRefExpr::VK_TLSLD: 1346 Variant = MCSymbolRefExpr::VK_PPC_TLSLD; 1347 break; 1348 default: 1349 return E; 1350 } 1351 return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context); 1352 } 1353 1354 case MCExpr::Unary: { 1355 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1356 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr()); 1357 if (Sub == UE->getSubExpr()) 1358 return E; 1359 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1360 } 1361 1362 case MCExpr::Binary: { 1363 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1364 const MCExpr *LHS = FixupVariantKind(BE->getLHS()); 1365 const MCExpr *RHS = FixupVariantKind(BE->getRHS()); 1366 if (LHS == BE->getLHS() && RHS == BE->getRHS()) 1367 return E; 1368 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1369 } 1370 } 1371 1372 llvm_unreachable("Invalid expression kind!"); 1373 } 1374 1375 /// ParseExpression. This differs from the default "parseExpression" in that 1376 /// it handles modifiers. 1377 bool PPCAsmParser:: 1378 ParseExpression(const MCExpr *&EVal) { 1379 1380 if (isDarwin()) 1381 return ParseDarwinExpression(EVal); 1382 1383 // (ELF Platforms) 1384 // Handle \code @l/@ha \endcode 1385 if (getParser().parseExpression(EVal)) 1386 return true; 1387 1388 EVal = FixupVariantKind(EVal); 1389 1390 PPCMCExpr::VariantKind Variant; 1391 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant); 1392 if (E) 1393 EVal = PPCMCExpr::create(Variant, E, getParser().getContext()); 1394 1395 return false; 1396 } 1397 1398 /// ParseDarwinExpression. (MachO Platforms) 1399 /// This differs from the default "parseExpression" in that it handles detection 1400 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present, 1401 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO 1402 /// syntax form so it is done here. TODO: Determine if there is merit in 1403 /// arranging for this to be done at a higher level. 1404 bool PPCAsmParser:: 1405 ParseDarwinExpression(const MCExpr *&EVal) { 1406 MCAsmParser &Parser = getParser(); 1407 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None; 1408 switch (getLexer().getKind()) { 1409 default: 1410 break; 1411 case AsmToken::Identifier: 1412 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus 1413 // something starting with any other char should be part of the 1414 // asm syntax. If handwritten asm includes an identifier like lo16, 1415 // then all bets are off - but no-one would do that, right? 1416 StringRef poss = Parser.getTok().getString(); 1417 if (poss.equals_lower("lo16")) { 1418 Variant = PPCMCExpr::VK_PPC_LO; 1419 } else if (poss.equals_lower("hi16")) { 1420 Variant = PPCMCExpr::VK_PPC_HI; 1421 } else if (poss.equals_lower("ha16")) { 1422 Variant = PPCMCExpr::VK_PPC_HA; 1423 } 1424 if (Variant != PPCMCExpr::VK_PPC_None) { 1425 Parser.Lex(); // Eat the xx16 1426 if (getLexer().isNot(AsmToken::LParen)) 1427 return Error(Parser.getTok().getLoc(), "expected '('"); 1428 Parser.Lex(); // Eat the '(' 1429 } 1430 break; 1431 } 1432 1433 if (getParser().parseExpression(EVal)) 1434 return true; 1435 1436 if (Variant != PPCMCExpr::VK_PPC_None) { 1437 if (getLexer().isNot(AsmToken::RParen)) 1438 return Error(Parser.getTok().getLoc(), "expected ')'"); 1439 Parser.Lex(); // Eat the ')' 1440 EVal = PPCMCExpr::create(Variant, EVal, getParser().getContext()); 1441 } 1442 return false; 1443 } 1444 1445 /// ParseOperand 1446 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and 1447 /// rNN for MachO. 1448 bool PPCAsmParser::ParseOperand(OperandVector &Operands) { 1449 MCAsmParser &Parser = getParser(); 1450 SMLoc S = Parser.getTok().getLoc(); 1451 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1452 const MCExpr *EVal; 1453 1454 // Attempt to parse the next token as an immediate 1455 switch (getLexer().getKind()) { 1456 // Special handling for register names. These are interpreted 1457 // as immediates corresponding to the register number. 1458 case AsmToken::Percent: 1459 Parser.Lex(); // Eat the '%'. 1460 unsigned RegNo; 1461 int64_t IntVal; 1462 if (MatchRegisterName(RegNo, IntVal)) 1463 return Error(S, "invalid register name"); 1464 1465 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1466 return false; 1467 1468 case AsmToken::Identifier: 1469 case AsmToken::LParen: 1470 case AsmToken::Plus: 1471 case AsmToken::Minus: 1472 case AsmToken::Integer: 1473 case AsmToken::Dot: 1474 case AsmToken::Dollar: 1475 case AsmToken::Exclaim: 1476 case AsmToken::Tilde: 1477 // Note that non-register-name identifiers from the compiler will begin 1478 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include 1479 // identifiers like r31foo - so we fall through in the event that parsing 1480 // a register name fails. 1481 if (isDarwin()) { 1482 unsigned RegNo; 1483 int64_t IntVal; 1484 if (!MatchRegisterName(RegNo, IntVal)) { 1485 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1486 return false; 1487 } 1488 } 1489 // All other expressions 1490 1491 if (!ParseExpression(EVal)) 1492 break; 1493 // Fall-through 1494 LLVM_FALLTHROUGH; 1495 default: 1496 return Error(S, "unknown operand"); 1497 } 1498 1499 // Push the parsed operand into the list of operands 1500 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64())); 1501 1502 // Check whether this is a TLS call expression 1503 bool TLSCall = false; 1504 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal)) 1505 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr"; 1506 1507 if (TLSCall && getLexer().is(AsmToken::LParen)) { 1508 const MCExpr *TLSSym; 1509 1510 Parser.Lex(); // Eat the '('. 1511 S = Parser.getTok().getLoc(); 1512 if (ParseExpression(TLSSym)) 1513 return Error(S, "invalid TLS call expression"); 1514 if (getLexer().isNot(AsmToken::RParen)) 1515 return Error(Parser.getTok().getLoc(), "missing ')'"); 1516 E = Parser.getTok().getLoc(); 1517 Parser.Lex(); // Eat the ')'. 1518 1519 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64())); 1520 } 1521 1522 // Otherwise, check for D-form memory operands 1523 if (!TLSCall && getLexer().is(AsmToken::LParen)) { 1524 Parser.Lex(); // Eat the '('. 1525 S = Parser.getTok().getLoc(); 1526 1527 int64_t IntVal; 1528 switch (getLexer().getKind()) { 1529 case AsmToken::Percent: 1530 Parser.Lex(); // Eat the '%'. 1531 unsigned RegNo; 1532 if (MatchRegisterName(RegNo, IntVal)) 1533 return Error(S, "invalid register name"); 1534 break; 1535 1536 case AsmToken::Integer: 1537 if (isDarwin()) 1538 return Error(S, "unexpected integer value"); 1539 else if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 || 1540 IntVal > 31) 1541 return Error(S, "invalid register number"); 1542 break; 1543 case AsmToken::Identifier: 1544 if (isDarwin()) { 1545 unsigned RegNo; 1546 if (!MatchRegisterName(RegNo, IntVal)) { 1547 break; 1548 } 1549 } 1550 LLVM_FALLTHROUGH; 1551 1552 default: 1553 return Error(S, "invalid memory operand"); 1554 } 1555 1556 E = Parser.getTok().getLoc(); 1557 if (parseToken(AsmToken::RParen, "missing ')'")) 1558 return true; 1559 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1560 } 1561 1562 return false; 1563 } 1564 1565 /// Parse an instruction mnemonic followed by its operands. 1566 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 1567 SMLoc NameLoc, OperandVector &Operands) { 1568 // The first operand is the token for the instruction name. 1569 // If the next character is a '+' or '-', we need to add it to the 1570 // instruction name, to match what TableGen is doing. 1571 std::string NewOpcode; 1572 if (parseOptionalToken(AsmToken::Plus)) { 1573 NewOpcode = Name; 1574 NewOpcode += '+'; 1575 Name = NewOpcode; 1576 } 1577 if (parseOptionalToken(AsmToken::Minus)) { 1578 NewOpcode = Name; 1579 NewOpcode += '-'; 1580 Name = NewOpcode; 1581 } 1582 // If the instruction ends in a '.', we need to create a separate 1583 // token for it, to match what TableGen is doing. 1584 size_t Dot = Name.find('.'); 1585 StringRef Mnemonic = Name.slice(0, Dot); 1586 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1587 Operands.push_back( 1588 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64())); 1589 else 1590 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64())); 1591 if (Dot != StringRef::npos) { 1592 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot); 1593 StringRef DotStr = Name.slice(Dot, StringRef::npos); 1594 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1595 Operands.push_back( 1596 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64())); 1597 else 1598 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64())); 1599 } 1600 1601 // If there are no more operands then finish 1602 if (parseOptionalToken(AsmToken::EndOfStatement)) 1603 return false; 1604 1605 // Parse the first operand 1606 if (ParseOperand(Operands)) 1607 return true; 1608 1609 while (!parseOptionalToken(AsmToken::EndOfStatement)) { 1610 if (parseToken(AsmToken::Comma) || ParseOperand(Operands)) 1611 return true; 1612 } 1613 1614 // We'll now deal with an unfortunate special case: the syntax for the dcbt 1615 // and dcbtst instructions differs for server vs. embedded cores. 1616 // The syntax for dcbt is: 1617 // dcbt ra, rb, th [server] 1618 // dcbt th, ra, rb [embedded] 1619 // where th can be omitted when it is 0. dcbtst is the same. We take the 1620 // server form to be the default, so swap the operands if we're parsing for 1621 // an embedded core (they'll be swapped again upon printing). 1622 if (getSTI().getFeatureBits()[PPC::FeatureBookE] && 1623 Operands.size() == 4 && 1624 (Name == "dcbt" || Name == "dcbtst")) { 1625 std::swap(Operands[1], Operands[3]); 1626 std::swap(Operands[2], Operands[1]); 1627 } 1628 1629 return false; 1630 } 1631 1632 /// ParseDirective parses the PPC specific directives 1633 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) { 1634 StringRef IDVal = DirectiveID.getIdentifier(); 1635 if (isDarwin()) { 1636 if (IDVal == ".machine") 1637 ParseDarwinDirectiveMachine(DirectiveID.getLoc()); 1638 else 1639 return true; 1640 } else if (IDVal == ".word") 1641 ParseDirectiveWord(2, DirectiveID); 1642 else if (IDVal == ".llong") 1643 ParseDirectiveWord(8, DirectiveID); 1644 else if (IDVal == ".tc") 1645 ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID); 1646 else if (IDVal == ".machine") 1647 ParseDirectiveMachine(DirectiveID.getLoc()); 1648 else if (IDVal == ".abiversion") 1649 ParseDirectiveAbiVersion(DirectiveID.getLoc()); 1650 else if (IDVal == ".localentry") 1651 ParseDirectiveLocalEntry(DirectiveID.getLoc()); 1652 else 1653 return true; 1654 return false; 1655 } 1656 1657 /// ParseDirectiveWord 1658 /// ::= .word [ expression (, expression)* ] 1659 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) { 1660 auto parseOp = [&]() -> bool { 1661 const MCExpr *Value; 1662 SMLoc ExprLoc = getParser().getTok().getLoc(); 1663 if (getParser().parseExpression(Value)) 1664 return true; 1665 if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) { 1666 assert(Size <= 8 && "Invalid size"); 1667 uint64_t IntValue = MCE->getValue(); 1668 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue)) 1669 return Error(ExprLoc, "literal value out of range for '" + 1670 ID.getIdentifier() + "' directive"); 1671 getStreamer().EmitIntValue(IntValue, Size); 1672 } else 1673 getStreamer().EmitValue(Value, Size, ExprLoc); 1674 return false; 1675 }; 1676 1677 if (parseMany(parseOp)) 1678 return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive"); 1679 return false; 1680 } 1681 1682 /// ParseDirectiveTC 1683 /// ::= .tc [ symbol (, expression)* ] 1684 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) { 1685 MCAsmParser &Parser = getParser(); 1686 // Skip TC symbol, which is only used with XCOFF. 1687 while (getLexer().isNot(AsmToken::EndOfStatement) 1688 && getLexer().isNot(AsmToken::Comma)) 1689 Parser.Lex(); 1690 if (parseToken(AsmToken::Comma)) 1691 return addErrorSuffix(" in '.tc' directive"); 1692 1693 // Align to word size. 1694 getParser().getStreamer().EmitValueToAlignment(Size); 1695 1696 // Emit expressions. 1697 return ParseDirectiveWord(Size, ID); 1698 } 1699 1700 /// ParseDirectiveMachine (ELF platforms) 1701 /// ::= .machine [ cpu | "push" | "pop" ] 1702 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) { 1703 MCAsmParser &Parser = getParser(); 1704 if (Parser.getTok().isNot(AsmToken::Identifier) && 1705 Parser.getTok().isNot(AsmToken::String)) 1706 return Error(L, "unexpected token in '.machine' directive"); 1707 1708 StringRef CPU = Parser.getTok().getIdentifier(); 1709 1710 // FIXME: Right now, the parser always allows any available 1711 // instruction, so the .machine directive is not useful. 1712 // Implement ".machine any" (by doing nothing) for the benefit 1713 // of existing assembler code. Likewise, we can then implement 1714 // ".machine push" and ".machine pop" as no-op. 1715 if (CPU != "any" && CPU != "push" && CPU != "pop") 1716 return TokError("unrecognized machine type"); 1717 1718 Parser.Lex(); 1719 1720 if (parseToken(AsmToken::EndOfStatement)) 1721 return addErrorSuffix(" in '.machine' directive"); 1722 1723 PPCTargetStreamer &TStreamer = 1724 *static_cast<PPCTargetStreamer *>( 1725 getParser().getStreamer().getTargetStreamer()); 1726 TStreamer.emitMachine(CPU); 1727 1728 return false; 1729 } 1730 1731 /// ParseDarwinDirectiveMachine (Mach-o platforms) 1732 /// ::= .machine cpu-identifier 1733 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) { 1734 MCAsmParser &Parser = getParser(); 1735 if (Parser.getTok().isNot(AsmToken::Identifier) && 1736 Parser.getTok().isNot(AsmToken::String)) 1737 return Error(L, "unexpected token in directive"); 1738 1739 StringRef CPU = Parser.getTok().getIdentifier(); 1740 Parser.Lex(); 1741 1742 // FIXME: this is only the 'default' set of cpu variants. 1743 // However we don't act on this information at present, this is simply 1744 // allowing parsing to proceed with minimal sanity checking. 1745 if (check(CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64", L, 1746 "unrecognized cpu type") || 1747 check(isPPC64() && (CPU == "ppc7400" || CPU == "ppc"), L, 1748 "wrong cpu type specified for 64bit") || 1749 check(!isPPC64() && CPU == "ppc64", L, 1750 "wrong cpu type specified for 32bit") || 1751 parseToken(AsmToken::EndOfStatement)) 1752 return addErrorSuffix(" in '.machine' directive"); 1753 return false; 1754 } 1755 1756 /// ParseDirectiveAbiVersion 1757 /// ::= .abiversion constant-expression 1758 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) { 1759 int64_t AbiVersion; 1760 if (check(getParser().parseAbsoluteExpression(AbiVersion), L, 1761 "expected constant expression") || 1762 parseToken(AsmToken::EndOfStatement)) 1763 return addErrorSuffix(" in '.abiversion' directive"); 1764 1765 PPCTargetStreamer &TStreamer = 1766 *static_cast<PPCTargetStreamer *>( 1767 getParser().getStreamer().getTargetStreamer()); 1768 TStreamer.emitAbiVersion(AbiVersion); 1769 1770 return false; 1771 } 1772 1773 /// ParseDirectiveLocalEntry 1774 /// ::= .localentry symbol, expression 1775 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) { 1776 StringRef Name; 1777 if (getParser().parseIdentifier(Name)) 1778 return Error(L, "expected identifier in '.localentry' directive"); 1779 1780 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name)); 1781 const MCExpr *Expr; 1782 1783 if (parseToken(AsmToken::Comma) || 1784 check(getParser().parseExpression(Expr), L, "expected expression") || 1785 parseToken(AsmToken::EndOfStatement)) 1786 return addErrorSuffix(" in '.localentry' directive"); 1787 1788 PPCTargetStreamer &TStreamer = 1789 *static_cast<PPCTargetStreamer *>( 1790 getParser().getStreamer().getTargetStreamer()); 1791 TStreamer.emitLocalEntry(Sym, Expr); 1792 1793 return false; 1794 } 1795 1796 1797 1798 /// Force static initialization. 1799 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCAsmParser() { 1800 RegisterMCAsmParser<PPCAsmParser> A(getThePPC32Target()); 1801 RegisterMCAsmParser<PPCAsmParser> B(getThePPC64Target()); 1802 RegisterMCAsmParser<PPCAsmParser> C(getThePPC64LETarget()); 1803 } 1804 1805 #define GET_REGISTER_MATCHER 1806 #define GET_MATCHER_IMPLEMENTATION 1807 #define GET_MNEMONIC_SPELL_CHECKER 1808 #include "PPCGenAsmMatcher.inc" 1809 1810 // Define this matcher function after the auto-generated include so we 1811 // have the match class enum definitions. 1812 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, 1813 unsigned Kind) { 1814 // If the kind is a token for a literal immediate, check if our asm 1815 // operand matches. This is for InstAliases which have a fixed-value 1816 // immediate in the syntax. 1817 int64_t ImmVal; 1818 switch (Kind) { 1819 case MCK_0: ImmVal = 0; break; 1820 case MCK_1: ImmVal = 1; break; 1821 case MCK_2: ImmVal = 2; break; 1822 case MCK_3: ImmVal = 3; break; 1823 case MCK_4: ImmVal = 4; break; 1824 case MCK_5: ImmVal = 5; break; 1825 case MCK_6: ImmVal = 6; break; 1826 case MCK_7: ImmVal = 7; break; 1827 default: return Match_InvalidOperand; 1828 } 1829 1830 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp); 1831 if (Op.isImm() && Op.getImm() == ImmVal) 1832 return Match_Success; 1833 1834 return Match_InvalidOperand; 1835 } 1836 1837 const MCExpr * 1838 PPCAsmParser::applyModifierToExpr(const MCExpr *E, 1839 MCSymbolRefExpr::VariantKind Variant, 1840 MCContext &Ctx) { 1841 switch (Variant) { 1842 case MCSymbolRefExpr::VK_PPC_LO: 1843 return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, Ctx); 1844 case MCSymbolRefExpr::VK_PPC_HI: 1845 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, Ctx); 1846 case MCSymbolRefExpr::VK_PPC_HA: 1847 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, Ctx); 1848 case MCSymbolRefExpr::VK_PPC_HIGH: 1849 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGH, E, Ctx); 1850 case MCSymbolRefExpr::VK_PPC_HIGHA: 1851 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHA, E, Ctx); 1852 case MCSymbolRefExpr::VK_PPC_HIGHER: 1853 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, Ctx); 1854 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1855 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, Ctx); 1856 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1857 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, Ctx); 1858 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1859 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, Ctx); 1860 default: 1861 return nullptr; 1862 } 1863 } 1864