1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCExpr.h" 10 #include "MCTargetDesc/PPCMCTargetDesc.h" 11 #include "PPCTargetStreamer.h" 12 #include "TargetInfo/PowerPCTargetInfo.h" 13 #include "llvm/ADT/STLExtras.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Twine.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCParser/MCAsmLexer.h" 21 #include "llvm/MC/MCParser/MCAsmParser.h" 22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 23 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 24 #include "llvm/MC/MCStreamer.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/MC/MCSymbolELF.h" 27 #include "llvm/Support/SourceMgr.h" 28 #include "llvm/Support/TargetRegistry.h" 29 #include "llvm/Support/raw_ostream.h" 30 31 using namespace llvm; 32 33 DEFINE_PPC_REGCLASSES; 34 35 // Evaluate an expression containing condition register 36 // or condition register field symbols. Returns positive 37 // value on success, or -1 on error. 38 static int64_t 39 EvaluateCRExpr(const MCExpr *E) { 40 switch (E->getKind()) { 41 case MCExpr::Target: 42 return -1; 43 44 case MCExpr::Constant: { 45 int64_t Res = cast<MCConstantExpr>(E)->getValue(); 46 return Res < 0 ? -1 : Res; 47 } 48 49 case MCExpr::SymbolRef: { 50 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 51 StringRef Name = SRE->getSymbol().getName(); 52 53 if (Name == "lt") return 0; 54 if (Name == "gt") return 1; 55 if (Name == "eq") return 2; 56 if (Name == "so") return 3; 57 if (Name == "un") return 3; 58 59 if (Name == "cr0") return 0; 60 if (Name == "cr1") return 1; 61 if (Name == "cr2") return 2; 62 if (Name == "cr3") return 3; 63 if (Name == "cr4") return 4; 64 if (Name == "cr5") return 5; 65 if (Name == "cr6") return 6; 66 if (Name == "cr7") return 7; 67 68 return -1; 69 } 70 71 case MCExpr::Unary: 72 return -1; 73 74 case MCExpr::Binary: { 75 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 76 int64_t LHSVal = EvaluateCRExpr(BE->getLHS()); 77 int64_t RHSVal = EvaluateCRExpr(BE->getRHS()); 78 int64_t Res; 79 80 if (LHSVal < 0 || RHSVal < 0) 81 return -1; 82 83 switch (BE->getOpcode()) { 84 default: return -1; 85 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break; 86 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break; 87 } 88 89 return Res < 0 ? -1 : Res; 90 } 91 } 92 93 llvm_unreachable("Invalid expression kind!"); 94 } 95 96 namespace { 97 98 struct PPCOperand; 99 100 class PPCAsmParser : public MCTargetAsmParser { 101 bool IsPPC64; 102 bool IsDarwin; 103 104 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); } 105 106 bool isPPC64() const { return IsPPC64; } 107 bool isDarwin() const { return IsDarwin; } 108 109 bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal); 110 111 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 112 OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, 113 SMLoc &EndLoc) override; 114 115 const MCExpr *ExtractModifierFromExpr(const MCExpr *E, 116 PPCMCExpr::VariantKind &Variant); 117 const MCExpr *FixupVariantKind(const MCExpr *E); 118 bool ParseExpression(const MCExpr *&EVal); 119 bool ParseDarwinExpression(const MCExpr *&EVal); 120 121 bool ParseOperand(OperandVector &Operands); 122 123 bool ParseDirectiveWord(unsigned Size, AsmToken ID); 124 bool ParseDirectiveTC(unsigned Size, AsmToken ID); 125 bool ParseDirectiveMachine(SMLoc L); 126 bool ParseDarwinDirectiveMachine(SMLoc L); 127 bool ParseDirectiveAbiVersion(SMLoc L); 128 bool ParseDirectiveLocalEntry(SMLoc L); 129 130 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 131 OperandVector &Operands, MCStreamer &Out, 132 uint64_t &ErrorInfo, 133 bool MatchingInlineAsm) override; 134 135 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops); 136 137 /// @name Auto-generated Match Functions 138 /// { 139 140 #define GET_ASSEMBLER_HEADER 141 #include "PPCGenAsmMatcher.inc" 142 143 /// } 144 145 146 public: 147 PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &, 148 const MCInstrInfo &MII, const MCTargetOptions &Options) 149 : MCTargetAsmParser(Options, STI, MII) { 150 // Check for 64-bit vs. 32-bit pointer mode. 151 const Triple &TheTriple = STI.getTargetTriple(); 152 IsPPC64 = TheTriple.isPPC64(); 153 IsDarwin = TheTriple.isMacOSX(); 154 // Initialize the set of available features. 155 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 156 } 157 158 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 159 SMLoc NameLoc, OperandVector &Operands) override; 160 161 bool ParseDirective(AsmToken DirectiveID) override; 162 163 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 164 unsigned Kind) override; 165 166 const MCExpr *applyModifierToExpr(const MCExpr *E, 167 MCSymbolRefExpr::VariantKind, 168 MCContext &Ctx) override; 169 }; 170 171 /// PPCOperand - Instances of this class represent a parsed PowerPC machine 172 /// instruction. 173 struct PPCOperand : public MCParsedAsmOperand { 174 enum KindTy { 175 Token, 176 Immediate, 177 ContextImmediate, 178 Expression, 179 TLSRegister 180 } Kind; 181 182 SMLoc StartLoc, EndLoc; 183 bool IsPPC64; 184 185 struct TokOp { 186 const char *Data; 187 unsigned Length; 188 }; 189 190 struct ImmOp { 191 int64_t Val; 192 }; 193 194 struct ExprOp { 195 const MCExpr *Val; 196 int64_t CRVal; // Cached result of EvaluateCRExpr(Val) 197 }; 198 199 struct TLSRegOp { 200 const MCSymbolRefExpr *Sym; 201 }; 202 203 union { 204 struct TokOp Tok; 205 struct ImmOp Imm; 206 struct ExprOp Expr; 207 struct TLSRegOp TLSReg; 208 }; 209 210 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 211 public: 212 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() { 213 Kind = o.Kind; 214 StartLoc = o.StartLoc; 215 EndLoc = o.EndLoc; 216 IsPPC64 = o.IsPPC64; 217 switch (Kind) { 218 case Token: 219 Tok = o.Tok; 220 break; 221 case Immediate: 222 case ContextImmediate: 223 Imm = o.Imm; 224 break; 225 case Expression: 226 Expr = o.Expr; 227 break; 228 case TLSRegister: 229 TLSReg = o.TLSReg; 230 break; 231 } 232 } 233 234 // Disable use of sized deallocation due to overallocation of PPCOperand 235 // objects in CreateTokenWithStringCopy. 236 void operator delete(void *p) { ::operator delete(p); } 237 238 /// getStartLoc - Get the location of the first token of this operand. 239 SMLoc getStartLoc() const override { return StartLoc; } 240 241 /// getEndLoc - Get the location of the last token of this operand. 242 SMLoc getEndLoc() const override { return EndLoc; } 243 244 /// getLocRange - Get the range between the first and last token of this 245 /// operand. 246 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 247 248 /// isPPC64 - True if this operand is for an instruction in 64-bit mode. 249 bool isPPC64() const { return IsPPC64; } 250 251 int64_t getImm() const { 252 assert(Kind == Immediate && "Invalid access!"); 253 return Imm.Val; 254 } 255 int64_t getImmS16Context() const { 256 assert((Kind == Immediate || Kind == ContextImmediate) && 257 "Invalid access!"); 258 if (Kind == Immediate) 259 return Imm.Val; 260 return static_cast<int16_t>(Imm.Val); 261 } 262 int64_t getImmU16Context() const { 263 assert((Kind == Immediate || Kind == ContextImmediate) && 264 "Invalid access!"); 265 return Imm.Val; 266 } 267 268 const MCExpr *getExpr() const { 269 assert(Kind == Expression && "Invalid access!"); 270 return Expr.Val; 271 } 272 273 int64_t getExprCRVal() const { 274 assert(Kind == Expression && "Invalid access!"); 275 return Expr.CRVal; 276 } 277 278 const MCExpr *getTLSReg() const { 279 assert(Kind == TLSRegister && "Invalid access!"); 280 return TLSReg.Sym; 281 } 282 283 unsigned getReg() const override { 284 assert(isRegNumber() && "Invalid access!"); 285 return (unsigned) Imm.Val; 286 } 287 288 unsigned getVSReg() const { 289 assert(isVSRegNumber() && "Invalid access!"); 290 return (unsigned) Imm.Val; 291 } 292 293 unsigned getCCReg() const { 294 assert(isCCRegNumber() && "Invalid access!"); 295 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 296 } 297 298 unsigned getCRBit() const { 299 assert(isCRBitNumber() && "Invalid access!"); 300 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 301 } 302 303 unsigned getCRBitMask() const { 304 assert(isCRBitMask() && "Invalid access!"); 305 return 7 - countTrailingZeros<uint64_t>(Imm.Val); 306 } 307 308 bool isToken() const override { return Kind == Token; } 309 bool isImm() const override { 310 return Kind == Immediate || Kind == Expression; 311 } 312 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } 313 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } 314 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } 315 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } 316 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } 317 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } 318 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } 319 bool isU6ImmX2() const { return Kind == Immediate && 320 isUInt<6>(getImm()) && 321 (getImm() & 1) == 0; } 322 bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); } 323 bool isU7ImmX4() const { return Kind == Immediate && 324 isUInt<7>(getImm()) && 325 (getImm() & 3) == 0; } 326 bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); } 327 bool isU8ImmX8() const { return Kind == Immediate && 328 isUInt<8>(getImm()) && 329 (getImm() & 7) == 0; } 330 331 bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); } 332 bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); } 333 bool isU16Imm() const { 334 switch (Kind) { 335 case Expression: 336 return true; 337 case Immediate: 338 case ContextImmediate: 339 return isUInt<16>(getImmU16Context()); 340 default: 341 return false; 342 } 343 } 344 bool isS16Imm() const { 345 switch (Kind) { 346 case Expression: 347 return true; 348 case Immediate: 349 case ContextImmediate: 350 return isInt<16>(getImmS16Context()); 351 default: 352 return false; 353 } 354 } 355 bool isS16ImmX4() const { return Kind == Expression || 356 (Kind == Immediate && isInt<16>(getImm()) && 357 (getImm() & 3) == 0); } 358 bool isS16ImmX16() const { return Kind == Expression || 359 (Kind == Immediate && isInt<16>(getImm()) && 360 (getImm() & 15) == 0); } 361 bool isS34ImmX16() const { 362 return Kind == Expression || 363 (Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0); 364 } 365 bool isS34Imm() const { 366 // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit 367 // ContextImmediate is needed. 368 return Kind == Expression || (Kind == Immediate && isInt<34>(getImm())); 369 } 370 371 bool isS17Imm() const { 372 switch (Kind) { 373 case Expression: 374 return true; 375 case Immediate: 376 case ContextImmediate: 377 return isInt<17>(getImmS16Context()); 378 default: 379 return false; 380 } 381 } 382 bool isTLSReg() const { return Kind == TLSRegister; } 383 bool isDirectBr() const { 384 if (Kind == Expression) 385 return true; 386 if (Kind != Immediate) 387 return false; 388 // Operand must be 64-bit aligned, signed 27-bit immediate. 389 if ((getImm() & 3) != 0) 390 return false; 391 if (isInt<26>(getImm())) 392 return true; 393 if (!IsPPC64) { 394 // In 32-bit mode, large 32-bit quantities wrap around. 395 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm()))) 396 return true; 397 } 398 return false; 399 } 400 bool isCondBr() const { return Kind == Expression || 401 (Kind == Immediate && isInt<16>(getImm()) && 402 (getImm() & 3) == 0); } 403 bool isImmZero() const { return Kind == Immediate && getImm() == 0; } 404 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } 405 bool isVSRegNumber() const { 406 return Kind == Immediate && isUInt<6>(getImm()); 407 } 408 bool isCCRegNumber() const { return (Kind == Expression 409 && isUInt<3>(getExprCRVal())) || 410 (Kind == Immediate 411 && isUInt<3>(getImm())); } 412 bool isCRBitNumber() const { return (Kind == Expression 413 && isUInt<5>(getExprCRVal())) || 414 (Kind == Immediate 415 && isUInt<5>(getImm())); } 416 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) && 417 isPowerOf2_32(getImm()); } 418 bool isATBitsAsHint() const { return false; } 419 bool isMem() const override { return false; } 420 bool isReg() const override { return false; } 421 422 void addRegOperands(MCInst &Inst, unsigned N) const { 423 llvm_unreachable("addRegOperands"); 424 } 425 426 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { 427 assert(N == 1 && "Invalid number of operands!"); 428 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 429 } 430 431 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { 432 assert(N == 1 && "Invalid number of operands!"); 433 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); 434 } 435 436 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { 437 assert(N == 1 && "Invalid number of operands!"); 438 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); 439 } 440 441 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { 442 assert(N == 1 && "Invalid number of operands!"); 443 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); 444 } 445 446 void addRegGxRCOperands(MCInst &Inst, unsigned N) const { 447 if (isPPC64()) 448 addRegG8RCOperands(Inst, N); 449 else 450 addRegGPRCOperands(Inst, N); 451 } 452 453 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const { 454 if (isPPC64()) 455 addRegG8RCNoX0Operands(Inst, N); 456 else 457 addRegGPRCNoR0Operands(Inst, N); 458 } 459 460 void addRegF4RCOperands(MCInst &Inst, unsigned N) const { 461 assert(N == 1 && "Invalid number of operands!"); 462 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 463 } 464 465 void addRegF8RCOperands(MCInst &Inst, unsigned N) const { 466 assert(N == 1 && "Invalid number of operands!"); 467 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 468 } 469 470 void addRegVFRCOperands(MCInst &Inst, unsigned N) const { 471 assert(N == 1 && "Invalid number of operands!"); 472 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); 473 } 474 475 void addRegVRRCOperands(MCInst &Inst, unsigned N) const { 476 assert(N == 1 && "Invalid number of operands!"); 477 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); 478 } 479 480 void addRegVSRCOperands(MCInst &Inst, unsigned N) const { 481 assert(N == 1 && "Invalid number of operands!"); 482 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); 483 } 484 485 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const { 486 assert(N == 1 && "Invalid number of operands!"); 487 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); 488 } 489 490 void addRegVSSRCOperands(MCInst &Inst, unsigned N) const { 491 assert(N == 1 && "Invalid number of operands!"); 492 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); 493 } 494 495 void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const { 496 assert(N == 1 && "Invalid number of operands!"); 497 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 498 } 499 500 void addRegSPERCOperands(MCInst &Inst, unsigned N) const { 501 assert(N == 1 && "Invalid number of operands!"); 502 Inst.addOperand(MCOperand::createReg(SPERegs[getReg()])); 503 } 504 505 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const { 506 assert(N == 1 && "Invalid number of operands!"); 507 Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()])); 508 } 509 510 void addRegCRRCOperands(MCInst &Inst, unsigned N) const { 511 assert(N == 1 && "Invalid number of operands!"); 512 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()])); 513 } 514 515 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const { 516 assert(N == 1 && "Invalid number of operands!"); 517 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()])); 518 } 519 520 void addImmOperands(MCInst &Inst, unsigned N) const { 521 assert(N == 1 && "Invalid number of operands!"); 522 if (Kind == Immediate) 523 Inst.addOperand(MCOperand::createImm(getImm())); 524 else 525 Inst.addOperand(MCOperand::createExpr(getExpr())); 526 } 527 528 void addS16ImmOperands(MCInst &Inst, unsigned N) const { 529 assert(N == 1 && "Invalid number of operands!"); 530 switch (Kind) { 531 case Immediate: 532 Inst.addOperand(MCOperand::createImm(getImm())); 533 break; 534 case ContextImmediate: 535 Inst.addOperand(MCOperand::createImm(getImmS16Context())); 536 break; 537 default: 538 Inst.addOperand(MCOperand::createExpr(getExpr())); 539 break; 540 } 541 } 542 543 void addU16ImmOperands(MCInst &Inst, unsigned N) const { 544 assert(N == 1 && "Invalid number of operands!"); 545 switch (Kind) { 546 case Immediate: 547 Inst.addOperand(MCOperand::createImm(getImm())); 548 break; 549 case ContextImmediate: 550 Inst.addOperand(MCOperand::createImm(getImmU16Context())); 551 break; 552 default: 553 Inst.addOperand(MCOperand::createExpr(getExpr())); 554 break; 555 } 556 } 557 558 void addBranchTargetOperands(MCInst &Inst, unsigned N) const { 559 assert(N == 1 && "Invalid number of operands!"); 560 if (Kind == Immediate) 561 Inst.addOperand(MCOperand::createImm(getImm() / 4)); 562 else 563 Inst.addOperand(MCOperand::createExpr(getExpr())); 564 } 565 566 void addTLSRegOperands(MCInst &Inst, unsigned N) const { 567 assert(N == 1 && "Invalid number of operands!"); 568 Inst.addOperand(MCOperand::createExpr(getTLSReg())); 569 } 570 571 StringRef getToken() const { 572 assert(Kind == Token && "Invalid access!"); 573 return StringRef(Tok.Data, Tok.Length); 574 } 575 576 void print(raw_ostream &OS) const override; 577 578 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S, 579 bool IsPPC64) { 580 auto Op = std::make_unique<PPCOperand>(Token); 581 Op->Tok.Data = Str.data(); 582 Op->Tok.Length = Str.size(); 583 Op->StartLoc = S; 584 Op->EndLoc = S; 585 Op->IsPPC64 = IsPPC64; 586 return Op; 587 } 588 589 static std::unique_ptr<PPCOperand> 590 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) { 591 // Allocate extra memory for the string and copy it. 592 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default 593 // deleter which will destroy them by simply using "delete", not correctly 594 // calling operator delete on this extra memory after calling the dtor 595 // explicitly. 596 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size()); 597 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token)); 598 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1); 599 Op->Tok.Length = Str.size(); 600 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size()); 601 Op->StartLoc = S; 602 Op->EndLoc = S; 603 Op->IsPPC64 = IsPPC64; 604 return Op; 605 } 606 607 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E, 608 bool IsPPC64) { 609 auto Op = std::make_unique<PPCOperand>(Immediate); 610 Op->Imm.Val = Val; 611 Op->StartLoc = S; 612 Op->EndLoc = E; 613 Op->IsPPC64 = IsPPC64; 614 return Op; 615 } 616 617 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S, 618 SMLoc E, bool IsPPC64) { 619 auto Op = std::make_unique<PPCOperand>(Expression); 620 Op->Expr.Val = Val; 621 Op->Expr.CRVal = EvaluateCRExpr(Val); 622 Op->StartLoc = S; 623 Op->EndLoc = E; 624 Op->IsPPC64 = IsPPC64; 625 return Op; 626 } 627 628 static std::unique_ptr<PPCOperand> 629 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) { 630 auto Op = std::make_unique<PPCOperand>(TLSRegister); 631 Op->TLSReg.Sym = Sym; 632 Op->StartLoc = S; 633 Op->EndLoc = E; 634 Op->IsPPC64 = IsPPC64; 635 return Op; 636 } 637 638 static std::unique_ptr<PPCOperand> 639 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) { 640 auto Op = std::make_unique<PPCOperand>(ContextImmediate); 641 Op->Imm.Val = Val; 642 Op->StartLoc = S; 643 Op->EndLoc = E; 644 Op->IsPPC64 = IsPPC64; 645 return Op; 646 } 647 648 static std::unique_ptr<PPCOperand> 649 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) { 650 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val)) 651 return CreateImm(CE->getValue(), S, E, IsPPC64); 652 653 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val)) 654 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS || 655 SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL) 656 return CreateTLSReg(SRE, S, E, IsPPC64); 657 658 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) { 659 int64_t Res; 660 if (TE->evaluateAsConstant(Res)) 661 return CreateContextImm(Res, S, E, IsPPC64); 662 } 663 664 return CreateExpr(Val, S, E, IsPPC64); 665 } 666 }; 667 668 } // end anonymous namespace. 669 670 void PPCOperand::print(raw_ostream &OS) const { 671 switch (Kind) { 672 case Token: 673 OS << "'" << getToken() << "'"; 674 break; 675 case Immediate: 676 case ContextImmediate: 677 OS << getImm(); 678 break; 679 case Expression: 680 OS << *getExpr(); 681 break; 682 case TLSRegister: 683 OS << *getTLSReg(); 684 break; 685 } 686 } 687 688 static void 689 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) { 690 if (Op.isImm()) { 691 Inst.addOperand(MCOperand::createImm(-Op.getImm())); 692 return; 693 } 694 const MCExpr *Expr = Op.getExpr(); 695 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) { 696 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) { 697 Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr())); 698 return; 699 } 700 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) { 701 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) { 702 const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(), 703 BinExpr->getLHS(), Ctx); 704 Inst.addOperand(MCOperand::createExpr(NE)); 705 return; 706 } 707 } 708 Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx))); 709 } 710 711 void PPCAsmParser::ProcessInstruction(MCInst &Inst, 712 const OperandVector &Operands) { 713 int Opcode = Inst.getOpcode(); 714 switch (Opcode) { 715 case PPC::DCBTx: 716 case PPC::DCBTT: 717 case PPC::DCBTSTx: 718 case PPC::DCBTSTT: { 719 MCInst TmpInst; 720 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? 721 PPC::DCBT : PPC::DCBTST); 722 TmpInst.addOperand(MCOperand::createImm( 723 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16)); 724 TmpInst.addOperand(Inst.getOperand(0)); 725 TmpInst.addOperand(Inst.getOperand(1)); 726 Inst = TmpInst; 727 break; 728 } 729 case PPC::DCBTCT: 730 case PPC::DCBTDS: { 731 MCInst TmpInst; 732 TmpInst.setOpcode(PPC::DCBT); 733 TmpInst.addOperand(Inst.getOperand(2)); 734 TmpInst.addOperand(Inst.getOperand(0)); 735 TmpInst.addOperand(Inst.getOperand(1)); 736 Inst = TmpInst; 737 break; 738 } 739 case PPC::DCBTSTCT: 740 case PPC::DCBTSTDS: { 741 MCInst TmpInst; 742 TmpInst.setOpcode(PPC::DCBTST); 743 TmpInst.addOperand(Inst.getOperand(2)); 744 TmpInst.addOperand(Inst.getOperand(0)); 745 TmpInst.addOperand(Inst.getOperand(1)); 746 Inst = TmpInst; 747 break; 748 } 749 case PPC::DCBFx: 750 case PPC::DCBFL: 751 case PPC::DCBFLP: { 752 int L = 0; 753 if (Opcode == PPC::DCBFL) 754 L = 1; 755 else if (Opcode == PPC::DCBFLP) 756 L = 3; 757 758 MCInst TmpInst; 759 TmpInst.setOpcode(PPC::DCBF); 760 TmpInst.addOperand(MCOperand::createImm(L)); 761 TmpInst.addOperand(Inst.getOperand(0)); 762 TmpInst.addOperand(Inst.getOperand(1)); 763 Inst = TmpInst; 764 break; 765 } 766 case PPC::LAx: { 767 MCInst TmpInst; 768 TmpInst.setOpcode(PPC::LA); 769 TmpInst.addOperand(Inst.getOperand(0)); 770 TmpInst.addOperand(Inst.getOperand(2)); 771 TmpInst.addOperand(Inst.getOperand(1)); 772 Inst = TmpInst; 773 break; 774 } 775 case PPC::SUBI: { 776 MCInst TmpInst; 777 TmpInst.setOpcode(PPC::ADDI); 778 TmpInst.addOperand(Inst.getOperand(0)); 779 TmpInst.addOperand(Inst.getOperand(1)); 780 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 781 Inst = TmpInst; 782 break; 783 } 784 case PPC::SUBIS: { 785 MCInst TmpInst; 786 TmpInst.setOpcode(PPC::ADDIS); 787 TmpInst.addOperand(Inst.getOperand(0)); 788 TmpInst.addOperand(Inst.getOperand(1)); 789 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 790 Inst = TmpInst; 791 break; 792 } 793 case PPC::SUBIC: { 794 MCInst TmpInst; 795 TmpInst.setOpcode(PPC::ADDIC); 796 TmpInst.addOperand(Inst.getOperand(0)); 797 TmpInst.addOperand(Inst.getOperand(1)); 798 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 799 Inst = TmpInst; 800 break; 801 } 802 case PPC::SUBIC_rec: { 803 MCInst TmpInst; 804 TmpInst.setOpcode(PPC::ADDIC_rec); 805 TmpInst.addOperand(Inst.getOperand(0)); 806 TmpInst.addOperand(Inst.getOperand(1)); 807 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 808 Inst = TmpInst; 809 break; 810 } 811 case PPC::EXTLWI: 812 case PPC::EXTLWI_rec: { 813 MCInst TmpInst; 814 int64_t N = Inst.getOperand(2).getImm(); 815 int64_t B = Inst.getOperand(3).getImm(); 816 TmpInst.setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec); 817 TmpInst.addOperand(Inst.getOperand(0)); 818 TmpInst.addOperand(Inst.getOperand(1)); 819 TmpInst.addOperand(MCOperand::createImm(B)); 820 TmpInst.addOperand(MCOperand::createImm(0)); 821 TmpInst.addOperand(MCOperand::createImm(N - 1)); 822 Inst = TmpInst; 823 break; 824 } 825 case PPC::EXTRWI: 826 case PPC::EXTRWI_rec: { 827 MCInst TmpInst; 828 int64_t N = Inst.getOperand(2).getImm(); 829 int64_t B = Inst.getOperand(3).getImm(); 830 TmpInst.setOpcode(Opcode == PPC::EXTRWI ? PPC::RLWINM : PPC::RLWINM_rec); 831 TmpInst.addOperand(Inst.getOperand(0)); 832 TmpInst.addOperand(Inst.getOperand(1)); 833 TmpInst.addOperand(MCOperand::createImm(B + N)); 834 TmpInst.addOperand(MCOperand::createImm(32 - N)); 835 TmpInst.addOperand(MCOperand::createImm(31)); 836 Inst = TmpInst; 837 break; 838 } 839 case PPC::INSLWI: 840 case PPC::INSLWI_rec: { 841 MCInst TmpInst; 842 int64_t N = Inst.getOperand(2).getImm(); 843 int64_t B = Inst.getOperand(3).getImm(); 844 TmpInst.setOpcode(Opcode == PPC::INSLWI ? PPC::RLWIMI : PPC::RLWIMI_rec); 845 TmpInst.addOperand(Inst.getOperand(0)); 846 TmpInst.addOperand(Inst.getOperand(0)); 847 TmpInst.addOperand(Inst.getOperand(1)); 848 TmpInst.addOperand(MCOperand::createImm(32 - B)); 849 TmpInst.addOperand(MCOperand::createImm(B)); 850 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 851 Inst = TmpInst; 852 break; 853 } 854 case PPC::INSRWI: 855 case PPC::INSRWI_rec: { 856 MCInst TmpInst; 857 int64_t N = Inst.getOperand(2).getImm(); 858 int64_t B = Inst.getOperand(3).getImm(); 859 TmpInst.setOpcode(Opcode == PPC::INSRWI ? PPC::RLWIMI : PPC::RLWIMI_rec); 860 TmpInst.addOperand(Inst.getOperand(0)); 861 TmpInst.addOperand(Inst.getOperand(0)); 862 TmpInst.addOperand(Inst.getOperand(1)); 863 TmpInst.addOperand(MCOperand::createImm(32 - (B + N))); 864 TmpInst.addOperand(MCOperand::createImm(B)); 865 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 866 Inst = TmpInst; 867 break; 868 } 869 case PPC::ROTRWI: 870 case PPC::ROTRWI_rec: { 871 MCInst TmpInst; 872 int64_t N = Inst.getOperand(2).getImm(); 873 TmpInst.setOpcode(Opcode == PPC::ROTRWI ? PPC::RLWINM : PPC::RLWINM_rec); 874 TmpInst.addOperand(Inst.getOperand(0)); 875 TmpInst.addOperand(Inst.getOperand(1)); 876 TmpInst.addOperand(MCOperand::createImm(32 - N)); 877 TmpInst.addOperand(MCOperand::createImm(0)); 878 TmpInst.addOperand(MCOperand::createImm(31)); 879 Inst = TmpInst; 880 break; 881 } 882 case PPC::SLWI: 883 case PPC::SLWI_rec: { 884 MCInst TmpInst; 885 int64_t N = Inst.getOperand(2).getImm(); 886 TmpInst.setOpcode(Opcode == PPC::SLWI ? PPC::RLWINM : PPC::RLWINM_rec); 887 TmpInst.addOperand(Inst.getOperand(0)); 888 TmpInst.addOperand(Inst.getOperand(1)); 889 TmpInst.addOperand(MCOperand::createImm(N)); 890 TmpInst.addOperand(MCOperand::createImm(0)); 891 TmpInst.addOperand(MCOperand::createImm(31 - N)); 892 Inst = TmpInst; 893 break; 894 } 895 case PPC::SRWI: 896 case PPC::SRWI_rec: { 897 MCInst TmpInst; 898 int64_t N = Inst.getOperand(2).getImm(); 899 TmpInst.setOpcode(Opcode == PPC::SRWI ? PPC::RLWINM : PPC::RLWINM_rec); 900 TmpInst.addOperand(Inst.getOperand(0)); 901 TmpInst.addOperand(Inst.getOperand(1)); 902 TmpInst.addOperand(MCOperand::createImm(32 - N)); 903 TmpInst.addOperand(MCOperand::createImm(N)); 904 TmpInst.addOperand(MCOperand::createImm(31)); 905 Inst = TmpInst; 906 break; 907 } 908 case PPC::CLRRWI: 909 case PPC::CLRRWI_rec: { 910 MCInst TmpInst; 911 int64_t N = Inst.getOperand(2).getImm(); 912 TmpInst.setOpcode(Opcode == PPC::CLRRWI ? PPC::RLWINM : PPC::RLWINM_rec); 913 TmpInst.addOperand(Inst.getOperand(0)); 914 TmpInst.addOperand(Inst.getOperand(1)); 915 TmpInst.addOperand(MCOperand::createImm(0)); 916 TmpInst.addOperand(MCOperand::createImm(0)); 917 TmpInst.addOperand(MCOperand::createImm(31 - N)); 918 Inst = TmpInst; 919 break; 920 } 921 case PPC::CLRLSLWI: 922 case PPC::CLRLSLWI_rec: { 923 MCInst TmpInst; 924 int64_t B = Inst.getOperand(2).getImm(); 925 int64_t N = Inst.getOperand(3).getImm(); 926 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI ? PPC::RLWINM : PPC::RLWINM_rec); 927 TmpInst.addOperand(Inst.getOperand(0)); 928 TmpInst.addOperand(Inst.getOperand(1)); 929 TmpInst.addOperand(MCOperand::createImm(N)); 930 TmpInst.addOperand(MCOperand::createImm(B - N)); 931 TmpInst.addOperand(MCOperand::createImm(31 - N)); 932 Inst = TmpInst; 933 break; 934 } 935 case PPC::EXTLDI: 936 case PPC::EXTLDI_rec: { 937 MCInst TmpInst; 938 int64_t N = Inst.getOperand(2).getImm(); 939 int64_t B = Inst.getOperand(3).getImm(); 940 TmpInst.setOpcode(Opcode == PPC::EXTLDI ? PPC::RLDICR : PPC::RLDICR_rec); 941 TmpInst.addOperand(Inst.getOperand(0)); 942 TmpInst.addOperand(Inst.getOperand(1)); 943 TmpInst.addOperand(MCOperand::createImm(B)); 944 TmpInst.addOperand(MCOperand::createImm(N - 1)); 945 Inst = TmpInst; 946 break; 947 } 948 case PPC::EXTRDI: 949 case PPC::EXTRDI_rec: { 950 MCInst TmpInst; 951 int64_t N = Inst.getOperand(2).getImm(); 952 int64_t B = Inst.getOperand(3).getImm(); 953 TmpInst.setOpcode(Opcode == PPC::EXTRDI ? PPC::RLDICL : PPC::RLDICL_rec); 954 TmpInst.addOperand(Inst.getOperand(0)); 955 TmpInst.addOperand(Inst.getOperand(1)); 956 TmpInst.addOperand(MCOperand::createImm(B + N)); 957 TmpInst.addOperand(MCOperand::createImm(64 - N)); 958 Inst = TmpInst; 959 break; 960 } 961 case PPC::INSRDI: 962 case PPC::INSRDI_rec: { 963 MCInst TmpInst; 964 int64_t N = Inst.getOperand(2).getImm(); 965 int64_t B = Inst.getOperand(3).getImm(); 966 TmpInst.setOpcode(Opcode == PPC::INSRDI ? PPC::RLDIMI : PPC::RLDIMI_rec); 967 TmpInst.addOperand(Inst.getOperand(0)); 968 TmpInst.addOperand(Inst.getOperand(0)); 969 TmpInst.addOperand(Inst.getOperand(1)); 970 TmpInst.addOperand(MCOperand::createImm(64 - (B + N))); 971 TmpInst.addOperand(MCOperand::createImm(B)); 972 Inst = TmpInst; 973 break; 974 } 975 case PPC::ROTRDI: 976 case PPC::ROTRDI_rec: { 977 MCInst TmpInst; 978 int64_t N = Inst.getOperand(2).getImm(); 979 TmpInst.setOpcode(Opcode == PPC::ROTRDI ? PPC::RLDICL : PPC::RLDICL_rec); 980 TmpInst.addOperand(Inst.getOperand(0)); 981 TmpInst.addOperand(Inst.getOperand(1)); 982 TmpInst.addOperand(MCOperand::createImm(64 - N)); 983 TmpInst.addOperand(MCOperand::createImm(0)); 984 Inst = TmpInst; 985 break; 986 } 987 case PPC::SLDI: 988 case PPC::SLDI_rec: { 989 MCInst TmpInst; 990 int64_t N = Inst.getOperand(2).getImm(); 991 TmpInst.setOpcode(Opcode == PPC::SLDI ? PPC::RLDICR : PPC::RLDICR_rec); 992 TmpInst.addOperand(Inst.getOperand(0)); 993 TmpInst.addOperand(Inst.getOperand(1)); 994 TmpInst.addOperand(MCOperand::createImm(N)); 995 TmpInst.addOperand(MCOperand::createImm(63 - N)); 996 Inst = TmpInst; 997 break; 998 } 999 case PPC::SUBPCIS: { 1000 MCInst TmpInst; 1001 int64_t N = Inst.getOperand(1).getImm(); 1002 TmpInst.setOpcode(PPC::ADDPCIS); 1003 TmpInst.addOperand(Inst.getOperand(0)); 1004 TmpInst.addOperand(MCOperand::createImm(-N)); 1005 Inst = TmpInst; 1006 break; 1007 } 1008 case PPC::SRDI: 1009 case PPC::SRDI_rec: { 1010 MCInst TmpInst; 1011 int64_t N = Inst.getOperand(2).getImm(); 1012 TmpInst.setOpcode(Opcode == PPC::SRDI ? PPC::RLDICL : PPC::RLDICL_rec); 1013 TmpInst.addOperand(Inst.getOperand(0)); 1014 TmpInst.addOperand(Inst.getOperand(1)); 1015 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1016 TmpInst.addOperand(MCOperand::createImm(N)); 1017 Inst = TmpInst; 1018 break; 1019 } 1020 case PPC::CLRRDI: 1021 case PPC::CLRRDI_rec: { 1022 MCInst TmpInst; 1023 int64_t N = Inst.getOperand(2).getImm(); 1024 TmpInst.setOpcode(Opcode == PPC::CLRRDI ? PPC::RLDICR : PPC::RLDICR_rec); 1025 TmpInst.addOperand(Inst.getOperand(0)); 1026 TmpInst.addOperand(Inst.getOperand(1)); 1027 TmpInst.addOperand(MCOperand::createImm(0)); 1028 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1029 Inst = TmpInst; 1030 break; 1031 } 1032 case PPC::CLRLSLDI: 1033 case PPC::CLRLSLDI_rec: { 1034 MCInst TmpInst; 1035 int64_t B = Inst.getOperand(2).getImm(); 1036 int64_t N = Inst.getOperand(3).getImm(); 1037 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI ? PPC::RLDIC : PPC::RLDIC_rec); 1038 TmpInst.addOperand(Inst.getOperand(0)); 1039 TmpInst.addOperand(Inst.getOperand(1)); 1040 TmpInst.addOperand(MCOperand::createImm(N)); 1041 TmpInst.addOperand(MCOperand::createImm(B - N)); 1042 Inst = TmpInst; 1043 break; 1044 } 1045 case PPC::RLWINMbm: 1046 case PPC::RLWINMbm_rec: { 1047 unsigned MB, ME; 1048 int64_t BM = Inst.getOperand(3).getImm(); 1049 if (!isRunOfOnes(BM, MB, ME)) 1050 break; 1051 1052 MCInst TmpInst; 1053 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINM_rec); 1054 TmpInst.addOperand(Inst.getOperand(0)); 1055 TmpInst.addOperand(Inst.getOperand(1)); 1056 TmpInst.addOperand(Inst.getOperand(2)); 1057 TmpInst.addOperand(MCOperand::createImm(MB)); 1058 TmpInst.addOperand(MCOperand::createImm(ME)); 1059 Inst = TmpInst; 1060 break; 1061 } 1062 case PPC::RLWIMIbm: 1063 case PPC::RLWIMIbm_rec: { 1064 unsigned MB, ME; 1065 int64_t BM = Inst.getOperand(3).getImm(); 1066 if (!isRunOfOnes(BM, MB, ME)) 1067 break; 1068 1069 MCInst TmpInst; 1070 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMI_rec); 1071 TmpInst.addOperand(Inst.getOperand(0)); 1072 TmpInst.addOperand(Inst.getOperand(0)); // The tied operand. 1073 TmpInst.addOperand(Inst.getOperand(1)); 1074 TmpInst.addOperand(Inst.getOperand(2)); 1075 TmpInst.addOperand(MCOperand::createImm(MB)); 1076 TmpInst.addOperand(MCOperand::createImm(ME)); 1077 Inst = TmpInst; 1078 break; 1079 } 1080 case PPC::RLWNMbm: 1081 case PPC::RLWNMbm_rec: { 1082 unsigned MB, ME; 1083 int64_t BM = Inst.getOperand(3).getImm(); 1084 if (!isRunOfOnes(BM, MB, ME)) 1085 break; 1086 1087 MCInst TmpInst; 1088 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNM_rec); 1089 TmpInst.addOperand(Inst.getOperand(0)); 1090 TmpInst.addOperand(Inst.getOperand(1)); 1091 TmpInst.addOperand(Inst.getOperand(2)); 1092 TmpInst.addOperand(MCOperand::createImm(MB)); 1093 TmpInst.addOperand(MCOperand::createImm(ME)); 1094 Inst = TmpInst; 1095 break; 1096 } 1097 case PPC::MFTB: { 1098 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) { 1099 assert(Inst.getNumOperands() == 2 && "Expecting two operands"); 1100 Inst.setOpcode(PPC::MFSPR); 1101 } 1102 break; 1103 } 1104 case PPC::CP_COPYx: 1105 case PPC::CP_COPY_FIRST: { 1106 MCInst TmpInst; 1107 TmpInst.setOpcode(PPC::CP_COPY); 1108 TmpInst.addOperand(Inst.getOperand(0)); 1109 TmpInst.addOperand(Inst.getOperand(1)); 1110 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1)); 1111 1112 Inst = TmpInst; 1113 break; 1114 } 1115 case PPC::CP_PASTEx : 1116 case PPC::CP_PASTE_LAST: { 1117 MCInst TmpInst; 1118 TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ? PPC::CP_PASTE 1119 : PPC::CP_PASTE_rec); 1120 TmpInst.addOperand(Inst.getOperand(0)); 1121 TmpInst.addOperand(Inst.getOperand(1)); 1122 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1)); 1123 1124 Inst = TmpInst; 1125 break; 1126 } 1127 } 1128 } 1129 1130 static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, 1131 unsigned VariantID = 0); 1132 1133 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 1134 OperandVector &Operands, 1135 MCStreamer &Out, uint64_t &ErrorInfo, 1136 bool MatchingInlineAsm) { 1137 MCInst Inst; 1138 1139 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { 1140 case Match_Success: 1141 // Post-process instructions (typically extended mnemonics) 1142 ProcessInstruction(Inst, Operands); 1143 Inst.setLoc(IDLoc); 1144 Out.emitInstruction(Inst, getSTI()); 1145 return false; 1146 case Match_MissingFeature: 1147 return Error(IDLoc, "instruction use requires an option to be enabled"); 1148 case Match_MnemonicFail: { 1149 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); 1150 std::string Suggestion = PPCMnemonicSpellCheck( 1151 ((PPCOperand &)*Operands[0]).getToken(), FBS); 1152 return Error(IDLoc, "invalid instruction" + Suggestion, 1153 ((PPCOperand &)*Operands[0]).getLocRange()); 1154 } 1155 case Match_InvalidOperand: { 1156 SMLoc ErrorLoc = IDLoc; 1157 if (ErrorInfo != ~0ULL) { 1158 if (ErrorInfo >= Operands.size()) 1159 return Error(IDLoc, "too few operands for instruction"); 1160 1161 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc(); 1162 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 1163 } 1164 1165 return Error(ErrorLoc, "invalid operand for instruction"); 1166 } 1167 } 1168 1169 llvm_unreachable("Implement any new match types added!"); 1170 } 1171 1172 bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) { 1173 if (getParser().getTok().is(AsmToken::Identifier)) { 1174 StringRef Name = getParser().getTok().getString(); 1175 if (Name.equals_lower("lr")) { 1176 RegNo = isPPC64()? PPC::LR8 : PPC::LR; 1177 IntVal = 8; 1178 } else if (Name.equals_lower("ctr")) { 1179 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR; 1180 IntVal = 9; 1181 } else if (Name.equals_lower("vrsave")) { 1182 RegNo = PPC::VRSAVE; 1183 IntVal = 256; 1184 } else if (Name.startswith_lower("r") && 1185 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1186 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal]; 1187 } else if (Name.startswith_lower("f") && 1188 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1189 RegNo = FRegs[IntVal]; 1190 } else if (Name.startswith_lower("vs") && 1191 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) { 1192 RegNo = VSRegs[IntVal]; 1193 } else if (Name.startswith_lower("v") && 1194 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1195 RegNo = VRegs[IntVal]; 1196 } else if (Name.startswith_lower("cr") && 1197 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { 1198 RegNo = CRRegs[IntVal]; 1199 } else 1200 return true; 1201 getParser().Lex(); 1202 return false; 1203 } 1204 return true; 1205 } 1206 1207 bool PPCAsmParser:: 1208 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 1209 if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success) 1210 return TokError("invalid register name"); 1211 return false; 1212 } 1213 1214 OperandMatchResultTy PPCAsmParser::tryParseRegister(unsigned &RegNo, 1215 SMLoc &StartLoc, 1216 SMLoc &EndLoc) { 1217 const AsmToken &Tok = getParser().getTok(); 1218 StartLoc = Tok.getLoc(); 1219 EndLoc = Tok.getEndLoc(); 1220 RegNo = 0; 1221 int64_t IntVal; 1222 if (MatchRegisterName(RegNo, IntVal)) 1223 return MatchOperand_NoMatch; 1224 return MatchOperand_Success; 1225 } 1226 1227 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan 1228 /// the expression and check for VK_PPC_LO/HI/HA 1229 /// symbol variants. If all symbols with modifier use the same 1230 /// variant, return the corresponding PPCMCExpr::VariantKind, 1231 /// and a modified expression using the default symbol variant. 1232 /// Otherwise, return NULL. 1233 const MCExpr *PPCAsmParser:: 1234 ExtractModifierFromExpr(const MCExpr *E, 1235 PPCMCExpr::VariantKind &Variant) { 1236 MCContext &Context = getParser().getContext(); 1237 Variant = PPCMCExpr::VK_PPC_None; 1238 1239 switch (E->getKind()) { 1240 case MCExpr::Target: 1241 case MCExpr::Constant: 1242 return nullptr; 1243 1244 case MCExpr::SymbolRef: { 1245 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1246 1247 switch (SRE->getKind()) { 1248 case MCSymbolRefExpr::VK_PPC_LO: 1249 Variant = PPCMCExpr::VK_PPC_LO; 1250 break; 1251 case MCSymbolRefExpr::VK_PPC_HI: 1252 Variant = PPCMCExpr::VK_PPC_HI; 1253 break; 1254 case MCSymbolRefExpr::VK_PPC_HA: 1255 Variant = PPCMCExpr::VK_PPC_HA; 1256 break; 1257 case MCSymbolRefExpr::VK_PPC_HIGH: 1258 Variant = PPCMCExpr::VK_PPC_HIGH; 1259 break; 1260 case MCSymbolRefExpr::VK_PPC_HIGHA: 1261 Variant = PPCMCExpr::VK_PPC_HIGHA; 1262 break; 1263 case MCSymbolRefExpr::VK_PPC_HIGHER: 1264 Variant = PPCMCExpr::VK_PPC_HIGHER; 1265 break; 1266 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1267 Variant = PPCMCExpr::VK_PPC_HIGHERA; 1268 break; 1269 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1270 Variant = PPCMCExpr::VK_PPC_HIGHEST; 1271 break; 1272 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1273 Variant = PPCMCExpr::VK_PPC_HIGHESTA; 1274 break; 1275 default: 1276 return nullptr; 1277 } 1278 1279 return MCSymbolRefExpr::create(&SRE->getSymbol(), Context); 1280 } 1281 1282 case MCExpr::Unary: { 1283 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1284 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant); 1285 if (!Sub) 1286 return nullptr; 1287 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1288 } 1289 1290 case MCExpr::Binary: { 1291 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1292 PPCMCExpr::VariantKind LHSVariant, RHSVariant; 1293 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant); 1294 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant); 1295 1296 if (!LHS && !RHS) 1297 return nullptr; 1298 1299 if (!LHS) LHS = BE->getLHS(); 1300 if (!RHS) RHS = BE->getRHS(); 1301 1302 if (LHSVariant == PPCMCExpr::VK_PPC_None) 1303 Variant = RHSVariant; 1304 else if (RHSVariant == PPCMCExpr::VK_PPC_None) 1305 Variant = LHSVariant; 1306 else if (LHSVariant == RHSVariant) 1307 Variant = LHSVariant; 1308 else 1309 return nullptr; 1310 1311 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1312 } 1313 } 1314 1315 llvm_unreachable("Invalid expression kind!"); 1316 } 1317 1318 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace 1319 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having 1320 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT. 1321 /// FIXME: This is a hack. 1322 const MCExpr *PPCAsmParser:: 1323 FixupVariantKind(const MCExpr *E) { 1324 MCContext &Context = getParser().getContext(); 1325 1326 switch (E->getKind()) { 1327 case MCExpr::Target: 1328 case MCExpr::Constant: 1329 return E; 1330 1331 case MCExpr::SymbolRef: { 1332 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1333 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; 1334 1335 switch (SRE->getKind()) { 1336 case MCSymbolRefExpr::VK_TLSGD: 1337 Variant = MCSymbolRefExpr::VK_PPC_TLSGD; 1338 break; 1339 case MCSymbolRefExpr::VK_TLSLD: 1340 Variant = MCSymbolRefExpr::VK_PPC_TLSLD; 1341 break; 1342 default: 1343 return E; 1344 } 1345 return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context); 1346 } 1347 1348 case MCExpr::Unary: { 1349 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1350 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr()); 1351 if (Sub == UE->getSubExpr()) 1352 return E; 1353 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1354 } 1355 1356 case MCExpr::Binary: { 1357 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1358 const MCExpr *LHS = FixupVariantKind(BE->getLHS()); 1359 const MCExpr *RHS = FixupVariantKind(BE->getRHS()); 1360 if (LHS == BE->getLHS() && RHS == BE->getRHS()) 1361 return E; 1362 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1363 } 1364 } 1365 1366 llvm_unreachable("Invalid expression kind!"); 1367 } 1368 1369 /// ParseExpression. This differs from the default "parseExpression" in that 1370 /// it handles modifiers. 1371 bool PPCAsmParser:: 1372 ParseExpression(const MCExpr *&EVal) { 1373 1374 if (isDarwin()) 1375 return ParseDarwinExpression(EVal); 1376 1377 // (ELF Platforms) 1378 // Handle \code @l/@ha \endcode 1379 if (getParser().parseExpression(EVal)) 1380 return true; 1381 1382 EVal = FixupVariantKind(EVal); 1383 1384 PPCMCExpr::VariantKind Variant; 1385 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant); 1386 if (E) 1387 EVal = PPCMCExpr::create(Variant, E, getParser().getContext()); 1388 1389 return false; 1390 } 1391 1392 /// ParseDarwinExpression. (MachO Platforms) 1393 /// This differs from the default "parseExpression" in that it handles detection 1394 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present, 1395 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO 1396 /// syntax form so it is done here. TODO: Determine if there is merit in 1397 /// arranging for this to be done at a higher level. 1398 bool PPCAsmParser:: 1399 ParseDarwinExpression(const MCExpr *&EVal) { 1400 MCAsmParser &Parser = getParser(); 1401 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None; 1402 switch (getLexer().getKind()) { 1403 default: 1404 break; 1405 case AsmToken::Identifier: 1406 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus 1407 // something starting with any other char should be part of the 1408 // asm syntax. If handwritten asm includes an identifier like lo16, 1409 // then all bets are off - but no-one would do that, right? 1410 StringRef poss = Parser.getTok().getString(); 1411 if (poss.equals_lower("lo16")) { 1412 Variant = PPCMCExpr::VK_PPC_LO; 1413 } else if (poss.equals_lower("hi16")) { 1414 Variant = PPCMCExpr::VK_PPC_HI; 1415 } else if (poss.equals_lower("ha16")) { 1416 Variant = PPCMCExpr::VK_PPC_HA; 1417 } 1418 if (Variant != PPCMCExpr::VK_PPC_None) { 1419 Parser.Lex(); // Eat the xx16 1420 if (getLexer().isNot(AsmToken::LParen)) 1421 return Error(Parser.getTok().getLoc(), "expected '('"); 1422 Parser.Lex(); // Eat the '(' 1423 } 1424 break; 1425 } 1426 1427 if (getParser().parseExpression(EVal)) 1428 return true; 1429 1430 if (Variant != PPCMCExpr::VK_PPC_None) { 1431 if (getLexer().isNot(AsmToken::RParen)) 1432 return Error(Parser.getTok().getLoc(), "expected ')'"); 1433 Parser.Lex(); // Eat the ')' 1434 EVal = PPCMCExpr::create(Variant, EVal, getParser().getContext()); 1435 } 1436 return false; 1437 } 1438 1439 /// ParseOperand 1440 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and 1441 /// rNN for MachO. 1442 bool PPCAsmParser::ParseOperand(OperandVector &Operands) { 1443 MCAsmParser &Parser = getParser(); 1444 SMLoc S = Parser.getTok().getLoc(); 1445 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1446 const MCExpr *EVal; 1447 1448 // Attempt to parse the next token as an immediate 1449 switch (getLexer().getKind()) { 1450 // Special handling for register names. These are interpreted 1451 // as immediates corresponding to the register number. 1452 case AsmToken::Percent: 1453 Parser.Lex(); // Eat the '%'. 1454 unsigned RegNo; 1455 int64_t IntVal; 1456 if (MatchRegisterName(RegNo, IntVal)) 1457 return Error(S, "invalid register name"); 1458 1459 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1460 return false; 1461 1462 case AsmToken::Identifier: 1463 case AsmToken::LParen: 1464 case AsmToken::Plus: 1465 case AsmToken::Minus: 1466 case AsmToken::Integer: 1467 case AsmToken::Dot: 1468 case AsmToken::Dollar: 1469 case AsmToken::Exclaim: 1470 case AsmToken::Tilde: 1471 // Note that non-register-name identifiers from the compiler will begin 1472 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include 1473 // identifiers like r31foo - so we fall through in the event that parsing 1474 // a register name fails. 1475 if (isDarwin()) { 1476 unsigned RegNo; 1477 int64_t IntVal; 1478 if (!MatchRegisterName(RegNo, IntVal)) { 1479 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1480 return false; 1481 } 1482 } 1483 // All other expressions 1484 1485 if (!ParseExpression(EVal)) 1486 break; 1487 // Fall-through 1488 LLVM_FALLTHROUGH; 1489 default: 1490 return Error(S, "unknown operand"); 1491 } 1492 1493 // Push the parsed operand into the list of operands 1494 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64())); 1495 1496 // Check whether this is a TLS call expression 1497 bool TLSCall = false; 1498 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal)) 1499 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr"; 1500 1501 if (TLSCall && getLexer().is(AsmToken::LParen)) { 1502 const MCExpr *TLSSym; 1503 1504 Parser.Lex(); // Eat the '('. 1505 S = Parser.getTok().getLoc(); 1506 if (ParseExpression(TLSSym)) 1507 return Error(S, "invalid TLS call expression"); 1508 if (getLexer().isNot(AsmToken::RParen)) 1509 return Error(Parser.getTok().getLoc(), "missing ')'"); 1510 E = Parser.getTok().getLoc(); 1511 Parser.Lex(); // Eat the ')'. 1512 1513 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64())); 1514 } 1515 1516 // Otherwise, check for D-form memory operands 1517 if (!TLSCall && getLexer().is(AsmToken::LParen)) { 1518 Parser.Lex(); // Eat the '('. 1519 S = Parser.getTok().getLoc(); 1520 1521 int64_t IntVal; 1522 switch (getLexer().getKind()) { 1523 case AsmToken::Percent: 1524 Parser.Lex(); // Eat the '%'. 1525 unsigned RegNo; 1526 if (MatchRegisterName(RegNo, IntVal)) 1527 return Error(S, "invalid register name"); 1528 break; 1529 1530 case AsmToken::Integer: 1531 if (isDarwin()) 1532 return Error(S, "unexpected integer value"); 1533 else if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 || 1534 IntVal > 31) 1535 return Error(S, "invalid register number"); 1536 break; 1537 case AsmToken::Identifier: 1538 if (isDarwin()) { 1539 unsigned RegNo; 1540 if (!MatchRegisterName(RegNo, IntVal)) { 1541 break; 1542 } 1543 } 1544 LLVM_FALLTHROUGH; 1545 1546 default: 1547 return Error(S, "invalid memory operand"); 1548 } 1549 1550 E = Parser.getTok().getLoc(); 1551 if (parseToken(AsmToken::RParen, "missing ')'")) 1552 return true; 1553 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1554 } 1555 1556 return false; 1557 } 1558 1559 /// Parse an instruction mnemonic followed by its operands. 1560 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 1561 SMLoc NameLoc, OperandVector &Operands) { 1562 // The first operand is the token for the instruction name. 1563 // If the next character is a '+' or '-', we need to add it to the 1564 // instruction name, to match what TableGen is doing. 1565 std::string NewOpcode; 1566 if (parseOptionalToken(AsmToken::Plus)) { 1567 NewOpcode = std::string(Name); 1568 NewOpcode += '+'; 1569 Name = NewOpcode; 1570 } 1571 if (parseOptionalToken(AsmToken::Minus)) { 1572 NewOpcode = std::string(Name); 1573 NewOpcode += '-'; 1574 Name = NewOpcode; 1575 } 1576 // If the instruction ends in a '.', we need to create a separate 1577 // token for it, to match what TableGen is doing. 1578 size_t Dot = Name.find('.'); 1579 StringRef Mnemonic = Name.slice(0, Dot); 1580 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1581 Operands.push_back( 1582 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64())); 1583 else 1584 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64())); 1585 if (Dot != StringRef::npos) { 1586 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot); 1587 StringRef DotStr = Name.slice(Dot, StringRef::npos); 1588 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1589 Operands.push_back( 1590 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64())); 1591 else 1592 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64())); 1593 } 1594 1595 // If there are no more operands then finish 1596 if (parseOptionalToken(AsmToken::EndOfStatement)) 1597 return false; 1598 1599 // Parse the first operand 1600 if (ParseOperand(Operands)) 1601 return true; 1602 1603 while (!parseOptionalToken(AsmToken::EndOfStatement)) { 1604 if (parseToken(AsmToken::Comma) || ParseOperand(Operands)) 1605 return true; 1606 } 1607 1608 // We'll now deal with an unfortunate special case: the syntax for the dcbt 1609 // and dcbtst instructions differs for server vs. embedded cores. 1610 // The syntax for dcbt is: 1611 // dcbt ra, rb, th [server] 1612 // dcbt th, ra, rb [embedded] 1613 // where th can be omitted when it is 0. dcbtst is the same. We take the 1614 // server form to be the default, so swap the operands if we're parsing for 1615 // an embedded core (they'll be swapped again upon printing). 1616 if (getSTI().getFeatureBits()[PPC::FeatureBookE] && 1617 Operands.size() == 4 && 1618 (Name == "dcbt" || Name == "dcbtst")) { 1619 std::swap(Operands[1], Operands[3]); 1620 std::swap(Operands[2], Operands[1]); 1621 } 1622 1623 return false; 1624 } 1625 1626 /// ParseDirective parses the PPC specific directives 1627 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) { 1628 StringRef IDVal = DirectiveID.getIdentifier(); 1629 if (isDarwin()) { 1630 if (IDVal == ".machine") 1631 ParseDarwinDirectiveMachine(DirectiveID.getLoc()); 1632 else 1633 return true; 1634 } else if (IDVal == ".word") 1635 ParseDirectiveWord(2, DirectiveID); 1636 else if (IDVal == ".llong") 1637 ParseDirectiveWord(8, DirectiveID); 1638 else if (IDVal == ".tc") 1639 ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID); 1640 else if (IDVal == ".machine") 1641 ParseDirectiveMachine(DirectiveID.getLoc()); 1642 else if (IDVal == ".abiversion") 1643 ParseDirectiveAbiVersion(DirectiveID.getLoc()); 1644 else if (IDVal == ".localentry") 1645 ParseDirectiveLocalEntry(DirectiveID.getLoc()); 1646 else 1647 return true; 1648 return false; 1649 } 1650 1651 /// ParseDirectiveWord 1652 /// ::= .word [ expression (, expression)* ] 1653 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) { 1654 auto parseOp = [&]() -> bool { 1655 const MCExpr *Value; 1656 SMLoc ExprLoc = getParser().getTok().getLoc(); 1657 if (getParser().parseExpression(Value)) 1658 return true; 1659 if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) { 1660 assert(Size <= 8 && "Invalid size"); 1661 uint64_t IntValue = MCE->getValue(); 1662 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue)) 1663 return Error(ExprLoc, "literal value out of range for '" + 1664 ID.getIdentifier() + "' directive"); 1665 getStreamer().emitIntValue(IntValue, Size); 1666 } else 1667 getStreamer().emitValue(Value, Size, ExprLoc); 1668 return false; 1669 }; 1670 1671 if (parseMany(parseOp)) 1672 return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive"); 1673 return false; 1674 } 1675 1676 /// ParseDirectiveTC 1677 /// ::= .tc [ symbol (, expression)* ] 1678 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) { 1679 MCAsmParser &Parser = getParser(); 1680 // Skip TC symbol, which is only used with XCOFF. 1681 while (getLexer().isNot(AsmToken::EndOfStatement) 1682 && getLexer().isNot(AsmToken::Comma)) 1683 Parser.Lex(); 1684 if (parseToken(AsmToken::Comma)) 1685 return addErrorSuffix(" in '.tc' directive"); 1686 1687 // Align to word size. 1688 getParser().getStreamer().emitValueToAlignment(Size); 1689 1690 // Emit expressions. 1691 return ParseDirectiveWord(Size, ID); 1692 } 1693 1694 /// ParseDirectiveMachine (ELF platforms) 1695 /// ::= .machine [ cpu | "push" | "pop" ] 1696 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) { 1697 MCAsmParser &Parser = getParser(); 1698 if (Parser.getTok().isNot(AsmToken::Identifier) && 1699 Parser.getTok().isNot(AsmToken::String)) 1700 return Error(L, "unexpected token in '.machine' directive"); 1701 1702 StringRef CPU = Parser.getTok().getIdentifier(); 1703 1704 // FIXME: Right now, the parser always allows any available 1705 // instruction, so the .machine directive is not useful. 1706 // Implement ".machine any" (by doing nothing) for the benefit 1707 // of existing assembler code. Likewise, we can then implement 1708 // ".machine push" and ".machine pop" as no-op. 1709 if (CPU != "any" && CPU != "push" && CPU != "pop") 1710 return TokError("unrecognized machine type"); 1711 1712 Parser.Lex(); 1713 1714 if (parseToken(AsmToken::EndOfStatement)) 1715 return addErrorSuffix(" in '.machine' directive"); 1716 1717 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>( 1718 getParser().getStreamer().getTargetStreamer()); 1719 if (TStreamer != nullptr) 1720 TStreamer->emitMachine(CPU); 1721 1722 return false; 1723 } 1724 1725 /// ParseDarwinDirectiveMachine (Mach-o platforms) 1726 /// ::= .machine cpu-identifier 1727 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) { 1728 MCAsmParser &Parser = getParser(); 1729 if (Parser.getTok().isNot(AsmToken::Identifier) && 1730 Parser.getTok().isNot(AsmToken::String)) 1731 return Error(L, "unexpected token in directive"); 1732 1733 StringRef CPU = Parser.getTok().getIdentifier(); 1734 Parser.Lex(); 1735 1736 // FIXME: this is only the 'default' set of cpu variants. 1737 // However we don't act on this information at present, this is simply 1738 // allowing parsing to proceed with minimal sanity checking. 1739 if (check(CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64", L, 1740 "unrecognized cpu type") || 1741 check(isPPC64() && (CPU == "ppc7400" || CPU == "ppc"), L, 1742 "wrong cpu type specified for 64bit") || 1743 check(!isPPC64() && CPU == "ppc64", L, 1744 "wrong cpu type specified for 32bit") || 1745 parseToken(AsmToken::EndOfStatement)) 1746 return addErrorSuffix(" in '.machine' directive"); 1747 return false; 1748 } 1749 1750 /// ParseDirectiveAbiVersion 1751 /// ::= .abiversion constant-expression 1752 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) { 1753 int64_t AbiVersion; 1754 if (check(getParser().parseAbsoluteExpression(AbiVersion), L, 1755 "expected constant expression") || 1756 parseToken(AsmToken::EndOfStatement)) 1757 return addErrorSuffix(" in '.abiversion' directive"); 1758 1759 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>( 1760 getParser().getStreamer().getTargetStreamer()); 1761 if (TStreamer != nullptr) 1762 TStreamer->emitAbiVersion(AbiVersion); 1763 1764 return false; 1765 } 1766 1767 /// ParseDirectiveLocalEntry 1768 /// ::= .localentry symbol, expression 1769 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) { 1770 StringRef Name; 1771 if (getParser().parseIdentifier(Name)) 1772 return Error(L, "expected identifier in '.localentry' directive"); 1773 1774 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name)); 1775 const MCExpr *Expr; 1776 1777 if (parseToken(AsmToken::Comma) || 1778 check(getParser().parseExpression(Expr), L, "expected expression") || 1779 parseToken(AsmToken::EndOfStatement)) 1780 return addErrorSuffix(" in '.localentry' directive"); 1781 1782 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>( 1783 getParser().getStreamer().getTargetStreamer()); 1784 if (TStreamer != nullptr) 1785 TStreamer->emitLocalEntry(Sym, Expr); 1786 1787 return false; 1788 } 1789 1790 1791 1792 /// Force static initialization. 1793 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCAsmParser() { 1794 RegisterMCAsmParser<PPCAsmParser> A(getThePPC32Target()); 1795 RegisterMCAsmParser<PPCAsmParser> B(getThePPC64Target()); 1796 RegisterMCAsmParser<PPCAsmParser> C(getThePPC64LETarget()); 1797 } 1798 1799 #define GET_REGISTER_MATCHER 1800 #define GET_MATCHER_IMPLEMENTATION 1801 #define GET_MNEMONIC_SPELL_CHECKER 1802 #include "PPCGenAsmMatcher.inc" 1803 1804 // Define this matcher function after the auto-generated include so we 1805 // have the match class enum definitions. 1806 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, 1807 unsigned Kind) { 1808 // If the kind is a token for a literal immediate, check if our asm 1809 // operand matches. This is for InstAliases which have a fixed-value 1810 // immediate in the syntax. 1811 int64_t ImmVal; 1812 switch (Kind) { 1813 case MCK_0: ImmVal = 0; break; 1814 case MCK_1: ImmVal = 1; break; 1815 case MCK_2: ImmVal = 2; break; 1816 case MCK_3: ImmVal = 3; break; 1817 case MCK_4: ImmVal = 4; break; 1818 case MCK_5: ImmVal = 5; break; 1819 case MCK_6: ImmVal = 6; break; 1820 case MCK_7: ImmVal = 7; break; 1821 default: return Match_InvalidOperand; 1822 } 1823 1824 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp); 1825 if (Op.isImm() && Op.getImm() == ImmVal) 1826 return Match_Success; 1827 1828 return Match_InvalidOperand; 1829 } 1830 1831 const MCExpr * 1832 PPCAsmParser::applyModifierToExpr(const MCExpr *E, 1833 MCSymbolRefExpr::VariantKind Variant, 1834 MCContext &Ctx) { 1835 switch (Variant) { 1836 case MCSymbolRefExpr::VK_PPC_LO: 1837 return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, Ctx); 1838 case MCSymbolRefExpr::VK_PPC_HI: 1839 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, Ctx); 1840 case MCSymbolRefExpr::VK_PPC_HA: 1841 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, Ctx); 1842 case MCSymbolRefExpr::VK_PPC_HIGH: 1843 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGH, E, Ctx); 1844 case MCSymbolRefExpr::VK_PPC_HIGHA: 1845 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHA, E, Ctx); 1846 case MCSymbolRefExpr::VK_PPC_HIGHER: 1847 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, Ctx); 1848 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1849 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, Ctx); 1850 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1851 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, Ctx); 1852 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1853 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, Ctx); 1854 default: 1855 return nullptr; 1856 } 1857 } 1858