1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCExpr.h" 10 #include "MCTargetDesc/PPCMCTargetDesc.h" 11 #include "PPCTargetStreamer.h" 12 #include "TargetInfo/PowerPCTargetInfo.h" 13 #include "llvm/ADT/STLExtras.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Twine.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCParser/MCAsmLexer.h" 21 #include "llvm/MC/MCParser/MCAsmParser.h" 22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 23 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 24 #include "llvm/MC/MCStreamer.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/MC/MCSymbolELF.h" 27 #include "llvm/Support/SourceMgr.h" 28 #include "llvm/Support/TargetRegistry.h" 29 #include "llvm/Support/raw_ostream.h" 30 31 using namespace llvm; 32 33 DEFINE_PPC_REGCLASSES; 34 35 // Evaluate an expression containing condition register 36 // or condition register field symbols. Returns positive 37 // value on success, or -1 on error. 38 static int64_t 39 EvaluateCRExpr(const MCExpr *E) { 40 switch (E->getKind()) { 41 case MCExpr::Target: 42 return -1; 43 44 case MCExpr::Constant: { 45 int64_t Res = cast<MCConstantExpr>(E)->getValue(); 46 return Res < 0 ? -1 : Res; 47 } 48 49 case MCExpr::SymbolRef: { 50 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 51 StringRef Name = SRE->getSymbol().getName(); 52 53 if (Name == "lt") return 0; 54 if (Name == "gt") return 1; 55 if (Name == "eq") return 2; 56 if (Name == "so") return 3; 57 if (Name == "un") return 3; 58 59 if (Name == "cr0") return 0; 60 if (Name == "cr1") return 1; 61 if (Name == "cr2") return 2; 62 if (Name == "cr3") return 3; 63 if (Name == "cr4") return 4; 64 if (Name == "cr5") return 5; 65 if (Name == "cr6") return 6; 66 if (Name == "cr7") return 7; 67 68 return -1; 69 } 70 71 case MCExpr::Unary: 72 return -1; 73 74 case MCExpr::Binary: { 75 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 76 int64_t LHSVal = EvaluateCRExpr(BE->getLHS()); 77 int64_t RHSVal = EvaluateCRExpr(BE->getRHS()); 78 int64_t Res; 79 80 if (LHSVal < 0 || RHSVal < 0) 81 return -1; 82 83 switch (BE->getOpcode()) { 84 default: return -1; 85 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break; 86 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break; 87 } 88 89 return Res < 0 ? -1 : Res; 90 } 91 } 92 93 llvm_unreachable("Invalid expression kind!"); 94 } 95 96 namespace { 97 98 struct PPCOperand; 99 100 class PPCAsmParser : public MCTargetAsmParser { 101 bool IsPPC64; 102 103 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); } 104 105 bool isPPC64() const { return IsPPC64; } 106 107 bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal); 108 109 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 110 OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, 111 SMLoc &EndLoc) override; 112 113 const MCExpr *ExtractModifierFromExpr(const MCExpr *E, 114 PPCMCExpr::VariantKind &Variant); 115 const MCExpr *FixupVariantKind(const MCExpr *E); 116 bool ParseExpression(const MCExpr *&EVal); 117 118 bool ParseOperand(OperandVector &Operands); 119 120 bool ParseDirectiveWord(unsigned Size, AsmToken ID); 121 bool ParseDirectiveTC(unsigned Size, AsmToken ID); 122 bool ParseDirectiveMachine(SMLoc L); 123 bool ParseDirectiveAbiVersion(SMLoc L); 124 bool ParseDirectiveLocalEntry(SMLoc L); 125 126 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 127 OperandVector &Operands, MCStreamer &Out, 128 uint64_t &ErrorInfo, 129 bool MatchingInlineAsm) override; 130 131 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops); 132 133 /// @name Auto-generated Match Functions 134 /// { 135 136 #define GET_ASSEMBLER_HEADER 137 #include "PPCGenAsmMatcher.inc" 138 139 /// } 140 141 142 public: 143 PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &, 144 const MCInstrInfo &MII, const MCTargetOptions &Options) 145 : MCTargetAsmParser(Options, STI, MII) { 146 // Check for 64-bit vs. 32-bit pointer mode. 147 const Triple &TheTriple = STI.getTargetTriple(); 148 IsPPC64 = TheTriple.isPPC64(); 149 // Initialize the set of available features. 150 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 151 } 152 153 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 154 SMLoc NameLoc, OperandVector &Operands) override; 155 156 bool ParseDirective(AsmToken DirectiveID) override; 157 158 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 159 unsigned Kind) override; 160 161 const MCExpr *applyModifierToExpr(const MCExpr *E, 162 MCSymbolRefExpr::VariantKind, 163 MCContext &Ctx) override; 164 }; 165 166 /// PPCOperand - Instances of this class represent a parsed PowerPC machine 167 /// instruction. 168 struct PPCOperand : public MCParsedAsmOperand { 169 enum KindTy { 170 Token, 171 Immediate, 172 ContextImmediate, 173 Expression, 174 TLSRegister 175 } Kind; 176 177 SMLoc StartLoc, EndLoc; 178 bool IsPPC64; 179 180 struct TokOp { 181 const char *Data; 182 unsigned Length; 183 }; 184 185 struct ImmOp { 186 int64_t Val; 187 }; 188 189 struct ExprOp { 190 const MCExpr *Val; 191 int64_t CRVal; // Cached result of EvaluateCRExpr(Val) 192 }; 193 194 struct TLSRegOp { 195 const MCSymbolRefExpr *Sym; 196 }; 197 198 union { 199 struct TokOp Tok; 200 struct ImmOp Imm; 201 struct ExprOp Expr; 202 struct TLSRegOp TLSReg; 203 }; 204 205 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 206 public: 207 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() { 208 Kind = o.Kind; 209 StartLoc = o.StartLoc; 210 EndLoc = o.EndLoc; 211 IsPPC64 = o.IsPPC64; 212 switch (Kind) { 213 case Token: 214 Tok = o.Tok; 215 break; 216 case Immediate: 217 case ContextImmediate: 218 Imm = o.Imm; 219 break; 220 case Expression: 221 Expr = o.Expr; 222 break; 223 case TLSRegister: 224 TLSReg = o.TLSReg; 225 break; 226 } 227 } 228 229 // Disable use of sized deallocation due to overallocation of PPCOperand 230 // objects in CreateTokenWithStringCopy. 231 void operator delete(void *p) { ::operator delete(p); } 232 233 /// getStartLoc - Get the location of the first token of this operand. 234 SMLoc getStartLoc() const override { return StartLoc; } 235 236 /// getEndLoc - Get the location of the last token of this operand. 237 SMLoc getEndLoc() const override { return EndLoc; } 238 239 /// getLocRange - Get the range between the first and last token of this 240 /// operand. 241 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 242 243 /// isPPC64 - True if this operand is for an instruction in 64-bit mode. 244 bool isPPC64() const { return IsPPC64; } 245 246 int64_t getImm() const { 247 assert(Kind == Immediate && "Invalid access!"); 248 return Imm.Val; 249 } 250 int64_t getImmS16Context() const { 251 assert((Kind == Immediate || Kind == ContextImmediate) && 252 "Invalid access!"); 253 if (Kind == Immediate) 254 return Imm.Val; 255 return static_cast<int16_t>(Imm.Val); 256 } 257 int64_t getImmU16Context() const { 258 assert((Kind == Immediate || Kind == ContextImmediate) && 259 "Invalid access!"); 260 return Imm.Val; 261 } 262 263 const MCExpr *getExpr() const { 264 assert(Kind == Expression && "Invalid access!"); 265 return Expr.Val; 266 } 267 268 int64_t getExprCRVal() const { 269 assert(Kind == Expression && "Invalid access!"); 270 return Expr.CRVal; 271 } 272 273 const MCExpr *getTLSReg() const { 274 assert(Kind == TLSRegister && "Invalid access!"); 275 return TLSReg.Sym; 276 } 277 278 unsigned getReg() const override { 279 assert(isRegNumber() && "Invalid access!"); 280 return (unsigned) Imm.Val; 281 } 282 283 unsigned getVSReg() const { 284 assert(isVSRegNumber() && "Invalid access!"); 285 return (unsigned) Imm.Val; 286 } 287 288 unsigned getACCReg() const { 289 assert(isACCRegNumber() && "Invalid access!"); 290 return (unsigned) Imm.Val; 291 } 292 293 unsigned getVSRpEvenReg() const { 294 assert(isVSRpEvenRegNumber() && "Invalid access!"); 295 return (unsigned) Imm.Val >> 1; 296 } 297 298 unsigned getCCReg() const { 299 assert(isCCRegNumber() && "Invalid access!"); 300 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 301 } 302 303 unsigned getCRBit() const { 304 assert(isCRBitNumber() && "Invalid access!"); 305 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 306 } 307 308 unsigned getCRBitMask() const { 309 assert(isCRBitMask() && "Invalid access!"); 310 return 7 - countTrailingZeros<uint64_t>(Imm.Val); 311 } 312 313 bool isToken() const override { return Kind == Token; } 314 bool isImm() const override { 315 return Kind == Immediate || Kind == Expression; 316 } 317 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } 318 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } 319 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } 320 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } 321 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } 322 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } 323 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } 324 bool isU6ImmX2() const { return Kind == Immediate && 325 isUInt<6>(getImm()) && 326 (getImm() & 1) == 0; } 327 bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); } 328 bool isU7ImmX4() const { return Kind == Immediate && 329 isUInt<7>(getImm()) && 330 (getImm() & 3) == 0; } 331 bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); } 332 bool isU8ImmX8() const { return Kind == Immediate && 333 isUInt<8>(getImm()) && 334 (getImm() & 7) == 0; } 335 336 bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); } 337 bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); } 338 bool isU16Imm() const { 339 switch (Kind) { 340 case Expression: 341 return true; 342 case Immediate: 343 case ContextImmediate: 344 return isUInt<16>(getImmU16Context()); 345 default: 346 return false; 347 } 348 } 349 bool isS16Imm() const { 350 switch (Kind) { 351 case Expression: 352 return true; 353 case Immediate: 354 case ContextImmediate: 355 return isInt<16>(getImmS16Context()); 356 default: 357 return false; 358 } 359 } 360 bool isS16ImmX4() const { return Kind == Expression || 361 (Kind == Immediate && isInt<16>(getImm()) && 362 (getImm() & 3) == 0); } 363 bool isS16ImmX16() const { return Kind == Expression || 364 (Kind == Immediate && isInt<16>(getImm()) && 365 (getImm() & 15) == 0); } 366 bool isS34ImmX16() const { 367 return Kind == Expression || 368 (Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0); 369 } 370 bool isS34Imm() const { 371 // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit 372 // ContextImmediate is needed. 373 return Kind == Expression || (Kind == Immediate && isInt<34>(getImm())); 374 } 375 376 bool isS17Imm() const { 377 switch (Kind) { 378 case Expression: 379 return true; 380 case Immediate: 381 case ContextImmediate: 382 return isInt<17>(getImmS16Context()); 383 default: 384 return false; 385 } 386 } 387 bool isTLSReg() const { return Kind == TLSRegister; } 388 bool isDirectBr() const { 389 if (Kind == Expression) 390 return true; 391 if (Kind != Immediate) 392 return false; 393 // Operand must be 64-bit aligned, signed 27-bit immediate. 394 if ((getImm() & 3) != 0) 395 return false; 396 if (isInt<26>(getImm())) 397 return true; 398 if (!IsPPC64) { 399 // In 32-bit mode, large 32-bit quantities wrap around. 400 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm()))) 401 return true; 402 } 403 return false; 404 } 405 bool isCondBr() const { return Kind == Expression || 406 (Kind == Immediate && isInt<16>(getImm()) && 407 (getImm() & 3) == 0); } 408 bool isImmZero() const { return Kind == Immediate && getImm() == 0; } 409 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } 410 bool isACCRegNumber() const { 411 return Kind == Immediate && isUInt<3>(getImm()); 412 } 413 bool isVSRpEvenRegNumber() const { 414 return Kind == Immediate && isUInt<6>(getImm()) && ((getImm() & 1) == 0); 415 } 416 bool isVSRegNumber() const { 417 return Kind == Immediate && isUInt<6>(getImm()); 418 } 419 bool isCCRegNumber() const { return (Kind == Expression 420 && isUInt<3>(getExprCRVal())) || 421 (Kind == Immediate 422 && isUInt<3>(getImm())); } 423 bool isCRBitNumber() const { return (Kind == Expression 424 && isUInt<5>(getExprCRVal())) || 425 (Kind == Immediate 426 && isUInt<5>(getImm())); } 427 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) && 428 isPowerOf2_32(getImm()); } 429 bool isATBitsAsHint() const { return false; } 430 bool isMem() const override { return false; } 431 bool isReg() const override { return false; } 432 433 void addRegOperands(MCInst &Inst, unsigned N) const { 434 llvm_unreachable("addRegOperands"); 435 } 436 437 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { 438 assert(N == 1 && "Invalid number of operands!"); 439 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 440 } 441 442 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { 443 assert(N == 1 && "Invalid number of operands!"); 444 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); 445 } 446 447 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { 448 assert(N == 1 && "Invalid number of operands!"); 449 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); 450 } 451 452 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { 453 assert(N == 1 && "Invalid number of operands!"); 454 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); 455 } 456 457 void addRegGxRCOperands(MCInst &Inst, unsigned N) const { 458 if (isPPC64()) 459 addRegG8RCOperands(Inst, N); 460 else 461 addRegGPRCOperands(Inst, N); 462 } 463 464 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const { 465 if (isPPC64()) 466 addRegG8RCNoX0Operands(Inst, N); 467 else 468 addRegGPRCNoR0Operands(Inst, N); 469 } 470 471 void addRegF4RCOperands(MCInst &Inst, unsigned N) const { 472 assert(N == 1 && "Invalid number of operands!"); 473 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 474 } 475 476 void addRegF8RCOperands(MCInst &Inst, unsigned N) const { 477 assert(N == 1 && "Invalid number of operands!"); 478 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 479 } 480 481 void addRegVFRCOperands(MCInst &Inst, unsigned N) const { 482 assert(N == 1 && "Invalid number of operands!"); 483 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); 484 } 485 486 void addRegVRRCOperands(MCInst &Inst, unsigned N) const { 487 assert(N == 1 && "Invalid number of operands!"); 488 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); 489 } 490 491 void addRegVSRCOperands(MCInst &Inst, unsigned N) const { 492 assert(N == 1 && "Invalid number of operands!"); 493 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); 494 } 495 496 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const { 497 assert(N == 1 && "Invalid number of operands!"); 498 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); 499 } 500 501 void addRegVSSRCOperands(MCInst &Inst, unsigned N) const { 502 assert(N == 1 && "Invalid number of operands!"); 503 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); 504 } 505 506 void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const { 507 assert(N == 1 && "Invalid number of operands!"); 508 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 509 } 510 511 void addRegSPERCOperands(MCInst &Inst, unsigned N) const { 512 assert(N == 1 && "Invalid number of operands!"); 513 Inst.addOperand(MCOperand::createReg(SPERegs[getReg()])); 514 } 515 516 void addRegACCRCOperands(MCInst &Inst, unsigned N) const { 517 assert(N == 1 && "Invalid number of operands!"); 518 Inst.addOperand(MCOperand::createReg(ACCRegs[getACCReg()])); 519 } 520 521 void addRegVSRpRCOperands(MCInst &Inst, unsigned N) const { 522 assert(N == 1 && "Invalid number of operands!"); 523 Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()])); 524 } 525 526 void addRegVSRpEvenRCOperands(MCInst &Inst, unsigned N) const { 527 assert(N == 1 && "Invalid number of operands!"); 528 Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()])); 529 } 530 531 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const { 532 assert(N == 1 && "Invalid number of operands!"); 533 Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()])); 534 } 535 536 void addRegCRRCOperands(MCInst &Inst, unsigned N) const { 537 assert(N == 1 && "Invalid number of operands!"); 538 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()])); 539 } 540 541 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const { 542 assert(N == 1 && "Invalid number of operands!"); 543 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()])); 544 } 545 546 void addImmOperands(MCInst &Inst, unsigned N) const { 547 assert(N == 1 && "Invalid number of operands!"); 548 if (Kind == Immediate) 549 Inst.addOperand(MCOperand::createImm(getImm())); 550 else 551 Inst.addOperand(MCOperand::createExpr(getExpr())); 552 } 553 554 void addS16ImmOperands(MCInst &Inst, unsigned N) const { 555 assert(N == 1 && "Invalid number of operands!"); 556 switch (Kind) { 557 case Immediate: 558 Inst.addOperand(MCOperand::createImm(getImm())); 559 break; 560 case ContextImmediate: 561 Inst.addOperand(MCOperand::createImm(getImmS16Context())); 562 break; 563 default: 564 Inst.addOperand(MCOperand::createExpr(getExpr())); 565 break; 566 } 567 } 568 569 void addU16ImmOperands(MCInst &Inst, unsigned N) const { 570 assert(N == 1 && "Invalid number of operands!"); 571 switch (Kind) { 572 case Immediate: 573 Inst.addOperand(MCOperand::createImm(getImm())); 574 break; 575 case ContextImmediate: 576 Inst.addOperand(MCOperand::createImm(getImmU16Context())); 577 break; 578 default: 579 Inst.addOperand(MCOperand::createExpr(getExpr())); 580 break; 581 } 582 } 583 584 void addBranchTargetOperands(MCInst &Inst, unsigned N) const { 585 assert(N == 1 && "Invalid number of operands!"); 586 if (Kind == Immediate) 587 Inst.addOperand(MCOperand::createImm(getImm() / 4)); 588 else 589 Inst.addOperand(MCOperand::createExpr(getExpr())); 590 } 591 592 void addTLSRegOperands(MCInst &Inst, unsigned N) const { 593 assert(N == 1 && "Invalid number of operands!"); 594 Inst.addOperand(MCOperand::createExpr(getTLSReg())); 595 } 596 597 StringRef getToken() const { 598 assert(Kind == Token && "Invalid access!"); 599 return StringRef(Tok.Data, Tok.Length); 600 } 601 602 void print(raw_ostream &OS) const override; 603 604 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S, 605 bool IsPPC64) { 606 auto Op = std::make_unique<PPCOperand>(Token); 607 Op->Tok.Data = Str.data(); 608 Op->Tok.Length = Str.size(); 609 Op->StartLoc = S; 610 Op->EndLoc = S; 611 Op->IsPPC64 = IsPPC64; 612 return Op; 613 } 614 615 static std::unique_ptr<PPCOperand> 616 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) { 617 // Allocate extra memory for the string and copy it. 618 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default 619 // deleter which will destroy them by simply using "delete", not correctly 620 // calling operator delete on this extra memory after calling the dtor 621 // explicitly. 622 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size()); 623 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token)); 624 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1); 625 Op->Tok.Length = Str.size(); 626 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size()); 627 Op->StartLoc = S; 628 Op->EndLoc = S; 629 Op->IsPPC64 = IsPPC64; 630 return Op; 631 } 632 633 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E, 634 bool IsPPC64) { 635 auto Op = std::make_unique<PPCOperand>(Immediate); 636 Op->Imm.Val = Val; 637 Op->StartLoc = S; 638 Op->EndLoc = E; 639 Op->IsPPC64 = IsPPC64; 640 return Op; 641 } 642 643 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S, 644 SMLoc E, bool IsPPC64) { 645 auto Op = std::make_unique<PPCOperand>(Expression); 646 Op->Expr.Val = Val; 647 Op->Expr.CRVal = EvaluateCRExpr(Val); 648 Op->StartLoc = S; 649 Op->EndLoc = E; 650 Op->IsPPC64 = IsPPC64; 651 return Op; 652 } 653 654 static std::unique_ptr<PPCOperand> 655 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) { 656 auto Op = std::make_unique<PPCOperand>(TLSRegister); 657 Op->TLSReg.Sym = Sym; 658 Op->StartLoc = S; 659 Op->EndLoc = E; 660 Op->IsPPC64 = IsPPC64; 661 return Op; 662 } 663 664 static std::unique_ptr<PPCOperand> 665 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) { 666 auto Op = std::make_unique<PPCOperand>(ContextImmediate); 667 Op->Imm.Val = Val; 668 Op->StartLoc = S; 669 Op->EndLoc = E; 670 Op->IsPPC64 = IsPPC64; 671 return Op; 672 } 673 674 static std::unique_ptr<PPCOperand> 675 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) { 676 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val)) 677 return CreateImm(CE->getValue(), S, E, IsPPC64); 678 679 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val)) 680 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS || 681 SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL) 682 return CreateTLSReg(SRE, S, E, IsPPC64); 683 684 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) { 685 int64_t Res; 686 if (TE->evaluateAsConstant(Res)) 687 return CreateContextImm(Res, S, E, IsPPC64); 688 } 689 690 return CreateExpr(Val, S, E, IsPPC64); 691 } 692 }; 693 694 } // end anonymous namespace. 695 696 void PPCOperand::print(raw_ostream &OS) const { 697 switch (Kind) { 698 case Token: 699 OS << "'" << getToken() << "'"; 700 break; 701 case Immediate: 702 case ContextImmediate: 703 OS << getImm(); 704 break; 705 case Expression: 706 OS << *getExpr(); 707 break; 708 case TLSRegister: 709 OS << *getTLSReg(); 710 break; 711 } 712 } 713 714 static void 715 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) { 716 if (Op.isImm()) { 717 Inst.addOperand(MCOperand::createImm(-Op.getImm())); 718 return; 719 } 720 const MCExpr *Expr = Op.getExpr(); 721 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) { 722 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) { 723 Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr())); 724 return; 725 } 726 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) { 727 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) { 728 const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(), 729 BinExpr->getLHS(), Ctx); 730 Inst.addOperand(MCOperand::createExpr(NE)); 731 return; 732 } 733 } 734 Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx))); 735 } 736 737 void PPCAsmParser::ProcessInstruction(MCInst &Inst, 738 const OperandVector &Operands) { 739 int Opcode = Inst.getOpcode(); 740 switch (Opcode) { 741 case PPC::DCBTx: 742 case PPC::DCBTT: 743 case PPC::DCBTSTx: 744 case PPC::DCBTSTT: { 745 MCInst TmpInst; 746 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? 747 PPC::DCBT : PPC::DCBTST); 748 TmpInst.addOperand(MCOperand::createImm( 749 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16)); 750 TmpInst.addOperand(Inst.getOperand(0)); 751 TmpInst.addOperand(Inst.getOperand(1)); 752 Inst = TmpInst; 753 break; 754 } 755 case PPC::DCBTCT: 756 case PPC::DCBTDS: { 757 MCInst TmpInst; 758 TmpInst.setOpcode(PPC::DCBT); 759 TmpInst.addOperand(Inst.getOperand(2)); 760 TmpInst.addOperand(Inst.getOperand(0)); 761 TmpInst.addOperand(Inst.getOperand(1)); 762 Inst = TmpInst; 763 break; 764 } 765 case PPC::DCBTSTCT: 766 case PPC::DCBTSTDS: { 767 MCInst TmpInst; 768 TmpInst.setOpcode(PPC::DCBTST); 769 TmpInst.addOperand(Inst.getOperand(2)); 770 TmpInst.addOperand(Inst.getOperand(0)); 771 TmpInst.addOperand(Inst.getOperand(1)); 772 Inst = TmpInst; 773 break; 774 } 775 case PPC::DCBFx: 776 case PPC::DCBFL: 777 case PPC::DCBFLP: 778 case PPC::DCBFPS: 779 case PPC::DCBSTPS: { 780 int L = 0; 781 if (Opcode == PPC::DCBFL) 782 L = 1; 783 else if (Opcode == PPC::DCBFLP) 784 L = 3; 785 else if (Opcode == PPC::DCBFPS) 786 L = 4; 787 else if (Opcode == PPC::DCBSTPS) 788 L = 6; 789 790 MCInst TmpInst; 791 TmpInst.setOpcode(PPC::DCBF); 792 TmpInst.addOperand(MCOperand::createImm(L)); 793 TmpInst.addOperand(Inst.getOperand(0)); 794 TmpInst.addOperand(Inst.getOperand(1)); 795 Inst = TmpInst; 796 break; 797 } 798 case PPC::LAx: { 799 MCInst TmpInst; 800 TmpInst.setOpcode(PPC::LA); 801 TmpInst.addOperand(Inst.getOperand(0)); 802 TmpInst.addOperand(Inst.getOperand(2)); 803 TmpInst.addOperand(Inst.getOperand(1)); 804 Inst = TmpInst; 805 break; 806 } 807 case PPC::SUBI: { 808 MCInst TmpInst; 809 TmpInst.setOpcode(PPC::ADDI); 810 TmpInst.addOperand(Inst.getOperand(0)); 811 TmpInst.addOperand(Inst.getOperand(1)); 812 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 813 Inst = TmpInst; 814 break; 815 } 816 case PPC::SUBIS: { 817 MCInst TmpInst; 818 TmpInst.setOpcode(PPC::ADDIS); 819 TmpInst.addOperand(Inst.getOperand(0)); 820 TmpInst.addOperand(Inst.getOperand(1)); 821 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 822 Inst = TmpInst; 823 break; 824 } 825 case PPC::SUBIC: { 826 MCInst TmpInst; 827 TmpInst.setOpcode(PPC::ADDIC); 828 TmpInst.addOperand(Inst.getOperand(0)); 829 TmpInst.addOperand(Inst.getOperand(1)); 830 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 831 Inst = TmpInst; 832 break; 833 } 834 case PPC::SUBIC_rec: { 835 MCInst TmpInst; 836 TmpInst.setOpcode(PPC::ADDIC_rec); 837 TmpInst.addOperand(Inst.getOperand(0)); 838 TmpInst.addOperand(Inst.getOperand(1)); 839 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 840 Inst = TmpInst; 841 break; 842 } 843 case PPC::EXTLWI: 844 case PPC::EXTLWI_rec: { 845 MCInst TmpInst; 846 int64_t N = Inst.getOperand(2).getImm(); 847 int64_t B = Inst.getOperand(3).getImm(); 848 TmpInst.setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec); 849 TmpInst.addOperand(Inst.getOperand(0)); 850 TmpInst.addOperand(Inst.getOperand(1)); 851 TmpInst.addOperand(MCOperand::createImm(B)); 852 TmpInst.addOperand(MCOperand::createImm(0)); 853 TmpInst.addOperand(MCOperand::createImm(N - 1)); 854 Inst = TmpInst; 855 break; 856 } 857 case PPC::EXTRWI: 858 case PPC::EXTRWI_rec: { 859 MCInst TmpInst; 860 int64_t N = Inst.getOperand(2).getImm(); 861 int64_t B = Inst.getOperand(3).getImm(); 862 TmpInst.setOpcode(Opcode == PPC::EXTRWI ? PPC::RLWINM : PPC::RLWINM_rec); 863 TmpInst.addOperand(Inst.getOperand(0)); 864 TmpInst.addOperand(Inst.getOperand(1)); 865 TmpInst.addOperand(MCOperand::createImm(B + N)); 866 TmpInst.addOperand(MCOperand::createImm(32 - N)); 867 TmpInst.addOperand(MCOperand::createImm(31)); 868 Inst = TmpInst; 869 break; 870 } 871 case PPC::INSLWI: 872 case PPC::INSLWI_rec: { 873 MCInst TmpInst; 874 int64_t N = Inst.getOperand(2).getImm(); 875 int64_t B = Inst.getOperand(3).getImm(); 876 TmpInst.setOpcode(Opcode == PPC::INSLWI ? PPC::RLWIMI : PPC::RLWIMI_rec); 877 TmpInst.addOperand(Inst.getOperand(0)); 878 TmpInst.addOperand(Inst.getOperand(0)); 879 TmpInst.addOperand(Inst.getOperand(1)); 880 TmpInst.addOperand(MCOperand::createImm(32 - B)); 881 TmpInst.addOperand(MCOperand::createImm(B)); 882 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 883 Inst = TmpInst; 884 break; 885 } 886 case PPC::INSRWI: 887 case PPC::INSRWI_rec: { 888 MCInst TmpInst; 889 int64_t N = Inst.getOperand(2).getImm(); 890 int64_t B = Inst.getOperand(3).getImm(); 891 TmpInst.setOpcode(Opcode == PPC::INSRWI ? PPC::RLWIMI : PPC::RLWIMI_rec); 892 TmpInst.addOperand(Inst.getOperand(0)); 893 TmpInst.addOperand(Inst.getOperand(0)); 894 TmpInst.addOperand(Inst.getOperand(1)); 895 TmpInst.addOperand(MCOperand::createImm(32 - (B + N))); 896 TmpInst.addOperand(MCOperand::createImm(B)); 897 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 898 Inst = TmpInst; 899 break; 900 } 901 case PPC::ROTRWI: 902 case PPC::ROTRWI_rec: { 903 MCInst TmpInst; 904 int64_t N = Inst.getOperand(2).getImm(); 905 TmpInst.setOpcode(Opcode == PPC::ROTRWI ? PPC::RLWINM : PPC::RLWINM_rec); 906 TmpInst.addOperand(Inst.getOperand(0)); 907 TmpInst.addOperand(Inst.getOperand(1)); 908 TmpInst.addOperand(MCOperand::createImm(32 - N)); 909 TmpInst.addOperand(MCOperand::createImm(0)); 910 TmpInst.addOperand(MCOperand::createImm(31)); 911 Inst = TmpInst; 912 break; 913 } 914 case PPC::SLWI: 915 case PPC::SLWI_rec: { 916 MCInst TmpInst; 917 int64_t N = Inst.getOperand(2).getImm(); 918 TmpInst.setOpcode(Opcode == PPC::SLWI ? PPC::RLWINM : PPC::RLWINM_rec); 919 TmpInst.addOperand(Inst.getOperand(0)); 920 TmpInst.addOperand(Inst.getOperand(1)); 921 TmpInst.addOperand(MCOperand::createImm(N)); 922 TmpInst.addOperand(MCOperand::createImm(0)); 923 TmpInst.addOperand(MCOperand::createImm(31 - N)); 924 Inst = TmpInst; 925 break; 926 } 927 case PPC::SRWI: 928 case PPC::SRWI_rec: { 929 MCInst TmpInst; 930 int64_t N = Inst.getOperand(2).getImm(); 931 TmpInst.setOpcode(Opcode == PPC::SRWI ? PPC::RLWINM : PPC::RLWINM_rec); 932 TmpInst.addOperand(Inst.getOperand(0)); 933 TmpInst.addOperand(Inst.getOperand(1)); 934 TmpInst.addOperand(MCOperand::createImm(32 - N)); 935 TmpInst.addOperand(MCOperand::createImm(N)); 936 TmpInst.addOperand(MCOperand::createImm(31)); 937 Inst = TmpInst; 938 break; 939 } 940 case PPC::CLRRWI: 941 case PPC::CLRRWI_rec: { 942 MCInst TmpInst; 943 int64_t N = Inst.getOperand(2).getImm(); 944 TmpInst.setOpcode(Opcode == PPC::CLRRWI ? PPC::RLWINM : PPC::RLWINM_rec); 945 TmpInst.addOperand(Inst.getOperand(0)); 946 TmpInst.addOperand(Inst.getOperand(1)); 947 TmpInst.addOperand(MCOperand::createImm(0)); 948 TmpInst.addOperand(MCOperand::createImm(0)); 949 TmpInst.addOperand(MCOperand::createImm(31 - N)); 950 Inst = TmpInst; 951 break; 952 } 953 case PPC::CLRLSLWI: 954 case PPC::CLRLSLWI_rec: { 955 MCInst TmpInst; 956 int64_t B = Inst.getOperand(2).getImm(); 957 int64_t N = Inst.getOperand(3).getImm(); 958 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI ? PPC::RLWINM : PPC::RLWINM_rec); 959 TmpInst.addOperand(Inst.getOperand(0)); 960 TmpInst.addOperand(Inst.getOperand(1)); 961 TmpInst.addOperand(MCOperand::createImm(N)); 962 TmpInst.addOperand(MCOperand::createImm(B - N)); 963 TmpInst.addOperand(MCOperand::createImm(31 - N)); 964 Inst = TmpInst; 965 break; 966 } 967 case PPC::EXTLDI: 968 case PPC::EXTLDI_rec: { 969 MCInst TmpInst; 970 int64_t N = Inst.getOperand(2).getImm(); 971 int64_t B = Inst.getOperand(3).getImm(); 972 TmpInst.setOpcode(Opcode == PPC::EXTLDI ? PPC::RLDICR : PPC::RLDICR_rec); 973 TmpInst.addOperand(Inst.getOperand(0)); 974 TmpInst.addOperand(Inst.getOperand(1)); 975 TmpInst.addOperand(MCOperand::createImm(B)); 976 TmpInst.addOperand(MCOperand::createImm(N - 1)); 977 Inst = TmpInst; 978 break; 979 } 980 case PPC::EXTRDI: 981 case PPC::EXTRDI_rec: { 982 MCInst TmpInst; 983 int64_t N = Inst.getOperand(2).getImm(); 984 int64_t B = Inst.getOperand(3).getImm(); 985 TmpInst.setOpcode(Opcode == PPC::EXTRDI ? PPC::RLDICL : PPC::RLDICL_rec); 986 TmpInst.addOperand(Inst.getOperand(0)); 987 TmpInst.addOperand(Inst.getOperand(1)); 988 TmpInst.addOperand(MCOperand::createImm(B + N)); 989 TmpInst.addOperand(MCOperand::createImm(64 - N)); 990 Inst = TmpInst; 991 break; 992 } 993 case PPC::INSRDI: 994 case PPC::INSRDI_rec: { 995 MCInst TmpInst; 996 int64_t N = Inst.getOperand(2).getImm(); 997 int64_t B = Inst.getOperand(3).getImm(); 998 TmpInst.setOpcode(Opcode == PPC::INSRDI ? PPC::RLDIMI : PPC::RLDIMI_rec); 999 TmpInst.addOperand(Inst.getOperand(0)); 1000 TmpInst.addOperand(Inst.getOperand(0)); 1001 TmpInst.addOperand(Inst.getOperand(1)); 1002 TmpInst.addOperand(MCOperand::createImm(64 - (B + N))); 1003 TmpInst.addOperand(MCOperand::createImm(B)); 1004 Inst = TmpInst; 1005 break; 1006 } 1007 case PPC::ROTRDI: 1008 case PPC::ROTRDI_rec: { 1009 MCInst TmpInst; 1010 int64_t N = Inst.getOperand(2).getImm(); 1011 TmpInst.setOpcode(Opcode == PPC::ROTRDI ? PPC::RLDICL : PPC::RLDICL_rec); 1012 TmpInst.addOperand(Inst.getOperand(0)); 1013 TmpInst.addOperand(Inst.getOperand(1)); 1014 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1015 TmpInst.addOperand(MCOperand::createImm(0)); 1016 Inst = TmpInst; 1017 break; 1018 } 1019 case PPC::SLDI: 1020 case PPC::SLDI_rec: { 1021 MCInst TmpInst; 1022 int64_t N = Inst.getOperand(2).getImm(); 1023 TmpInst.setOpcode(Opcode == PPC::SLDI ? PPC::RLDICR : PPC::RLDICR_rec); 1024 TmpInst.addOperand(Inst.getOperand(0)); 1025 TmpInst.addOperand(Inst.getOperand(1)); 1026 TmpInst.addOperand(MCOperand::createImm(N)); 1027 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1028 Inst = TmpInst; 1029 break; 1030 } 1031 case PPC::SUBPCIS: { 1032 MCInst TmpInst; 1033 int64_t N = Inst.getOperand(1).getImm(); 1034 TmpInst.setOpcode(PPC::ADDPCIS); 1035 TmpInst.addOperand(Inst.getOperand(0)); 1036 TmpInst.addOperand(MCOperand::createImm(-N)); 1037 Inst = TmpInst; 1038 break; 1039 } 1040 case PPC::SRDI: 1041 case PPC::SRDI_rec: { 1042 MCInst TmpInst; 1043 int64_t N = Inst.getOperand(2).getImm(); 1044 TmpInst.setOpcode(Opcode == PPC::SRDI ? PPC::RLDICL : PPC::RLDICL_rec); 1045 TmpInst.addOperand(Inst.getOperand(0)); 1046 TmpInst.addOperand(Inst.getOperand(1)); 1047 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1048 TmpInst.addOperand(MCOperand::createImm(N)); 1049 Inst = TmpInst; 1050 break; 1051 } 1052 case PPC::CLRRDI: 1053 case PPC::CLRRDI_rec: { 1054 MCInst TmpInst; 1055 int64_t N = Inst.getOperand(2).getImm(); 1056 TmpInst.setOpcode(Opcode == PPC::CLRRDI ? PPC::RLDICR : PPC::RLDICR_rec); 1057 TmpInst.addOperand(Inst.getOperand(0)); 1058 TmpInst.addOperand(Inst.getOperand(1)); 1059 TmpInst.addOperand(MCOperand::createImm(0)); 1060 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1061 Inst = TmpInst; 1062 break; 1063 } 1064 case PPC::CLRLSLDI: 1065 case PPC::CLRLSLDI_rec: { 1066 MCInst TmpInst; 1067 int64_t B = Inst.getOperand(2).getImm(); 1068 int64_t N = Inst.getOperand(3).getImm(); 1069 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI ? PPC::RLDIC : PPC::RLDIC_rec); 1070 TmpInst.addOperand(Inst.getOperand(0)); 1071 TmpInst.addOperand(Inst.getOperand(1)); 1072 TmpInst.addOperand(MCOperand::createImm(N)); 1073 TmpInst.addOperand(MCOperand::createImm(B - N)); 1074 Inst = TmpInst; 1075 break; 1076 } 1077 case PPC::RLWINMbm: 1078 case PPC::RLWINMbm_rec: { 1079 unsigned MB, ME; 1080 int64_t BM = Inst.getOperand(3).getImm(); 1081 if (!isRunOfOnes(BM, MB, ME)) 1082 break; 1083 1084 MCInst TmpInst; 1085 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINM_rec); 1086 TmpInst.addOperand(Inst.getOperand(0)); 1087 TmpInst.addOperand(Inst.getOperand(1)); 1088 TmpInst.addOperand(Inst.getOperand(2)); 1089 TmpInst.addOperand(MCOperand::createImm(MB)); 1090 TmpInst.addOperand(MCOperand::createImm(ME)); 1091 Inst = TmpInst; 1092 break; 1093 } 1094 case PPC::RLWIMIbm: 1095 case PPC::RLWIMIbm_rec: { 1096 unsigned MB, ME; 1097 int64_t BM = Inst.getOperand(3).getImm(); 1098 if (!isRunOfOnes(BM, MB, ME)) 1099 break; 1100 1101 MCInst TmpInst; 1102 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMI_rec); 1103 TmpInst.addOperand(Inst.getOperand(0)); 1104 TmpInst.addOperand(Inst.getOperand(0)); // The tied operand. 1105 TmpInst.addOperand(Inst.getOperand(1)); 1106 TmpInst.addOperand(Inst.getOperand(2)); 1107 TmpInst.addOperand(MCOperand::createImm(MB)); 1108 TmpInst.addOperand(MCOperand::createImm(ME)); 1109 Inst = TmpInst; 1110 break; 1111 } 1112 case PPC::RLWNMbm: 1113 case PPC::RLWNMbm_rec: { 1114 unsigned MB, ME; 1115 int64_t BM = Inst.getOperand(3).getImm(); 1116 if (!isRunOfOnes(BM, MB, ME)) 1117 break; 1118 1119 MCInst TmpInst; 1120 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNM_rec); 1121 TmpInst.addOperand(Inst.getOperand(0)); 1122 TmpInst.addOperand(Inst.getOperand(1)); 1123 TmpInst.addOperand(Inst.getOperand(2)); 1124 TmpInst.addOperand(MCOperand::createImm(MB)); 1125 TmpInst.addOperand(MCOperand::createImm(ME)); 1126 Inst = TmpInst; 1127 break; 1128 } 1129 case PPC::MFTB: { 1130 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) { 1131 assert(Inst.getNumOperands() == 2 && "Expecting two operands"); 1132 Inst.setOpcode(PPC::MFSPR); 1133 } 1134 break; 1135 } 1136 case PPC::CP_COPYx: 1137 case PPC::CP_COPY_FIRST: { 1138 MCInst TmpInst; 1139 TmpInst.setOpcode(PPC::CP_COPY); 1140 TmpInst.addOperand(Inst.getOperand(0)); 1141 TmpInst.addOperand(Inst.getOperand(1)); 1142 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1)); 1143 1144 Inst = TmpInst; 1145 break; 1146 } 1147 case PPC::CP_PASTEx : 1148 case PPC::CP_PASTE_LAST: { 1149 MCInst TmpInst; 1150 TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ? PPC::CP_PASTE 1151 : PPC::CP_PASTE_rec); 1152 TmpInst.addOperand(Inst.getOperand(0)); 1153 TmpInst.addOperand(Inst.getOperand(1)); 1154 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1)); 1155 1156 Inst = TmpInst; 1157 break; 1158 } 1159 } 1160 } 1161 1162 static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, 1163 unsigned VariantID = 0); 1164 1165 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 1166 OperandVector &Operands, 1167 MCStreamer &Out, uint64_t &ErrorInfo, 1168 bool MatchingInlineAsm) { 1169 MCInst Inst; 1170 1171 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { 1172 case Match_Success: 1173 // Post-process instructions (typically extended mnemonics) 1174 ProcessInstruction(Inst, Operands); 1175 Inst.setLoc(IDLoc); 1176 Out.emitInstruction(Inst, getSTI()); 1177 return false; 1178 case Match_MissingFeature: 1179 return Error(IDLoc, "instruction use requires an option to be enabled"); 1180 case Match_MnemonicFail: { 1181 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); 1182 std::string Suggestion = PPCMnemonicSpellCheck( 1183 ((PPCOperand &)*Operands[0]).getToken(), FBS); 1184 return Error(IDLoc, "invalid instruction" + Suggestion, 1185 ((PPCOperand &)*Operands[0]).getLocRange()); 1186 } 1187 case Match_InvalidOperand: { 1188 SMLoc ErrorLoc = IDLoc; 1189 if (ErrorInfo != ~0ULL) { 1190 if (ErrorInfo >= Operands.size()) 1191 return Error(IDLoc, "too few operands for instruction"); 1192 1193 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc(); 1194 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 1195 } 1196 1197 return Error(ErrorLoc, "invalid operand for instruction"); 1198 } 1199 } 1200 1201 llvm_unreachable("Implement any new match types added!"); 1202 } 1203 1204 bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) { 1205 if (getParser().getTok().is(AsmToken::Percent)) 1206 getParser().Lex(); // Eat the '%'. 1207 1208 if (!getParser().getTok().is(AsmToken::Identifier)) 1209 return true; 1210 1211 StringRef Name = getParser().getTok().getString(); 1212 if (Name.equals_lower("lr")) { 1213 RegNo = isPPC64() ? PPC::LR8 : PPC::LR; 1214 IntVal = 8; 1215 } else if (Name.equals_lower("ctr")) { 1216 RegNo = isPPC64() ? PPC::CTR8 : PPC::CTR; 1217 IntVal = 9; 1218 } else if (Name.equals_lower("vrsave")) { 1219 RegNo = PPC::VRSAVE; 1220 IntVal = 256; 1221 } else if (Name.startswith_lower("r") && 1222 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1223 RegNo = isPPC64() ? XRegs[IntVal] : RRegs[IntVal]; 1224 } else if (Name.startswith_lower("f") && 1225 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1226 RegNo = FRegs[IntVal]; 1227 } else if (Name.startswith_lower("vs") && 1228 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) { 1229 RegNo = VSRegs[IntVal]; 1230 } else if (Name.startswith_lower("v") && 1231 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1232 RegNo = VRegs[IntVal]; 1233 } else if (Name.startswith_lower("cr") && 1234 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { 1235 RegNo = CRRegs[IntVal]; 1236 } else 1237 return true; 1238 getParser().Lex(); 1239 return false; 1240 } 1241 1242 bool PPCAsmParser:: 1243 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 1244 if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success) 1245 return TokError("invalid register name"); 1246 return false; 1247 } 1248 1249 OperandMatchResultTy PPCAsmParser::tryParseRegister(unsigned &RegNo, 1250 SMLoc &StartLoc, 1251 SMLoc &EndLoc) { 1252 const AsmToken &Tok = getParser().getTok(); 1253 StartLoc = Tok.getLoc(); 1254 EndLoc = Tok.getEndLoc(); 1255 RegNo = 0; 1256 int64_t IntVal; 1257 if (MatchRegisterName(RegNo, IntVal)) 1258 return MatchOperand_NoMatch; 1259 return MatchOperand_Success; 1260 } 1261 1262 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan 1263 /// the expression and check for VK_PPC_LO/HI/HA 1264 /// symbol variants. If all symbols with modifier use the same 1265 /// variant, return the corresponding PPCMCExpr::VariantKind, 1266 /// and a modified expression using the default symbol variant. 1267 /// Otherwise, return NULL. 1268 const MCExpr *PPCAsmParser:: 1269 ExtractModifierFromExpr(const MCExpr *E, 1270 PPCMCExpr::VariantKind &Variant) { 1271 MCContext &Context = getParser().getContext(); 1272 Variant = PPCMCExpr::VK_PPC_None; 1273 1274 switch (E->getKind()) { 1275 case MCExpr::Target: 1276 case MCExpr::Constant: 1277 return nullptr; 1278 1279 case MCExpr::SymbolRef: { 1280 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1281 1282 switch (SRE->getKind()) { 1283 case MCSymbolRefExpr::VK_PPC_LO: 1284 Variant = PPCMCExpr::VK_PPC_LO; 1285 break; 1286 case MCSymbolRefExpr::VK_PPC_HI: 1287 Variant = PPCMCExpr::VK_PPC_HI; 1288 break; 1289 case MCSymbolRefExpr::VK_PPC_HA: 1290 Variant = PPCMCExpr::VK_PPC_HA; 1291 break; 1292 case MCSymbolRefExpr::VK_PPC_HIGH: 1293 Variant = PPCMCExpr::VK_PPC_HIGH; 1294 break; 1295 case MCSymbolRefExpr::VK_PPC_HIGHA: 1296 Variant = PPCMCExpr::VK_PPC_HIGHA; 1297 break; 1298 case MCSymbolRefExpr::VK_PPC_HIGHER: 1299 Variant = PPCMCExpr::VK_PPC_HIGHER; 1300 break; 1301 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1302 Variant = PPCMCExpr::VK_PPC_HIGHERA; 1303 break; 1304 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1305 Variant = PPCMCExpr::VK_PPC_HIGHEST; 1306 break; 1307 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1308 Variant = PPCMCExpr::VK_PPC_HIGHESTA; 1309 break; 1310 default: 1311 return nullptr; 1312 } 1313 1314 return MCSymbolRefExpr::create(&SRE->getSymbol(), Context); 1315 } 1316 1317 case MCExpr::Unary: { 1318 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1319 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant); 1320 if (!Sub) 1321 return nullptr; 1322 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1323 } 1324 1325 case MCExpr::Binary: { 1326 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1327 PPCMCExpr::VariantKind LHSVariant, RHSVariant; 1328 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant); 1329 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant); 1330 1331 if (!LHS && !RHS) 1332 return nullptr; 1333 1334 if (!LHS) LHS = BE->getLHS(); 1335 if (!RHS) RHS = BE->getRHS(); 1336 1337 if (LHSVariant == PPCMCExpr::VK_PPC_None) 1338 Variant = RHSVariant; 1339 else if (RHSVariant == PPCMCExpr::VK_PPC_None) 1340 Variant = LHSVariant; 1341 else if (LHSVariant == RHSVariant) 1342 Variant = LHSVariant; 1343 else 1344 return nullptr; 1345 1346 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1347 } 1348 } 1349 1350 llvm_unreachable("Invalid expression kind!"); 1351 } 1352 1353 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace 1354 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having 1355 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT. 1356 /// FIXME: This is a hack. 1357 const MCExpr *PPCAsmParser:: 1358 FixupVariantKind(const MCExpr *E) { 1359 MCContext &Context = getParser().getContext(); 1360 1361 switch (E->getKind()) { 1362 case MCExpr::Target: 1363 case MCExpr::Constant: 1364 return E; 1365 1366 case MCExpr::SymbolRef: { 1367 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1368 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; 1369 1370 switch (SRE->getKind()) { 1371 case MCSymbolRefExpr::VK_TLSGD: 1372 Variant = MCSymbolRefExpr::VK_PPC_TLSGD; 1373 break; 1374 case MCSymbolRefExpr::VK_TLSLD: 1375 Variant = MCSymbolRefExpr::VK_PPC_TLSLD; 1376 break; 1377 default: 1378 return E; 1379 } 1380 return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context); 1381 } 1382 1383 case MCExpr::Unary: { 1384 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1385 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr()); 1386 if (Sub == UE->getSubExpr()) 1387 return E; 1388 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1389 } 1390 1391 case MCExpr::Binary: { 1392 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1393 const MCExpr *LHS = FixupVariantKind(BE->getLHS()); 1394 const MCExpr *RHS = FixupVariantKind(BE->getRHS()); 1395 if (LHS == BE->getLHS() && RHS == BE->getRHS()) 1396 return E; 1397 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1398 } 1399 } 1400 1401 llvm_unreachable("Invalid expression kind!"); 1402 } 1403 1404 /// ParseExpression. This differs from the default "parseExpression" in that 1405 /// it handles modifiers. 1406 bool PPCAsmParser:: 1407 ParseExpression(const MCExpr *&EVal) { 1408 // (ELF Platforms) 1409 // Handle \code @l/@ha \endcode 1410 if (getParser().parseExpression(EVal)) 1411 return true; 1412 1413 EVal = FixupVariantKind(EVal); 1414 1415 PPCMCExpr::VariantKind Variant; 1416 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant); 1417 if (E) 1418 EVal = PPCMCExpr::create(Variant, E, getParser().getContext()); 1419 1420 return false; 1421 } 1422 1423 /// ParseOperand 1424 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and 1425 /// rNN for MachO. 1426 bool PPCAsmParser::ParseOperand(OperandVector &Operands) { 1427 MCAsmParser &Parser = getParser(); 1428 SMLoc S = Parser.getTok().getLoc(); 1429 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1430 const MCExpr *EVal; 1431 1432 // Attempt to parse the next token as an immediate 1433 switch (getLexer().getKind()) { 1434 // Special handling for register names. These are interpreted 1435 // as immediates corresponding to the register number. 1436 case AsmToken::Percent: { 1437 unsigned RegNo; 1438 int64_t IntVal; 1439 if (MatchRegisterName(RegNo, IntVal)) 1440 return Error(S, "invalid register name"); 1441 1442 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1443 return false; 1444 } 1445 case AsmToken::Identifier: 1446 case AsmToken::LParen: 1447 case AsmToken::Plus: 1448 case AsmToken::Minus: 1449 case AsmToken::Integer: 1450 case AsmToken::Dot: 1451 case AsmToken::Dollar: 1452 case AsmToken::Exclaim: 1453 case AsmToken::Tilde: 1454 if (!ParseExpression(EVal)) 1455 break; 1456 // Fall-through 1457 LLVM_FALLTHROUGH; 1458 default: 1459 return Error(S, "unknown operand"); 1460 } 1461 1462 // Push the parsed operand into the list of operands 1463 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64())); 1464 1465 // Check whether this is a TLS call expression 1466 bool TLSCall = false; 1467 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal)) 1468 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr"; 1469 1470 if (TLSCall && getLexer().is(AsmToken::LParen)) { 1471 const MCExpr *TLSSym; 1472 1473 Parser.Lex(); // Eat the '('. 1474 S = Parser.getTok().getLoc(); 1475 if (ParseExpression(TLSSym)) 1476 return Error(S, "invalid TLS call expression"); 1477 if (getLexer().isNot(AsmToken::RParen)) 1478 return Error(Parser.getTok().getLoc(), "missing ')'"); 1479 E = Parser.getTok().getLoc(); 1480 Parser.Lex(); // Eat the ')'. 1481 1482 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64())); 1483 } 1484 1485 // Otherwise, check for D-form memory operands 1486 if (!TLSCall && getLexer().is(AsmToken::LParen)) { 1487 Parser.Lex(); // Eat the '('. 1488 S = Parser.getTok().getLoc(); 1489 1490 int64_t IntVal; 1491 switch (getLexer().getKind()) { 1492 case AsmToken::Percent: { 1493 unsigned RegNo; 1494 if (MatchRegisterName(RegNo, IntVal)) 1495 return Error(S, "invalid register name"); 1496 break; 1497 } 1498 case AsmToken::Integer: 1499 if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 || 1500 IntVal > 31) 1501 return Error(S, "invalid register number"); 1502 break; 1503 case AsmToken::Identifier: 1504 default: 1505 return Error(S, "invalid memory operand"); 1506 } 1507 1508 E = Parser.getTok().getLoc(); 1509 if (parseToken(AsmToken::RParen, "missing ')'")) 1510 return true; 1511 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1512 } 1513 1514 return false; 1515 } 1516 1517 /// Parse an instruction mnemonic followed by its operands. 1518 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 1519 SMLoc NameLoc, OperandVector &Operands) { 1520 // The first operand is the token for the instruction name. 1521 // If the next character is a '+' or '-', we need to add it to the 1522 // instruction name, to match what TableGen is doing. 1523 std::string NewOpcode; 1524 if (parseOptionalToken(AsmToken::Plus)) { 1525 NewOpcode = std::string(Name); 1526 NewOpcode += '+'; 1527 Name = NewOpcode; 1528 } 1529 if (parseOptionalToken(AsmToken::Minus)) { 1530 NewOpcode = std::string(Name); 1531 NewOpcode += '-'; 1532 Name = NewOpcode; 1533 } 1534 // If the instruction ends in a '.', we need to create a separate 1535 // token for it, to match what TableGen is doing. 1536 size_t Dot = Name.find('.'); 1537 StringRef Mnemonic = Name.slice(0, Dot); 1538 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1539 Operands.push_back( 1540 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64())); 1541 else 1542 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64())); 1543 if (Dot != StringRef::npos) { 1544 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot); 1545 StringRef DotStr = Name.slice(Dot, StringRef::npos); 1546 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1547 Operands.push_back( 1548 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64())); 1549 else 1550 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64())); 1551 } 1552 1553 // If there are no more operands then finish 1554 if (parseOptionalToken(AsmToken::EndOfStatement)) 1555 return false; 1556 1557 // Parse the first operand 1558 if (ParseOperand(Operands)) 1559 return true; 1560 1561 while (!parseOptionalToken(AsmToken::EndOfStatement)) { 1562 if (parseToken(AsmToken::Comma) || ParseOperand(Operands)) 1563 return true; 1564 } 1565 1566 // We'll now deal with an unfortunate special case: the syntax for the dcbt 1567 // and dcbtst instructions differs for server vs. embedded cores. 1568 // The syntax for dcbt is: 1569 // dcbt ra, rb, th [server] 1570 // dcbt th, ra, rb [embedded] 1571 // where th can be omitted when it is 0. dcbtst is the same. We take the 1572 // server form to be the default, so swap the operands if we're parsing for 1573 // an embedded core (they'll be swapped again upon printing). 1574 if (getSTI().getFeatureBits()[PPC::FeatureBookE] && 1575 Operands.size() == 4 && 1576 (Name == "dcbt" || Name == "dcbtst")) { 1577 std::swap(Operands[1], Operands[3]); 1578 std::swap(Operands[2], Operands[1]); 1579 } 1580 1581 return false; 1582 } 1583 1584 /// ParseDirective parses the PPC specific directives 1585 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) { 1586 StringRef IDVal = DirectiveID.getIdentifier(); 1587 if (IDVal == ".word") 1588 ParseDirectiveWord(2, DirectiveID); 1589 else if (IDVal == ".llong") 1590 ParseDirectiveWord(8, DirectiveID); 1591 else if (IDVal == ".tc") 1592 ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID); 1593 else if (IDVal == ".machine") 1594 ParseDirectiveMachine(DirectiveID.getLoc()); 1595 else if (IDVal == ".abiversion") 1596 ParseDirectiveAbiVersion(DirectiveID.getLoc()); 1597 else if (IDVal == ".localentry") 1598 ParseDirectiveLocalEntry(DirectiveID.getLoc()); 1599 else 1600 return true; 1601 return false; 1602 } 1603 1604 /// ParseDirectiveWord 1605 /// ::= .word [ expression (, expression)* ] 1606 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) { 1607 auto parseOp = [&]() -> bool { 1608 const MCExpr *Value; 1609 SMLoc ExprLoc = getParser().getTok().getLoc(); 1610 if (getParser().parseExpression(Value)) 1611 return true; 1612 if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) { 1613 assert(Size <= 8 && "Invalid size"); 1614 uint64_t IntValue = MCE->getValue(); 1615 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue)) 1616 return Error(ExprLoc, "literal value out of range for '" + 1617 ID.getIdentifier() + "' directive"); 1618 getStreamer().emitIntValue(IntValue, Size); 1619 } else 1620 getStreamer().emitValue(Value, Size, ExprLoc); 1621 return false; 1622 }; 1623 1624 if (parseMany(parseOp)) 1625 return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive"); 1626 return false; 1627 } 1628 1629 /// ParseDirectiveTC 1630 /// ::= .tc [ symbol (, expression)* ] 1631 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) { 1632 MCAsmParser &Parser = getParser(); 1633 // Skip TC symbol, which is only used with XCOFF. 1634 while (getLexer().isNot(AsmToken::EndOfStatement) 1635 && getLexer().isNot(AsmToken::Comma)) 1636 Parser.Lex(); 1637 if (parseToken(AsmToken::Comma)) 1638 return addErrorSuffix(" in '.tc' directive"); 1639 1640 // Align to word size. 1641 getParser().getStreamer().emitValueToAlignment(Size); 1642 1643 // Emit expressions. 1644 return ParseDirectiveWord(Size, ID); 1645 } 1646 1647 /// ParseDirectiveMachine (ELF platforms) 1648 /// ::= .machine [ cpu | "push" | "pop" ] 1649 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) { 1650 MCAsmParser &Parser = getParser(); 1651 if (Parser.getTok().isNot(AsmToken::Identifier) && 1652 Parser.getTok().isNot(AsmToken::String)) 1653 return Error(L, "unexpected token in '.machine' directive"); 1654 1655 StringRef CPU = Parser.getTok().getIdentifier(); 1656 1657 // FIXME: Right now, the parser always allows any available 1658 // instruction, so the .machine directive is not useful. 1659 // Implement ".machine any" (by doing nothing) for the benefit 1660 // of existing assembler code. Likewise, we can then implement 1661 // ".machine push" and ".machine pop" as no-op. 1662 if (CPU != "any" && CPU != "push" && CPU != "pop" && CPU != "ppc64") 1663 return TokError("unrecognized machine type"); 1664 1665 Parser.Lex(); 1666 1667 if (parseToken(AsmToken::EndOfStatement)) 1668 return addErrorSuffix(" in '.machine' directive"); 1669 1670 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>( 1671 getParser().getStreamer().getTargetStreamer()); 1672 if (TStreamer != nullptr) 1673 TStreamer->emitMachine(CPU); 1674 1675 return false; 1676 } 1677 1678 /// ParseDirectiveAbiVersion 1679 /// ::= .abiversion constant-expression 1680 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) { 1681 int64_t AbiVersion; 1682 if (check(getParser().parseAbsoluteExpression(AbiVersion), L, 1683 "expected constant expression") || 1684 parseToken(AsmToken::EndOfStatement)) 1685 return addErrorSuffix(" in '.abiversion' directive"); 1686 1687 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>( 1688 getParser().getStreamer().getTargetStreamer()); 1689 if (TStreamer != nullptr) 1690 TStreamer->emitAbiVersion(AbiVersion); 1691 1692 return false; 1693 } 1694 1695 /// ParseDirectiveLocalEntry 1696 /// ::= .localentry symbol, expression 1697 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) { 1698 StringRef Name; 1699 if (getParser().parseIdentifier(Name)) 1700 return Error(L, "expected identifier in '.localentry' directive"); 1701 1702 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name)); 1703 const MCExpr *Expr; 1704 1705 if (parseToken(AsmToken::Comma) || 1706 check(getParser().parseExpression(Expr), L, "expected expression") || 1707 parseToken(AsmToken::EndOfStatement)) 1708 return addErrorSuffix(" in '.localentry' directive"); 1709 1710 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>( 1711 getParser().getStreamer().getTargetStreamer()); 1712 if (TStreamer != nullptr) 1713 TStreamer->emitLocalEntry(Sym, Expr); 1714 1715 return false; 1716 } 1717 1718 1719 1720 /// Force static initialization. 1721 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCAsmParser() { 1722 RegisterMCAsmParser<PPCAsmParser> A(getThePPC32Target()); 1723 RegisterMCAsmParser<PPCAsmParser> B(getThePPC64Target()); 1724 RegisterMCAsmParser<PPCAsmParser> C(getThePPC64LETarget()); 1725 } 1726 1727 #define GET_REGISTER_MATCHER 1728 #define GET_MATCHER_IMPLEMENTATION 1729 #define GET_MNEMONIC_SPELL_CHECKER 1730 #include "PPCGenAsmMatcher.inc" 1731 1732 // Define this matcher function after the auto-generated include so we 1733 // have the match class enum definitions. 1734 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, 1735 unsigned Kind) { 1736 // If the kind is a token for a literal immediate, check if our asm 1737 // operand matches. This is for InstAliases which have a fixed-value 1738 // immediate in the syntax. 1739 int64_t ImmVal; 1740 switch (Kind) { 1741 case MCK_0: ImmVal = 0; break; 1742 case MCK_1: ImmVal = 1; break; 1743 case MCK_2: ImmVal = 2; break; 1744 case MCK_3: ImmVal = 3; break; 1745 case MCK_4: ImmVal = 4; break; 1746 case MCK_5: ImmVal = 5; break; 1747 case MCK_6: ImmVal = 6; break; 1748 case MCK_7: ImmVal = 7; break; 1749 default: return Match_InvalidOperand; 1750 } 1751 1752 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp); 1753 if (Op.isImm() && Op.getImm() == ImmVal) 1754 return Match_Success; 1755 1756 return Match_InvalidOperand; 1757 } 1758 1759 const MCExpr * 1760 PPCAsmParser::applyModifierToExpr(const MCExpr *E, 1761 MCSymbolRefExpr::VariantKind Variant, 1762 MCContext &Ctx) { 1763 switch (Variant) { 1764 case MCSymbolRefExpr::VK_PPC_LO: 1765 return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, Ctx); 1766 case MCSymbolRefExpr::VK_PPC_HI: 1767 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, Ctx); 1768 case MCSymbolRefExpr::VK_PPC_HA: 1769 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, Ctx); 1770 case MCSymbolRefExpr::VK_PPC_HIGH: 1771 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGH, E, Ctx); 1772 case MCSymbolRefExpr::VK_PPC_HIGHA: 1773 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHA, E, Ctx); 1774 case MCSymbolRefExpr::VK_PPC_HIGHER: 1775 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, Ctx); 1776 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1777 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, Ctx); 1778 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1779 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, Ctx); 1780 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1781 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, Ctx); 1782 default: 1783 return nullptr; 1784 } 1785 } 1786