xref: /llvm-project/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (revision 024a623c5599bd11839939dfed0eeecbc389201e) 
1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCExpr.h"
11 #include "MCTargetDesc/PPCMCTargetDesc.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/MC/MCSymbolELF.h"
30 #include "llvm/Support/SourceMgr.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Support/raw_ostream.h"
33 
34 using namespace llvm;
35 
36 static const MCPhysReg RRegs[32] = {
37   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
38   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
39   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
40   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
41   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
42   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
43   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
44   PPC::R28, PPC::R29, PPC::R30, PPC::R31
45 };
46 static const MCPhysReg RRegsNoR0[32] = {
47   PPC::ZERO,
48             PPC::R1,  PPC::R2,  PPC::R3,
49   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
50   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
51   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
52   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
53   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
54   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
55   PPC::R28, PPC::R29, PPC::R30, PPC::R31
56 };
57 static const MCPhysReg XRegs[32] = {
58   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
59   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
60   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
61   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
62   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
63   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
64   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
65   PPC::X28, PPC::X29, PPC::X30, PPC::X31
66 };
67 static const MCPhysReg XRegsNoX0[32] = {
68   PPC::ZERO8,
69             PPC::X1,  PPC::X2,  PPC::X3,
70   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
71   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
72   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
73   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
74   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
75   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
76   PPC::X28, PPC::X29, PPC::X30, PPC::X31
77 };
78 static const MCPhysReg FRegs[32] = {
79   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
80   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
81   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
82   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
83   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
84   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
85   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
86   PPC::F28, PPC::F29, PPC::F30, PPC::F31
87 };
88 static const MCPhysReg VRegs[32] = {
89   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
90   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
91   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
92   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
93   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
94   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
95   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
96   PPC::V28, PPC::V29, PPC::V30, PPC::V31
97 };
98 static const MCPhysReg VSRegs[64] = {
99   PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
100   PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
101   PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
102   PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
103   PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
104   PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
105   PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
106   PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
107 
108   PPC::VSH0,  PPC::VSH1,  PPC::VSH2,  PPC::VSH3,
109   PPC::VSH4,  PPC::VSH5,  PPC::VSH6,  PPC::VSH7,
110   PPC::VSH8,  PPC::VSH9,  PPC::VSH10, PPC::VSH11,
111   PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
112   PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
113   PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
114   PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
115   PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
116 };
117 static const MCPhysReg VSFRegs[64] = {
118   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
119   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
120   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
121   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
122   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
123   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
124   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
125   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
126 
127   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
128   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
129   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
130   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
131   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
132   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
133   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
134   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
135 };
136 static const MCPhysReg VSSRegs[64] = {
137   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
138   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
139   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
140   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
141   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
142   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
143   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
144   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
145 
146   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
147   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
148   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
149   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
150   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
151   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
152   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
153   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
154 };
155 static unsigned QFRegs[32] = {
156   PPC::QF0,  PPC::QF1,  PPC::QF2,  PPC::QF3,
157   PPC::QF4,  PPC::QF5,  PPC::QF6,  PPC::QF7,
158   PPC::QF8,  PPC::QF9,  PPC::QF10, PPC::QF11,
159   PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
160   PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
161   PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
162   PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
163   PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
164 };
165 static const MCPhysReg CRBITRegs[32] = {
166   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
167   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
168   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
169   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
170   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
171   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
172   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
173   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
174 };
175 static const MCPhysReg CRRegs[8] = {
176   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
177   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
178 };
179 
180 // Evaluate an expression containing condition register
181 // or condition register field symbols.  Returns positive
182 // value on success, or -1 on error.
183 static int64_t
184 EvaluateCRExpr(const MCExpr *E) {
185   switch (E->getKind()) {
186   case MCExpr::Target:
187     return -1;
188 
189   case MCExpr::Constant: {
190     int64_t Res = cast<MCConstantExpr>(E)->getValue();
191     return Res < 0 ? -1 : Res;
192   }
193 
194   case MCExpr::SymbolRef: {
195     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
196     StringRef Name = SRE->getSymbol().getName();
197 
198     if (Name == "lt") return 0;
199     if (Name == "gt") return 1;
200     if (Name == "eq") return 2;
201     if (Name == "so") return 3;
202     if (Name == "un") return 3;
203 
204     if (Name == "cr0") return 0;
205     if (Name == "cr1") return 1;
206     if (Name == "cr2") return 2;
207     if (Name == "cr3") return 3;
208     if (Name == "cr4") return 4;
209     if (Name == "cr5") return 5;
210     if (Name == "cr6") return 6;
211     if (Name == "cr7") return 7;
212 
213     return -1;
214   }
215 
216   case MCExpr::Unary:
217     return -1;
218 
219   case MCExpr::Binary: {
220     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
221     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
222     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
223     int64_t Res;
224 
225     if (LHSVal < 0 || RHSVal < 0)
226       return -1;
227 
228     switch (BE->getOpcode()) {
229     default: return -1;
230     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
231     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
232     }
233 
234     return Res < 0 ? -1 : Res;
235   }
236   }
237 
238   llvm_unreachable("Invalid expression kind!");
239 }
240 
241 namespace {
242 
243 struct PPCOperand;
244 
245 class PPCAsmParser : public MCTargetAsmParser {
246   const MCInstrInfo &MII;
247   bool IsPPC64;
248   bool IsDarwin;
249 
250   void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
251   bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
252 
253   bool isPPC64() const { return IsPPC64; }
254   bool isDarwin() const { return IsDarwin; }
255 
256   bool MatchRegisterName(const AsmToken &Tok,
257                          unsigned &RegNo, int64_t &IntVal);
258 
259   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
260 
261   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
262                                         PPCMCExpr::VariantKind &Variant);
263   const MCExpr *FixupVariantKind(const MCExpr *E);
264   bool ParseExpression(const MCExpr *&EVal);
265   bool ParseDarwinExpression(const MCExpr *&EVal);
266 
267   bool ParseOperand(OperandVector &Operands);
268 
269   bool ParseDirectiveWord(unsigned Size, SMLoc L);
270   bool ParseDirectiveTC(unsigned Size, SMLoc L);
271   bool ParseDirectiveMachine(SMLoc L);
272   bool ParseDarwinDirectiveMachine(SMLoc L);
273   bool ParseDirectiveAbiVersion(SMLoc L);
274   bool ParseDirectiveLocalEntry(SMLoc L);
275 
276   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
277                                OperandVector &Operands, MCStreamer &Out,
278                                uint64_t &ErrorInfo,
279                                bool MatchingInlineAsm) override;
280 
281   void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
282 
283   /// @name Auto-generated Match Functions
284   /// {
285 
286 #define GET_ASSEMBLER_HEADER
287 #include "PPCGenAsmMatcher.inc"
288 
289   /// }
290 
291 
292 public:
293   PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
294                const MCInstrInfo &MII, const MCTargetOptions &Options)
295     : MCTargetAsmParser(Options, STI), MII(MII) {
296     // Check for 64-bit vs. 32-bit pointer mode.
297     Triple TheTriple(STI.getTargetTriple());
298     IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
299                TheTriple.getArch() == Triple::ppc64le);
300     IsDarwin = TheTriple.isMacOSX();
301     // Initialize the set of available features.
302     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
303   }
304 
305   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
306                         SMLoc NameLoc, OperandVector &Operands) override;
307 
308   bool ParseDirective(AsmToken DirectiveID) override;
309 
310   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
311                                       unsigned Kind) override;
312 
313   const MCExpr *applyModifierToExpr(const MCExpr *E,
314                                     MCSymbolRefExpr::VariantKind,
315                                     MCContext &Ctx) override;
316 };
317 
318 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
319 /// instruction.
320 struct PPCOperand : public MCParsedAsmOperand {
321   enum KindTy {
322     Token,
323     Immediate,
324     ContextImmediate,
325     Expression,
326     TLSRegister
327   } Kind;
328 
329   SMLoc StartLoc, EndLoc;
330   bool IsPPC64;
331 
332   struct TokOp {
333     const char *Data;
334     unsigned Length;
335   };
336 
337   struct ImmOp {
338     int64_t Val;
339   };
340 
341   struct ExprOp {
342     const MCExpr *Val;
343     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
344   };
345 
346   struct TLSRegOp {
347     const MCSymbolRefExpr *Sym;
348   };
349 
350   union {
351     struct TokOp Tok;
352     struct ImmOp Imm;
353     struct ExprOp Expr;
354     struct TLSRegOp TLSReg;
355   };
356 
357   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
358 public:
359   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
360     Kind = o.Kind;
361     StartLoc = o.StartLoc;
362     EndLoc = o.EndLoc;
363     IsPPC64 = o.IsPPC64;
364     switch (Kind) {
365     case Token:
366       Tok = o.Tok;
367       break;
368     case Immediate:
369     case ContextImmediate:
370       Imm = o.Imm;
371       break;
372     case Expression:
373       Expr = o.Expr;
374       break;
375     case TLSRegister:
376       TLSReg = o.TLSReg;
377       break;
378     }
379   }
380 
381   // Disable use of sized deallocation due to overallocation of PPCOperand
382   // objects in CreateTokenWithStringCopy.
383   void operator delete(void *p) { ::operator delete(p); }
384 
385   /// getStartLoc - Get the location of the first token of this operand.
386   SMLoc getStartLoc() const override { return StartLoc; }
387 
388   /// getEndLoc - Get the location of the last token of this operand.
389   SMLoc getEndLoc() const override { return EndLoc; }
390 
391   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
392   bool isPPC64() const { return IsPPC64; }
393 
394   int64_t getImm() const {
395     assert(Kind == Immediate && "Invalid access!");
396     return Imm.Val;
397   }
398   int64_t getImmS16Context() const {
399     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
400     if (Kind == Immediate)
401       return Imm.Val;
402     return static_cast<int16_t>(Imm.Val);
403   }
404   int64_t getImmU16Context() const {
405     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
406     return Imm.Val;
407   }
408 
409   const MCExpr *getExpr() const {
410     assert(Kind == Expression && "Invalid access!");
411     return Expr.Val;
412   }
413 
414   int64_t getExprCRVal() const {
415     assert(Kind == Expression && "Invalid access!");
416     return Expr.CRVal;
417   }
418 
419   const MCExpr *getTLSReg() const {
420     assert(Kind == TLSRegister && "Invalid access!");
421     return TLSReg.Sym;
422   }
423 
424   unsigned getReg() const override {
425     assert(isRegNumber() && "Invalid access!");
426     return (unsigned) Imm.Val;
427   }
428 
429   unsigned getVSReg() const {
430     assert(isVSRegNumber() && "Invalid access!");
431     return (unsigned) Imm.Val;
432   }
433 
434   unsigned getCCReg() const {
435     assert(isCCRegNumber() && "Invalid access!");
436     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
437   }
438 
439   unsigned getCRBit() const {
440     assert(isCRBitNumber() && "Invalid access!");
441     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
442   }
443 
444   unsigned getCRBitMask() const {
445     assert(isCRBitMask() && "Invalid access!");
446     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
447   }
448 
449   bool isToken() const override { return Kind == Token; }
450   bool isImm() const override { return Kind == Immediate || Kind == Expression; }
451   bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
452   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
453   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
454   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
455   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
456   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
457   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
458   bool isU6ImmX2() const { return Kind == Immediate &&
459                                   isUInt<6>(getImm()) &&
460                                   (getImm() & 1) == 0; }
461   bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
462   bool isU7ImmX4() const { return Kind == Immediate &&
463                                   isUInt<7>(getImm()) &&
464                                   (getImm() & 3) == 0; }
465   bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
466   bool isU8ImmX8() const { return Kind == Immediate &&
467                                   isUInt<8>(getImm()) &&
468                                   (getImm() & 7) == 0; }
469 
470   bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
471   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
472   bool isU16Imm() const {
473     switch (Kind) {
474       case Expression:
475         return true;
476       case Immediate:
477       case ContextImmediate:
478         return isUInt<16>(getImmU16Context());
479       default:
480         return false;
481     }
482   }
483   bool isS16Imm() const {
484     switch (Kind) {
485       case Expression:
486         return true;
487       case Immediate:
488       case ContextImmediate:
489         return isInt<16>(getImmS16Context());
490       default:
491         return false;
492     }
493   }
494   bool isS16ImmX4() const { return Kind == Expression ||
495                                    (Kind == Immediate && isInt<16>(getImm()) &&
496                                     (getImm() & 3) == 0); }
497   bool isS16ImmX16() const { return Kind == Expression ||
498                                     (Kind == Immediate && isInt<16>(getImm()) &&
499                                      (getImm() & 15) == 0); }
500   bool isS17Imm() const {
501     switch (Kind) {
502       case Expression:
503         return true;
504       case Immediate:
505       case ContextImmediate:
506         return isInt<17>(getImmS16Context());
507       default:
508         return false;
509     }
510   }
511   bool isTLSReg() const { return Kind == TLSRegister; }
512   bool isDirectBr() const {
513     if (Kind == Expression)
514       return true;
515     if (Kind != Immediate)
516       return false;
517     // Operand must be 64-bit aligned, signed 27-bit immediate.
518     if ((getImm() & 3) != 0)
519       return false;
520     if (isInt<26>(getImm()))
521       return true;
522     if (!IsPPC64) {
523       // In 32-bit mode, large 32-bit quantities wrap around.
524       if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
525         return true;
526     }
527     return false;
528   }
529   bool isCondBr() const { return Kind == Expression ||
530                                  (Kind == Immediate && isInt<16>(getImm()) &&
531                                   (getImm() & 3) == 0); }
532   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
533   bool isD8RCRegNumber() const { return Kind == Immediate &&
534                                         isUInt<5>(getImm()) &&
535                                         // required even register id
536                                         !(getImm() & 0x1); }
537   bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
538   bool isCCRegNumber() const { return (Kind == Expression
539                                        && isUInt<3>(getExprCRVal())) ||
540                                       (Kind == Immediate
541                                        && isUInt<3>(getImm())); }
542   bool isCRBitNumber() const { return (Kind == Expression
543                                        && isUInt<5>(getExprCRVal())) ||
544                                       (Kind == Immediate
545                                        && isUInt<5>(getImm())); }
546   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
547                                     isPowerOf2_32(getImm()); }
548   bool isMem() const override { return false; }
549   bool isReg() const override { return false; }
550 
551   void addRegOperands(MCInst &Inst, unsigned N) const {
552     llvm_unreachable("addRegOperands");
553   }
554 
555   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
556     assert(N == 1 && "Invalid number of operands!");
557     Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
558   }
559 
560   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
561     assert(N == 1 && "Invalid number of operands!");
562     Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
563   }
564 
565   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
566     assert(N == 1 && "Invalid number of operands!");
567     Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
568   }
569 
570   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
571     assert(N == 1 && "Invalid number of operands!");
572     Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
573   }
574 
575   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
576     if (isPPC64())
577       addRegG8RCOperands(Inst, N);
578     else
579       addRegGPRCOperands(Inst, N);
580   }
581 
582   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
583     if (isPPC64())
584       addRegG8RCNoX0Operands(Inst, N);
585     else
586       addRegGPRCNoR0Operands(Inst, N);
587   }
588 
589   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
590     assert(N == 1 && "Invalid number of operands!");
591     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
592   }
593 
594   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
595     assert(N == 1 && "Invalid number of operands!");
596     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
597   }
598 
599   void addRegD8RCOperands(MCInst &Inst, unsigned N) const {
600     assert(N == 1 && "Invalid number of operands!");
601     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
602   }
603 
604   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
605     assert(N == 1 && "Invalid number of operands!");
606     Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
607   }
608 
609   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
610     assert(N == 1 && "Invalid number of operands!");
611     Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
612   }
613 
614   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
615     assert(N == 1 && "Invalid number of operands!");
616     Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
617   }
618 
619   void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
620     assert(N == 1 && "Invalid number of operands!");
621     Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
622   }
623 
624   void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
625     assert(N == 1 && "Invalid number of operands!");
626     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
627   }
628 
629   void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
630     assert(N == 1 && "Invalid number of operands!");
631     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
632   }
633 
634   void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
635     assert(N == 1 && "Invalid number of operands!");
636     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
637   }
638 
639   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
640     assert(N == 1 && "Invalid number of operands!");
641     Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
642   }
643 
644   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
645     assert(N == 1 && "Invalid number of operands!");
646     Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
647   }
648 
649   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
650     assert(N == 1 && "Invalid number of operands!");
651     Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
652   }
653 
654   void addImmOperands(MCInst &Inst, unsigned N) const {
655     assert(N == 1 && "Invalid number of operands!");
656     if (Kind == Immediate)
657       Inst.addOperand(MCOperand::createImm(getImm()));
658     else
659       Inst.addOperand(MCOperand::createExpr(getExpr()));
660   }
661 
662   void addS16ImmOperands(MCInst &Inst, unsigned N) const {
663     assert(N == 1 && "Invalid number of operands!");
664     switch (Kind) {
665       case Immediate:
666         Inst.addOperand(MCOperand::createImm(getImm()));
667         break;
668       case ContextImmediate:
669         Inst.addOperand(MCOperand::createImm(getImmS16Context()));
670         break;
671       default:
672         Inst.addOperand(MCOperand::createExpr(getExpr()));
673         break;
674     }
675   }
676 
677   void addU16ImmOperands(MCInst &Inst, unsigned N) const {
678     assert(N == 1 && "Invalid number of operands!");
679     switch (Kind) {
680       case Immediate:
681         Inst.addOperand(MCOperand::createImm(getImm()));
682         break;
683       case ContextImmediate:
684         Inst.addOperand(MCOperand::createImm(getImmU16Context()));
685         break;
686       default:
687         Inst.addOperand(MCOperand::createExpr(getExpr()));
688         break;
689     }
690   }
691 
692   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
693     assert(N == 1 && "Invalid number of operands!");
694     if (Kind == Immediate)
695       Inst.addOperand(MCOperand::createImm(getImm() / 4));
696     else
697       Inst.addOperand(MCOperand::createExpr(getExpr()));
698   }
699 
700   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
701     assert(N == 1 && "Invalid number of operands!");
702     Inst.addOperand(MCOperand::createExpr(getTLSReg()));
703   }
704 
705   StringRef getToken() const {
706     assert(Kind == Token && "Invalid access!");
707     return StringRef(Tok.Data, Tok.Length);
708   }
709 
710   void print(raw_ostream &OS) const override;
711 
712   static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
713                                                  bool IsPPC64) {
714     auto Op = make_unique<PPCOperand>(Token);
715     Op->Tok.Data = Str.data();
716     Op->Tok.Length = Str.size();
717     Op->StartLoc = S;
718     Op->EndLoc = S;
719     Op->IsPPC64 = IsPPC64;
720     return Op;
721   }
722 
723   static std::unique_ptr<PPCOperand>
724   CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
725     // Allocate extra memory for the string and copy it.
726     // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
727     // deleter which will destroy them by simply using "delete", not correctly
728     // calling operator delete on this extra memory after calling the dtor
729     // explicitly.
730     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
731     std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
732     Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
733     Op->Tok.Length = Str.size();
734     std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
735     Op->StartLoc = S;
736     Op->EndLoc = S;
737     Op->IsPPC64 = IsPPC64;
738     return Op;
739   }
740 
741   static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
742                                                bool IsPPC64) {
743     auto Op = make_unique<PPCOperand>(Immediate);
744     Op->Imm.Val = Val;
745     Op->StartLoc = S;
746     Op->EndLoc = E;
747     Op->IsPPC64 = IsPPC64;
748     return Op;
749   }
750 
751   static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
752                                                 SMLoc E, bool IsPPC64) {
753     auto Op = make_unique<PPCOperand>(Expression);
754     Op->Expr.Val = Val;
755     Op->Expr.CRVal = EvaluateCRExpr(Val);
756     Op->StartLoc = S;
757     Op->EndLoc = E;
758     Op->IsPPC64 = IsPPC64;
759     return Op;
760   }
761 
762   static std::unique_ptr<PPCOperand>
763   CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
764     auto Op = make_unique<PPCOperand>(TLSRegister);
765     Op->TLSReg.Sym = Sym;
766     Op->StartLoc = S;
767     Op->EndLoc = E;
768     Op->IsPPC64 = IsPPC64;
769     return Op;
770   }
771 
772   static std::unique_ptr<PPCOperand>
773   CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
774     auto Op = make_unique<PPCOperand>(ContextImmediate);
775     Op->Imm.Val = Val;
776     Op->StartLoc = S;
777     Op->EndLoc = E;
778     Op->IsPPC64 = IsPPC64;
779     return Op;
780   }
781 
782   static std::unique_ptr<PPCOperand>
783   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
784     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
785       return CreateImm(CE->getValue(), S, E, IsPPC64);
786 
787     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
788       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
789         return CreateTLSReg(SRE, S, E, IsPPC64);
790 
791     if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
792       int64_t Res;
793       if (TE->evaluateAsConstant(Res))
794         return CreateContextImm(Res, S, E, IsPPC64);
795     }
796 
797     return CreateExpr(Val, S, E, IsPPC64);
798   }
799 };
800 
801 } // end anonymous namespace.
802 
803 void PPCOperand::print(raw_ostream &OS) const {
804   switch (Kind) {
805   case Token:
806     OS << "'" << getToken() << "'";
807     break;
808   case Immediate:
809   case ContextImmediate:
810     OS << getImm();
811     break;
812   case Expression:
813     OS << *getExpr();
814     break;
815   case TLSRegister:
816     OS << *getTLSReg();
817     break;
818   }
819 }
820 
821 static void
822 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
823   if (Op.isImm()) {
824     Inst.addOperand(MCOperand::createImm(-Op.getImm()));
825     return;
826   }
827   const MCExpr *Expr = Op.getExpr();
828   if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
829     if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
830       Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
831       return;
832     }
833   } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
834     if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
835       const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
836                                                  BinExpr->getLHS(), Ctx);
837       Inst.addOperand(MCOperand::createExpr(NE));
838       return;
839     }
840   }
841   Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx)));
842 }
843 
844 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
845                                       const OperandVector &Operands) {
846   int Opcode = Inst.getOpcode();
847   switch (Opcode) {
848   case PPC::DCBTx:
849   case PPC::DCBTT:
850   case PPC::DCBTSTx:
851   case PPC::DCBTSTT: {
852     MCInst TmpInst;
853     TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
854                       PPC::DCBT : PPC::DCBTST);
855     TmpInst.addOperand(MCOperand::createImm(
856       (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
857     TmpInst.addOperand(Inst.getOperand(0));
858     TmpInst.addOperand(Inst.getOperand(1));
859     Inst = TmpInst;
860     break;
861   }
862   case PPC::DCBTCT:
863   case PPC::DCBTDS: {
864     MCInst TmpInst;
865     TmpInst.setOpcode(PPC::DCBT);
866     TmpInst.addOperand(Inst.getOperand(2));
867     TmpInst.addOperand(Inst.getOperand(0));
868     TmpInst.addOperand(Inst.getOperand(1));
869     Inst = TmpInst;
870     break;
871   }
872   case PPC::DCBTSTCT:
873   case PPC::DCBTSTDS: {
874     MCInst TmpInst;
875     TmpInst.setOpcode(PPC::DCBTST);
876     TmpInst.addOperand(Inst.getOperand(2));
877     TmpInst.addOperand(Inst.getOperand(0));
878     TmpInst.addOperand(Inst.getOperand(1));
879     Inst = TmpInst;
880     break;
881   }
882   case PPC::LAx: {
883     MCInst TmpInst;
884     TmpInst.setOpcode(PPC::LA);
885     TmpInst.addOperand(Inst.getOperand(0));
886     TmpInst.addOperand(Inst.getOperand(2));
887     TmpInst.addOperand(Inst.getOperand(1));
888     Inst = TmpInst;
889     break;
890   }
891   case PPC::SUBI: {
892     MCInst TmpInst;
893     TmpInst.setOpcode(PPC::ADDI);
894     TmpInst.addOperand(Inst.getOperand(0));
895     TmpInst.addOperand(Inst.getOperand(1));
896     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
897     Inst = TmpInst;
898     break;
899   }
900   case PPC::SUBIS: {
901     MCInst TmpInst;
902     TmpInst.setOpcode(PPC::ADDIS);
903     TmpInst.addOperand(Inst.getOperand(0));
904     TmpInst.addOperand(Inst.getOperand(1));
905     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
906     Inst = TmpInst;
907     break;
908   }
909   case PPC::SUBIC: {
910     MCInst TmpInst;
911     TmpInst.setOpcode(PPC::ADDIC);
912     TmpInst.addOperand(Inst.getOperand(0));
913     TmpInst.addOperand(Inst.getOperand(1));
914     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
915     Inst = TmpInst;
916     break;
917   }
918   case PPC::SUBICo: {
919     MCInst TmpInst;
920     TmpInst.setOpcode(PPC::ADDICo);
921     TmpInst.addOperand(Inst.getOperand(0));
922     TmpInst.addOperand(Inst.getOperand(1));
923     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
924     Inst = TmpInst;
925     break;
926   }
927   case PPC::EXTLWI:
928   case PPC::EXTLWIo: {
929     MCInst TmpInst;
930     int64_t N = Inst.getOperand(2).getImm();
931     int64_t B = Inst.getOperand(3).getImm();
932     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
933     TmpInst.addOperand(Inst.getOperand(0));
934     TmpInst.addOperand(Inst.getOperand(1));
935     TmpInst.addOperand(MCOperand::createImm(B));
936     TmpInst.addOperand(MCOperand::createImm(0));
937     TmpInst.addOperand(MCOperand::createImm(N - 1));
938     Inst = TmpInst;
939     break;
940   }
941   case PPC::EXTRWI:
942   case PPC::EXTRWIo: {
943     MCInst TmpInst;
944     int64_t N = Inst.getOperand(2).getImm();
945     int64_t B = Inst.getOperand(3).getImm();
946     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
947     TmpInst.addOperand(Inst.getOperand(0));
948     TmpInst.addOperand(Inst.getOperand(1));
949     TmpInst.addOperand(MCOperand::createImm(B + N));
950     TmpInst.addOperand(MCOperand::createImm(32 - N));
951     TmpInst.addOperand(MCOperand::createImm(31));
952     Inst = TmpInst;
953     break;
954   }
955   case PPC::INSLWI:
956   case PPC::INSLWIo: {
957     MCInst TmpInst;
958     int64_t N = Inst.getOperand(2).getImm();
959     int64_t B = Inst.getOperand(3).getImm();
960     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
961     TmpInst.addOperand(Inst.getOperand(0));
962     TmpInst.addOperand(Inst.getOperand(0));
963     TmpInst.addOperand(Inst.getOperand(1));
964     TmpInst.addOperand(MCOperand::createImm(32 - B));
965     TmpInst.addOperand(MCOperand::createImm(B));
966     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
967     Inst = TmpInst;
968     break;
969   }
970   case PPC::INSRWI:
971   case PPC::INSRWIo: {
972     MCInst TmpInst;
973     int64_t N = Inst.getOperand(2).getImm();
974     int64_t B = Inst.getOperand(3).getImm();
975     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
976     TmpInst.addOperand(Inst.getOperand(0));
977     TmpInst.addOperand(Inst.getOperand(0));
978     TmpInst.addOperand(Inst.getOperand(1));
979     TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
980     TmpInst.addOperand(MCOperand::createImm(B));
981     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
982     Inst = TmpInst;
983     break;
984   }
985   case PPC::ROTRWI:
986   case PPC::ROTRWIo: {
987     MCInst TmpInst;
988     int64_t N = Inst.getOperand(2).getImm();
989     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
990     TmpInst.addOperand(Inst.getOperand(0));
991     TmpInst.addOperand(Inst.getOperand(1));
992     TmpInst.addOperand(MCOperand::createImm(32 - N));
993     TmpInst.addOperand(MCOperand::createImm(0));
994     TmpInst.addOperand(MCOperand::createImm(31));
995     Inst = TmpInst;
996     break;
997   }
998   case PPC::SLWI:
999   case PPC::SLWIo: {
1000     MCInst TmpInst;
1001     int64_t N = Inst.getOperand(2).getImm();
1002     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
1003     TmpInst.addOperand(Inst.getOperand(0));
1004     TmpInst.addOperand(Inst.getOperand(1));
1005     TmpInst.addOperand(MCOperand::createImm(N));
1006     TmpInst.addOperand(MCOperand::createImm(0));
1007     TmpInst.addOperand(MCOperand::createImm(31 - N));
1008     Inst = TmpInst;
1009     break;
1010   }
1011   case PPC::SRWI:
1012   case PPC::SRWIo: {
1013     MCInst TmpInst;
1014     int64_t N = Inst.getOperand(2).getImm();
1015     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
1016     TmpInst.addOperand(Inst.getOperand(0));
1017     TmpInst.addOperand(Inst.getOperand(1));
1018     TmpInst.addOperand(MCOperand::createImm(32 - N));
1019     TmpInst.addOperand(MCOperand::createImm(N));
1020     TmpInst.addOperand(MCOperand::createImm(31));
1021     Inst = TmpInst;
1022     break;
1023   }
1024   case PPC::CLRRWI:
1025   case PPC::CLRRWIo: {
1026     MCInst TmpInst;
1027     int64_t N = Inst.getOperand(2).getImm();
1028     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
1029     TmpInst.addOperand(Inst.getOperand(0));
1030     TmpInst.addOperand(Inst.getOperand(1));
1031     TmpInst.addOperand(MCOperand::createImm(0));
1032     TmpInst.addOperand(MCOperand::createImm(0));
1033     TmpInst.addOperand(MCOperand::createImm(31 - N));
1034     Inst = TmpInst;
1035     break;
1036   }
1037   case PPC::CLRLSLWI:
1038   case PPC::CLRLSLWIo: {
1039     MCInst TmpInst;
1040     int64_t B = Inst.getOperand(2).getImm();
1041     int64_t N = Inst.getOperand(3).getImm();
1042     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
1043     TmpInst.addOperand(Inst.getOperand(0));
1044     TmpInst.addOperand(Inst.getOperand(1));
1045     TmpInst.addOperand(MCOperand::createImm(N));
1046     TmpInst.addOperand(MCOperand::createImm(B - N));
1047     TmpInst.addOperand(MCOperand::createImm(31 - N));
1048     Inst = TmpInst;
1049     break;
1050   }
1051   case PPC::EXTLDI:
1052   case PPC::EXTLDIo: {
1053     MCInst TmpInst;
1054     int64_t N = Inst.getOperand(2).getImm();
1055     int64_t B = Inst.getOperand(3).getImm();
1056     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1057     TmpInst.addOperand(Inst.getOperand(0));
1058     TmpInst.addOperand(Inst.getOperand(1));
1059     TmpInst.addOperand(MCOperand::createImm(B));
1060     TmpInst.addOperand(MCOperand::createImm(N - 1));
1061     Inst = TmpInst;
1062     break;
1063   }
1064   case PPC::EXTRDI:
1065   case PPC::EXTRDIo: {
1066     MCInst TmpInst;
1067     int64_t N = Inst.getOperand(2).getImm();
1068     int64_t B = Inst.getOperand(3).getImm();
1069     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1070     TmpInst.addOperand(Inst.getOperand(0));
1071     TmpInst.addOperand(Inst.getOperand(1));
1072     TmpInst.addOperand(MCOperand::createImm(B + N));
1073     TmpInst.addOperand(MCOperand::createImm(64 - N));
1074     Inst = TmpInst;
1075     break;
1076   }
1077   case PPC::INSRDI:
1078   case PPC::INSRDIo: {
1079     MCInst TmpInst;
1080     int64_t N = Inst.getOperand(2).getImm();
1081     int64_t B = Inst.getOperand(3).getImm();
1082     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1083     TmpInst.addOperand(Inst.getOperand(0));
1084     TmpInst.addOperand(Inst.getOperand(0));
1085     TmpInst.addOperand(Inst.getOperand(1));
1086     TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
1087     TmpInst.addOperand(MCOperand::createImm(B));
1088     Inst = TmpInst;
1089     break;
1090   }
1091   case PPC::ROTRDI:
1092   case PPC::ROTRDIo: {
1093     MCInst TmpInst;
1094     int64_t N = Inst.getOperand(2).getImm();
1095     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1096     TmpInst.addOperand(Inst.getOperand(0));
1097     TmpInst.addOperand(Inst.getOperand(1));
1098     TmpInst.addOperand(MCOperand::createImm(64 - N));
1099     TmpInst.addOperand(MCOperand::createImm(0));
1100     Inst = TmpInst;
1101     break;
1102   }
1103   case PPC::SLDI:
1104   case PPC::SLDIo: {
1105     MCInst TmpInst;
1106     int64_t N = Inst.getOperand(2).getImm();
1107     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1108     TmpInst.addOperand(Inst.getOperand(0));
1109     TmpInst.addOperand(Inst.getOperand(1));
1110     TmpInst.addOperand(MCOperand::createImm(N));
1111     TmpInst.addOperand(MCOperand::createImm(63 - N));
1112     Inst = TmpInst;
1113     break;
1114   }
1115   case PPC::SRDI:
1116   case PPC::SRDIo: {
1117     MCInst TmpInst;
1118     int64_t N = Inst.getOperand(2).getImm();
1119     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1120     TmpInst.addOperand(Inst.getOperand(0));
1121     TmpInst.addOperand(Inst.getOperand(1));
1122     TmpInst.addOperand(MCOperand::createImm(64 - N));
1123     TmpInst.addOperand(MCOperand::createImm(N));
1124     Inst = TmpInst;
1125     break;
1126   }
1127   case PPC::CLRRDI:
1128   case PPC::CLRRDIo: {
1129     MCInst TmpInst;
1130     int64_t N = Inst.getOperand(2).getImm();
1131     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1132     TmpInst.addOperand(Inst.getOperand(0));
1133     TmpInst.addOperand(Inst.getOperand(1));
1134     TmpInst.addOperand(MCOperand::createImm(0));
1135     TmpInst.addOperand(MCOperand::createImm(63 - N));
1136     Inst = TmpInst;
1137     break;
1138   }
1139   case PPC::CLRLSLDI:
1140   case PPC::CLRLSLDIo: {
1141     MCInst TmpInst;
1142     int64_t B = Inst.getOperand(2).getImm();
1143     int64_t N = Inst.getOperand(3).getImm();
1144     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1145     TmpInst.addOperand(Inst.getOperand(0));
1146     TmpInst.addOperand(Inst.getOperand(1));
1147     TmpInst.addOperand(MCOperand::createImm(N));
1148     TmpInst.addOperand(MCOperand::createImm(B - N));
1149     Inst = TmpInst;
1150     break;
1151   }
1152   case PPC::RLWINMbm:
1153   case PPC::RLWINMobm: {
1154     unsigned MB, ME;
1155     int64_t BM = Inst.getOperand(3).getImm();
1156     if (!isRunOfOnes(BM, MB, ME))
1157       break;
1158 
1159     MCInst TmpInst;
1160     TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1161     TmpInst.addOperand(Inst.getOperand(0));
1162     TmpInst.addOperand(Inst.getOperand(1));
1163     TmpInst.addOperand(Inst.getOperand(2));
1164     TmpInst.addOperand(MCOperand::createImm(MB));
1165     TmpInst.addOperand(MCOperand::createImm(ME));
1166     Inst = TmpInst;
1167     break;
1168   }
1169   case PPC::RLWIMIbm:
1170   case PPC::RLWIMIobm: {
1171     unsigned MB, ME;
1172     int64_t BM = Inst.getOperand(3).getImm();
1173     if (!isRunOfOnes(BM, MB, ME))
1174       break;
1175 
1176     MCInst TmpInst;
1177     TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1178     TmpInst.addOperand(Inst.getOperand(0));
1179     TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1180     TmpInst.addOperand(Inst.getOperand(1));
1181     TmpInst.addOperand(Inst.getOperand(2));
1182     TmpInst.addOperand(MCOperand::createImm(MB));
1183     TmpInst.addOperand(MCOperand::createImm(ME));
1184     Inst = TmpInst;
1185     break;
1186   }
1187   case PPC::RLWNMbm:
1188   case PPC::RLWNMobm: {
1189     unsigned MB, ME;
1190     int64_t BM = Inst.getOperand(3).getImm();
1191     if (!isRunOfOnes(BM, MB, ME))
1192       break;
1193 
1194     MCInst TmpInst;
1195     TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1196     TmpInst.addOperand(Inst.getOperand(0));
1197     TmpInst.addOperand(Inst.getOperand(1));
1198     TmpInst.addOperand(Inst.getOperand(2));
1199     TmpInst.addOperand(MCOperand::createImm(MB));
1200     TmpInst.addOperand(MCOperand::createImm(ME));
1201     Inst = TmpInst;
1202     break;
1203   }
1204   case PPC::MFTB: {
1205     if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1206       assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1207       Inst.setOpcode(PPC::MFSPR);
1208     }
1209     break;
1210   }
1211   case PPC::CP_COPYx:
1212   case PPC::CP_COPY_FIRST: {
1213     MCInst TmpInst;
1214     TmpInst.setOpcode(PPC::CP_COPY);
1215     TmpInst.addOperand(Inst.getOperand(0));
1216     TmpInst.addOperand(Inst.getOperand(1));
1217     TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1));
1218 
1219     Inst = TmpInst;
1220     break;
1221   }
1222   case PPC::CP_PASTEx :
1223   case PPC::CP_PASTE_LAST: {
1224     MCInst TmpInst;
1225     TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ?
1226                       PPC::CP_PASTE : PPC::CP_PASTEo);
1227     TmpInst.addOperand(Inst.getOperand(0));
1228     TmpInst.addOperand(Inst.getOperand(1));
1229     TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1));
1230 
1231     Inst = TmpInst;
1232     break;
1233   }
1234   // ISA3.0 Instructions:
1235   case PPC::SUBPCIS:
1236   case PPC::LNIA: {
1237     MCInst TmpInst;
1238     TmpInst.setOpcode(PPC::ADDPCIS);
1239     TmpInst.addOperand(Inst.getOperand(0));
1240     if (Opcode == PPC::SUBPCIS)
1241       addNegOperand(TmpInst, Inst.getOperand(1), getContext());
1242     else
1243       TmpInst.addOperand(MCOperand::createImm(0));
1244     Inst = TmpInst;
1245     break;
1246   }
1247   }
1248 }
1249 
1250 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1251                                            OperandVector &Operands,
1252                                            MCStreamer &Out, uint64_t &ErrorInfo,
1253                                            bool MatchingInlineAsm) {
1254   MCInst Inst;
1255 
1256   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1257   case Match_Success:
1258     // Post-process instructions (typically extended mnemonics)
1259     ProcessInstruction(Inst, Operands);
1260     Inst.setLoc(IDLoc);
1261     Out.EmitInstruction(Inst, getSTI());
1262     return false;
1263   case Match_MissingFeature:
1264     return Error(IDLoc, "instruction use requires an option to be enabled");
1265   case Match_MnemonicFail:
1266     return Error(IDLoc, "unrecognized instruction mnemonic");
1267   case Match_InvalidOperand: {
1268     SMLoc ErrorLoc = IDLoc;
1269     if (ErrorInfo != ~0ULL) {
1270       if (ErrorInfo >= Operands.size())
1271         return Error(IDLoc, "too few operands for instruction");
1272 
1273       ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1274       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1275     }
1276 
1277     return Error(ErrorLoc, "invalid operand for instruction");
1278   }
1279   }
1280 
1281   llvm_unreachable("Implement any new match types added!");
1282 }
1283 
1284 bool PPCAsmParser::
1285 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1286   if (Tok.is(AsmToken::Identifier)) {
1287     StringRef Name = Tok.getString();
1288 
1289     if (Name.equals_lower("lr")) {
1290       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1291       IntVal = 8;
1292       return false;
1293     } else if (Name.equals_lower("ctr")) {
1294       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1295       IntVal = 9;
1296       return false;
1297     } else if (Name.equals_lower("vrsave")) {
1298       RegNo = PPC::VRSAVE;
1299       IntVal = 256;
1300       return false;
1301     } else if (Name.startswith_lower("r") &&
1302                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1303       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1304       return false;
1305     } else if (Name.startswith_lower("f") &&
1306                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1307       RegNo = FRegs[IntVal];
1308       return false;
1309     } else if (Name.startswith_lower("vs") &&
1310                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1311       RegNo = VSRegs[IntVal];
1312       return false;
1313     } else if (Name.startswith_lower("v") &&
1314                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1315       RegNo = VRegs[IntVal];
1316       return false;
1317     } else if (Name.startswith_lower("q") &&
1318                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1319       RegNo = QFRegs[IntVal];
1320       return false;
1321     } else if (Name.startswith_lower("cr") &&
1322                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1323       RegNo = CRRegs[IntVal];
1324       return false;
1325     }
1326   }
1327 
1328   return true;
1329 }
1330 
1331 bool PPCAsmParser::
1332 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1333   MCAsmParser &Parser = getParser();
1334   const AsmToken &Tok = Parser.getTok();
1335   StartLoc = Tok.getLoc();
1336   EndLoc = Tok.getEndLoc();
1337   RegNo = 0;
1338   int64_t IntVal;
1339 
1340   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1341     Parser.Lex(); // Eat identifier token.
1342     return false;
1343   }
1344 
1345   return Error(StartLoc, "invalid register name");
1346 }
1347 
1348 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1349 /// the expression and check for VK_PPC_LO/HI/HA
1350 /// symbol variants.  If all symbols with modifier use the same
1351 /// variant, return the corresponding PPCMCExpr::VariantKind,
1352 /// and a modified expression using the default symbol variant.
1353 /// Otherwise, return NULL.
1354 const MCExpr *PPCAsmParser::
1355 ExtractModifierFromExpr(const MCExpr *E,
1356                         PPCMCExpr::VariantKind &Variant) {
1357   MCContext &Context = getParser().getContext();
1358   Variant = PPCMCExpr::VK_PPC_None;
1359 
1360   switch (E->getKind()) {
1361   case MCExpr::Target:
1362   case MCExpr::Constant:
1363     return nullptr;
1364 
1365   case MCExpr::SymbolRef: {
1366     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1367 
1368     switch (SRE->getKind()) {
1369     case MCSymbolRefExpr::VK_PPC_LO:
1370       Variant = PPCMCExpr::VK_PPC_LO;
1371       break;
1372     case MCSymbolRefExpr::VK_PPC_HI:
1373       Variant = PPCMCExpr::VK_PPC_HI;
1374       break;
1375     case MCSymbolRefExpr::VK_PPC_HA:
1376       Variant = PPCMCExpr::VK_PPC_HA;
1377       break;
1378     case MCSymbolRefExpr::VK_PPC_HIGHER:
1379       Variant = PPCMCExpr::VK_PPC_HIGHER;
1380       break;
1381     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1382       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1383       break;
1384     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1385       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1386       break;
1387     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1388       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1389       break;
1390     default:
1391       return nullptr;
1392     }
1393 
1394     return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1395   }
1396 
1397   case MCExpr::Unary: {
1398     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1399     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1400     if (!Sub)
1401       return nullptr;
1402     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1403   }
1404 
1405   case MCExpr::Binary: {
1406     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1407     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1408     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1409     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1410 
1411     if (!LHS && !RHS)
1412       return nullptr;
1413 
1414     if (!LHS) LHS = BE->getLHS();
1415     if (!RHS) RHS = BE->getRHS();
1416 
1417     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1418       Variant = RHSVariant;
1419     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1420       Variant = LHSVariant;
1421     else if (LHSVariant == RHSVariant)
1422       Variant = LHSVariant;
1423     else
1424       return nullptr;
1425 
1426     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1427   }
1428   }
1429 
1430   llvm_unreachable("Invalid expression kind!");
1431 }
1432 
1433 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1434 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1435 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1436 /// FIXME: This is a hack.
1437 const MCExpr *PPCAsmParser::
1438 FixupVariantKind(const MCExpr *E) {
1439   MCContext &Context = getParser().getContext();
1440 
1441   switch (E->getKind()) {
1442   case MCExpr::Target:
1443   case MCExpr::Constant:
1444     return E;
1445 
1446   case MCExpr::SymbolRef: {
1447     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1448     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1449 
1450     switch (SRE->getKind()) {
1451     case MCSymbolRefExpr::VK_TLSGD:
1452       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1453       break;
1454     case MCSymbolRefExpr::VK_TLSLD:
1455       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1456       break;
1457     default:
1458       return E;
1459     }
1460     return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1461   }
1462 
1463   case MCExpr::Unary: {
1464     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1465     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1466     if (Sub == UE->getSubExpr())
1467       return E;
1468     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1469   }
1470 
1471   case MCExpr::Binary: {
1472     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1473     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1474     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1475     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1476       return E;
1477     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1478   }
1479   }
1480 
1481   llvm_unreachable("Invalid expression kind!");
1482 }
1483 
1484 /// ParseExpression.  This differs from the default "parseExpression" in that
1485 /// it handles modifiers.
1486 bool PPCAsmParser::
1487 ParseExpression(const MCExpr *&EVal) {
1488 
1489   if (isDarwin())
1490     return ParseDarwinExpression(EVal);
1491 
1492   // (ELF Platforms)
1493   // Handle \code @l/@ha \endcode
1494   if (getParser().parseExpression(EVal))
1495     return true;
1496 
1497   EVal = FixupVariantKind(EVal);
1498 
1499   PPCMCExpr::VariantKind Variant;
1500   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1501   if (E)
1502     EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext());
1503 
1504   return false;
1505 }
1506 
1507 /// ParseDarwinExpression.  (MachO Platforms)
1508 /// This differs from the default "parseExpression" in that it handles detection
1509 /// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1510 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1511 /// syntax form so it is done here.  TODO: Determine if there is merit in arranging
1512 /// for this to be done at a higher level.
1513 bool PPCAsmParser::
1514 ParseDarwinExpression(const MCExpr *&EVal) {
1515   MCAsmParser &Parser = getParser();
1516   PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1517   switch (getLexer().getKind()) {
1518   default:
1519     break;
1520   case AsmToken::Identifier:
1521     // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1522     // something starting with any other char should be part of the
1523     // asm syntax.  If handwritten asm includes an identifier like lo16,
1524     // then all bets are off - but no-one would do that, right?
1525     StringRef poss = Parser.getTok().getString();
1526     if (poss.equals_lower("lo16")) {
1527       Variant = PPCMCExpr::VK_PPC_LO;
1528     } else if (poss.equals_lower("hi16")) {
1529       Variant = PPCMCExpr::VK_PPC_HI;
1530     } else if (poss.equals_lower("ha16")) {
1531       Variant = PPCMCExpr::VK_PPC_HA;
1532     }
1533     if (Variant != PPCMCExpr::VK_PPC_None) {
1534       Parser.Lex(); // Eat the xx16
1535       if (getLexer().isNot(AsmToken::LParen))
1536         return Error(Parser.getTok().getLoc(), "expected '('");
1537       Parser.Lex(); // Eat the '('
1538     }
1539     break;
1540   }
1541 
1542   if (getParser().parseExpression(EVal))
1543     return true;
1544 
1545   if (Variant != PPCMCExpr::VK_PPC_None) {
1546     if (getLexer().isNot(AsmToken::RParen))
1547       return Error(Parser.getTok().getLoc(), "expected ')'");
1548     Parser.Lex(); // Eat the ')'
1549     EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext());
1550   }
1551   return false;
1552 }
1553 
1554 /// ParseOperand
1555 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1556 /// rNN for MachO.
1557 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1558   MCAsmParser &Parser = getParser();
1559   SMLoc S = Parser.getTok().getLoc();
1560   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1561   const MCExpr *EVal;
1562 
1563   // Attempt to parse the next token as an immediate
1564   switch (getLexer().getKind()) {
1565   // Special handling for register names.  These are interpreted
1566   // as immediates corresponding to the register number.
1567   case AsmToken::Percent:
1568     Parser.Lex(); // Eat the '%'.
1569     unsigned RegNo;
1570     int64_t IntVal;
1571     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1572       Parser.Lex(); // Eat the identifier token.
1573       Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1574       return false;
1575     }
1576     return Error(S, "invalid register name");
1577 
1578   case AsmToken::Identifier:
1579     // Note that non-register-name identifiers from the compiler will begin
1580     // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1581     // identifiers like r31foo - so we fall through in the event that parsing
1582     // a register name fails.
1583     if (isDarwin()) {
1584       unsigned RegNo;
1585       int64_t IntVal;
1586       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1587         Parser.Lex(); // Eat the identifier token.
1588         Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1589         return false;
1590       }
1591     }
1592   // Fall-through to process non-register-name identifiers as expression.
1593   // All other expressions
1594   case AsmToken::LParen:
1595   case AsmToken::Plus:
1596   case AsmToken::Minus:
1597   case AsmToken::Integer:
1598   case AsmToken::Dot:
1599   case AsmToken::Dollar:
1600   case AsmToken::Exclaim:
1601   case AsmToken::Tilde:
1602     if (!ParseExpression(EVal))
1603       break;
1604     /* fall through */
1605   default:
1606     return Error(S, "unknown operand");
1607   }
1608 
1609   // Push the parsed operand into the list of operands
1610   Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1611 
1612   // Check whether this is a TLS call expression
1613   bool TLSCall = false;
1614   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1615     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1616 
1617   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1618     const MCExpr *TLSSym;
1619 
1620     Parser.Lex(); // Eat the '('.
1621     S = Parser.getTok().getLoc();
1622     if (ParseExpression(TLSSym))
1623       return Error(S, "invalid TLS call expression");
1624     if (getLexer().isNot(AsmToken::RParen))
1625       return Error(Parser.getTok().getLoc(), "missing ')'");
1626     E = Parser.getTok().getLoc();
1627     Parser.Lex(); // Eat the ')'.
1628 
1629     Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1630   }
1631 
1632   // Otherwise, check for D-form memory operands
1633   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1634     Parser.Lex(); // Eat the '('.
1635     S = Parser.getTok().getLoc();
1636 
1637     int64_t IntVal;
1638     switch (getLexer().getKind()) {
1639     case AsmToken::Percent:
1640       Parser.Lex(); // Eat the '%'.
1641       unsigned RegNo;
1642       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1643         return Error(S, "invalid register name");
1644       Parser.Lex(); // Eat the identifier token.
1645       break;
1646 
1647     case AsmToken::Integer:
1648       if (!isDarwin()) {
1649         if (getParser().parseAbsoluteExpression(IntVal) ||
1650           IntVal < 0 || IntVal > 31)
1651         return Error(S, "invalid register number");
1652       } else {
1653         return Error(S, "unexpected integer value");
1654       }
1655       break;
1656 
1657    case AsmToken::Identifier:
1658     if (isDarwin()) {
1659       unsigned RegNo;
1660       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1661         Parser.Lex(); // Eat the identifier token.
1662         break;
1663       }
1664     }
1665     // Fall-through..
1666 
1667     default:
1668       return Error(S, "invalid memory operand");
1669     }
1670 
1671     if (getLexer().isNot(AsmToken::RParen))
1672       return Error(Parser.getTok().getLoc(), "missing ')'");
1673     E = Parser.getTok().getLoc();
1674     Parser.Lex(); // Eat the ')'.
1675 
1676     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1677   }
1678 
1679   return false;
1680 }
1681 
1682 /// Parse an instruction mnemonic followed by its operands.
1683 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1684                                     SMLoc NameLoc, OperandVector &Operands) {
1685   // The first operand is the token for the instruction name.
1686   // If the next character is a '+' or '-', we need to add it to the
1687   // instruction name, to match what TableGen is doing.
1688   std::string NewOpcode;
1689   if (getLexer().is(AsmToken::Plus)) {
1690     getLexer().Lex();
1691     NewOpcode = Name;
1692     NewOpcode += '+';
1693     Name = NewOpcode;
1694   }
1695   if (getLexer().is(AsmToken::Minus)) {
1696     getLexer().Lex();
1697     NewOpcode = Name;
1698     NewOpcode += '-';
1699     Name = NewOpcode;
1700   }
1701   // If the instruction ends in a '.', we need to create a separate
1702   // token for it, to match what TableGen is doing.
1703   size_t Dot = Name.find('.');
1704   StringRef Mnemonic = Name.slice(0, Dot);
1705   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1706     Operands.push_back(
1707         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1708   else
1709     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1710   if (Dot != StringRef::npos) {
1711     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1712     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1713     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1714       Operands.push_back(
1715           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1716     else
1717       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1718   }
1719 
1720   // If there are no more operands then finish
1721   if (getLexer().is(AsmToken::EndOfStatement))
1722     return false;
1723 
1724   // Parse the first operand
1725   if (ParseOperand(Operands))
1726     return true;
1727 
1728   while (getLexer().isNot(AsmToken::EndOfStatement) &&
1729          getLexer().is(AsmToken::Comma)) {
1730     // Consume the comma token
1731     getLexer().Lex();
1732 
1733     // Parse the next operand
1734     if (ParseOperand(Operands))
1735       return true;
1736   }
1737 
1738   // We'll now deal with an unfortunate special case: the syntax for the dcbt
1739   // and dcbtst instructions differs for server vs. embedded cores.
1740   //  The syntax for dcbt is:
1741   //    dcbt ra, rb, th [server]
1742   //    dcbt th, ra, rb [embedded]
1743   //  where th can be omitted when it is 0. dcbtst is the same. We take the
1744   //  server form to be the default, so swap the operands if we're parsing for
1745   //  an embedded core (they'll be swapped again upon printing).
1746   if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1747       Operands.size() == 4 &&
1748       (Name == "dcbt" || Name == "dcbtst")) {
1749     std::swap(Operands[1], Operands[3]);
1750     std::swap(Operands[2], Operands[1]);
1751   }
1752 
1753   return false;
1754 }
1755 
1756 /// ParseDirective parses the PPC specific directives
1757 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1758   StringRef IDVal = DirectiveID.getIdentifier();
1759   if (!isDarwin()) {
1760     if (IDVal == ".word")
1761       return ParseDirectiveWord(2, DirectiveID.getLoc());
1762     if (IDVal == ".llong")
1763       return ParseDirectiveWord(8, DirectiveID.getLoc());
1764     if (IDVal == ".tc")
1765       return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1766     if (IDVal == ".machine")
1767       return ParseDirectiveMachine(DirectiveID.getLoc());
1768     if (IDVal == ".abiversion")
1769       return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1770     if (IDVal == ".localentry")
1771       return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1772   } else {
1773     if (IDVal == ".machine")
1774       return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1775   }
1776   return true;
1777 }
1778 
1779 /// ParseDirectiveWord
1780 ///  ::= .word [ expression (, expression)* ]
1781 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1782   MCAsmParser &Parser = getParser();
1783   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1784     for (;;) {
1785       const MCExpr *Value;
1786       SMLoc ExprLoc = getLexer().getLoc();
1787       if (getParser().parseExpression(Value))
1788         return false;
1789 
1790       if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1791         assert(Size <= 8 && "Invalid size");
1792         uint64_t IntValue = MCE->getValue();
1793         if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
1794           return Error(ExprLoc, "literal value out of range for directive");
1795         getStreamer().EmitIntValue(IntValue, Size);
1796       } else {
1797         getStreamer().EmitValue(Value, Size, ExprLoc);
1798       }
1799 
1800       if (getLexer().is(AsmToken::EndOfStatement))
1801         break;
1802 
1803       if (getLexer().isNot(AsmToken::Comma))
1804         return Error(L, "unexpected token in directive");
1805       Parser.Lex();
1806     }
1807   }
1808 
1809   Parser.Lex();
1810   return false;
1811 }
1812 
1813 /// ParseDirectiveTC
1814 ///  ::= .tc [ symbol (, expression)* ]
1815 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1816   MCAsmParser &Parser = getParser();
1817   // Skip TC symbol, which is only used with XCOFF.
1818   while (getLexer().isNot(AsmToken::EndOfStatement)
1819          && getLexer().isNot(AsmToken::Comma))
1820     Parser.Lex();
1821   if (getLexer().isNot(AsmToken::Comma)) {
1822     Error(L, "unexpected token in directive");
1823     return false;
1824   }
1825   Parser.Lex();
1826 
1827   // Align to word size.
1828   getParser().getStreamer().EmitValueToAlignment(Size);
1829 
1830   // Emit expressions.
1831   return ParseDirectiveWord(Size, L);
1832 }
1833 
1834 /// ParseDirectiveMachine (ELF platforms)
1835 ///  ::= .machine [ cpu | "push" | "pop" ]
1836 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1837   MCAsmParser &Parser = getParser();
1838   if (getLexer().isNot(AsmToken::Identifier) &&
1839       getLexer().isNot(AsmToken::String)) {
1840     Error(L, "unexpected token in directive");
1841     return false;
1842   }
1843 
1844   StringRef CPU = Parser.getTok().getIdentifier();
1845   Parser.Lex();
1846 
1847   // FIXME: Right now, the parser always allows any available
1848   // instruction, so the .machine directive is not useful.
1849   // Implement ".machine any" (by doing nothing) for the benefit
1850   // of existing assembler code.  Likewise, we can then implement
1851   // ".machine push" and ".machine pop" as no-op.
1852   if (CPU != "any" && CPU != "push" && CPU != "pop") {
1853     Error(L, "unrecognized machine type");
1854     return false;
1855   }
1856 
1857   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1858     Error(L, "unexpected token in directive");
1859     return false;
1860   }
1861   PPCTargetStreamer &TStreamer =
1862       *static_cast<PPCTargetStreamer *>(
1863            getParser().getStreamer().getTargetStreamer());
1864   TStreamer.emitMachine(CPU);
1865 
1866   return false;
1867 }
1868 
1869 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1870 ///  ::= .machine cpu-identifier
1871 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1872   MCAsmParser &Parser = getParser();
1873   if (getLexer().isNot(AsmToken::Identifier) &&
1874       getLexer().isNot(AsmToken::String)) {
1875     Error(L, "unexpected token in directive");
1876     return false;
1877   }
1878 
1879   StringRef CPU = Parser.getTok().getIdentifier();
1880   Parser.Lex();
1881 
1882   // FIXME: this is only the 'default' set of cpu variants.
1883   // However we don't act on this information at present, this is simply
1884   // allowing parsing to proceed with minimal sanity checking.
1885   if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1886     Error(L, "unrecognized cpu type");
1887     return false;
1888   }
1889 
1890   if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1891     Error(L, "wrong cpu type specified for 64bit");
1892     return false;
1893   }
1894   if (!isPPC64() && CPU == "ppc64") {
1895     Error(L, "wrong cpu type specified for 32bit");
1896     return false;
1897   }
1898 
1899   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1900     Error(L, "unexpected token in directive");
1901     return false;
1902   }
1903 
1904   return false;
1905 }
1906 
1907 /// ParseDirectiveAbiVersion
1908 ///  ::= .abiversion constant-expression
1909 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1910   int64_t AbiVersion;
1911   if (getParser().parseAbsoluteExpression(AbiVersion)){
1912     Error(L, "expected constant expression");
1913     return false;
1914   }
1915   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1916     Error(L, "unexpected token in directive");
1917     return false;
1918   }
1919 
1920   PPCTargetStreamer &TStreamer =
1921       *static_cast<PPCTargetStreamer *>(
1922            getParser().getStreamer().getTargetStreamer());
1923   TStreamer.emitAbiVersion(AbiVersion);
1924 
1925   return false;
1926 }
1927 
1928 /// ParseDirectiveLocalEntry
1929 ///  ::= .localentry symbol, expression
1930 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1931   StringRef Name;
1932   if (getParser().parseIdentifier(Name)) {
1933     Error(L, "expected identifier in directive");
1934     return false;
1935   }
1936   MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1937 
1938   if (getLexer().isNot(AsmToken::Comma)) {
1939     Error(L, "unexpected token in directive");
1940     return false;
1941   }
1942   Lex();
1943 
1944   const MCExpr *Expr;
1945   if (getParser().parseExpression(Expr)) {
1946     Error(L, "expected expression");
1947     return false;
1948   }
1949 
1950   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1951     Error(L, "unexpected token in directive");
1952     return false;
1953   }
1954 
1955   PPCTargetStreamer &TStreamer =
1956       *static_cast<PPCTargetStreamer *>(
1957            getParser().getStreamer().getTargetStreamer());
1958   TStreamer.emitLocalEntry(Sym, Expr);
1959 
1960   return false;
1961 }
1962 
1963 
1964 
1965 /// Force static initialization.
1966 extern "C" void LLVMInitializePowerPCAsmParser() {
1967   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1968   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1969   RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1970 }
1971 
1972 #define GET_REGISTER_MATCHER
1973 #define GET_MATCHER_IMPLEMENTATION
1974 #include "PPCGenAsmMatcher.inc"
1975 
1976 // Define this matcher function after the auto-generated include so we
1977 // have the match class enum definitions.
1978 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1979                                                   unsigned Kind) {
1980   // If the kind is a token for a literal immediate, check if our asm
1981   // operand matches. This is for InstAliases which have a fixed-value
1982   // immediate in the syntax.
1983   int64_t ImmVal;
1984   switch (Kind) {
1985     case MCK_0: ImmVal = 0; break;
1986     case MCK_1: ImmVal = 1; break;
1987     case MCK_2: ImmVal = 2; break;
1988     case MCK_3: ImmVal = 3; break;
1989     case MCK_4: ImmVal = 4; break;
1990     case MCK_5: ImmVal = 5; break;
1991     case MCK_6: ImmVal = 6; break;
1992     case MCK_7: ImmVal = 7; break;
1993     default: return Match_InvalidOperand;
1994   }
1995 
1996   PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1997   if (Op.isImm() && Op.getImm() == ImmVal)
1998     return Match_Success;
1999 
2000   return Match_InvalidOperand;
2001 }
2002 
2003 const MCExpr *
2004 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
2005                                   MCSymbolRefExpr::VariantKind Variant,
2006                                   MCContext &Ctx) {
2007   switch (Variant) {
2008   case MCSymbolRefExpr::VK_PPC_LO:
2009     return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
2010   case MCSymbolRefExpr::VK_PPC_HI:
2011     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
2012   case MCSymbolRefExpr::VK_PPC_HA:
2013     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
2014   case MCSymbolRefExpr::VK_PPC_HIGHER:
2015     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
2016   case MCSymbolRefExpr::VK_PPC_HIGHERA:
2017     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
2018   case MCSymbolRefExpr::VK_PPC_HIGHEST:
2019     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
2020   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
2021     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
2022   default:
2023     return nullptr;
2024   }
2025 }
2026