xref: /llvm-project/llvm/lib/Target/Mips/MipsSubtarget.h (revision 26b87aad9e2d34d53df67522dc5aea5f7c54a458) 
1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the Mips specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
14 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 
16 #include "MCTargetDesc/MipsABIInfo.h"
17 #include "MipsFrameLowering.h"
18 #include "MipsISelLowering.h"
19 #include "MipsInstrInfo.h"
20 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
23 #include "llvm/CodeGen/RegisterBankInfo.h"
24 #include "llvm/CodeGen/TargetSubtargetInfo.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/MC/MCInstrItineraries.h"
27 #include "llvm/Support/ErrorHandling.h"
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "MipsGenSubtargetInfo.inc"
31 
32 namespace llvm {
33 class StringRef;
34 
35 class MipsTargetMachine;
36 
37 class MipsSubtarget : public MipsGenSubtargetInfo {
38   virtual void anchor();
39 
40   enum MipsArchEnum {
41     MipsDefault,
42     Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
43     Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
44   };
45 
46   enum class CPU { P5600 };
47 
48   // Used to avoid printing dsp warnings multiple times.
49   static bool DspWarningPrinted;
50 
51   // Used to avoid printing msa warnings multiple times.
52   static bool MSAWarningPrinted;
53 
54   // Used to avoid printing crc warnings multiple times.
55   static bool CRCWarningPrinted;
56 
57   // Used to avoid printing ginv warnings multiple times.
58   static bool GINVWarningPrinted;
59 
60   // Used to avoid printing Mips1 warnings multiple times.
61   static bool MIPS1WarningPrinted;
62 
63   // Used to avoid printing virt warnings multiple times.
64   static bool VirtWarningPrinted;
65 
66   // Mips architecture version
67   MipsArchEnum MipsArchVersion;
68 
69   // Processor implementation (unused but required to exist by
70   // tablegen-erated code).
71   CPU ProcImpl;
72 
73   // IsLittle - The target is Little Endian
74   bool IsLittle;
75 
76   // IsSoftFloat - The target does not support any floating point instructions.
77   bool IsSoftFloat;
78 
79   // IsSingleFloat - The target only supports single precision float
80   // point operations. This enable the target to use all 32 32-bit
81   // floating point registers instead of only using even ones.
82   bool IsSingleFloat;
83 
84   // IsFPXX - MIPS O32 modeless ABI.
85   bool IsFPXX;
86 
87   // NoABICalls - Disable SVR4-style position-independent code.
88   bool NoABICalls;
89 
90   // Abs2008 - Use IEEE 754-2008 abs.fmt instruction.
91   bool Abs2008;
92 
93   // IsFP64bit - The target processor has 64-bit floating point registers.
94   bool IsFP64bit;
95 
96   /// Are odd single-precision registers permitted?
97   /// This corresponds to -modd-spreg and -mno-odd-spreg
98   bool UseOddSPReg;
99 
100   // IsNan2008 - IEEE 754-2008 NaN encoding.
101   bool IsNaN2008bit;
102 
103   // IsGP64bit - General-purpose registers are 64 bits wide
104   bool IsGP64bit;
105 
106   // IsPTR64bit - Pointers are 64 bit wide
107   bool IsPTR64bit;
108 
109   // HasVFPU - Processor has a vector floating point unit.
110   bool HasVFPU;
111 
112   // CPU supports cnMIPS (Cavium Networks Octeon CPU).
113   bool HasCnMips;
114 
115   // CPU supports cnMIPSP (Cavium Networks Octeon+ CPU).
116   bool HasCnMipsP;
117 
118   // isLinux - Target system is Linux. Is false we consider ELFOS for now.
119   bool IsLinux;
120 
121   // UseSmallSection - Small section is used.
122   bool UseSmallSection;
123 
124   /// Features related to the presence of specific instructions.
125 
126   // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
127   bool HasMips3_32;
128 
129   // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
130   bool HasMips3_32r2;
131 
132   // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
133   bool HasMips4_32;
134 
135   // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
136   bool HasMips4_32r2;
137 
138   // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
139   bool HasMips5_32r2;
140 
141   // InMips16 -- can process Mips16 instructions
142   bool InMips16Mode;
143 
144   // Mips16 hard float
145   bool InMips16HardFloat;
146 
147   // InMicroMips -- can process MicroMips instructions
148   bool InMicroMipsMode;
149 
150   // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
151   bool HasDSP, HasDSPR2, HasDSPR3;
152 
153   // Has3D -- Supports Mips3D ASE.
154   bool Has3D;
155 
156   // Allow mixed Mips16 and Mips32 in one source file
157   bool AllowMixed16_32;
158 
159   // Optimize for space by compiling all functions as Mips 16 unless
160   // it needs floating point. Functions needing floating point are
161   // compiled as Mips32
162   bool Os16;
163 
164   // HasMSA -- supports MSA ASE.
165   bool HasMSA;
166 
167   // UseTCCInDIV -- Enables the use of trapping in the assembler.
168   bool UseTCCInDIV;
169 
170   // Sym32 -- On Mips64 symbols are 32 bits.
171   bool HasSym32;
172 
173   // HasEVA -- supports EVA ASE.
174   bool HasEVA;
175 
176   // nomadd4 - disables generation of 4-operand madd.s, madd.d and
177   // related instructions.
178   bool DisableMadd4;
179 
180   // HasMT -- support MT ASE.
181   bool HasMT;
182 
183   // HasCRC -- supports R6 CRC ASE
184   bool HasCRC;
185 
186   // HasVirt -- supports Virtualization ASE
187   bool HasVirt;
188 
189   // HasGINV -- supports R6 Global INValidate ASE
190   bool HasGINV;
191 
192   // Use hazard variants of the jump register instructions for indirect
193   // function calls and jump tables.
194   bool UseIndirectJumpsHazard;
195 
196   // Disable use of the `jal` instruction.
197   bool UseLongCalls = false;
198 
199   // Assume 32-bit GOT.
200   bool UseXGOT = false;
201 
202   // Disable unaligned load store for r6.
203   bool StrictAlign;
204 
205   /// The minimum alignment known to hold of the stack frame on
206   /// entry to the function and which must be maintained by every function.
207   Align stackAlignment;
208 
209   /// The overridden stack alignment.
210   MaybeAlign StackAlignOverride;
211 
212   InstrItineraryData InstrItins;
213 
214   // We can override the determination of whether we are in mips16 mode
215   // as from the command line
216   enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
217 
218   const MipsTargetMachine &TM;
219 
220   Triple TargetTriple;
221 
222   std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
223   std::unique_ptr<const MipsInstrInfo> InstrInfo;
224   std::unique_ptr<const MipsFrameLowering> FrameLowering;
225   std::unique_ptr<const MipsTargetLowering> TLInfo;
226 
227 public:
228   bool isPositionIndependent() const;
229   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
230   bool enablePostRAScheduler() const override;
231   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
232   CodeGenOptLevel getOptLevelToEnablePostRAScheduler() const override;
233 
234   bool isABI_N64() const;
235   bool isABI_N32() const;
236   bool isABI_O32() const;
237   const MipsABIInfo &getABI() const;
238   bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
239 
240   /// This constructor initializes the data members to match that
241   /// of the specified triple.
242   MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
243                 const MipsTargetMachine &TM, MaybeAlign StackAlignOverride);
244 
245   ~MipsSubtarget() override;
246 
247   /// ParseSubtargetFeatures - Parses features string setting specified
248   /// subtarget options.  Definition of function is auto generated by tblgen.
249   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
250 
251   bool hasMips1() const { return MipsArchVersion >= Mips1; }
252   bool hasMips2() const { return MipsArchVersion >= Mips2; }
253   bool hasMips3() const { return MipsArchVersion >= Mips3; }
254   bool hasMips4() const { return MipsArchVersion >= Mips4; }
255   bool hasMips5() const { return MipsArchVersion >= Mips5; }
256   bool hasMips4_32() const { return HasMips4_32; }
257   bool hasMips4_32r2() const { return HasMips4_32r2; }
258   bool hasMips32() const {
259     return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
260            hasMips64();
261   }
262   bool hasMips32r2() const {
263     return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
264            hasMips64r2();
265   }
266   bool hasMips32r3() const {
267     return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
268            hasMips64r2();
269   }
270   bool hasMips32r5() const {
271     return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
272            hasMips64r5();
273   }
274   bool hasMips32r6() const {
275     return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
276            hasMips64r6();
277   }
278   bool hasMips64() const { return MipsArchVersion >= Mips64; }
279   bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
280   bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
281   bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
282   bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
283 
284   bool hasCnMips() const { return HasCnMips; }
285   bool hasCnMipsP() const { return HasCnMipsP; }
286 
287   bool isLittle() const { return IsLittle; }
288   bool isABICalls() const { return !NoABICalls; }
289   bool isFPXX() const { return IsFPXX; }
290   bool isFP64bit() const { return IsFP64bit; }
291   bool useOddSPReg() const { return UseOddSPReg; }
292   bool noOddSPReg() const { return !UseOddSPReg; }
293   bool isNaN2008() const { return IsNaN2008bit; }
294   bool inAbs2008Mode() const { return Abs2008; }
295   bool isGP64bit() const { return IsGP64bit; }
296   bool isGP32bit() const { return !IsGP64bit; }
297   unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
298   bool isPTR64bit() const { return IsPTR64bit; }
299   bool isPTR32bit() const { return !IsPTR64bit; }
300   bool hasSym32() const {
301     return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
302   }
303   bool isSingleFloat() const { return IsSingleFloat; }
304   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
305   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
306   bool hasVFPU() const { return HasVFPU; }
307   bool inMips16Mode() const { return InMips16Mode; }
308   bool inMips16ModeDefault() const {
309     return InMips16Mode;
310   }
311   // Hard float for mips16 means essentially to compile as soft float
312   // but to use a runtime library for soft float that is written with
313   // native mips32 floating point instructions (those runtime routines
314   // run in mips32 hard float mode).
315   bool inMips16HardFloat() const {
316     return inMips16Mode() && InMips16HardFloat;
317   }
318   bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; }
319   bool inMicroMips32r6Mode() const {
320     return inMicroMipsMode() && hasMips32r6();
321   }
322   bool hasDSP() const { return HasDSP; }
323   bool hasDSPR2() const { return HasDSPR2; }
324   bool hasDSPR3() const { return HasDSPR3; }
325   bool has3D() const { return Has3D; }
326   bool hasMSA() const { return HasMSA; }
327   bool disableMadd4() const { return DisableMadd4; }
328   bool hasEVA() const { return HasEVA; }
329   bool hasMT() const { return HasMT; }
330   bool hasCRC() const { return HasCRC; }
331   bool hasVirt() const { return HasVirt; }
332   bool hasGINV() const { return HasGINV; }
333   bool useIndirectJumpsHazard() const {
334     return UseIndirectJumpsHazard && hasMips32r2();
335   }
336   bool useSmallSection() const { return UseSmallSection; }
337 
338   bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; }
339 
340   bool useSoftFloat() const { return IsSoftFloat; }
341 
342   bool useLongCalls() const { return UseLongCalls; }
343 
344   bool useXGOT() const { return UseXGOT; }
345 
346   bool enableLongBranchPass() const {
347     return hasStandardEncoding() || inMicroMipsMode() || allowMixed16_32();
348   }
349 
350   /// Features related to the presence of specific instructions.
351   bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
352   bool hasMTHC1() const { return hasMips32r2(); }
353 
354   bool allowMixed16_32() const { return inMips16ModeDefault() |
355                                         AllowMixed16_32; }
356 
357   bool os16() const { return Os16; }
358 
359   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
360   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
361 
362   bool isXRaySupported() const override { return true; }
363 
364   // for now constant islands are on for the whole compilation unit but we only
365   // really use them if in addition we are in mips16 mode
366   static bool useConstantIslands();
367 
368   Align getStackAlignment() const { return stackAlignment; }
369 
370   // Grab relocation model
371   Reloc::Model getRelocationModel() const;
372 
373   MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
374                                                  const TargetMachine &TM);
375 
376   /// Does the system support unaligned memory access.
377   ///
378   /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
379   /// specify which component of the system provides it. Hardware, software, and
380   /// hybrid implementations are all valid.
381   bool systemSupportsUnalignedAccess() const {
382     return hasMips32r6() && !StrictAlign;
383   }
384 
385   // Set helper classes
386   void setHelperClassesMips16();
387   void setHelperClassesMipsSE();
388 
389   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
390 
391   const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
392   const TargetFrameLowering *getFrameLowering() const override {
393     return FrameLowering.get();
394   }
395   const MipsRegisterInfo *getRegisterInfo() const override {
396     return &InstrInfo->getRegisterInfo();
397   }
398   const MipsTargetLowering *getTargetLowering() const override {
399     return TLInfo.get();
400   }
401   const InstrItineraryData *getInstrItineraryData() const override {
402     return &InstrItins;
403   }
404 
405 protected:
406   // GlobalISel related APIs.
407   std::unique_ptr<CallLowering> CallLoweringInfo;
408   std::unique_ptr<LegalizerInfo> Legalizer;
409   std::unique_ptr<RegisterBankInfo> RegBankInfo;
410   std::unique_ptr<InstructionSelector> InstSelector;
411 
412 public:
413   const CallLowering *getCallLowering() const override;
414   const LegalizerInfo *getLegalizerInfo() const override;
415   const RegisterBankInfo *getRegBankInfo() const override;
416   InstructionSelector *getInstructionSelector() const override;
417 };
418 } // End llvm namespace
419 
420 #endif
421