1//===-- M68kInstrAtomics.td - Atomics Instructions ---------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9foreach size = [8, 16, 32] in { 10 def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_ARI:$ptr), 11 (!cast<MxInst>("MOV"#size#"dj") !cast<MxMemOp>("MxARI"#size):$ptr)>; 12 13 def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_ARII:$ptr), 14 (!cast<MxInst>("MOV"#size#"df") !cast<MxMemOp>("MxARII"#size):$ptr)>; 15 16 def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_ARID:$ptr), 17 (!cast<MxInst>("MOV"#size#"dp") !cast<MxMemOp>("MxARID"#size):$ptr)>; 18 19 def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_PCD:$ptr), 20 (!cast<MxInst>("MOV"#size#"dq") !cast<MxMemOp>("MxPCD"#size):$ptr)>; 21 22 def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_PCI:$ptr), 23 (!cast<MxInst>("MOV"#size#"dk") !cast<MxMemOp>("MxPCI"#size):$ptr)>; 24 25 def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_ARI:$ptr), 26 (!cast<MxInst>("MOV"#size#"jd") !cast<MxMemOp>("MxARI"#size):$ptr, 27 !cast<MxRegOp>("MxDRD"#size):$val)>; 28 29 def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_ARII:$ptr), 30 (!cast<MxInst>("MOV"#size#"fd") !cast<MxMemOp>("MxARII"#size):$ptr, 31 !cast<MxRegOp>("MxDRD"#size):$val)>; 32 33 def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_ARID:$ptr), 34 (!cast<MxInst>("MOV"#size#"pd") !cast<MxMemOp>("MxARID"#size):$ptr, 35 !cast<MxRegOp>("MxDRD"#size):$val)>; 36 37 def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_PCD:$ptr), 38 (!cast<MxInst>("MOV"#size#"qd") !cast<MxMemOp>("MxPCD"#size):$ptr, 39 !cast<MxRegOp>("MxDRD"#size):$val)>; 40 41 def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_PCI:$ptr), 42 (!cast<MxInst>("MOV"#size#"kd") !cast<MxMemOp>("MxPCI"#size):$ptr, 43 !cast<MxRegOp>("MxDRD"#size):$val)>; 44} 45 46let Predicates = [AtLeastM68020] in { 47class MxCASARIOp<bits<2> size_encoding, MxType type> 48 : MxInst<(outs type.ROp:$out), 49 (ins type.ROp:$dc, type.ROp:$du, !cast<MxMemOp>("MxARI"#type.Size):$mem), 50 "cas."#type.Prefix#" $dc, $du, $mem"> { 51 let Inst = (ascend 52 (descend 0b00001, size_encoding, 0b011, MxEncAddrMode_j<"mem">.EA), 53 (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3)) 54 ); 55 let Constraints = "$out = $dc"; 56 let mayLoad = 1; 57 let mayStore = 1; 58} 59 60def CASARI8 : MxCASARIOp<0x1, MxType8d>; 61def CASARI16 : MxCASARIOp<0x2, MxType16d>; 62def CASARI32 : MxCASARIOp<0x3, MxType32d>; 63 64class MxCASARIDOp<bits<2> size_encoding, MxType type> 65 : MxInst<(outs type.ROp:$out), 66 (ins type.ROp:$dc, type.ROp:$du, !cast<MxMemOp>("MxARID"#type.Size):$mem), 67 "cas."#type.Prefix#" $dc, $du, $mem"> { 68 let Inst = (ascend 69 (descend 0b00001, size_encoding, 0b011, MxEncAddrMode_p<"mem">.EA), 70 (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3)) 71 ); 72 let Constraints = "$out = $dc"; 73 let mayLoad = 1; 74 let mayStore = 1; 75} 76 77def CASARID8 : MxCASARIDOp<0x1, MxType8d>; 78def CASARID16 : MxCASARIDOp<0x2, MxType16d>; 79def CASARID32 : MxCASARIDOp<0x3, MxType32d>; 80 81class MxCASARIIOp<bits<2> size_encoding, MxType type> 82 : MxInst<(outs type.ROp:$out), 83 (ins type.ROp:$dc, type.ROp:$du, !cast<MxMemOp>("MxARII"#type.Size):$mem), 84 "cas."#type.Prefix#" $dc, $du, $mem"> { 85 let Inst = (ascend 86 (descend 0b00001, size_encoding, 0b011, MxEncAddrMode_f<"mem">.EA), 87 (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3)) 88 ); 89 let Constraints = "$out = $dc"; 90 let mayLoad = 1; 91 let mayStore = 1; 92} 93 94def CASARII8 : MxCASARIIOp<0x1, MxType8d>; 95def CASARII16 : MxCASARIIOp<0x2, MxType16d>; 96def CASARII32 : MxCASARIIOp<0x3, MxType32d>; 97 98class MxCASALOp<bits<2> size_encoding, MxType type> 99 : MxInst<(outs type.ROp:$out), 100 (ins type.ROp:$dc, type.ROp:$du, !cast<MxMemOp>("MxAL"#type.Size):$mem), 101 "cas."#type.Prefix#" $dc, $du, $mem"> { 102 let Inst = (ascend 103 (descend 0b00001, size_encoding, 0b011, MxEncAddrMode_abs<"mem">.EA), 104 (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3)) 105 ); 106 let Constraints = "$out = $dc"; 107 let mayLoad = 1; 108 let mayStore = 1; 109} 110 111def CASAL8 : MxCASALOp<0x1, MxType8d>; 112def CASAL16 : MxCASALOp<0x2, MxType16d>; 113def CASAL32 : MxCASALOp<0x3, MxType32d>; 114 115foreach mode = ["ARI", "ARII", "ARID", "AL"] in { 116foreach size = [8, 16, 32] in { 117 def : Pat<(!cast<SDPatternOperator>("atomic_cmp_swap_i"#size) !cast<ComplexPattern>("MxCP_"#mode):$ptr, 118 !cast<MxRegOp>("MxDRD"#size):$cmp, 119 !cast<MxRegOp>("MxDRD"#size):$new), 120 (!cast<MxInst>("CAS"#mode#size) !cast<MxRegOp>("MxDRD"#size):$cmp, 121 !cast<MxRegOp>("MxDRD"#size):$new, 122 !cast<MxMemOp>("Mx"#mode#size):$ptr)>; 123} // size 124} // addr mode 125} // let Predicates = [AtLeastM68020] 126