1//===- LoongArchLSXInstrInfo.td - LoongArch LSX instructions -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the SIMD extension instructions. 10// 11//===----------------------------------------------------------------------===// 12 13def SDT_LoongArchVreplve : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 14 SDTCisInt<1>, SDTCisVec<1>, 15 SDTCisSameAs<0, 1>, SDTCisInt<2>]>; 16def SDT_LoongArchVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>; 17 18def SDT_LoongArchVShuf : SDTypeProfile<1, 3, [SDTCisVec<0>, 19 SDTCisInt<1>, SDTCisVec<1>, 20 SDTCisSameAs<0, 2>, 21 SDTCisSameAs<2, 3>]>; 22def SDT_LoongArchV2R : SDTypeProfile<1, 2, [SDTCisVec<0>, 23 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; 24def SDT_LoongArchV1RUimm: SDTypeProfile<1, 2, [SDTCisVec<0>, 25 SDTCisSameAs<0,1>, SDTCisVT<2, i64>]>; 26def SDT_LoongArchVreplgr2vr : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>]>; 27def SDT_LoongArchVFRECIPE : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVec<0>, SDTCisSameAs<0, 1>]>; 28def SDT_LoongArchVFRSQRTE : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVec<0>, SDTCisSameAs<0, 1>]>; 29 30// Target nodes. 31def loongarch_vreplve : SDNode<"LoongArchISD::VREPLVE", SDT_LoongArchVreplve>; 32def loongarch_vall_nonzero : SDNode<"LoongArchISD::VALL_NONZERO", 33 SDT_LoongArchVecCond>; 34def loongarch_vany_nonzero : SDNode<"LoongArchISD::VANY_NONZERO", 35 SDT_LoongArchVecCond>; 36def loongarch_vall_zero : SDNode<"LoongArchISD::VALL_ZERO", 37 SDT_LoongArchVecCond>; 38def loongarch_vany_zero : SDNode<"LoongArchISD::VANY_ZERO", 39 SDT_LoongArchVecCond>; 40 41def loongarch_vpick_sext_elt : SDNode<"LoongArchISD::VPICK_SEXT_ELT", 42 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>>; 43def loongarch_vpick_zext_elt : SDNode<"LoongArchISD::VPICK_ZEXT_ELT", 44 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>>; 45 46def loongarch_vshuf: SDNode<"LoongArchISD::VSHUF", SDT_LoongArchVShuf>; 47def loongarch_vpickev: SDNode<"LoongArchISD::VPICKEV", SDT_LoongArchV2R>; 48def loongarch_vpickod: SDNode<"LoongArchISD::VPICKOD", SDT_LoongArchV2R>; 49def loongarch_vpackev: SDNode<"LoongArchISD::VPACKEV", SDT_LoongArchV2R>; 50def loongarch_vpackod: SDNode<"LoongArchISD::VPACKOD", SDT_LoongArchV2R>; 51def loongarch_vilvl: SDNode<"LoongArchISD::VILVL", SDT_LoongArchV2R>; 52def loongarch_vilvh: SDNode<"LoongArchISD::VILVH", SDT_LoongArchV2R>; 53 54def loongarch_vshuf4i: SDNode<"LoongArchISD::VSHUF4I", SDT_LoongArchV1RUimm>; 55def loongarch_vreplvei: SDNode<"LoongArchISD::VREPLVEI", SDT_LoongArchV1RUimm>; 56def loongarch_vreplgr2vr: SDNode<"LoongArchISD::VREPLGR2VR", SDT_LoongArchVreplgr2vr>; 57 58def loongarch_vfrecipe: SDNode<"LoongArchISD::FRECIPE", SDT_LoongArchVFRECIPE>; 59def loongarch_vfrsqrte: SDNode<"LoongArchISD::FRSQRTE", SDT_LoongArchVFRSQRTE>; 60 61def immZExt1 : ImmLeaf<i64, [{return isUInt<1>(Imm);}]>; 62def immZExt2 : ImmLeaf<i64, [{return isUInt<2>(Imm);}]>; 63def immZExt3 : ImmLeaf<i64, [{return isUInt<3>(Imm);}]>; 64def immZExt4 : ImmLeaf<i64, [{return isUInt<4>(Imm);}]>; 65def immZExt8 : ImmLeaf<i64, [{return isUInt<8>(Imm);}]>; 66 67class VecCond<SDPatternOperator OpNode, ValueType TyNode, 68 RegisterClass RC = LSX128> 69 : Pseudo<(outs GPR:$rd), (ins RC:$vj), 70 [(set GPR:$rd, (OpNode (TyNode RC:$vj)))]> { 71 let hasSideEffects = 0; 72 let mayLoad = 0; 73 let mayStore = 0; 74 let usesCustomInserter = 1; 75} 76 77def vsplat_imm_eq_1 : PatFrags<(ops), [(build_vector)], [{ 78 APInt Imm; 79 EVT EltTy = N->getValueType(0).getVectorElementType(); 80 81 if (N->getOpcode() == ISD::BITCAST) 82 N = N->getOperand(0).getNode(); 83 84 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 85 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 86}]>; 87 88def vsplati8_imm_eq_7 : PatFrags<(ops), [(build_vector)], [{ 89 APInt Imm; 90 EVT EltTy = N->getValueType(0).getVectorElementType(); 91 92 if (N->getOpcode() == ISD::BITCAST) 93 N = N->getOperand(0).getNode(); 94 95 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 96 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 7; 97}]>; 98def vsplati16_imm_eq_15 : PatFrags<(ops), [(build_vector)], [{ 99 APInt Imm; 100 EVT EltTy = N->getValueType(0).getVectorElementType(); 101 102 if (N->getOpcode() == ISD::BITCAST) 103 N = N->getOperand(0).getNode(); 104 105 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 106 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 15; 107}]>; 108def vsplati32_imm_eq_31 : PatFrags<(ops), [(build_vector)], [{ 109 APInt Imm; 110 EVT EltTy = N->getValueType(0).getVectorElementType(); 111 112 if (N->getOpcode() == ISD::BITCAST) 113 N = N->getOperand(0).getNode(); 114 115 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 116 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 31; 117}]>; 118def vsplati64_imm_eq_63 : PatFrags<(ops), [(build_vector)], [{ 119 APInt Imm; 120 EVT EltTy = N->getValueType(0).getVectorElementType(); 121 122 if (N->getOpcode() == ISD::BITCAST) 123 N = N->getOperand(0).getNode(); 124 125 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 126 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63; 127}]>; 128 129def vsplatf32_fpimm_eq_1 130 : PatFrags<(ops), [(bitconvert (v4i32 (build_vector))), 131 (bitconvert (v8i32 (build_vector)))], [{ 132 APInt Imm; 133 EVT EltTy = N->getValueType(0).getVectorElementType(); 134 N = N->getOperand(0).getNode(); 135 136 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 137 Imm.getBitWidth() == EltTy.getSizeInBits() && 138 Imm == APFloat(+1.0f).bitcastToAPInt(); 139}]>; 140def vsplatf64_fpimm_eq_1 141 : PatFrags<(ops), [(bitconvert (v2i64 (build_vector))), 142 (bitconvert (v4i64 (build_vector)))], [{ 143 APInt Imm; 144 EVT EltTy = N->getValueType(0).getVectorElementType(); 145 N = N->getOperand(0).getNode(); 146 147 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 148 Imm.getBitWidth() == EltTy.getSizeInBits() && 149 Imm == APFloat(+1.0).bitcastToAPInt(); 150}]>; 151 152def vsplati8imm7 : PatFrag<(ops node:$reg), 153 (and node:$reg, vsplati8_imm_eq_7)>; 154def vsplati16imm15 : PatFrag<(ops node:$reg), 155 (and node:$reg, vsplati16_imm_eq_15)>; 156def vsplati32imm31 : PatFrag<(ops node:$reg), 157 (and node:$reg, vsplati32_imm_eq_31)>; 158def vsplati64imm63 : PatFrag<(ops node:$reg), 159 (and node:$reg, vsplati64_imm_eq_63)>; 160 161foreach N = [3, 4, 5, 6, 8] in 162 def SplatPat_uimm#N : ComplexPattern<vAny, 1, "selectVSplatImm<"#N#">", 163 [build_vector, bitconvert], [], 2>; 164 165foreach N = [5] in 166 def SplatPat_simm#N : ComplexPattern<vAny, 1, "selectVSplatImm<"#N#", true>", 167 [build_vector, bitconvert]>; 168 169def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", 170 [build_vector, bitconvert]>; 171 172def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", 173 [build_vector, bitconvert]>; 174 175def muladd : PatFrag<(ops node:$vd, node:$vj, node:$vk), 176 (add node:$vd, (mul node:$vj, node:$vk))>; 177 178def mulsub : PatFrag<(ops node:$vd, node:$vj, node:$vk), 179 (sub node:$vd, (mul node:$vj, node:$vk))>; 180 181def lsxsplati8 : PatFrag<(ops node:$e0), 182 (v16i8 (build_vector node:$e0, node:$e0, 183 node:$e0, node:$e0, 184 node:$e0, node:$e0, 185 node:$e0, node:$e0, 186 node:$e0, node:$e0, 187 node:$e0, node:$e0, 188 node:$e0, node:$e0, 189 node:$e0, node:$e0))>; 190def lsxsplati16 : PatFrag<(ops node:$e0), 191 (v8i16 (build_vector node:$e0, node:$e0, 192 node:$e0, node:$e0, 193 node:$e0, node:$e0, 194 node:$e0, node:$e0))>; 195def lsxsplati32 : PatFrag<(ops node:$e0), 196 (v4i32 (build_vector node:$e0, node:$e0, 197 node:$e0, node:$e0))>; 198def lsxsplati64 : PatFrag<(ops node:$e0), 199 (v2i64 (build_vector node:$e0, node:$e0))>; 200def lsxsplatf32 : PatFrag<(ops node:$e0), 201 (v4f32 (build_vector node:$e0, node:$e0, 202 node:$e0, node:$e0))>; 203def lsxsplatf64 : PatFrag<(ops node:$e0), 204 (v2f64 (build_vector node:$e0, node:$e0))>; 205 206def to_valid_timm : SDNodeXForm<timm, [{ 207 auto CN = cast<ConstantSDNode>(N); 208 return CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(N), Subtarget->getGRLenVT()); 209}]>; 210 211// FP immediate of VLDI patterns. 212def f32imm_vldi : PatLeaf<(fpimm), [{ 213 const auto &TLI = 214 *static_cast<const LoongArchTargetLowering*>(getTargetLowering()); 215 return TLI.isFPImmVLDILegal(N->getValueAPF(), MVT::f32); 216}]>; 217def f64imm_vldi : PatLeaf<(fpimm), [{ 218 const auto &TLI = 219 *static_cast<const LoongArchTargetLowering*>(getTargetLowering()); 220 return TLI.isFPImmVLDILegal(N->getValueAPF(), MVT::f64); 221}]>; 222 223def to_f32imm_vldi : SDNodeXForm<fpimm, [{ 224 uint64_t x = N->getValueAPF().bitcastToAPInt().getZExtValue(); 225 x = (0b11011 << 8) | (((x >> 24) & 0xc0) ^ 0x40) | ((x >> 19) & 0x3f); 226 return CurDAG->getSignedTargetConstant(SignExtend32<13>(x), SDLoc(N), 227 MVT::i32); 228}]>; 229def to_f64imm_vldi : SDNodeXForm<fpimm, [{ 230 uint64_t x = N->getValueAPF().bitcastToAPInt().getZExtValue(); 231 x = (0b11100 << 8) | (((x >> 56) & 0xc0) ^ 0x40) | ((x >> 48) & 0x3f); 232 return CurDAG->getSignedTargetConstant(SignExtend32<13>(x), SDLoc(N), 233 MVT::i32); 234}]>; 235 236//===----------------------------------------------------------------------===// 237// Instruction class templates 238//===----------------------------------------------------------------------===// 239 240class LSX1RI13_VI<bits<32> op, Operand ImmOpnd = simm13> 241 : Fmt1RI13_VI<op, (outs LSX128:$vd), (ins ImmOpnd:$imm13), "$vd, $imm13">; 242 243class LSX2R_VV<bits<32> op> 244 : Fmt2R_VV<op, (outs LSX128:$vd), (ins LSX128:$vj), "$vd, $vj">; 245 246class LSX2R_VR<bits<32> op> 247 : Fmt2R_VR<op, (outs LSX128:$vd), (ins GPR:$rj), "$vd, $rj">; 248 249class LSX2R_CV<bits<32> op> 250 : Fmt2R_CV<op, (outs CFR:$cd), (ins LSX128:$vj), "$cd, $vj">; 251 252class LSX2RI1_VVI<bits<32> op, Operand ImmOpnd = uimm1> 253 : Fmt2RI1_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm1), 254 "$vd, $vj, $imm1">; 255 256class LSX2RI1_RVI<bits<32> op, Operand ImmOpnd = uimm1> 257 : Fmt2RI1_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm1), 258 "$rd, $vj, $imm1">; 259 260class LSX2RI2_VVI<bits<32> op, Operand ImmOpnd = uimm2> 261 : Fmt2RI2_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm2), 262 "$vd, $vj, $imm2">; 263 264class LSX2RI2_RVI<bits<32> op, Operand ImmOpnd = uimm2> 265 : Fmt2RI2_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm2), 266 "$rd, $vj, $imm2">; 267 268class LSX2RI3_VVI<bits<32> op, Operand ImmOpnd = uimm3> 269 : Fmt2RI3_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm3), 270 "$vd, $vj, $imm3">; 271 272class LSX2RI3_RVI<bits<32> op, Operand ImmOpnd = uimm3> 273 : Fmt2RI3_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm3), 274 "$rd, $vj, $imm3">; 275 276class LSX2RI4_VVI<bits<32> op, Operand ImmOpnd = uimm4> 277 : Fmt2RI4_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm4), 278 "$vd, $vj, $imm4">; 279 280class LSX2RI4_RVI<bits<32> op, Operand ImmOpnd = uimm4> 281 : Fmt2RI4_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm4), 282 "$rd, $vj, $imm4">; 283 284class LSX2RI5_VVI<bits<32> op, Operand ImmOpnd = uimm5> 285 : Fmt2RI5_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm5), 286 "$vd, $vj, $imm5">; 287 288class LSX2RI6_VVI<bits<32> op, Operand ImmOpnd = uimm6> 289 : Fmt2RI6_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm6), 290 "$vd, $vj, $imm6">; 291 292class LSX2RI8_VVI<bits<32> op, Operand ImmOpnd = uimm8> 293 : Fmt2RI8_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm8), 294 "$vd, $vj, $imm8">; 295 296class LSX2RI8I1_VRII<bits<32> op, Operand ImmOpnd = simm8, 297 Operand IdxOpnd = uimm1> 298 : Fmt2RI8I1_VRII<op, (outs), 299 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm1), 300 "$vd, $rj, $imm8, $imm1">; 301class LSX2RI8I2_VRII<bits<32> op, Operand ImmOpnd = simm8, 302 Operand IdxOpnd = uimm2> 303 : Fmt2RI8I2_VRII<op, (outs), 304 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm2), 305 "$vd, $rj, $imm8, $imm2">; 306class LSX2RI8I3_VRII<bits<32> op, Operand ImmOpnd = simm8, 307 Operand IdxOpnd = uimm3> 308 : Fmt2RI8I3_VRII<op, (outs), 309 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm3), 310 "$vd, $rj, $imm8, $imm3">; 311class LSX2RI8I4_VRII<bits<32> op, Operand ImmOpnd = simm8, 312 Operand IdxOpnd = uimm4> 313 : Fmt2RI8I4_VRII<op, (outs), 314 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm4), 315 "$vd, $rj, $imm8, $imm4">; 316 317class LSX3R_VVV<bits<32> op> 318 : Fmt3R_VVV<op, (outs LSX128:$vd), (ins LSX128:$vj, LSX128:$vk), 319 "$vd, $vj, $vk">; 320 321class LSX3R_VVR<bits<32> op> 322 : Fmt3R_VVR<op, (outs LSX128:$vd), (ins LSX128:$vj, GPR:$rk), 323 "$vd, $vj, $rk">; 324 325class LSX4R_VVVV<bits<32> op> 326 : Fmt4R_VVVV<op, (outs LSX128:$vd), 327 (ins LSX128:$vj, LSX128:$vk, LSX128:$va), 328 "$vd, $vj, $vk, $va">; 329 330let Constraints = "$vd = $dst" in { 331 332class LSX2RI1_VVRI<bits<32> op, Operand ImmOpnd = uimm1> 333 : Fmt2RI1_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm1), 334 "$vd, $rj, $imm1">; 335class LSX2RI2_VVRI<bits<32> op, Operand ImmOpnd = uimm2> 336 : Fmt2RI2_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm2), 337 "$vd, $rj, $imm2">; 338class LSX2RI3_VVRI<bits<32> op, Operand ImmOpnd = uimm3> 339 : Fmt2RI3_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm3), 340 "$vd, $rj, $imm3">; 341class LSX2RI4_VVRI<bits<32> op, Operand ImmOpnd = uimm4> 342 : Fmt2RI4_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm4), 343 "$vd, $rj, $imm4">; 344 345class LSX2RI4_VVVI<bits<32> op, Operand ImmOpnd = uimm4> 346 : Fmt2RI4_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm4), 347 "$vd, $vj, $imm4">; 348class LSX2RI5_VVVI<bits<32> op, Operand ImmOpnd = uimm5> 349 : Fmt2RI5_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm5), 350 "$vd, $vj, $imm5">; 351class LSX2RI6_VVVI<bits<32> op, Operand ImmOpnd = uimm6> 352 : Fmt2RI6_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm6), 353 "$vd, $vj, $imm6">; 354class LSX2RI7_VVVI<bits<32> op, Operand ImmOpnd = uimm7> 355 : Fmt2RI7_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm7), 356 "$vd, $vj, $imm7">; 357 358class LSX2RI8_VVVI<bits<32> op, Operand ImmOpnd = uimm8> 359 : Fmt2RI8_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm8), 360 "$vd, $vj, $imm8">; 361 362class LSX3R_VVVV<bits<32> op> 363 : Fmt3R_VVV<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, LSX128:$vk), 364 "$vd, $vj, $vk">; 365 366} // Constraints = "$vd = $dst" 367 368class LSX2RI9_Load<bits<32> op, Operand ImmOpnd = simm9_lsl3> 369 : Fmt2RI9_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm9), 370 "$vd, $rj, $imm9">; 371class LSX2RI10_Load<bits<32> op, Operand ImmOpnd = simm10_lsl2> 372 : Fmt2RI10_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm10), 373 "$vd, $rj, $imm10">; 374class LSX2RI11_Load<bits<32> op, Operand ImmOpnd = simm11_lsl1> 375 : Fmt2RI11_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm11), 376 "$vd, $rj, $imm11">; 377class LSX2RI12_Load<bits<32> op, Operand ImmOpnd = simm12> 378 : Fmt2RI12_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm12), 379 "$vd, $rj, $imm12">; 380class LSX2RI12_Store<bits<32> op, Operand ImmOpnd = simm12> 381 : Fmt2RI12_VRI<op, (outs), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm12), 382 "$vd, $rj, $imm12">; 383 384class LSX3R_Load<bits<32> op> 385 : Fmt3R_VRR<op, (outs LSX128:$vd), (ins GPR:$rj, GPR:$rk), 386 "$vd, $rj, $rk">; 387class LSX3R_Store<bits<32> op> 388 : Fmt3R_VRR<op, (outs), (ins LSX128:$vd, GPR:$rj, GPR:$rk), 389 "$vd, $rj, $rk">; 390 391//===----------------------------------------------------------------------===// 392// Instructions 393//===----------------------------------------------------------------------===// 394 395let hasSideEffects = 0, Predicates = [HasExtLSX] in { 396 397let mayLoad = 0, mayStore = 0 in { 398 399def VADD_B : LSX3R_VVV<0x700a0000>; 400def VADD_H : LSX3R_VVV<0x700a8000>; 401def VADD_W : LSX3R_VVV<0x700b0000>; 402def VADD_D : LSX3R_VVV<0x700b8000>; 403def VADD_Q : LSX3R_VVV<0x712d0000>; 404 405def VSUB_B : LSX3R_VVV<0x700c0000>; 406def VSUB_H : LSX3R_VVV<0x700c8000>; 407def VSUB_W : LSX3R_VVV<0x700d0000>; 408def VSUB_D : LSX3R_VVV<0x700d8000>; 409def VSUB_Q : LSX3R_VVV<0x712d8000>; 410 411def VADDI_BU : LSX2RI5_VVI<0x728a0000>; 412def VADDI_HU : LSX2RI5_VVI<0x728a8000>; 413def VADDI_WU : LSX2RI5_VVI<0x728b0000>; 414def VADDI_DU : LSX2RI5_VVI<0x728b8000>; 415 416def VSUBI_BU : LSX2RI5_VVI<0x728c0000>; 417def VSUBI_HU : LSX2RI5_VVI<0x728c8000>; 418def VSUBI_WU : LSX2RI5_VVI<0x728d0000>; 419def VSUBI_DU : LSX2RI5_VVI<0x728d8000>; 420 421def VNEG_B : LSX2R_VV<0x729c3000>; 422def VNEG_H : LSX2R_VV<0x729c3400>; 423def VNEG_W : LSX2R_VV<0x729c3800>; 424def VNEG_D : LSX2R_VV<0x729c3c00>; 425 426def VSADD_B : LSX3R_VVV<0x70460000>; 427def VSADD_H : LSX3R_VVV<0x70468000>; 428def VSADD_W : LSX3R_VVV<0x70470000>; 429def VSADD_D : LSX3R_VVV<0x70478000>; 430def VSADD_BU : LSX3R_VVV<0x704a0000>; 431def VSADD_HU : LSX3R_VVV<0x704a8000>; 432def VSADD_WU : LSX3R_VVV<0x704b0000>; 433def VSADD_DU : LSX3R_VVV<0x704b8000>; 434 435def VSSUB_B : LSX3R_VVV<0x70480000>; 436def VSSUB_H : LSX3R_VVV<0x70488000>; 437def VSSUB_W : LSX3R_VVV<0x70490000>; 438def VSSUB_D : LSX3R_VVV<0x70498000>; 439def VSSUB_BU : LSX3R_VVV<0x704c0000>; 440def VSSUB_HU : LSX3R_VVV<0x704c8000>; 441def VSSUB_WU : LSX3R_VVV<0x704d0000>; 442def VSSUB_DU : LSX3R_VVV<0x704d8000>; 443 444def VHADDW_H_B : LSX3R_VVV<0x70540000>; 445def VHADDW_W_H : LSX3R_VVV<0x70548000>; 446def VHADDW_D_W : LSX3R_VVV<0x70550000>; 447def VHADDW_Q_D : LSX3R_VVV<0x70558000>; 448def VHADDW_HU_BU : LSX3R_VVV<0x70580000>; 449def VHADDW_WU_HU : LSX3R_VVV<0x70588000>; 450def VHADDW_DU_WU : LSX3R_VVV<0x70590000>; 451def VHADDW_QU_DU : LSX3R_VVV<0x70598000>; 452 453def VHSUBW_H_B : LSX3R_VVV<0x70560000>; 454def VHSUBW_W_H : LSX3R_VVV<0x70568000>; 455def VHSUBW_D_W : LSX3R_VVV<0x70570000>; 456def VHSUBW_Q_D : LSX3R_VVV<0x70578000>; 457def VHSUBW_HU_BU : LSX3R_VVV<0x705a0000>; 458def VHSUBW_WU_HU : LSX3R_VVV<0x705a8000>; 459def VHSUBW_DU_WU : LSX3R_VVV<0x705b0000>; 460def VHSUBW_QU_DU : LSX3R_VVV<0x705b8000>; 461 462def VADDWEV_H_B : LSX3R_VVV<0x701e0000>; 463def VADDWEV_W_H : LSX3R_VVV<0x701e8000>; 464def VADDWEV_D_W : LSX3R_VVV<0x701f0000>; 465def VADDWEV_Q_D : LSX3R_VVV<0x701f8000>; 466def VADDWOD_H_B : LSX3R_VVV<0x70220000>; 467def VADDWOD_W_H : LSX3R_VVV<0x70228000>; 468def VADDWOD_D_W : LSX3R_VVV<0x70230000>; 469def VADDWOD_Q_D : LSX3R_VVV<0x70238000>; 470 471def VSUBWEV_H_B : LSX3R_VVV<0x70200000>; 472def VSUBWEV_W_H : LSX3R_VVV<0x70208000>; 473def VSUBWEV_D_W : LSX3R_VVV<0x70210000>; 474def VSUBWEV_Q_D : LSX3R_VVV<0x70218000>; 475def VSUBWOD_H_B : LSX3R_VVV<0x70240000>; 476def VSUBWOD_W_H : LSX3R_VVV<0x70248000>; 477def VSUBWOD_D_W : LSX3R_VVV<0x70250000>; 478def VSUBWOD_Q_D : LSX3R_VVV<0x70258000>; 479 480def VADDWEV_H_BU : LSX3R_VVV<0x702e0000>; 481def VADDWEV_W_HU : LSX3R_VVV<0x702e8000>; 482def VADDWEV_D_WU : LSX3R_VVV<0x702f0000>; 483def VADDWEV_Q_DU : LSX3R_VVV<0x702f8000>; 484def VADDWOD_H_BU : LSX3R_VVV<0x70320000>; 485def VADDWOD_W_HU : LSX3R_VVV<0x70328000>; 486def VADDWOD_D_WU : LSX3R_VVV<0x70330000>; 487def VADDWOD_Q_DU : LSX3R_VVV<0x70338000>; 488 489def VSUBWEV_H_BU : LSX3R_VVV<0x70300000>; 490def VSUBWEV_W_HU : LSX3R_VVV<0x70308000>; 491def VSUBWEV_D_WU : LSX3R_VVV<0x70310000>; 492def VSUBWEV_Q_DU : LSX3R_VVV<0x70318000>; 493def VSUBWOD_H_BU : LSX3R_VVV<0x70340000>; 494def VSUBWOD_W_HU : LSX3R_VVV<0x70348000>; 495def VSUBWOD_D_WU : LSX3R_VVV<0x70350000>; 496def VSUBWOD_Q_DU : LSX3R_VVV<0x70358000>; 497 498def VADDWEV_H_BU_B : LSX3R_VVV<0x703e0000>; 499def VADDWEV_W_HU_H : LSX3R_VVV<0x703e8000>; 500def VADDWEV_D_WU_W : LSX3R_VVV<0x703f0000>; 501def VADDWEV_Q_DU_D : LSX3R_VVV<0x703f8000>; 502def VADDWOD_H_BU_B : LSX3R_VVV<0x70400000>; 503def VADDWOD_W_HU_H : LSX3R_VVV<0x70408000>; 504def VADDWOD_D_WU_W : LSX3R_VVV<0x70410000>; 505def VADDWOD_Q_DU_D : LSX3R_VVV<0x70418000>; 506 507def VAVG_B : LSX3R_VVV<0x70640000>; 508def VAVG_H : LSX3R_VVV<0x70648000>; 509def VAVG_W : LSX3R_VVV<0x70650000>; 510def VAVG_D : LSX3R_VVV<0x70658000>; 511def VAVG_BU : LSX3R_VVV<0x70660000>; 512def VAVG_HU : LSX3R_VVV<0x70668000>; 513def VAVG_WU : LSX3R_VVV<0x70670000>; 514def VAVG_DU : LSX3R_VVV<0x70678000>; 515def VAVGR_B : LSX3R_VVV<0x70680000>; 516def VAVGR_H : LSX3R_VVV<0x70688000>; 517def VAVGR_W : LSX3R_VVV<0x70690000>; 518def VAVGR_D : LSX3R_VVV<0x70698000>; 519def VAVGR_BU : LSX3R_VVV<0x706a0000>; 520def VAVGR_HU : LSX3R_VVV<0x706a8000>; 521def VAVGR_WU : LSX3R_VVV<0x706b0000>; 522def VAVGR_DU : LSX3R_VVV<0x706b8000>; 523 524def VABSD_B : LSX3R_VVV<0x70600000>; 525def VABSD_H : LSX3R_VVV<0x70608000>; 526def VABSD_W : LSX3R_VVV<0x70610000>; 527def VABSD_D : LSX3R_VVV<0x70618000>; 528def VABSD_BU : LSX3R_VVV<0x70620000>; 529def VABSD_HU : LSX3R_VVV<0x70628000>; 530def VABSD_WU : LSX3R_VVV<0x70630000>; 531def VABSD_DU : LSX3R_VVV<0x70638000>; 532 533def VADDA_B : LSX3R_VVV<0x705c0000>; 534def VADDA_H : LSX3R_VVV<0x705c8000>; 535def VADDA_W : LSX3R_VVV<0x705d0000>; 536def VADDA_D : LSX3R_VVV<0x705d8000>; 537 538def VMAX_B : LSX3R_VVV<0x70700000>; 539def VMAX_H : LSX3R_VVV<0x70708000>; 540def VMAX_W : LSX3R_VVV<0x70710000>; 541def VMAX_D : LSX3R_VVV<0x70718000>; 542def VMAXI_B : LSX2RI5_VVI<0x72900000, simm5>; 543def VMAXI_H : LSX2RI5_VVI<0x72908000, simm5>; 544def VMAXI_W : LSX2RI5_VVI<0x72910000, simm5>; 545def VMAXI_D : LSX2RI5_VVI<0x72918000, simm5>; 546def VMAX_BU : LSX3R_VVV<0x70740000>; 547def VMAX_HU : LSX3R_VVV<0x70748000>; 548def VMAX_WU : LSX3R_VVV<0x70750000>; 549def VMAX_DU : LSX3R_VVV<0x70758000>; 550def VMAXI_BU : LSX2RI5_VVI<0x72940000>; 551def VMAXI_HU : LSX2RI5_VVI<0x72948000>; 552def VMAXI_WU : LSX2RI5_VVI<0x72950000>; 553def VMAXI_DU : LSX2RI5_VVI<0x72958000>; 554 555def VMIN_B : LSX3R_VVV<0x70720000>; 556def VMIN_H : LSX3R_VVV<0x70728000>; 557def VMIN_W : LSX3R_VVV<0x70730000>; 558def VMIN_D : LSX3R_VVV<0x70738000>; 559def VMINI_B : LSX2RI5_VVI<0x72920000, simm5>; 560def VMINI_H : LSX2RI5_VVI<0x72928000, simm5>; 561def VMINI_W : LSX2RI5_VVI<0x72930000, simm5>; 562def VMINI_D : LSX2RI5_VVI<0x72938000, simm5>; 563def VMIN_BU : LSX3R_VVV<0x70760000>; 564def VMIN_HU : LSX3R_VVV<0x70768000>; 565def VMIN_WU : LSX3R_VVV<0x70770000>; 566def VMIN_DU : LSX3R_VVV<0x70778000>; 567def VMINI_BU : LSX2RI5_VVI<0x72960000>; 568def VMINI_HU : LSX2RI5_VVI<0x72968000>; 569def VMINI_WU : LSX2RI5_VVI<0x72970000>; 570def VMINI_DU : LSX2RI5_VVI<0x72978000>; 571 572def VMUL_B : LSX3R_VVV<0x70840000>; 573def VMUL_H : LSX3R_VVV<0x70848000>; 574def VMUL_W : LSX3R_VVV<0x70850000>; 575def VMUL_D : LSX3R_VVV<0x70858000>; 576 577def VMUH_B : LSX3R_VVV<0x70860000>; 578def VMUH_H : LSX3R_VVV<0x70868000>; 579def VMUH_W : LSX3R_VVV<0x70870000>; 580def VMUH_D : LSX3R_VVV<0x70878000>; 581def VMUH_BU : LSX3R_VVV<0x70880000>; 582def VMUH_HU : LSX3R_VVV<0x70888000>; 583def VMUH_WU : LSX3R_VVV<0x70890000>; 584def VMUH_DU : LSX3R_VVV<0x70898000>; 585 586def VMULWEV_H_B : LSX3R_VVV<0x70900000>; 587def VMULWEV_W_H : LSX3R_VVV<0x70908000>; 588def VMULWEV_D_W : LSX3R_VVV<0x70910000>; 589def VMULWEV_Q_D : LSX3R_VVV<0x70918000>; 590def VMULWOD_H_B : LSX3R_VVV<0x70920000>; 591def VMULWOD_W_H : LSX3R_VVV<0x70928000>; 592def VMULWOD_D_W : LSX3R_VVV<0x70930000>; 593def VMULWOD_Q_D : LSX3R_VVV<0x70938000>; 594def VMULWEV_H_BU : LSX3R_VVV<0x70980000>; 595def VMULWEV_W_HU : LSX3R_VVV<0x70988000>; 596def VMULWEV_D_WU : LSX3R_VVV<0x70990000>; 597def VMULWEV_Q_DU : LSX3R_VVV<0x70998000>; 598def VMULWOD_H_BU : LSX3R_VVV<0x709a0000>; 599def VMULWOD_W_HU : LSX3R_VVV<0x709a8000>; 600def VMULWOD_D_WU : LSX3R_VVV<0x709b0000>; 601def VMULWOD_Q_DU : LSX3R_VVV<0x709b8000>; 602def VMULWEV_H_BU_B : LSX3R_VVV<0x70a00000>; 603def VMULWEV_W_HU_H : LSX3R_VVV<0x70a08000>; 604def VMULWEV_D_WU_W : LSX3R_VVV<0x70a10000>; 605def VMULWEV_Q_DU_D : LSX3R_VVV<0x70a18000>; 606def VMULWOD_H_BU_B : LSX3R_VVV<0x70a20000>; 607def VMULWOD_W_HU_H : LSX3R_VVV<0x70a28000>; 608def VMULWOD_D_WU_W : LSX3R_VVV<0x70a30000>; 609def VMULWOD_Q_DU_D : LSX3R_VVV<0x70a38000>; 610 611def VMADD_B : LSX3R_VVVV<0x70a80000>; 612def VMADD_H : LSX3R_VVVV<0x70a88000>; 613def VMADD_W : LSX3R_VVVV<0x70a90000>; 614def VMADD_D : LSX3R_VVVV<0x70a98000>; 615 616def VMSUB_B : LSX3R_VVVV<0x70aa0000>; 617def VMSUB_H : LSX3R_VVVV<0x70aa8000>; 618def VMSUB_W : LSX3R_VVVV<0x70ab0000>; 619def VMSUB_D : LSX3R_VVVV<0x70ab8000>; 620 621def VMADDWEV_H_B : LSX3R_VVVV<0x70ac0000>; 622def VMADDWEV_W_H : LSX3R_VVVV<0x70ac8000>; 623def VMADDWEV_D_W : LSX3R_VVVV<0x70ad0000>; 624def VMADDWEV_Q_D : LSX3R_VVVV<0x70ad8000>; 625def VMADDWOD_H_B : LSX3R_VVVV<0x70ae0000>; 626def VMADDWOD_W_H : LSX3R_VVVV<0x70ae8000>; 627def VMADDWOD_D_W : LSX3R_VVVV<0x70af0000>; 628def VMADDWOD_Q_D : LSX3R_VVVV<0x70af8000>; 629def VMADDWEV_H_BU : LSX3R_VVVV<0x70b40000>; 630def VMADDWEV_W_HU : LSX3R_VVVV<0x70b48000>; 631def VMADDWEV_D_WU : LSX3R_VVVV<0x70b50000>; 632def VMADDWEV_Q_DU : LSX3R_VVVV<0x70b58000>; 633def VMADDWOD_H_BU : LSX3R_VVVV<0x70b60000>; 634def VMADDWOD_W_HU : LSX3R_VVVV<0x70b68000>; 635def VMADDWOD_D_WU : LSX3R_VVVV<0x70b70000>; 636def VMADDWOD_Q_DU : LSX3R_VVVV<0x70b78000>; 637def VMADDWEV_H_BU_B : LSX3R_VVVV<0x70bc0000>; 638def VMADDWEV_W_HU_H : LSX3R_VVVV<0x70bc8000>; 639def VMADDWEV_D_WU_W : LSX3R_VVVV<0x70bd0000>; 640def VMADDWEV_Q_DU_D : LSX3R_VVVV<0x70bd8000>; 641def VMADDWOD_H_BU_B : LSX3R_VVVV<0x70be0000>; 642def VMADDWOD_W_HU_H : LSX3R_VVVV<0x70be8000>; 643def VMADDWOD_D_WU_W : LSX3R_VVVV<0x70bf0000>; 644def VMADDWOD_Q_DU_D : LSX3R_VVVV<0x70bf8000>; 645 646def VDIV_B : LSX3R_VVV<0x70e00000>; 647def VDIV_H : LSX3R_VVV<0x70e08000>; 648def VDIV_W : LSX3R_VVV<0x70e10000>; 649def VDIV_D : LSX3R_VVV<0x70e18000>; 650def VDIV_BU : LSX3R_VVV<0x70e40000>; 651def VDIV_HU : LSX3R_VVV<0x70e48000>; 652def VDIV_WU : LSX3R_VVV<0x70e50000>; 653def VDIV_DU : LSX3R_VVV<0x70e58000>; 654 655def VMOD_B : LSX3R_VVV<0x70e20000>; 656def VMOD_H : LSX3R_VVV<0x70e28000>; 657def VMOD_W : LSX3R_VVV<0x70e30000>; 658def VMOD_D : LSX3R_VVV<0x70e38000>; 659def VMOD_BU : LSX3R_VVV<0x70e60000>; 660def VMOD_HU : LSX3R_VVV<0x70e68000>; 661def VMOD_WU : LSX3R_VVV<0x70e70000>; 662def VMOD_DU : LSX3R_VVV<0x70e78000>; 663 664def VSAT_B : LSX2RI3_VVI<0x73242000>; 665def VSAT_H : LSX2RI4_VVI<0x73244000>; 666def VSAT_W : LSX2RI5_VVI<0x73248000>; 667def VSAT_D : LSX2RI6_VVI<0x73250000>; 668def VSAT_BU : LSX2RI3_VVI<0x73282000>; 669def VSAT_HU : LSX2RI4_VVI<0x73284000>; 670def VSAT_WU : LSX2RI5_VVI<0x73288000>; 671def VSAT_DU : LSX2RI6_VVI<0x73290000>; 672 673def VEXTH_H_B : LSX2R_VV<0x729ee000>; 674def VEXTH_W_H : LSX2R_VV<0x729ee400>; 675def VEXTH_D_W : LSX2R_VV<0x729ee800>; 676def VEXTH_Q_D : LSX2R_VV<0x729eec00>; 677def VEXTH_HU_BU : LSX2R_VV<0x729ef000>; 678def VEXTH_WU_HU : LSX2R_VV<0x729ef400>; 679def VEXTH_DU_WU : LSX2R_VV<0x729ef800>; 680def VEXTH_QU_DU : LSX2R_VV<0x729efc00>; 681 682def VSIGNCOV_B : LSX3R_VVV<0x712e0000>; 683def VSIGNCOV_H : LSX3R_VVV<0x712e8000>; 684def VSIGNCOV_W : LSX3R_VVV<0x712f0000>; 685def VSIGNCOV_D : LSX3R_VVV<0x712f8000>; 686 687def VMSKLTZ_B : LSX2R_VV<0x729c4000>; 688def VMSKLTZ_H : LSX2R_VV<0x729c4400>; 689def VMSKLTZ_W : LSX2R_VV<0x729c4800>; 690def VMSKLTZ_D : LSX2R_VV<0x729c4c00>; 691 692def VMSKGEZ_B : LSX2R_VV<0x729c5000>; 693 694def VMSKNZ_B : LSX2R_VV<0x729c6000>; 695 696let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 697def VLDI : LSX1RI13_VI<0x73e00000>; 698} 699 700def VAND_V : LSX3R_VVV<0x71260000>; 701def VOR_V : LSX3R_VVV<0x71268000>; 702def VXOR_V : LSX3R_VVV<0x71270000>; 703def VNOR_V : LSX3R_VVV<0x71278000>; 704def VANDN_V : LSX3R_VVV<0x71280000>; 705def VORN_V : LSX3R_VVV<0x71288000>; 706 707def VANDI_B : LSX2RI8_VVI<0x73d00000>; 708def VORI_B : LSX2RI8_VVI<0x73d40000>; 709def VXORI_B : LSX2RI8_VVI<0x73d80000>; 710def VNORI_B : LSX2RI8_VVI<0x73dc0000>; 711 712def VSLL_B : LSX3R_VVV<0x70e80000>; 713def VSLL_H : LSX3R_VVV<0x70e88000>; 714def VSLL_W : LSX3R_VVV<0x70e90000>; 715def VSLL_D : LSX3R_VVV<0x70e98000>; 716def VSLLI_B : LSX2RI3_VVI<0x732c2000>; 717def VSLLI_H : LSX2RI4_VVI<0x732c4000>; 718def VSLLI_W : LSX2RI5_VVI<0x732c8000>; 719def VSLLI_D : LSX2RI6_VVI<0x732d0000>; 720 721def VSRL_B : LSX3R_VVV<0x70ea0000>; 722def VSRL_H : LSX3R_VVV<0x70ea8000>; 723def VSRL_W : LSX3R_VVV<0x70eb0000>; 724def VSRL_D : LSX3R_VVV<0x70eb8000>; 725def VSRLI_B : LSX2RI3_VVI<0x73302000>; 726def VSRLI_H : LSX2RI4_VVI<0x73304000>; 727def VSRLI_W : LSX2RI5_VVI<0x73308000>; 728def VSRLI_D : LSX2RI6_VVI<0x73310000>; 729 730def VSRA_B : LSX3R_VVV<0x70ec0000>; 731def VSRA_H : LSX3R_VVV<0x70ec8000>; 732def VSRA_W : LSX3R_VVV<0x70ed0000>; 733def VSRA_D : LSX3R_VVV<0x70ed8000>; 734def VSRAI_B : LSX2RI3_VVI<0x73342000>; 735def VSRAI_H : LSX2RI4_VVI<0x73344000>; 736def VSRAI_W : LSX2RI5_VVI<0x73348000>; 737def VSRAI_D : LSX2RI6_VVI<0x73350000>; 738 739def VROTR_B : LSX3R_VVV<0x70ee0000>; 740def VROTR_H : LSX3R_VVV<0x70ee8000>; 741def VROTR_W : LSX3R_VVV<0x70ef0000>; 742def VROTR_D : LSX3R_VVV<0x70ef8000>; 743def VROTRI_B : LSX2RI3_VVI<0x72a02000>; 744def VROTRI_H : LSX2RI4_VVI<0x72a04000>; 745def VROTRI_W : LSX2RI5_VVI<0x72a08000>; 746def VROTRI_D : LSX2RI6_VVI<0x72a10000>; 747 748def VSLLWIL_H_B : LSX2RI3_VVI<0x73082000>; 749def VSLLWIL_W_H : LSX2RI4_VVI<0x73084000>; 750def VSLLWIL_D_W : LSX2RI5_VVI<0x73088000>; 751def VEXTL_Q_D : LSX2R_VV<0x73090000>; 752def VSLLWIL_HU_BU : LSX2RI3_VVI<0x730c2000>; 753def VSLLWIL_WU_HU : LSX2RI4_VVI<0x730c4000>; 754def VSLLWIL_DU_WU : LSX2RI5_VVI<0x730c8000>; 755def VEXTL_QU_DU : LSX2R_VV<0x730d0000>; 756 757def VSRLR_B : LSX3R_VVV<0x70f00000>; 758def VSRLR_H : LSX3R_VVV<0x70f08000>; 759def VSRLR_W : LSX3R_VVV<0x70f10000>; 760def VSRLR_D : LSX3R_VVV<0x70f18000>; 761def VSRLRI_B : LSX2RI3_VVI<0x72a42000>; 762def VSRLRI_H : LSX2RI4_VVI<0x72a44000>; 763def VSRLRI_W : LSX2RI5_VVI<0x72a48000>; 764def VSRLRI_D : LSX2RI6_VVI<0x72a50000>; 765 766def VSRAR_B : LSX3R_VVV<0x70f20000>; 767def VSRAR_H : LSX3R_VVV<0x70f28000>; 768def VSRAR_W : LSX3R_VVV<0x70f30000>; 769def VSRAR_D : LSX3R_VVV<0x70f38000>; 770def VSRARI_B : LSX2RI3_VVI<0x72a82000>; 771def VSRARI_H : LSX2RI4_VVI<0x72a84000>; 772def VSRARI_W : LSX2RI5_VVI<0x72a88000>; 773def VSRARI_D : LSX2RI6_VVI<0x72a90000>; 774 775def VSRLN_B_H : LSX3R_VVV<0x70f48000>; 776def VSRLN_H_W : LSX3R_VVV<0x70f50000>; 777def VSRLN_W_D : LSX3R_VVV<0x70f58000>; 778def VSRAN_B_H : LSX3R_VVV<0x70f68000>; 779def VSRAN_H_W : LSX3R_VVV<0x70f70000>; 780def VSRAN_W_D : LSX3R_VVV<0x70f78000>; 781 782def VSRLNI_B_H : LSX2RI4_VVVI<0x73404000>; 783def VSRLNI_H_W : LSX2RI5_VVVI<0x73408000>; 784def VSRLNI_W_D : LSX2RI6_VVVI<0x73410000>; 785def VSRLNI_D_Q : LSX2RI7_VVVI<0x73420000>; 786def VSRANI_B_H : LSX2RI4_VVVI<0x73584000>; 787def VSRANI_H_W : LSX2RI5_VVVI<0x73588000>; 788def VSRANI_W_D : LSX2RI6_VVVI<0x73590000>; 789def VSRANI_D_Q : LSX2RI7_VVVI<0x735a0000>; 790 791def VSRLRN_B_H : LSX3R_VVV<0x70f88000>; 792def VSRLRN_H_W : LSX3R_VVV<0x70f90000>; 793def VSRLRN_W_D : LSX3R_VVV<0x70f98000>; 794def VSRARN_B_H : LSX3R_VVV<0x70fa8000>; 795def VSRARN_H_W : LSX3R_VVV<0x70fb0000>; 796def VSRARN_W_D : LSX3R_VVV<0x70fb8000>; 797 798def VSRLRNI_B_H : LSX2RI4_VVVI<0x73444000>; 799def VSRLRNI_H_W : LSX2RI5_VVVI<0x73448000>; 800def VSRLRNI_W_D : LSX2RI6_VVVI<0x73450000>; 801def VSRLRNI_D_Q : LSX2RI7_VVVI<0x73460000>; 802def VSRARNI_B_H : LSX2RI4_VVVI<0x735c4000>; 803def VSRARNI_H_W : LSX2RI5_VVVI<0x735c8000>; 804def VSRARNI_W_D : LSX2RI6_VVVI<0x735d0000>; 805def VSRARNI_D_Q : LSX2RI7_VVVI<0x735e0000>; 806 807def VSSRLN_B_H : LSX3R_VVV<0x70fc8000>; 808def VSSRLN_H_W : LSX3R_VVV<0x70fd0000>; 809def VSSRLN_W_D : LSX3R_VVV<0x70fd8000>; 810def VSSRAN_B_H : LSX3R_VVV<0x70fe8000>; 811def VSSRAN_H_W : LSX3R_VVV<0x70ff0000>; 812def VSSRAN_W_D : LSX3R_VVV<0x70ff8000>; 813def VSSRLN_BU_H : LSX3R_VVV<0x71048000>; 814def VSSRLN_HU_W : LSX3R_VVV<0x71050000>; 815def VSSRLN_WU_D : LSX3R_VVV<0x71058000>; 816def VSSRAN_BU_H : LSX3R_VVV<0x71068000>; 817def VSSRAN_HU_W : LSX3R_VVV<0x71070000>; 818def VSSRAN_WU_D : LSX3R_VVV<0x71078000>; 819 820def VSSRLNI_B_H : LSX2RI4_VVVI<0x73484000>; 821def VSSRLNI_H_W : LSX2RI5_VVVI<0x73488000>; 822def VSSRLNI_W_D : LSX2RI6_VVVI<0x73490000>; 823def VSSRLNI_D_Q : LSX2RI7_VVVI<0x734a0000>; 824def VSSRANI_B_H : LSX2RI4_VVVI<0x73604000>; 825def VSSRANI_H_W : LSX2RI5_VVVI<0x73608000>; 826def VSSRANI_W_D : LSX2RI6_VVVI<0x73610000>; 827def VSSRANI_D_Q : LSX2RI7_VVVI<0x73620000>; 828def VSSRLNI_BU_H : LSX2RI4_VVVI<0x734c4000>; 829def VSSRLNI_HU_W : LSX2RI5_VVVI<0x734c8000>; 830def VSSRLNI_WU_D : LSX2RI6_VVVI<0x734d0000>; 831def VSSRLNI_DU_Q : LSX2RI7_VVVI<0x734e0000>; 832def VSSRANI_BU_H : LSX2RI4_VVVI<0x73644000>; 833def VSSRANI_HU_W : LSX2RI5_VVVI<0x73648000>; 834def VSSRANI_WU_D : LSX2RI6_VVVI<0x73650000>; 835def VSSRANI_DU_Q : LSX2RI7_VVVI<0x73660000>; 836 837def VSSRLRN_B_H : LSX3R_VVV<0x71008000>; 838def VSSRLRN_H_W : LSX3R_VVV<0x71010000>; 839def VSSRLRN_W_D : LSX3R_VVV<0x71018000>; 840def VSSRARN_B_H : LSX3R_VVV<0x71028000>; 841def VSSRARN_H_W : LSX3R_VVV<0x71030000>; 842def VSSRARN_W_D : LSX3R_VVV<0x71038000>; 843def VSSRLRN_BU_H : LSX3R_VVV<0x71088000>; 844def VSSRLRN_HU_W : LSX3R_VVV<0x71090000>; 845def VSSRLRN_WU_D : LSX3R_VVV<0x71098000>; 846def VSSRARN_BU_H : LSX3R_VVV<0x710a8000>; 847def VSSRARN_HU_W : LSX3R_VVV<0x710b0000>; 848def VSSRARN_WU_D : LSX3R_VVV<0x710b8000>; 849 850def VSSRLRNI_B_H : LSX2RI4_VVVI<0x73504000>; 851def VSSRLRNI_H_W : LSX2RI5_VVVI<0x73508000>; 852def VSSRLRNI_W_D : LSX2RI6_VVVI<0x73510000>; 853def VSSRLRNI_D_Q : LSX2RI7_VVVI<0x73520000>; 854def VSSRARNI_B_H : LSX2RI4_VVVI<0x73684000>; 855def VSSRARNI_H_W : LSX2RI5_VVVI<0x73688000>; 856def VSSRARNI_W_D : LSX2RI6_VVVI<0x73690000>; 857def VSSRARNI_D_Q : LSX2RI7_VVVI<0x736a0000>; 858def VSSRLRNI_BU_H : LSX2RI4_VVVI<0x73544000>; 859def VSSRLRNI_HU_W : LSX2RI5_VVVI<0x73548000>; 860def VSSRLRNI_WU_D : LSX2RI6_VVVI<0x73550000>; 861def VSSRLRNI_DU_Q : LSX2RI7_VVVI<0x73560000>; 862def VSSRARNI_BU_H : LSX2RI4_VVVI<0x736c4000>; 863def VSSRARNI_HU_W : LSX2RI5_VVVI<0x736c8000>; 864def VSSRARNI_WU_D : LSX2RI6_VVVI<0x736d0000>; 865def VSSRARNI_DU_Q : LSX2RI7_VVVI<0x736e0000>; 866 867def VCLO_B : LSX2R_VV<0x729c0000>; 868def VCLO_H : LSX2R_VV<0x729c0400>; 869def VCLO_W : LSX2R_VV<0x729c0800>; 870def VCLO_D : LSX2R_VV<0x729c0c00>; 871def VCLZ_B : LSX2R_VV<0x729c1000>; 872def VCLZ_H : LSX2R_VV<0x729c1400>; 873def VCLZ_W : LSX2R_VV<0x729c1800>; 874def VCLZ_D : LSX2R_VV<0x729c1c00>; 875 876def VPCNT_B : LSX2R_VV<0x729c2000>; 877def VPCNT_H : LSX2R_VV<0x729c2400>; 878def VPCNT_W : LSX2R_VV<0x729c2800>; 879def VPCNT_D : LSX2R_VV<0x729c2c00>; 880 881def VBITCLR_B : LSX3R_VVV<0x710c0000>; 882def VBITCLR_H : LSX3R_VVV<0x710c8000>; 883def VBITCLR_W : LSX3R_VVV<0x710d0000>; 884def VBITCLR_D : LSX3R_VVV<0x710d8000>; 885def VBITCLRI_B : LSX2RI3_VVI<0x73102000>; 886def VBITCLRI_H : LSX2RI4_VVI<0x73104000>; 887def VBITCLRI_W : LSX2RI5_VVI<0x73108000>; 888def VBITCLRI_D : LSX2RI6_VVI<0x73110000>; 889 890def VBITSET_B : LSX3R_VVV<0x710e0000>; 891def VBITSET_H : LSX3R_VVV<0x710e8000>; 892def VBITSET_W : LSX3R_VVV<0x710f0000>; 893def VBITSET_D : LSX3R_VVV<0x710f8000>; 894def VBITSETI_B : LSX2RI3_VVI<0x73142000>; 895def VBITSETI_H : LSX2RI4_VVI<0x73144000>; 896def VBITSETI_W : LSX2RI5_VVI<0x73148000>; 897def VBITSETI_D : LSX2RI6_VVI<0x73150000>; 898 899def VBITREV_B : LSX3R_VVV<0x71100000>; 900def VBITREV_H : LSX3R_VVV<0x71108000>; 901def VBITREV_W : LSX3R_VVV<0x71110000>; 902def VBITREV_D : LSX3R_VVV<0x71118000>; 903def VBITREVI_B : LSX2RI3_VVI<0x73182000>; 904def VBITREVI_H : LSX2RI4_VVI<0x73184000>; 905def VBITREVI_W : LSX2RI5_VVI<0x73188000>; 906def VBITREVI_D : LSX2RI6_VVI<0x73190000>; 907 908def VFRSTP_B : LSX3R_VVVV<0x712b0000>; 909def VFRSTP_H : LSX3R_VVVV<0x712b8000>; 910def VFRSTPI_B : LSX2RI5_VVVI<0x729a0000>; 911def VFRSTPI_H : LSX2RI5_VVVI<0x729a8000>; 912 913def VFADD_S : LSX3R_VVV<0x71308000>; 914def VFADD_D : LSX3R_VVV<0x71310000>; 915def VFSUB_S : LSX3R_VVV<0x71328000>; 916def VFSUB_D : LSX3R_VVV<0x71330000>; 917def VFMUL_S : LSX3R_VVV<0x71388000>; 918def VFMUL_D : LSX3R_VVV<0x71390000>; 919def VFDIV_S : LSX3R_VVV<0x713a8000>; 920def VFDIV_D : LSX3R_VVV<0x713b0000>; 921 922def VFMADD_S : LSX4R_VVVV<0x09100000>; 923def VFMADD_D : LSX4R_VVVV<0x09200000>; 924def VFMSUB_S : LSX4R_VVVV<0x09500000>; 925def VFMSUB_D : LSX4R_VVVV<0x09600000>; 926def VFNMADD_S : LSX4R_VVVV<0x09900000>; 927def VFNMADD_D : LSX4R_VVVV<0x09a00000>; 928def VFNMSUB_S : LSX4R_VVVV<0x09d00000>; 929def VFNMSUB_D : LSX4R_VVVV<0x09e00000>; 930 931def VFMAX_S : LSX3R_VVV<0x713c8000>; 932def VFMAX_D : LSX3R_VVV<0x713d0000>; 933def VFMIN_S : LSX3R_VVV<0x713e8000>; 934def VFMIN_D : LSX3R_VVV<0x713f0000>; 935 936def VFMAXA_S : LSX3R_VVV<0x71408000>; 937def VFMAXA_D : LSX3R_VVV<0x71410000>; 938def VFMINA_S : LSX3R_VVV<0x71428000>; 939def VFMINA_D : LSX3R_VVV<0x71430000>; 940 941def VFLOGB_S : LSX2R_VV<0x729cc400>; 942def VFLOGB_D : LSX2R_VV<0x729cc800>; 943 944def VFCLASS_S : LSX2R_VV<0x729cd400>; 945def VFCLASS_D : LSX2R_VV<0x729cd800>; 946 947def VFSQRT_S : LSX2R_VV<0x729ce400>; 948def VFSQRT_D : LSX2R_VV<0x729ce800>; 949def VFRECIP_S : LSX2R_VV<0x729cf400>; 950def VFRECIP_D : LSX2R_VV<0x729cf800>; 951def VFRSQRT_S : LSX2R_VV<0x729d0400>; 952def VFRSQRT_D : LSX2R_VV<0x729d0800>; 953def VFRECIPE_S : LSX2R_VV<0x729d1400>; 954def VFRECIPE_D : LSX2R_VV<0x729d1800>; 955def VFRSQRTE_S : LSX2R_VV<0x729d2400>; 956def VFRSQRTE_D : LSX2R_VV<0x729d2800>; 957 958def VFCVTL_S_H : LSX2R_VV<0x729de800>; 959def VFCVTH_S_H : LSX2R_VV<0x729dec00>; 960def VFCVTL_D_S : LSX2R_VV<0x729df000>; 961def VFCVTH_D_S : LSX2R_VV<0x729df400>; 962def VFCVT_H_S : LSX3R_VVV<0x71460000>; 963def VFCVT_S_D : LSX3R_VVV<0x71468000>; 964 965def VFRINTRNE_S : LSX2R_VV<0x729d7400>; 966def VFRINTRNE_D : LSX2R_VV<0x729d7800>; 967def VFRINTRZ_S : LSX2R_VV<0x729d6400>; 968def VFRINTRZ_D : LSX2R_VV<0x729d6800>; 969def VFRINTRP_S : LSX2R_VV<0x729d5400>; 970def VFRINTRP_D : LSX2R_VV<0x729d5800>; 971def VFRINTRM_S : LSX2R_VV<0x729d4400>; 972def VFRINTRM_D : LSX2R_VV<0x729d4800>; 973def VFRINT_S : LSX2R_VV<0x729d3400>; 974def VFRINT_D : LSX2R_VV<0x729d3800>; 975 976def VFTINTRNE_W_S : LSX2R_VV<0x729e5000>; 977def VFTINTRNE_L_D : LSX2R_VV<0x729e5400>; 978def VFTINTRZ_W_S : LSX2R_VV<0x729e4800>; 979def VFTINTRZ_L_D : LSX2R_VV<0x729e4c00>; 980def VFTINTRP_W_S : LSX2R_VV<0x729e4000>; 981def VFTINTRP_L_D : LSX2R_VV<0x729e4400>; 982def VFTINTRM_W_S : LSX2R_VV<0x729e3800>; 983def VFTINTRM_L_D : LSX2R_VV<0x729e3c00>; 984def VFTINT_W_S : LSX2R_VV<0x729e3000>; 985def VFTINT_L_D : LSX2R_VV<0x729e3400>; 986def VFTINTRZ_WU_S : LSX2R_VV<0x729e7000>; 987def VFTINTRZ_LU_D : LSX2R_VV<0x729e7400>; 988def VFTINT_WU_S : LSX2R_VV<0x729e5800>; 989def VFTINT_LU_D : LSX2R_VV<0x729e5c00>; 990 991def VFTINTRNE_W_D : LSX3R_VVV<0x714b8000>; 992def VFTINTRZ_W_D : LSX3R_VVV<0x714b0000>; 993def VFTINTRP_W_D : LSX3R_VVV<0x714a8000>; 994def VFTINTRM_W_D : LSX3R_VVV<0x714a0000>; 995def VFTINT_W_D : LSX3R_VVV<0x71498000>; 996 997def VFTINTRNEL_L_S : LSX2R_VV<0x729ea000>; 998def VFTINTRNEH_L_S : LSX2R_VV<0x729ea400>; 999def VFTINTRZL_L_S : LSX2R_VV<0x729e9800>; 1000def VFTINTRZH_L_S : LSX2R_VV<0x729e9c00>; 1001def VFTINTRPL_L_S : LSX2R_VV<0x729e9000>; 1002def VFTINTRPH_L_S : LSX2R_VV<0x729e9400>; 1003def VFTINTRML_L_S : LSX2R_VV<0x729e8800>; 1004def VFTINTRMH_L_S : LSX2R_VV<0x729e8c00>; 1005def VFTINTL_L_S : LSX2R_VV<0x729e8000>; 1006def VFTINTH_L_S : LSX2R_VV<0x729e8400>; 1007 1008def VFFINT_S_W : LSX2R_VV<0x729e0000>; 1009def VFFINT_D_L : LSX2R_VV<0x729e0800>; 1010def VFFINT_S_WU : LSX2R_VV<0x729e0400>; 1011def VFFINT_D_LU : LSX2R_VV<0x729e0c00>; 1012def VFFINTL_D_W : LSX2R_VV<0x729e1000>; 1013def VFFINTH_D_W : LSX2R_VV<0x729e1400>; 1014def VFFINT_S_L : LSX3R_VVV<0x71480000>; 1015 1016def VSEQ_B : LSX3R_VVV<0x70000000>; 1017def VSEQ_H : LSX3R_VVV<0x70008000>; 1018def VSEQ_W : LSX3R_VVV<0x70010000>; 1019def VSEQ_D : LSX3R_VVV<0x70018000>; 1020def VSEQI_B : LSX2RI5_VVI<0x72800000, simm5>; 1021def VSEQI_H : LSX2RI5_VVI<0x72808000, simm5>; 1022def VSEQI_W : LSX2RI5_VVI<0x72810000, simm5>; 1023def VSEQI_D : LSX2RI5_VVI<0x72818000, simm5>; 1024 1025def VSLE_B : LSX3R_VVV<0x70020000>; 1026def VSLE_H : LSX3R_VVV<0x70028000>; 1027def VSLE_W : LSX3R_VVV<0x70030000>; 1028def VSLE_D : LSX3R_VVV<0x70038000>; 1029def VSLEI_B : LSX2RI5_VVI<0x72820000, simm5>; 1030def VSLEI_H : LSX2RI5_VVI<0x72828000, simm5>; 1031def VSLEI_W : LSX2RI5_VVI<0x72830000, simm5>; 1032def VSLEI_D : LSX2RI5_VVI<0x72838000, simm5>; 1033 1034def VSLE_BU : LSX3R_VVV<0x70040000>; 1035def VSLE_HU : LSX3R_VVV<0x70048000>; 1036def VSLE_WU : LSX3R_VVV<0x70050000>; 1037def VSLE_DU : LSX3R_VVV<0x70058000>; 1038def VSLEI_BU : LSX2RI5_VVI<0x72840000>; 1039def VSLEI_HU : LSX2RI5_VVI<0x72848000>; 1040def VSLEI_WU : LSX2RI5_VVI<0x72850000>; 1041def VSLEI_DU : LSX2RI5_VVI<0x72858000>; 1042 1043def VSLT_B : LSX3R_VVV<0x70060000>; 1044def VSLT_H : LSX3R_VVV<0x70068000>; 1045def VSLT_W : LSX3R_VVV<0x70070000>; 1046def VSLT_D : LSX3R_VVV<0x70078000>; 1047def VSLTI_B : LSX2RI5_VVI<0x72860000, simm5>; 1048def VSLTI_H : LSX2RI5_VVI<0x72868000, simm5>; 1049def VSLTI_W : LSX2RI5_VVI<0x72870000, simm5>; 1050def VSLTI_D : LSX2RI5_VVI<0x72878000, simm5>; 1051 1052def VSLT_BU : LSX3R_VVV<0x70080000>; 1053def VSLT_HU : LSX3R_VVV<0x70088000>; 1054def VSLT_WU : LSX3R_VVV<0x70090000>; 1055def VSLT_DU : LSX3R_VVV<0x70098000>; 1056def VSLTI_BU : LSX2RI5_VVI<0x72880000>; 1057def VSLTI_HU : LSX2RI5_VVI<0x72888000>; 1058def VSLTI_WU : LSX2RI5_VVI<0x72890000>; 1059def VSLTI_DU : LSX2RI5_VVI<0x72898000>; 1060 1061def VFCMP_CAF_S : LSX3R_VVV<0x0c500000>; 1062def VFCMP_SAF_S : LSX3R_VVV<0x0c508000>; 1063def VFCMP_CLT_S : LSX3R_VVV<0x0c510000>; 1064def VFCMP_SLT_S : LSX3R_VVV<0x0c518000>; 1065def VFCMP_CEQ_S : LSX3R_VVV<0x0c520000>; 1066def VFCMP_SEQ_S : LSX3R_VVV<0x0c528000>; 1067def VFCMP_CLE_S : LSX3R_VVV<0x0c530000>; 1068def VFCMP_SLE_S : LSX3R_VVV<0x0c538000>; 1069def VFCMP_CUN_S : LSX3R_VVV<0x0c540000>; 1070def VFCMP_SUN_S : LSX3R_VVV<0x0c548000>; 1071def VFCMP_CULT_S : LSX3R_VVV<0x0c550000>; 1072def VFCMP_SULT_S : LSX3R_VVV<0x0c558000>; 1073def VFCMP_CUEQ_S : LSX3R_VVV<0x0c560000>; 1074def VFCMP_SUEQ_S : LSX3R_VVV<0x0c568000>; 1075def VFCMP_CULE_S : LSX3R_VVV<0x0c570000>; 1076def VFCMP_SULE_S : LSX3R_VVV<0x0c578000>; 1077def VFCMP_CNE_S : LSX3R_VVV<0x0c580000>; 1078def VFCMP_SNE_S : LSX3R_VVV<0x0c588000>; 1079def VFCMP_COR_S : LSX3R_VVV<0x0c5a0000>; 1080def VFCMP_SOR_S : LSX3R_VVV<0x0c5a8000>; 1081def VFCMP_CUNE_S : LSX3R_VVV<0x0c5c0000>; 1082def VFCMP_SUNE_S : LSX3R_VVV<0x0c5c8000>; 1083 1084def VFCMP_CAF_D : LSX3R_VVV<0x0c600000>; 1085def VFCMP_SAF_D : LSX3R_VVV<0x0c608000>; 1086def VFCMP_CLT_D : LSX3R_VVV<0x0c610000>; 1087def VFCMP_SLT_D : LSX3R_VVV<0x0c618000>; 1088def VFCMP_CEQ_D : LSX3R_VVV<0x0c620000>; 1089def VFCMP_SEQ_D : LSX3R_VVV<0x0c628000>; 1090def VFCMP_CLE_D : LSX3R_VVV<0x0c630000>; 1091def VFCMP_SLE_D : LSX3R_VVV<0x0c638000>; 1092def VFCMP_CUN_D : LSX3R_VVV<0x0c640000>; 1093def VFCMP_SUN_D : LSX3R_VVV<0x0c648000>; 1094def VFCMP_CULT_D : LSX3R_VVV<0x0c650000>; 1095def VFCMP_SULT_D : LSX3R_VVV<0x0c658000>; 1096def VFCMP_CUEQ_D : LSX3R_VVV<0x0c660000>; 1097def VFCMP_SUEQ_D : LSX3R_VVV<0x0c668000>; 1098def VFCMP_CULE_D : LSX3R_VVV<0x0c670000>; 1099def VFCMP_SULE_D : LSX3R_VVV<0x0c678000>; 1100def VFCMP_CNE_D : LSX3R_VVV<0x0c680000>; 1101def VFCMP_SNE_D : LSX3R_VVV<0x0c688000>; 1102def VFCMP_COR_D : LSX3R_VVV<0x0c6a0000>; 1103def VFCMP_SOR_D : LSX3R_VVV<0x0c6a8000>; 1104def VFCMP_CUNE_D : LSX3R_VVV<0x0c6c0000>; 1105def VFCMP_SUNE_D : LSX3R_VVV<0x0c6c8000>; 1106 1107def VBITSEL_V : LSX4R_VVVV<0x0d100000>; 1108 1109def VBITSELI_B : LSX2RI8_VVVI<0x73c40000>; 1110 1111def VSETEQZ_V : LSX2R_CV<0x729c9800>; 1112def VSETNEZ_V : LSX2R_CV<0x729c9c00>; 1113def VSETANYEQZ_B : LSX2R_CV<0x729ca000>; 1114def VSETANYEQZ_H : LSX2R_CV<0x729ca400>; 1115def VSETANYEQZ_W : LSX2R_CV<0x729ca800>; 1116def VSETANYEQZ_D : LSX2R_CV<0x729cac00>; 1117def VSETALLNEZ_B : LSX2R_CV<0x729cb000>; 1118def VSETALLNEZ_H : LSX2R_CV<0x729cb400>; 1119def VSETALLNEZ_W : LSX2R_CV<0x729cb800>; 1120def VSETALLNEZ_D : LSX2R_CV<0x729cbc00>; 1121 1122def VINSGR2VR_B : LSX2RI4_VVRI<0x72eb8000>; 1123def VINSGR2VR_H : LSX2RI3_VVRI<0x72ebc000>; 1124def VINSGR2VR_W : LSX2RI2_VVRI<0x72ebe000>; 1125def VINSGR2VR_D : LSX2RI1_VVRI<0x72ebf000>; 1126def VPICKVE2GR_B : LSX2RI4_RVI<0x72ef8000>; 1127def VPICKVE2GR_H : LSX2RI3_RVI<0x72efc000>; 1128def VPICKVE2GR_W : LSX2RI2_RVI<0x72efe000>; 1129def VPICKVE2GR_D : LSX2RI1_RVI<0x72eff000>; 1130def VPICKVE2GR_BU : LSX2RI4_RVI<0x72f38000>; 1131def VPICKVE2GR_HU : LSX2RI3_RVI<0x72f3c000>; 1132def VPICKVE2GR_WU : LSX2RI2_RVI<0x72f3e000>; 1133def VPICKVE2GR_DU : LSX2RI1_RVI<0x72f3f000>; 1134 1135def VREPLGR2VR_B : LSX2R_VR<0x729f0000>; 1136def VREPLGR2VR_H : LSX2R_VR<0x729f0400>; 1137def VREPLGR2VR_W : LSX2R_VR<0x729f0800>; 1138def VREPLGR2VR_D : LSX2R_VR<0x729f0c00>; 1139 1140def VREPLVE_B : LSX3R_VVR<0x71220000>; 1141def VREPLVE_H : LSX3R_VVR<0x71228000>; 1142def VREPLVE_W : LSX3R_VVR<0x71230000>; 1143def VREPLVE_D : LSX3R_VVR<0x71238000>; 1144def VREPLVEI_B : LSX2RI4_VVI<0x72f78000>; 1145def VREPLVEI_H : LSX2RI3_VVI<0x72f7c000>; 1146def VREPLVEI_W : LSX2RI2_VVI<0x72f7e000>; 1147def VREPLVEI_D : LSX2RI1_VVI<0x72f7f000>; 1148 1149def VBSLL_V : LSX2RI5_VVI<0x728e0000>; 1150def VBSRL_V : LSX2RI5_VVI<0x728e8000>; 1151 1152def VPACKEV_B : LSX3R_VVV<0x71160000>; 1153def VPACKEV_H : LSX3R_VVV<0x71168000>; 1154def VPACKEV_W : LSX3R_VVV<0x71170000>; 1155def VPACKEV_D : LSX3R_VVV<0x71178000>; 1156def VPACKOD_B : LSX3R_VVV<0x71180000>; 1157def VPACKOD_H : LSX3R_VVV<0x71188000>; 1158def VPACKOD_W : LSX3R_VVV<0x71190000>; 1159def VPACKOD_D : LSX3R_VVV<0x71198000>; 1160 1161def VPICKEV_B : LSX3R_VVV<0x711e0000>; 1162def VPICKEV_H : LSX3R_VVV<0x711e8000>; 1163def VPICKEV_W : LSX3R_VVV<0x711f0000>; 1164def VPICKEV_D : LSX3R_VVV<0x711f8000>; 1165def VPICKOD_B : LSX3R_VVV<0x71200000>; 1166def VPICKOD_H : LSX3R_VVV<0x71208000>; 1167def VPICKOD_W : LSX3R_VVV<0x71210000>; 1168def VPICKOD_D : LSX3R_VVV<0x71218000>; 1169 1170def VILVL_B : LSX3R_VVV<0x711a0000>; 1171def VILVL_H : LSX3R_VVV<0x711a8000>; 1172def VILVL_W : LSX3R_VVV<0x711b0000>; 1173def VILVL_D : LSX3R_VVV<0x711b8000>; 1174def VILVH_B : LSX3R_VVV<0x711c0000>; 1175def VILVH_H : LSX3R_VVV<0x711c8000>; 1176def VILVH_W : LSX3R_VVV<0x711d0000>; 1177def VILVH_D : LSX3R_VVV<0x711d8000>; 1178 1179def VSHUF_B : LSX4R_VVVV<0x0d500000>; 1180 1181def VSHUF_H : LSX3R_VVVV<0x717a8000>; 1182def VSHUF_W : LSX3R_VVVV<0x717b0000>; 1183def VSHUF_D : LSX3R_VVVV<0x717b8000>; 1184 1185def VSHUF4I_B : LSX2RI8_VVI<0x73900000>; 1186def VSHUF4I_H : LSX2RI8_VVI<0x73940000>; 1187def VSHUF4I_W : LSX2RI8_VVI<0x73980000>; 1188def VSHUF4I_D : LSX2RI8_VVVI<0x739c0000>; 1189 1190def VPERMI_W : LSX2RI8_VVVI<0x73e40000>; 1191 1192def VEXTRINS_D : LSX2RI8_VVVI<0x73800000>; 1193def VEXTRINS_W : LSX2RI8_VVVI<0x73840000>; 1194def VEXTRINS_H : LSX2RI8_VVVI<0x73880000>; 1195def VEXTRINS_B : LSX2RI8_VVVI<0x738c0000>; 1196} // mayLoad = 0, mayStore = 0 1197 1198let mayLoad = 1, mayStore = 0 in { 1199def VLD : LSX2RI12_Load<0x2c000000>; 1200def VLDX : LSX3R_Load<0x38400000>; 1201 1202def VLDREPL_B : LSX2RI12_Load<0x30800000>; 1203def VLDREPL_H : LSX2RI11_Load<0x30400000>; 1204def VLDREPL_W : LSX2RI10_Load<0x30200000>; 1205def VLDREPL_D : LSX2RI9_Load<0x30100000>; 1206} // mayLoad = 1, mayStore = 0 1207 1208let mayLoad = 0, mayStore = 1 in { 1209def VST : LSX2RI12_Store<0x2c400000>; 1210def VSTX : LSX3R_Store<0x38440000>; 1211 1212def VSTELM_B : LSX2RI8I4_VRII<0x31800000>; 1213def VSTELM_H : LSX2RI8I3_VRII<0x31400000, simm8_lsl1>; 1214def VSTELM_W : LSX2RI8I2_VRII<0x31200000, simm8_lsl2>; 1215def VSTELM_D : LSX2RI8I1_VRII<0x31100000, simm8_lsl3>; 1216} // mayLoad = 0, mayStore = 1 1217 1218} // hasSideEffects = 0, Predicates = [HasExtLSX] 1219 1220/// Pseudo-instructions 1221 1222let Predicates = [HasExtLSX] in { 1223 1224let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, 1225 isAsmParserOnly = 1 in { 1226def PseudoVREPLI_B : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1227 "vrepli.b", "$vd, $imm">; 1228def PseudoVREPLI_H : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1229 "vrepli.h", "$vd, $imm">; 1230def PseudoVREPLI_W : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1231 "vrepli.w", "$vd, $imm">; 1232def PseudoVREPLI_D : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1233 "vrepli.d", "$vd, $imm">; 1234} 1235 1236def PseudoVBNZ_B : VecCond<loongarch_vall_nonzero, v16i8>; 1237def PseudoVBNZ_H : VecCond<loongarch_vall_nonzero, v8i16>; 1238def PseudoVBNZ_W : VecCond<loongarch_vall_nonzero, v4i32>; 1239def PseudoVBNZ_D : VecCond<loongarch_vall_nonzero, v2i64>; 1240def PseudoVBNZ : VecCond<loongarch_vany_nonzero, v16i8>; 1241 1242def PseudoVBZ_B : VecCond<loongarch_vall_zero, v16i8>; 1243def PseudoVBZ_H : VecCond<loongarch_vall_zero, v8i16>; 1244def PseudoVBZ_W : VecCond<loongarch_vall_zero, v4i32>; 1245def PseudoVBZ_D : VecCond<loongarch_vall_zero, v2i64>; 1246def PseudoVBZ : VecCond<loongarch_vany_zero, v16i8>; 1247 1248let usesCustomInserter = 1 in 1249def PseudoCTPOP : Pseudo<(outs GPR:$rd), (ins GPR:$rj), 1250 [(set GPR:$rd, (ctpop GPR:$rj))]>; 1251 1252} // Predicates = [HasExtLSX] 1253 1254multiclass PatVr<SDPatternOperator OpNode, string Inst> { 1255 def : Pat<(v16i8 (OpNode (v16i8 LSX128:$vj))), 1256 (!cast<LAInst>(Inst#"_B") LSX128:$vj)>; 1257 def : Pat<(v8i16 (OpNode (v8i16 LSX128:$vj))), 1258 (!cast<LAInst>(Inst#"_H") LSX128:$vj)>; 1259 def : Pat<(v4i32 (OpNode (v4i32 LSX128:$vj))), 1260 (!cast<LAInst>(Inst#"_W") LSX128:$vj)>; 1261 def : Pat<(v2i64 (OpNode (v2i64 LSX128:$vj))), 1262 (!cast<LAInst>(Inst#"_D") LSX128:$vj)>; 1263} 1264 1265multiclass PatVrF<SDPatternOperator OpNode, string Inst> { 1266 def : Pat<(v4f32 (OpNode (v4f32 LSX128:$vj))), 1267 (!cast<LAInst>(Inst#"_S") LSX128:$vj)>; 1268 def : Pat<(v2f64 (OpNode (v2f64 LSX128:$vj))), 1269 (!cast<LAInst>(Inst#"_D") LSX128:$vj)>; 1270} 1271 1272multiclass PatVrVr<SDPatternOperator OpNode, string Inst> { 1273 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1274 (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>; 1275 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1276 (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>; 1277 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1278 (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>; 1279 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1280 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1281} 1282 1283multiclass PatVrVrF<SDPatternOperator OpNode, string Inst> { 1284 def : Pat<(OpNode (v4f32 LSX128:$vj), (v4f32 LSX128:$vk)), 1285 (!cast<LAInst>(Inst#"_S") LSX128:$vj, LSX128:$vk)>; 1286 def : Pat<(OpNode (v2f64 LSX128:$vj), (v2f64 LSX128:$vk)), 1287 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1288} 1289 1290multiclass PatVrVrU<SDPatternOperator OpNode, string Inst> { 1291 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1292 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, LSX128:$vk)>; 1293 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1294 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, LSX128:$vk)>; 1295 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1296 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, LSX128:$vk)>; 1297 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1298 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, LSX128:$vk)>; 1299} 1300 1301multiclass PatVrSimm5<SDPatternOperator OpNode, string Inst> { 1302 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 (SplatPat_simm5 simm5:$imm))), 1303 (!cast<LAInst>(Inst#"_B") LSX128:$vj, simm5:$imm)>; 1304 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_simm5 simm5:$imm))), 1305 (!cast<LAInst>(Inst#"_H") LSX128:$vj, simm5:$imm)>; 1306 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_simm5 simm5:$imm))), 1307 (!cast<LAInst>(Inst#"_W") LSX128:$vj, simm5:$imm)>; 1308 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 (SplatPat_simm5 simm5:$imm))), 1309 (!cast<LAInst>(Inst#"_D") LSX128:$vj, simm5:$imm)>; 1310} 1311 1312multiclass PatVrUimm5<SDPatternOperator OpNode, string Inst> { 1313 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm5 uimm5:$imm))), 1314 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, uimm5:$imm)>; 1315 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_uimm5 uimm5:$imm))), 1316 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, uimm5:$imm)>; 1317 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_uimm5 uimm5:$imm))), 1318 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, uimm5:$imm)>; 1319 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 (SplatPat_uimm5 uimm5:$imm))), 1320 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, uimm5:$imm)>; 1321} 1322 1323multiclass PatVrVrVr<SDPatternOperator OpNode, string Inst> { 1324 def : Pat<(OpNode (v16i8 LSX128:$vd), (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1325 (!cast<LAInst>(Inst#"_B") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1326 def : Pat<(OpNode (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1327 (!cast<LAInst>(Inst#"_H") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1328 def : Pat<(OpNode (v4i32 LSX128:$vd), (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1329 (!cast<LAInst>(Inst#"_W") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1330 def : Pat<(OpNode (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1331 (!cast<LAInst>(Inst#"_D") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1332} 1333 1334multiclass PatShiftVrVr<SDPatternOperator OpNode, string Inst> { 1335 def : Pat<(OpNode (v16i8 LSX128:$vj), (and vsplati8_imm_eq_7, 1336 (v16i8 LSX128:$vk))), 1337 (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>; 1338 def : Pat<(OpNode (v8i16 LSX128:$vj), (and vsplati16_imm_eq_15, 1339 (v8i16 LSX128:$vk))), 1340 (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>; 1341 def : Pat<(OpNode (v4i32 LSX128:$vj), (and vsplati32_imm_eq_31, 1342 (v4i32 LSX128:$vk))), 1343 (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>; 1344 def : Pat<(OpNode (v2i64 LSX128:$vj), (and vsplati64_imm_eq_63, 1345 (v2i64 LSX128:$vk))), 1346 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1347} 1348 1349multiclass PatShiftVrUimm<SDPatternOperator OpNode, string Inst> { 1350 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm3 uimm3:$imm))), 1351 (!cast<LAInst>(Inst#"_B") LSX128:$vj, uimm3:$imm)>; 1352 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_uimm4 uimm4:$imm))), 1353 (!cast<LAInst>(Inst#"_H") LSX128:$vj, uimm4:$imm)>; 1354 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_uimm5 uimm5:$imm))), 1355 (!cast<LAInst>(Inst#"_W") LSX128:$vj, uimm5:$imm)>; 1356 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 (SplatPat_uimm6 uimm6:$imm))), 1357 (!cast<LAInst>(Inst#"_D") LSX128:$vj, uimm6:$imm)>; 1358} 1359 1360multiclass PatCCVrSimm5<CondCode CC, string Inst> { 1361 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), 1362 (v16i8 (SplatPat_simm5 simm5:$imm)), CC)), 1363 (!cast<LAInst>(Inst#"_B") LSX128:$vj, simm5:$imm)>; 1364 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), 1365 (v8i16 (SplatPat_simm5 simm5:$imm)), CC)), 1366 (!cast<LAInst>(Inst#"_H") LSX128:$vj, simm5:$imm)>; 1367 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), 1368 (v4i32 (SplatPat_simm5 simm5:$imm)), CC)), 1369 (!cast<LAInst>(Inst#"_W") LSX128:$vj, simm5:$imm)>; 1370 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), 1371 (v2i64 (SplatPat_simm5 simm5:$imm)), CC)), 1372 (!cast<LAInst>(Inst#"_D") LSX128:$vj, simm5:$imm)>; 1373} 1374 1375multiclass PatCCVrUimm5<CondCode CC, string Inst> { 1376 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), 1377 (v16i8 (SplatPat_uimm5 uimm5:$imm)), CC)), 1378 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, uimm5:$imm)>; 1379 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), 1380 (v8i16 (SplatPat_uimm5 uimm5:$imm)), CC)), 1381 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, uimm5:$imm)>; 1382 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), 1383 (v4i32 (SplatPat_uimm5 uimm5:$imm)), CC)), 1384 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, uimm5:$imm)>; 1385 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), 1386 (v2i64 (SplatPat_uimm5 uimm5:$imm)), CC)), 1387 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, uimm5:$imm)>; 1388} 1389 1390multiclass PatCCVrVr<CondCode CC, string Inst> { 1391 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), (v16i8 LSX128:$vk), CC)), 1392 (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>; 1393 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), (v8i16 LSX128:$vk), CC)), 1394 (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>; 1395 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), (v4i32 LSX128:$vk), CC)), 1396 (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>; 1397 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), (v2i64 LSX128:$vk), CC)), 1398 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1399} 1400 1401multiclass PatCCVrVrU<CondCode CC, string Inst> { 1402 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), (v16i8 LSX128:$vk), CC)), 1403 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, LSX128:$vk)>; 1404 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), (v8i16 LSX128:$vk), CC)), 1405 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, LSX128:$vk)>; 1406 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), (v4i32 LSX128:$vk), CC)), 1407 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, LSX128:$vk)>; 1408 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), (v2i64 LSX128:$vk), CC)), 1409 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, LSX128:$vk)>; 1410} 1411 1412multiclass PatCCVrVrF<CondCode CC, string Inst> { 1413 def : Pat<(v4i32 (setcc (v4f32 LSX128:$vj), (v4f32 LSX128:$vk), CC)), 1414 (!cast<LAInst>(Inst#"_S") LSX128:$vj, LSX128:$vk)>; 1415 def : Pat<(v2i64 (setcc (v2f64 LSX128:$vj), (v2f64 LSX128:$vk), CC)), 1416 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1417} 1418 1419let Predicates = [HasExtLSX] in { 1420 1421// VADD_{B/H/W/D} 1422defm : PatVrVr<add, "VADD">; 1423// VSUB_{B/H/W/D} 1424defm : PatVrVr<sub, "VSUB">; 1425 1426// VADDI_{B/H/W/D}U 1427defm : PatVrUimm5<add, "VADDI">; 1428// VSUBI_{B/H/W/D}U 1429defm : PatVrUimm5<sub, "VSUBI">; 1430 1431// VNEG_{B/H/W/D} 1432def : Pat<(sub immAllZerosV, (v16i8 LSX128:$vj)), (VNEG_B LSX128:$vj)>; 1433def : Pat<(sub immAllZerosV, (v8i16 LSX128:$vj)), (VNEG_H LSX128:$vj)>; 1434def : Pat<(sub immAllZerosV, (v4i32 LSX128:$vj)), (VNEG_W LSX128:$vj)>; 1435def : Pat<(sub immAllZerosV, (v2i64 LSX128:$vj)), (VNEG_D LSX128:$vj)>; 1436 1437// VMAX[I]_{B/H/W/D}[U] 1438defm : PatVrVr<smax, "VMAX">; 1439defm : PatVrVrU<umax, "VMAX">; 1440defm : PatVrSimm5<smax, "VMAXI">; 1441defm : PatVrUimm5<umax, "VMAXI">; 1442 1443// VMIN[I]_{B/H/W/D}[U] 1444defm : PatVrVr<smin, "VMIN">; 1445defm : PatVrVrU<umin, "VMIN">; 1446defm : PatVrSimm5<smin, "VMINI">; 1447defm : PatVrUimm5<umin, "VMINI">; 1448 1449// VMUL_{B/H/W/D} 1450defm : PatVrVr<mul, "VMUL">; 1451 1452// VMUH_{B/H/W/D}[U] 1453defm : PatVrVr<mulhs, "VMUH">; 1454defm : PatVrVrU<mulhu, "VMUH">; 1455 1456// VMADD_{B/H/W/D} 1457defm : PatVrVrVr<muladd, "VMADD">; 1458// VMSUB_{B/H/W/D} 1459defm : PatVrVrVr<mulsub, "VMSUB">; 1460 1461// VDIV_{B/H/W/D}[U] 1462defm : PatVrVr<sdiv, "VDIV">; 1463defm : PatVrVrU<udiv, "VDIV">; 1464 1465// VMOD_{B/H/W/D}[U] 1466defm : PatVrVr<srem, "VMOD">; 1467defm : PatVrVrU<urem, "VMOD">; 1468 1469// VAND_V 1470foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1471def : Pat<(and (vt LSX128:$vj), (vt LSX128:$vk)), 1472 (VAND_V LSX128:$vj, LSX128:$vk)>; 1473// VOR_V 1474foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1475def : Pat<(or (vt LSX128:$vj), (vt LSX128:$vk)), 1476 (VOR_V LSX128:$vj, LSX128:$vk)>; 1477// VXOR_V 1478foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1479def : Pat<(xor (vt LSX128:$vj), (vt LSX128:$vk)), 1480 (VXOR_V LSX128:$vj, LSX128:$vk)>; 1481// VNOR_V 1482foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1483def : Pat<(vnot (or (vt LSX128:$vj), (vt LSX128:$vk))), 1484 (VNOR_V LSX128:$vj, LSX128:$vk)>; 1485 1486// VANDI_B 1487def : Pat<(and (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))), 1488 (VANDI_B LSX128:$vj, uimm8:$imm)>; 1489// VORI_B 1490def : Pat<(or (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))), 1491 (VORI_B LSX128:$vj, uimm8:$imm)>; 1492 1493// VXORI_B 1494def : Pat<(xor (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))), 1495 (VXORI_B LSX128:$vj, uimm8:$imm)>; 1496 1497// VSLL[I]_{B/H/W/D} 1498defm : PatVrVr<shl, "VSLL">; 1499defm : PatShiftVrVr<shl, "VSLL">; 1500defm : PatShiftVrUimm<shl, "VSLLI">; 1501 1502// VSRL[I]_{B/H/W/D} 1503defm : PatVrVr<srl, "VSRL">; 1504defm : PatShiftVrVr<srl, "VSRL">; 1505defm : PatShiftVrUimm<srl, "VSRLI">; 1506 1507// VSRA[I]_{B/H/W/D} 1508defm : PatVrVr<sra, "VSRA">; 1509defm : PatShiftVrVr<sra, "VSRA">; 1510defm : PatShiftVrUimm<sra, "VSRAI">; 1511 1512// VCLZ_{B/H/W/D} 1513defm : PatVr<ctlz, "VCLZ">; 1514 1515// VPCNT_{B/H/W/D} 1516defm : PatVr<ctpop, "VPCNT">; 1517 1518// VBITCLR_{B/H/W/D} 1519def : Pat<(and v16i8:$vj, (vnot (shl vsplat_imm_eq_1, v16i8:$vk))), 1520 (v16i8 (VBITCLR_B v16i8:$vj, v16i8:$vk))>; 1521def : Pat<(and v8i16:$vj, (vnot (shl vsplat_imm_eq_1, v8i16:$vk))), 1522 (v8i16 (VBITCLR_H v8i16:$vj, v8i16:$vk))>; 1523def : Pat<(and v4i32:$vj, (vnot (shl vsplat_imm_eq_1, v4i32:$vk))), 1524 (v4i32 (VBITCLR_W v4i32:$vj, v4i32:$vk))>; 1525def : Pat<(and v2i64:$vj, (vnot (shl vsplat_imm_eq_1, v2i64:$vk))), 1526 (v2i64 (VBITCLR_D v2i64:$vj, v2i64:$vk))>; 1527def : Pat<(and v16i8:$vj, (vnot (shl vsplat_imm_eq_1, 1528 (vsplati8imm7 v16i8:$vk)))), 1529 (v16i8 (VBITCLR_B v16i8:$vj, v16i8:$vk))>; 1530def : Pat<(and v8i16:$vj, (vnot (shl vsplat_imm_eq_1, 1531 (vsplati16imm15 v8i16:$vk)))), 1532 (v8i16 (VBITCLR_H v8i16:$vj, v8i16:$vk))>; 1533def : Pat<(and v4i32:$vj, (vnot (shl vsplat_imm_eq_1, 1534 (vsplati32imm31 v4i32:$vk)))), 1535 (v4i32 (VBITCLR_W v4i32:$vj, v4i32:$vk))>; 1536def : Pat<(and v2i64:$vj, (vnot (shl vsplat_imm_eq_1, 1537 (vsplati64imm63 v2i64:$vk)))), 1538 (v2i64 (VBITCLR_D v2i64:$vj, v2i64:$vk))>; 1539 1540// VBITCLRI_{B/H/W/D} 1541def : Pat<(and (v16i8 LSX128:$vj), (v16i8 (vsplat_uimm_inv_pow2 uimm3:$imm))), 1542 (VBITCLRI_B LSX128:$vj, uimm3:$imm)>; 1543def : Pat<(and (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_inv_pow2 uimm4:$imm))), 1544 (VBITCLRI_H LSX128:$vj, uimm4:$imm)>; 1545def : Pat<(and (v4i32 LSX128:$vj), (v4i32 (vsplat_uimm_inv_pow2 uimm5:$imm))), 1546 (VBITCLRI_W LSX128:$vj, uimm5:$imm)>; 1547def : Pat<(and (v2i64 LSX128:$vj), (v2i64 (vsplat_uimm_inv_pow2 uimm6:$imm))), 1548 (VBITCLRI_D LSX128:$vj, uimm6:$imm)>; 1549 1550// VBITSET_{B/H/W/D} 1551def : Pat<(or v16i8:$vj, (shl vsplat_imm_eq_1, v16i8:$vk)), 1552 (v16i8 (VBITSET_B v16i8:$vj, v16i8:$vk))>; 1553def : Pat<(or v8i16:$vj, (shl vsplat_imm_eq_1, v8i16:$vk)), 1554 (v8i16 (VBITSET_H v8i16:$vj, v8i16:$vk))>; 1555def : Pat<(or v4i32:$vj, (shl vsplat_imm_eq_1, v4i32:$vk)), 1556 (v4i32 (VBITSET_W v4i32:$vj, v4i32:$vk))>; 1557def : Pat<(or v2i64:$vj, (shl vsplat_imm_eq_1, v2i64:$vk)), 1558 (v2i64 (VBITSET_D v2i64:$vj, v2i64:$vk))>; 1559def : Pat<(or v16i8:$vj, (shl vsplat_imm_eq_1, (vsplati8imm7 v16i8:$vk))), 1560 (v16i8 (VBITSET_B v16i8:$vj, v16i8:$vk))>; 1561def : Pat<(or v8i16:$vj, (shl vsplat_imm_eq_1, (vsplati16imm15 v8i16:$vk))), 1562 (v8i16 (VBITSET_H v8i16:$vj, v8i16:$vk))>; 1563def : Pat<(or v4i32:$vj, (shl vsplat_imm_eq_1, (vsplati32imm31 v4i32:$vk))), 1564 (v4i32 (VBITSET_W v4i32:$vj, v4i32:$vk))>; 1565def : Pat<(or v2i64:$vj, (shl vsplat_imm_eq_1, (vsplati64imm63 v2i64:$vk))), 1566 (v2i64 (VBITSET_D v2i64:$vj, v2i64:$vk))>; 1567 1568// VBITSETI_{B/H/W/D} 1569def : Pat<(or (v16i8 LSX128:$vj), (v16i8 (vsplat_uimm_pow2 uimm3:$imm))), 1570 (VBITSETI_B LSX128:$vj, uimm3:$imm)>; 1571def : Pat<(or (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_pow2 uimm4:$imm))), 1572 (VBITSETI_H LSX128:$vj, uimm4:$imm)>; 1573def : Pat<(or (v4i32 LSX128:$vj), (v4i32 (vsplat_uimm_pow2 uimm5:$imm))), 1574 (VBITSETI_W LSX128:$vj, uimm5:$imm)>; 1575def : Pat<(or (v2i64 LSX128:$vj), (v2i64 (vsplat_uimm_pow2 uimm6:$imm))), 1576 (VBITSETI_D LSX128:$vj, uimm6:$imm)>; 1577 1578// VBITREV_{B/H/W/D} 1579def : Pat<(xor v16i8:$vj, (shl vsplat_imm_eq_1, v16i8:$vk)), 1580 (v16i8 (VBITREV_B v16i8:$vj, v16i8:$vk))>; 1581def : Pat<(xor v8i16:$vj, (shl vsplat_imm_eq_1, v8i16:$vk)), 1582 (v8i16 (VBITREV_H v8i16:$vj, v8i16:$vk))>; 1583def : Pat<(xor v4i32:$vj, (shl vsplat_imm_eq_1, v4i32:$vk)), 1584 (v4i32 (VBITREV_W v4i32:$vj, v4i32:$vk))>; 1585def : Pat<(xor v2i64:$vj, (shl vsplat_imm_eq_1, v2i64:$vk)), 1586 (v2i64 (VBITREV_D v2i64:$vj, v2i64:$vk))>; 1587def : Pat<(xor v16i8:$vj, (shl vsplat_imm_eq_1, (vsplati8imm7 v16i8:$vk))), 1588 (v16i8 (VBITREV_B v16i8:$vj, v16i8:$vk))>; 1589def : Pat<(xor v8i16:$vj, (shl vsplat_imm_eq_1, (vsplati16imm15 v8i16:$vk))), 1590 (v8i16 (VBITREV_H v8i16:$vj, v8i16:$vk))>; 1591def : Pat<(xor v4i32:$vj, (shl vsplat_imm_eq_1, (vsplati32imm31 v4i32:$vk))), 1592 (v4i32 (VBITREV_W v4i32:$vj, v4i32:$vk))>; 1593def : Pat<(xor v2i64:$vj, (shl vsplat_imm_eq_1, (vsplati64imm63 v2i64:$vk))), 1594 (v2i64 (VBITREV_D v2i64:$vj, v2i64:$vk))>; 1595 1596// VBITREVI_{B/H/W/D} 1597def : Pat<(xor (v16i8 LSX128:$vj), (v16i8 (vsplat_uimm_pow2 uimm3:$imm))), 1598 (VBITREVI_B LSX128:$vj, uimm3:$imm)>; 1599def : Pat<(xor (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_pow2 uimm4:$imm))), 1600 (VBITREVI_H LSX128:$vj, uimm4:$imm)>; 1601def : Pat<(xor (v4i32 LSX128:$vj), (v4i32 (vsplat_uimm_pow2 uimm5:$imm))), 1602 (VBITREVI_W LSX128:$vj, uimm5:$imm)>; 1603def : Pat<(xor (v2i64 LSX128:$vj), (v2i64 (vsplat_uimm_pow2 uimm6:$imm))), 1604 (VBITREVI_D LSX128:$vj, uimm6:$imm)>; 1605 1606// Vector bswaps 1607def : Pat<(bswap (v8i16 LSX128:$vj)), (VSHUF4I_B LSX128:$vj, 0b10110001)>; 1608def : Pat<(bswap (v4i32 LSX128:$vj)), (VSHUF4I_B LSX128:$vj, 0b00011011)>; 1609def : Pat<(bswap (v2i64 LSX128:$vj)), 1610 (VSHUF4I_W (VSHUF4I_B LSX128:$vj, 0b00011011), 0b10110001)>; 1611 1612// VFADD_{S/D} 1613defm : PatVrVrF<fadd, "VFADD">; 1614 1615// VFSUB_{S/D} 1616defm : PatVrVrF<fsub, "VFSUB">; 1617 1618// VFMUL_{S/D} 1619defm : PatVrVrF<fmul, "VFMUL">; 1620 1621// VFDIV_{S/D} 1622defm : PatVrVrF<fdiv, "VFDIV">; 1623 1624// VFMADD_{S/D} 1625def : Pat<(fma v4f32:$vj, v4f32:$vk, v4f32:$va), 1626 (VFMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1627def : Pat<(fma v2f64:$vj, v2f64:$vk, v2f64:$va), 1628 (VFMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1629 1630// VFMSUB_{S/D} 1631def : Pat<(fma v4f32:$vj, v4f32:$vk, (fneg v4f32:$va)), 1632 (VFMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1633def : Pat<(fma v2f64:$vj, v2f64:$vk, (fneg v2f64:$va)), 1634 (VFMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1635 1636// VFNMADD_{S/D} 1637def : Pat<(fneg (fma v4f32:$vj, v4f32:$vk, v4f32:$va)), 1638 (VFNMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1639def : Pat<(fneg (fma v2f64:$vj, v2f64:$vk, v2f64:$va)), 1640 (VFNMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1641def : Pat<(fma_nsz (fneg v4f32:$vj), v4f32:$vk, (fneg v4f32:$va)), 1642 (VFNMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1643def : Pat<(fma_nsz (fneg v2f64:$vj), v2f64:$vk, (fneg v2f64:$va)), 1644 (VFNMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1645 1646// VFNMSUB_{S/D} 1647def : Pat<(fneg (fma v4f32:$vj, v4f32:$vk, (fneg v4f32:$va))), 1648 (VFNMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1649def : Pat<(fneg (fma v2f64:$vj, v2f64:$vk, (fneg v2f64:$va))), 1650 (VFNMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1651def : Pat<(fma_nsz (fneg v4f32:$vj), v4f32:$vk, v4f32:$va), 1652 (VFNMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1653def : Pat<(fma_nsz (fneg v2f64:$vj), v2f64:$vk, v2f64:$va), 1654 (VFNMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1655 1656// VFSQRT_{S/D} 1657defm : PatVrF<fsqrt, "VFSQRT">; 1658 1659// VFRECIP_{S/D} 1660def : Pat<(fdiv vsplatf32_fpimm_eq_1, v4f32:$vj), 1661 (VFRECIP_S v4f32:$vj)>; 1662def : Pat<(fdiv vsplatf64_fpimm_eq_1, v2f64:$vj), 1663 (VFRECIP_D v2f64:$vj)>; 1664 1665// VFRSQRT_{S/D} 1666def : Pat<(fdiv vsplatf32_fpimm_eq_1, (fsqrt v4f32:$vj)), 1667 (VFRSQRT_S v4f32:$vj)>; 1668def : Pat<(fdiv vsplatf64_fpimm_eq_1, (fsqrt v2f64:$vj)), 1669 (VFRSQRT_D v2f64:$vj)>; 1670 1671// VSEQ[I]_{B/H/W/D} 1672defm : PatCCVrSimm5<SETEQ, "VSEQI">; 1673defm : PatCCVrVr<SETEQ, "VSEQ">; 1674 1675// VSLE[I]_{B/H/W/D}[U] 1676defm : PatCCVrSimm5<SETLE, "VSLEI">; 1677defm : PatCCVrUimm5<SETULE, "VSLEI">; 1678defm : PatCCVrVr<SETLE, "VSLE">; 1679defm : PatCCVrVrU<SETULE, "VSLE">; 1680 1681// VSLT[I]_{B/H/W/D}[U] 1682defm : PatCCVrSimm5<SETLT, "VSLTI">; 1683defm : PatCCVrUimm5<SETULT, "VSLTI">; 1684defm : PatCCVrVr<SETLT, "VSLT">; 1685defm : PatCCVrVrU<SETULT, "VSLT">; 1686 1687// VFCMP.cond.{S/D} 1688defm : PatCCVrVrF<SETEQ, "VFCMP_CEQ">; 1689defm : PatCCVrVrF<SETOEQ, "VFCMP_CEQ">; 1690defm : PatCCVrVrF<SETUEQ, "VFCMP_CUEQ">; 1691 1692defm : PatCCVrVrF<SETLE, "VFCMP_CLE">; 1693defm : PatCCVrVrF<SETOLE, "VFCMP_CLE">; 1694defm : PatCCVrVrF<SETULE, "VFCMP_CULE">; 1695 1696defm : PatCCVrVrF<SETLT, "VFCMP_CLT">; 1697defm : PatCCVrVrF<SETOLT, "VFCMP_CLT">; 1698defm : PatCCVrVrF<SETULT, "VFCMP_CULT">; 1699 1700defm : PatCCVrVrF<SETNE, "VFCMP_CNE">; 1701defm : PatCCVrVrF<SETONE, "VFCMP_CNE">; 1702defm : PatCCVrVrF<SETUNE, "VFCMP_CUNE">; 1703 1704defm : PatCCVrVrF<SETO, "VFCMP_COR">; 1705defm : PatCCVrVrF<SETUO, "VFCMP_CUN">; 1706 1707// VINSGR2VR_{B/H/W/D} 1708def : Pat<(vector_insert v16i8:$vd, GRLenVT:$rj, uimm4:$imm), 1709 (VINSGR2VR_B v16i8:$vd, GRLenVT:$rj, uimm4:$imm)>; 1710def : Pat<(vector_insert v8i16:$vd, GRLenVT:$rj, uimm3:$imm), 1711 (VINSGR2VR_H v8i16:$vd, GRLenVT:$rj, uimm3:$imm)>; 1712def : Pat<(vector_insert v4i32:$vd, GRLenVT:$rj, uimm2:$imm), 1713 (VINSGR2VR_W v4i32:$vd, GRLenVT:$rj, uimm2:$imm)>; 1714def : Pat<(vector_insert v2i64:$vd, GRLenVT:$rj, uimm1:$imm), 1715 (VINSGR2VR_D v2i64:$vd, GRLenVT:$rj, uimm1:$imm)>; 1716 1717def : Pat<(vector_insert v4f32:$vd, FPR32:$fj, uimm2:$imm), 1718 (VINSGR2VR_W $vd, (COPY_TO_REGCLASS FPR32:$fj, GPR), uimm2:$imm)>; 1719def : Pat<(vector_insert v2f64:$vd, FPR64:$fj, uimm1:$imm), 1720 (VINSGR2VR_D $vd, (COPY_TO_REGCLASS FPR64:$fj, GPR), uimm1:$imm)>; 1721 1722// scalar_to_vector 1723def : Pat<(v4f32 (scalar_to_vector FPR32:$fj)), 1724 (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32)>; 1725def : Pat<(v2f64 (scalar_to_vector FPR64:$fj)), 1726 (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64)>; 1727 1728// VPICKVE2GR_{B/H/W}[U] 1729def : Pat<(loongarch_vpick_sext_elt v16i8:$vd, uimm4:$imm, i8), 1730 (VPICKVE2GR_B v16i8:$vd, uimm4:$imm)>; 1731def : Pat<(loongarch_vpick_sext_elt v8i16:$vd, uimm3:$imm, i16), 1732 (VPICKVE2GR_H v8i16:$vd, uimm3:$imm)>; 1733def : Pat<(loongarch_vpick_sext_elt v4i32:$vd, uimm2:$imm, i32), 1734 (VPICKVE2GR_W v4i32:$vd, uimm2:$imm)>; 1735 1736def : Pat<(loongarch_vpick_zext_elt v16i8:$vd, uimm4:$imm, i8), 1737 (VPICKVE2GR_BU v16i8:$vd, uimm4:$imm)>; 1738def : Pat<(loongarch_vpick_zext_elt v8i16:$vd, uimm3:$imm, i16), 1739 (VPICKVE2GR_HU v8i16:$vd, uimm3:$imm)>; 1740def : Pat<(loongarch_vpick_zext_elt v4i32:$vd, uimm2:$imm, i32), 1741 (VPICKVE2GR_WU v4i32:$vd, uimm2:$imm)>; 1742 1743// VREPLGR2VR_{B/H/W/D} 1744def : Pat<(lsxsplati8 GPR:$rj), (VREPLGR2VR_B GPR:$rj)>; 1745def : Pat<(lsxsplati16 GPR:$rj), (VREPLGR2VR_H GPR:$rj)>; 1746def : Pat<(lsxsplati32 GPR:$rj), (VREPLGR2VR_W GPR:$rj)>; 1747def : Pat<(lsxsplati64 GPR:$rj), (VREPLGR2VR_D GPR:$rj)>; 1748 1749def : Pat<(v16i8 (loongarch_vreplgr2vr GRLenVT:$rj)), 1750 (v16i8 (VREPLGR2VR_B GRLenVT:$rj))>; 1751def : Pat<(v8i16 (loongarch_vreplgr2vr GRLenVT:$rj)), 1752 (v8i16 (VREPLGR2VR_H GRLenVT:$rj))>; 1753def : Pat<(v4i32 (loongarch_vreplgr2vr GRLenVT:$rj)), 1754 (v4i32 (VREPLGR2VR_W GRLenVT:$rj))>; 1755def : Pat<(v2i64 (loongarch_vreplgr2vr GRLenVT:$rj)), 1756 (v2i64 (VREPLGR2VR_D GRLenVT:$rj))>; 1757 1758// VREPLVE_{B/H/W/D} 1759def : Pat<(loongarch_vreplve v16i8:$vj, GRLenVT:$rk), 1760 (VREPLVE_B v16i8:$vj, GRLenVT:$rk)>; 1761def : Pat<(loongarch_vreplve v8i16:$vj, GRLenVT:$rk), 1762 (VREPLVE_H v8i16:$vj, GRLenVT:$rk)>; 1763def : Pat<(loongarch_vreplve v4i32:$vj, GRLenVT:$rk), 1764 (VREPLVE_W v4i32:$vj, GRLenVT:$rk)>; 1765def : Pat<(loongarch_vreplve v2i64:$vj, GRLenVT:$rk), 1766 (VREPLVE_D v2i64:$vj, GRLenVT:$rk)>; 1767 1768// VSHUF_{B/H/W/D} 1769def : Pat<(loongarch_vshuf v16i8:$va, v16i8:$vj, v16i8:$vk), 1770 (VSHUF_B v16i8:$vj, v16i8:$vk, v16i8:$va)>; 1771def : Pat<(loongarch_vshuf v8i16:$vd, v8i16:$vj, v8i16:$vk), 1772 (VSHUF_H v8i16:$vd, v8i16:$vj, v8i16:$vk)>; 1773def : Pat<(loongarch_vshuf v4i32:$vd, v4i32:$vj, v4i32:$vk), 1774 (VSHUF_W v4i32:$vd, v4i32:$vj, v4i32:$vk)>; 1775def : Pat<(loongarch_vshuf v2i64:$vd, v2i64:$vj, v2i64:$vk), 1776 (VSHUF_D v2i64:$vd, v2i64:$vj, v2i64:$vk)>; 1777def : Pat<(loongarch_vshuf v4i32:$vd, v4f32:$vj, v4f32:$vk), 1778 (VSHUF_W v4i32:$vd, v4f32:$vj, v4f32:$vk)>; 1779def : Pat<(loongarch_vshuf v2i64:$vd, v2f64:$vj, v2f64:$vk), 1780 (VSHUF_D v2i64:$vd, v2f64:$vj, v2f64:$vk)>; 1781 1782// VPICKEV_{B/H/W/D} 1783def : Pat<(loongarch_vpickev v16i8:$vj, v16i8:$vk), 1784 (VPICKEV_B v16i8:$vj, v16i8:$vk)>; 1785def : Pat<(loongarch_vpickev v8i16:$vj, v8i16:$vk), 1786 (VPICKEV_H v8i16:$vj, v8i16:$vk)>; 1787def : Pat<(loongarch_vpickev v4i32:$vj, v4i32:$vk), 1788 (VPICKEV_W v4i32:$vj, v4i32:$vk)>; 1789def : Pat<(loongarch_vpickev v2i64:$vj, v2i64:$vk), 1790 (VPICKEV_D v2i64:$vj, v2i64:$vk)>; 1791def : Pat<(loongarch_vpickev v4f32:$vj, v4f32:$vk), 1792 (VPICKEV_W v4f32:$vj, v4f32:$vk)>; 1793def : Pat<(loongarch_vpickev v2f64:$vj, v2f64:$vk), 1794 (VPICKEV_D v2f64:$vj, v2f64:$vk)>; 1795 1796// VPICKOD_{B/H/W/D} 1797def : Pat<(loongarch_vpickod v16i8:$vj, v16i8:$vk), 1798 (VPICKOD_B v16i8:$vj, v16i8:$vk)>; 1799def : Pat<(loongarch_vpickod v8i16:$vj, v8i16:$vk), 1800 (VPICKOD_H v8i16:$vj, v8i16:$vk)>; 1801def : Pat<(loongarch_vpickod v4i32:$vj, v4i32:$vk), 1802 (VPICKOD_W v4i32:$vj, v4i32:$vk)>; 1803def : Pat<(loongarch_vpickod v2i64:$vj, v2i64:$vk), 1804 (VPICKOD_D v2i64:$vj, v2i64:$vk)>; 1805def : Pat<(loongarch_vpickod v4f32:$vj, v4f32:$vk), 1806 (VPICKOD_W v4f32:$vj, v4f32:$vk)>; 1807def : Pat<(loongarch_vpickod v2f64:$vj, v2f64:$vk), 1808 (VPICKOD_D v2f64:$vj, v2f64:$vk)>; 1809 1810// VPACKEV_{B/H/W/D} 1811def : Pat<(loongarch_vpackev v16i8:$vj, v16i8:$vk), 1812 (VPACKEV_B v16i8:$vj, v16i8:$vk)>; 1813def : Pat<(loongarch_vpackev v8i16:$vj, v8i16:$vk), 1814 (VPACKEV_H v8i16:$vj, v8i16:$vk)>; 1815def : Pat<(loongarch_vpackev v4i32:$vj, v4i32:$vk), 1816 (VPACKEV_W v4i32:$vj, v4i32:$vk)>; 1817def : Pat<(loongarch_vpackev v2i64:$vj, v2i64:$vk), 1818 (VPACKEV_D v2i64:$vj, v2i64:$vk)>; 1819def : Pat<(loongarch_vpackev v4f32:$vj, v4f32:$vk), 1820 (VPACKEV_W v4f32:$vj, v4f32:$vk)>; 1821def : Pat<(loongarch_vpackev v2f64:$vj, v2f64:$vk), 1822 (VPACKEV_D v2f64:$vj, v2f64:$vk)>; 1823 1824// VPACKOD_{B/H/W/D} 1825def : Pat<(loongarch_vpackod v16i8:$vj, v16i8:$vk), 1826 (VPACKOD_B v16i8:$vj, v16i8:$vk)>; 1827def : Pat<(loongarch_vpackod v8i16:$vj, v8i16:$vk), 1828 (VPACKOD_H v8i16:$vj, v8i16:$vk)>; 1829def : Pat<(loongarch_vpackod v4i32:$vj, v4i32:$vk), 1830 (VPACKOD_W v4i32:$vj, v4i32:$vk)>; 1831def : Pat<(loongarch_vpackod v2i64:$vj, v2i64:$vk), 1832 (VPACKOD_D v2i64:$vj, v2i64:$vk)>; 1833def : Pat<(loongarch_vpackod v4f32:$vj, v4f32:$vk), 1834 (VPACKOD_W v4f32:$vj, v4f32:$vk)>; 1835def : Pat<(loongarch_vpackod v2f64:$vj, v2f64:$vk), 1836 (VPACKOD_D v2f64:$vj, v2f64:$vk)>; 1837 1838// VILVL_{B/H/W/D} 1839def : Pat<(loongarch_vilvl v16i8:$vj, v16i8:$vk), 1840 (VILVL_B v16i8:$vj, v16i8:$vk)>; 1841def : Pat<(loongarch_vilvl v8i16:$vj, v8i16:$vk), 1842 (VILVL_H v8i16:$vj, v8i16:$vk)>; 1843def : Pat<(loongarch_vilvl v4i32:$vj, v4i32:$vk), 1844 (VILVL_W v4i32:$vj, v4i32:$vk)>; 1845def : Pat<(loongarch_vilvl v2i64:$vj, v2i64:$vk), 1846 (VILVL_D v2i64:$vj, v2i64:$vk)>; 1847def : Pat<(loongarch_vilvl v4f32:$vj, v4f32:$vk), 1848 (VILVL_W v4f32:$vj, v4f32:$vk)>; 1849def : Pat<(loongarch_vilvl v2f64:$vj, v2f64:$vk), 1850 (VILVL_D v2f64:$vj, v2f64:$vk)>; 1851 1852// VILVH_{B/H/W/D} 1853def : Pat<(loongarch_vilvh v16i8:$vj, v16i8:$vk), 1854 (VILVH_B v16i8:$vj, v16i8:$vk)>; 1855def : Pat<(loongarch_vilvh v8i16:$vj, v8i16:$vk), 1856 (VILVH_H v8i16:$vj, v8i16:$vk)>; 1857def : Pat<(loongarch_vilvh v4i32:$vj, v4i32:$vk), 1858 (VILVH_W v4i32:$vj, v4i32:$vk)>; 1859def : Pat<(loongarch_vilvh v2i64:$vj, v2i64:$vk), 1860 (VILVH_D v2i64:$vj, v2i64:$vk)>; 1861def : Pat<(loongarch_vilvh v4f32:$vj, v4f32:$vk), 1862 (VILVH_W v4f32:$vj, v4f32:$vk)>; 1863def : Pat<(loongarch_vilvh v2f64:$vj, v2f64:$vk), 1864 (VILVH_D v2f64:$vj, v2f64:$vk)>; 1865 1866// VSHUF4I_{B/H/W} 1867def : Pat<(loongarch_vshuf4i v16i8:$vj, immZExt8:$ui8), 1868 (VSHUF4I_B v16i8:$vj, immZExt8:$ui8)>; 1869def : Pat<(loongarch_vshuf4i v8i16:$vj, immZExt8:$ui8), 1870 (VSHUF4I_H v8i16:$vj, immZExt8:$ui8)>; 1871def : Pat<(loongarch_vshuf4i v4i32:$vj, immZExt8:$ui8), 1872 (VSHUF4I_W v4i32:$vj, immZExt8:$ui8)>; 1873def : Pat<(loongarch_vshuf4i v4f32:$vj, immZExt8:$ui8), 1874 (VSHUF4I_W v4f32:$vj, immZExt8:$ui8)>; 1875 1876// VREPLVEI_{B/H/W/D} 1877def : Pat<(loongarch_vreplvei v16i8:$vj, immZExt4:$ui4), 1878 (VREPLVEI_B v16i8:$vj, immZExt4:$ui4)>; 1879def : Pat<(loongarch_vreplvei v8i16:$vj, immZExt3:$ui3), 1880 (VREPLVEI_H v8i16:$vj, immZExt3:$ui3)>; 1881def : Pat<(loongarch_vreplvei v4i32:$vj, immZExt2:$ui2), 1882 (VREPLVEI_W v4i32:$vj, immZExt2:$ui2)>; 1883def : Pat<(loongarch_vreplvei v2i64:$vj, immZExt1:$ui1), 1884 (VREPLVEI_D v2i64:$vj, immZExt1:$ui1)>; 1885def : Pat<(loongarch_vreplvei v4f32:$vj, immZExt2:$ui2), 1886 (VREPLVEI_W v4f32:$vj, immZExt2:$ui2)>; 1887def : Pat<(loongarch_vreplvei v2f64:$vj, immZExt1:$ui1), 1888 (VREPLVEI_D v2f64:$vj, immZExt1:$ui1)>; 1889 1890// VREPLVEI_{W/D} 1891def : Pat<(lsxsplatf32 FPR32:$fj), 1892 (VREPLVEI_W (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)>; 1893def : Pat<(lsxsplatf64 FPR64:$fj), 1894 (VREPLVEI_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)>; 1895 1896// Loads/Stores 1897foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { 1898 defm : LdPat<load, VLD, vt>; 1899 def : RegRegLdPat<load, VLDX, vt>; 1900 defm : StPat<store, VST, LSX128, vt>; 1901 def : RegRegStPat<store, VSTX, LSX128, vt>; 1902} 1903 1904// Vector extraction with constant index. 1905def : Pat<(i64 (vector_extract v16i8:$vj, uimm4:$imm)), 1906 (VPICKVE2GR_B v16i8:$vj, uimm4:$imm)>; 1907def : Pat<(i64 (vector_extract v8i16:$vj, uimm3:$imm)), 1908 (VPICKVE2GR_H v8i16:$vj, uimm3:$imm)>; 1909def : Pat<(i64 (vector_extract v4i32:$vj, uimm2:$imm)), 1910 (VPICKVE2GR_W v4i32:$vj, uimm2:$imm)>; 1911def : Pat<(i64 (vector_extract v2i64:$vj, uimm1:$imm)), 1912 (VPICKVE2GR_D v2i64:$vj, uimm1:$imm)>; 1913def : Pat<(f32 (vector_extract v4f32:$vj, uimm2:$imm)), 1914 (f32 (EXTRACT_SUBREG (VREPLVEI_W v4f32:$vj, uimm2:$imm), sub_32))>; 1915def : Pat<(f64 (vector_extract v2f64:$vj, uimm1:$imm)), 1916 (f64 (EXTRACT_SUBREG (VREPLVEI_D v2f64:$vj, uimm1:$imm), sub_64))>; 1917 1918// Vector extraction with variable index. 1919def : Pat<(i64 (vector_extract v16i8:$vj, i64:$rk)), 1920 (SRAI_W (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (VREPLVE_B v16i8:$vj, 1921 i64:$rk), 1922 sub_32)), 1923 GPR), (i64 24))>; 1924def : Pat<(i64 (vector_extract v8i16:$vj, i64:$rk)), 1925 (SRAI_W (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (VREPLVE_H v8i16:$vj, 1926 i64:$rk), 1927 sub_32)), 1928 GPR), (i64 16))>; 1929def : Pat<(i64 (vector_extract v4i32:$vj, i64:$rk)), 1930 (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (VREPLVE_W v4i32:$vj, i64:$rk), 1931 sub_32)), 1932 GPR)>; 1933def : Pat<(i64 (vector_extract v2i64:$vj, i64:$rk)), 1934 (COPY_TO_REGCLASS (f64 (EXTRACT_SUBREG (VREPLVE_D v2i64:$vj, i64:$rk), 1935 sub_64)), 1936 GPR)>; 1937def : Pat<(f32 (vector_extract v4f32:$vj, i64:$rk)), 1938 (f32 (EXTRACT_SUBREG (VREPLVE_W v4f32:$vj, i64:$rk), sub_32))>; 1939def : Pat<(f64 (vector_extract v2f64:$vj, i64:$rk)), 1940 (f64 (EXTRACT_SUBREG (VREPLVE_D v2f64:$vj, i64:$rk), sub_64))>; 1941 1942// vselect 1943def : Pat<(v16i8 (vselect LSX128:$vd, (v16i8 (SplatPat_uimm8 uimm8:$imm)), 1944 LSX128:$vj)), 1945 (VBITSELI_B LSX128:$vd, LSX128:$vj, uimm8:$imm)>; 1946foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in 1947 def : Pat<(vt (vselect LSX128:$va, LSX128:$vk, LSX128:$vj)), 1948 (VBITSEL_V LSX128:$vj, LSX128:$vk, LSX128:$va)>; 1949 1950// fneg 1951def : Pat<(fneg (v4f32 LSX128:$vj)), (VBITREVI_W LSX128:$vj, 31)>; 1952def : Pat<(fneg (v2f64 LSX128:$vj)), (VBITREVI_D LSX128:$vj, 63)>; 1953 1954// VFFINT_{S_W/D_L} 1955def : Pat<(v4f32 (sint_to_fp v4i32:$vj)), (VFFINT_S_W v4i32:$vj)>; 1956def : Pat<(v2f64 (sint_to_fp v2i64:$vj)), (VFFINT_D_L v2i64:$vj)>; 1957 1958// VFFINT_{S_WU/D_LU} 1959def : Pat<(v4f32 (uint_to_fp v4i32:$vj)), (VFFINT_S_WU v4i32:$vj)>; 1960def : Pat<(v2f64 (uint_to_fp v2i64:$vj)), (VFFINT_D_LU v2i64:$vj)>; 1961 1962// VFTINTRZ_{W_S/L_D} 1963def : Pat<(v4i32 (fp_to_sint v4f32:$vj)), (VFTINTRZ_W_S v4f32:$vj)>; 1964def : Pat<(v2i64 (fp_to_sint v2f64:$vj)), (VFTINTRZ_L_D v2f64:$vj)>; 1965 1966// VFTINTRZ_{W_SU/L_DU} 1967def : Pat<(v4i32 (fp_to_uint v4f32:$vj)), (VFTINTRZ_WU_S v4f32:$vj)>; 1968def : Pat<(v2i64 (fp_to_uint v2f64:$vj)), (VFTINTRZ_LU_D v2f64:$vj)>; 1969 1970// Vector loads floating-point constants 1971def : Pat<(f32 f32imm_vldi:$in), 1972 (f32 (EXTRACT_SUBREG (VLDI (to_f32imm_vldi f32imm_vldi:$in)), sub_32))>; 1973def : Pat<(f64 f64imm_vldi:$in), 1974 (f64 (EXTRACT_SUBREG (VLDI (to_f64imm_vldi f64imm_vldi:$in)), sub_64))>; 1975 1976} // Predicates = [HasExtLSX] 1977 1978/// Intrinsic pattern 1979 1980class deriveLSXIntrinsic<string Inst> { 1981 Intrinsic ret = !cast<Intrinsic>(!tolower("int_loongarch_lsx_"#Inst)); 1982} 1983 1984let Predicates = [HasExtLSX] in { 1985 1986// vty: v16i8/v8i16/v4i32/v2i64 1987// Pat<(Intrinsic vty:$vj, vty:$vk), 1988// (LAInst vty:$vj, vty:$vk)>; 1989foreach Inst = ["VSADD_B", "VSADD_BU", "VSSUB_B", "VSSUB_BU", 1990 "VHADDW_H_B", "VHADDW_HU_BU", "VHSUBW_H_B", "VHSUBW_HU_BU", 1991 "VADDWEV_H_B", "VADDWOD_H_B", "VSUBWEV_H_B", "VSUBWOD_H_B", 1992 "VADDWEV_H_BU", "VADDWOD_H_BU", "VSUBWEV_H_BU", "VSUBWOD_H_BU", 1993 "VADDWEV_H_BU_B", "VADDWOD_H_BU_B", 1994 "VAVG_B", "VAVG_BU", "VAVGR_B", "VAVGR_BU", 1995 "VABSD_B", "VABSD_BU", "VADDA_B", "VMUH_B", "VMUH_BU", 1996 "VMULWEV_H_B", "VMULWOD_H_B", "VMULWEV_H_BU", "VMULWOD_H_BU", 1997 "VMULWEV_H_BU_B", "VMULWOD_H_BU_B", "VSIGNCOV_B", 1998 "VANDN_V", "VORN_V", "VROTR_B", "VSRLR_B", "VSRAR_B", 1999 "VSEQ_B", "VSLE_B", "VSLE_BU", "VSLT_B", "VSLT_BU", 2000 "VPACKEV_B", "VPACKOD_B", "VPICKEV_B", "VPICKOD_B", 2001 "VILVL_B", "VILVH_B"] in 2002 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2003 (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 2004 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 2005foreach Inst = ["VSADD_H", "VSADD_HU", "VSSUB_H", "VSSUB_HU", 2006 "VHADDW_W_H", "VHADDW_WU_HU", "VHSUBW_W_H", "VHSUBW_WU_HU", 2007 "VADDWEV_W_H", "VADDWOD_W_H", "VSUBWEV_W_H", "VSUBWOD_W_H", 2008 "VADDWEV_W_HU", "VADDWOD_W_HU", "VSUBWEV_W_HU", "VSUBWOD_W_HU", 2009 "VADDWEV_W_HU_H", "VADDWOD_W_HU_H", 2010 "VAVG_H", "VAVG_HU", "VAVGR_H", "VAVGR_HU", 2011 "VABSD_H", "VABSD_HU", "VADDA_H", "VMUH_H", "VMUH_HU", 2012 "VMULWEV_W_H", "VMULWOD_W_H", "VMULWEV_W_HU", "VMULWOD_W_HU", 2013 "VMULWEV_W_HU_H", "VMULWOD_W_HU_H", "VSIGNCOV_H", "VROTR_H", 2014 "VSRLR_H", "VSRAR_H", "VSRLN_B_H", "VSRAN_B_H", "VSRLRN_B_H", 2015 "VSRARN_B_H", "VSSRLN_B_H", "VSSRAN_B_H", "VSSRLN_BU_H", 2016 "VSSRAN_BU_H", "VSSRLRN_B_H", "VSSRARN_B_H", "VSSRLRN_BU_H", 2017 "VSSRARN_BU_H", 2018 "VSEQ_H", "VSLE_H", "VSLE_HU", "VSLT_H", "VSLT_HU", 2019 "VPACKEV_H", "VPACKOD_H", "VPICKEV_H", "VPICKOD_H", 2020 "VILVL_H", "VILVH_H"] in 2021 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2022 (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 2023 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 2024foreach Inst = ["VSADD_W", "VSADD_WU", "VSSUB_W", "VSSUB_WU", 2025 "VHADDW_D_W", "VHADDW_DU_WU", "VHSUBW_D_W", "VHSUBW_DU_WU", 2026 "VADDWEV_D_W", "VADDWOD_D_W", "VSUBWEV_D_W", "VSUBWOD_D_W", 2027 "VADDWEV_D_WU", "VADDWOD_D_WU", "VSUBWEV_D_WU", "VSUBWOD_D_WU", 2028 "VADDWEV_D_WU_W", "VADDWOD_D_WU_W", 2029 "VAVG_W", "VAVG_WU", "VAVGR_W", "VAVGR_WU", 2030 "VABSD_W", "VABSD_WU", "VADDA_W", "VMUH_W", "VMUH_WU", 2031 "VMULWEV_D_W", "VMULWOD_D_W", "VMULWEV_D_WU", "VMULWOD_D_WU", 2032 "VMULWEV_D_WU_W", "VMULWOD_D_WU_W", "VSIGNCOV_W", "VROTR_W", 2033 "VSRLR_W", "VSRAR_W", "VSRLN_H_W", "VSRAN_H_W", "VSRLRN_H_W", 2034 "VSRARN_H_W", "VSSRLN_H_W", "VSSRAN_H_W", "VSSRLN_HU_W", 2035 "VSSRAN_HU_W", "VSSRLRN_H_W", "VSSRARN_H_W", "VSSRLRN_HU_W", 2036 "VSSRARN_HU_W", 2037 "VSEQ_W", "VSLE_W", "VSLE_WU", "VSLT_W", "VSLT_WU", 2038 "VPACKEV_W", "VPACKOD_W", "VPICKEV_W", "VPICKOD_W", 2039 "VILVL_W", "VILVH_W"] in 2040 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2041 (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 2042 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 2043foreach Inst = ["VADD_Q", "VSUB_Q", 2044 "VSADD_D", "VSADD_DU", "VSSUB_D", "VSSUB_DU", 2045 "VHADDW_Q_D", "VHADDW_QU_DU", "VHSUBW_Q_D", "VHSUBW_QU_DU", 2046 "VADDWEV_Q_D", "VADDWOD_Q_D", "VSUBWEV_Q_D", "VSUBWOD_Q_D", 2047 "VADDWEV_Q_DU", "VADDWOD_Q_DU", "VSUBWEV_Q_DU", "VSUBWOD_Q_DU", 2048 "VADDWEV_Q_DU_D", "VADDWOD_Q_DU_D", 2049 "VAVG_D", "VAVG_DU", "VAVGR_D", "VAVGR_DU", 2050 "VABSD_D", "VABSD_DU", "VADDA_D", "VMUH_D", "VMUH_DU", 2051 "VMULWEV_Q_D", "VMULWOD_Q_D", "VMULWEV_Q_DU", "VMULWOD_Q_DU", 2052 "VMULWEV_Q_DU_D", "VMULWOD_Q_DU_D", "VSIGNCOV_D", "VROTR_D", 2053 "VSRLR_D", "VSRAR_D", "VSRLN_W_D", "VSRAN_W_D", "VSRLRN_W_D", 2054 "VSRARN_W_D", "VSSRLN_W_D", "VSSRAN_W_D", "VSSRLN_WU_D", 2055 "VSSRAN_WU_D", "VSSRLRN_W_D", "VSSRARN_W_D", "VSSRLRN_WU_D", 2056 "VSSRARN_WU_D", "VFFINT_S_L", 2057 "VSEQ_D", "VSLE_D", "VSLE_DU", "VSLT_D", "VSLT_DU", 2058 "VPACKEV_D", "VPACKOD_D", "VPICKEV_D", "VPICKOD_D", 2059 "VILVL_D", "VILVH_D"] in 2060 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2061 (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 2062 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 2063 2064// vty: v16i8/v8i16/v4i32/v2i64 2065// Pat<(Intrinsic vty:$vd, vty:$vj, vty:$vk), 2066// (LAInst vty:$vd, vty:$vj, vty:$vk)>; 2067foreach Inst = ["VMADDWEV_H_B", "VMADDWOD_H_B", "VMADDWEV_H_BU", 2068 "VMADDWOD_H_BU", "VMADDWEV_H_BU_B", "VMADDWOD_H_BU_B"] in 2069 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2070 (v8i16 LSX128:$vd), (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 2071 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2072foreach Inst = ["VMADDWEV_W_H", "VMADDWOD_W_H", "VMADDWEV_W_HU", 2073 "VMADDWOD_W_HU", "VMADDWEV_W_HU_H", "VMADDWOD_W_HU_H"] in 2074 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2075 (v4i32 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 2076 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2077foreach Inst = ["VMADDWEV_D_W", "VMADDWOD_D_W", "VMADDWEV_D_WU", 2078 "VMADDWOD_D_WU", "VMADDWEV_D_WU_W", "VMADDWOD_D_WU_W"] in 2079 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2080 (v2i64 LSX128:$vd), (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 2081 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2082foreach Inst = ["VMADDWEV_Q_D", "VMADDWOD_Q_D", "VMADDWEV_Q_DU", 2083 "VMADDWOD_Q_DU", "VMADDWEV_Q_DU_D", "VMADDWOD_Q_DU_D"] in 2084 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2085 (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 2086 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2087 2088// vty: v16i8/v8i16/v4i32/v2i64 2089// Pat<(Intrinsic vty:$vj), 2090// (LAInst vty:$vj)>; 2091foreach Inst = ["VEXTH_H_B", "VEXTH_HU_BU", 2092 "VMSKLTZ_B", "VMSKGEZ_B", "VMSKNZ_B", 2093 "VCLO_B"] in 2094 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v16i8 LSX128:$vj)), 2095 (!cast<LAInst>(Inst) LSX128:$vj)>; 2096foreach Inst = ["VEXTH_W_H", "VEXTH_WU_HU", "VMSKLTZ_H", 2097 "VCLO_H", "VFCVTL_S_H", "VFCVTH_S_H"] in 2098 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v8i16 LSX128:$vj)), 2099 (!cast<LAInst>(Inst) LSX128:$vj)>; 2100foreach Inst = ["VEXTH_D_W", "VEXTH_DU_WU", "VMSKLTZ_W", 2101 "VCLO_W", "VFFINT_S_W", "VFFINT_S_WU", 2102 "VFFINTL_D_W", "VFFINTH_D_W"] in 2103 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4i32 LSX128:$vj)), 2104 (!cast<LAInst>(Inst) LSX128:$vj)>; 2105foreach Inst = ["VEXTH_Q_D", "VEXTH_QU_DU", "VMSKLTZ_D", 2106 "VEXTL_Q_D", "VEXTL_QU_DU", 2107 "VCLO_D", "VFFINT_D_L", "VFFINT_D_LU"] in 2108 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2i64 LSX128:$vj)), 2109 (!cast<LAInst>(Inst) LSX128:$vj)>; 2110 2111// Pat<(Intrinsic timm:$imm) 2112// (LAInst timm:$imm)>; 2113def : Pat<(int_loongarch_lsx_vldi timm:$imm), 2114 (VLDI (to_valid_timm timm:$imm))>; 2115foreach Inst = ["VREPLI_B", "VREPLI_H", "VREPLI_W", "VREPLI_D"] in 2116 def : Pat<(deriveLSXIntrinsic<Inst>.ret timm:$imm), 2117 (!cast<LAInst>("Pseudo"#Inst) (to_valid_timm timm:$imm))>; 2118 2119// vty: v16i8/v8i16/v4i32/v2i64 2120// Pat<(Intrinsic vty:$vj, timm:$imm) 2121// (LAInst vty:$vj, timm:$imm)>; 2122foreach Inst = ["VSAT_B", "VSAT_BU", "VNORI_B", "VROTRI_B", "VSLLWIL_H_B", 2123 "VSLLWIL_HU_BU", "VSRLRI_B", "VSRARI_B", 2124 "VSEQI_B", "VSLEI_B", "VSLEI_BU", "VSLTI_B", "VSLTI_BU", 2125 "VREPLVEI_B", "VBSLL_V", "VBSRL_V", "VSHUF4I_B"] in 2126 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v16i8 LSX128:$vj), timm:$imm), 2127 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 2128foreach Inst = ["VSAT_H", "VSAT_HU", "VROTRI_H", "VSLLWIL_W_H", 2129 "VSLLWIL_WU_HU", "VSRLRI_H", "VSRARI_H", 2130 "VSEQI_H", "VSLEI_H", "VSLEI_HU", "VSLTI_H", "VSLTI_HU", 2131 "VREPLVEI_H", "VSHUF4I_H"] in 2132 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v8i16 LSX128:$vj), timm:$imm), 2133 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 2134foreach Inst = ["VSAT_W", "VSAT_WU", "VROTRI_W", "VSLLWIL_D_W", 2135 "VSLLWIL_DU_WU", "VSRLRI_W", "VSRARI_W", 2136 "VSEQI_W", "VSLEI_W", "VSLEI_WU", "VSLTI_W", "VSLTI_WU", 2137 "VREPLVEI_W", "VSHUF4I_W"] in 2138 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4i32 LSX128:$vj), timm:$imm), 2139 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 2140foreach Inst = ["VSAT_D", "VSAT_DU", "VROTRI_D", "VSRLRI_D", "VSRARI_D", 2141 "VSEQI_D", "VSLEI_D", "VSLEI_DU", "VSLTI_D", "VSLTI_DU", 2142 "VPICKVE2GR_D", "VPICKVE2GR_DU", 2143 "VREPLVEI_D"] in 2144 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2i64 LSX128:$vj), timm:$imm), 2145 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 2146 2147// vty: v16i8/v8i16/v4i32/v2i64 2148// Pat<(Intrinsic vty:$vd, vty:$vj, timm:$imm) 2149// (LAInst vty:$vd, vty:$vj, timm:$imm)>; 2150foreach Inst = ["VSRLNI_B_H", "VSRANI_B_H", "VSRLRNI_B_H", "VSRARNI_B_H", 2151 "VSSRLNI_B_H", "VSSRANI_B_H", "VSSRLNI_BU_H", "VSSRANI_BU_H", 2152 "VSSRLRNI_B_H", "VSSRARNI_B_H", "VSSRLRNI_BU_H", "VSSRARNI_BU_H", 2153 "VFRSTPI_B", "VBITSELI_B", "VEXTRINS_B"] in 2154 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2155 (v16i8 LSX128:$vd), (v16i8 LSX128:$vj), timm:$imm), 2156 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 2157 (to_valid_timm timm:$imm))>; 2158foreach Inst = ["VSRLNI_H_W", "VSRANI_H_W", "VSRLRNI_H_W", "VSRARNI_H_W", 2159 "VSSRLNI_H_W", "VSSRANI_H_W", "VSSRLNI_HU_W", "VSSRANI_HU_W", 2160 "VSSRLRNI_H_W", "VSSRARNI_H_W", "VSSRLRNI_HU_W", "VSSRARNI_HU_W", 2161 "VFRSTPI_H", "VEXTRINS_H"] in 2162 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2163 (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), timm:$imm), 2164 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 2165 (to_valid_timm timm:$imm))>; 2166foreach Inst = ["VSRLNI_W_D", "VSRANI_W_D", "VSRLRNI_W_D", "VSRARNI_W_D", 2167 "VSSRLNI_W_D", "VSSRANI_W_D", "VSSRLNI_WU_D", "VSSRANI_WU_D", 2168 "VSSRLRNI_W_D", "VSSRARNI_W_D", "VSSRLRNI_WU_D", "VSSRARNI_WU_D", 2169 "VPERMI_W", "VEXTRINS_W"] in 2170 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2171 (v4i32 LSX128:$vd), (v4i32 LSX128:$vj), timm:$imm), 2172 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 2173 (to_valid_timm timm:$imm))>; 2174foreach Inst = ["VSRLNI_D_Q", "VSRANI_D_Q", "VSRLRNI_D_Q", "VSRARNI_D_Q", 2175 "VSSRLNI_D_Q", "VSSRANI_D_Q", "VSSRLNI_DU_Q", "VSSRANI_DU_Q", 2176 "VSSRLRNI_D_Q", "VSSRARNI_D_Q", "VSSRLRNI_DU_Q", "VSSRARNI_DU_Q", 2177 "VSHUF4I_D", "VEXTRINS_D"] in 2178 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2179 (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), timm:$imm), 2180 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 2181 (to_valid_timm timm:$imm))>; 2182 2183// vty: v16i8/v8i16/v4i32/v2i64 2184// Pat<(Intrinsic vty:$vd, vty:$vj, vty:$vk), 2185// (LAInst vty:$vd, vty:$vj, vty:$vk)>; 2186foreach Inst = ["VFRSTP_B", "VBITSEL_V", "VSHUF_B"] in 2187 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2188 (v16i8 LSX128:$vd), (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 2189 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2190foreach Inst = ["VFRSTP_H", "VSHUF_H"] in 2191 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2192 (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 2193 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2194def : Pat<(int_loongarch_lsx_vshuf_w (v4i32 LSX128:$vd), (v4i32 LSX128:$vj), 2195 (v4i32 LSX128:$vk)), 2196 (VSHUF_W LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2197def : Pat<(int_loongarch_lsx_vshuf_d (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), 2198 (v2i64 LSX128:$vk)), 2199 (VSHUF_D LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2200 2201// vty: v4f32/v2f64 2202// Pat<(Intrinsic vty:$vj, vty:$vk, vty:$va), 2203// (LAInst vty:$vj, vty:$vk, vty:$va)>; 2204foreach Inst = ["VFMSUB_S", "VFNMADD_S", "VFNMSUB_S"] in 2205 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2206 (v4f32 LSX128:$vj), (v4f32 LSX128:$vk), (v4f32 LSX128:$va)), 2207 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk, LSX128:$va)>; 2208foreach Inst = ["VFMSUB_D", "VFNMADD_D", "VFNMSUB_D"] in 2209 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2210 (v2f64 LSX128:$vj), (v2f64 LSX128:$vk), (v2f64 LSX128:$va)), 2211 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk, LSX128:$va)>; 2212 2213// vty: v4f32/v2f64 2214// Pat<(Intrinsic vty:$vj, vty:$vk), 2215// (LAInst vty:$vj, vty:$vk)>; 2216foreach Inst = ["VFMAX_S", "VFMIN_S", "VFMAXA_S", "VFMINA_S", "VFCVT_H_S", 2217 "VFCMP_CAF_S", "VFCMP_CUN_S", "VFCMP_CEQ_S", "VFCMP_CUEQ_S", 2218 "VFCMP_CLT_S", "VFCMP_CULT_S", "VFCMP_CLE_S", "VFCMP_CULE_S", 2219 "VFCMP_CNE_S", "VFCMP_COR_S", "VFCMP_CUNE_S", 2220 "VFCMP_SAF_S", "VFCMP_SUN_S", "VFCMP_SEQ_S", "VFCMP_SUEQ_S", 2221 "VFCMP_SLT_S", "VFCMP_SULT_S", "VFCMP_SLE_S", "VFCMP_SULE_S", 2222 "VFCMP_SNE_S", "VFCMP_SOR_S", "VFCMP_SUNE_S"] in 2223 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2224 (v4f32 LSX128:$vj), (v4f32 LSX128:$vk)), 2225 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 2226foreach Inst = ["VFMAX_D", "VFMIN_D", "VFMAXA_D", "VFMINA_D", "VFCVT_S_D", 2227 "VFTINTRNE_W_D", "VFTINTRZ_W_D", "VFTINTRP_W_D", "VFTINTRM_W_D", 2228 "VFTINT_W_D", 2229 "VFCMP_CAF_D", "VFCMP_CUN_D", "VFCMP_CEQ_D", "VFCMP_CUEQ_D", 2230 "VFCMP_CLT_D", "VFCMP_CULT_D", "VFCMP_CLE_D", "VFCMP_CULE_D", 2231 "VFCMP_CNE_D", "VFCMP_COR_D", "VFCMP_CUNE_D", 2232 "VFCMP_SAF_D", "VFCMP_SUN_D", "VFCMP_SEQ_D", "VFCMP_SUEQ_D", 2233 "VFCMP_SLT_D", "VFCMP_SULT_D", "VFCMP_SLE_D", "VFCMP_SULE_D", 2234 "VFCMP_SNE_D", "VFCMP_SOR_D", "VFCMP_SUNE_D"] in 2235 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2236 (v2f64 LSX128:$vj), (v2f64 LSX128:$vk)), 2237 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 2238 2239// vty: v4f32/v2f64 2240// Pat<(Intrinsic vty:$vj), 2241// (LAInst vty:$vj)>; 2242foreach Inst = ["VFLOGB_S", "VFCLASS_S", "VFSQRT_S", "VFRECIP_S", "VFRSQRT_S", 2243 "VFRINT_S", "VFCVTL_D_S", "VFCVTH_D_S", 2244 "VFRINTRNE_S", "VFRINTRZ_S", "VFRINTRP_S", "VFRINTRM_S", 2245 "VFTINTRNE_W_S", "VFTINTRZ_W_S", "VFTINTRP_W_S", "VFTINTRM_W_S", 2246 "VFTINT_W_S", "VFTINTRZ_WU_S", "VFTINT_WU_S", 2247 "VFTINTRNEL_L_S", "VFTINTRNEH_L_S", "VFTINTRZL_L_S", 2248 "VFTINTRZH_L_S", "VFTINTRPL_L_S", "VFTINTRPH_L_S", 2249 "VFTINTRML_L_S", "VFTINTRMH_L_S", "VFTINTL_L_S", 2250 "VFTINTH_L_S"] in 2251 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4f32 LSX128:$vj)), 2252 (!cast<LAInst>(Inst) LSX128:$vj)>; 2253foreach Inst = ["VFLOGB_D", "VFCLASS_D", "VFSQRT_D", "VFRECIP_D", "VFRSQRT_D", 2254 "VFRINT_D", 2255 "VFRINTRNE_D", "VFRINTRZ_D", "VFRINTRP_D", "VFRINTRM_D", 2256 "VFTINTRNE_L_D", "VFTINTRZ_L_D", "VFTINTRP_L_D", "VFTINTRM_L_D", 2257 "VFTINT_L_D", "VFTINTRZ_LU_D", "VFTINT_LU_D"] in 2258 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2f64 LSX128:$vj)), 2259 (!cast<LAInst>(Inst) LSX128:$vj)>; 2260 2261// 128-Bit vector FP approximate reciprocal operation 2262let Predicates = [HasFrecipe] in { 2263foreach Inst = ["VFRECIPE_S", "VFRSQRTE_S"] in 2264 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4f32 LSX128:$vj)), 2265 (!cast<LAInst>(Inst) LSX128:$vj)>; 2266foreach Inst = ["VFRECIPE_D", "VFRSQRTE_D"] in 2267 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2f64 LSX128:$vj)), 2268 (!cast<LAInst>(Inst) LSX128:$vj)>; 2269 2270def : Pat<(loongarch_vfrecipe v4f32:$src), 2271 (VFRECIPE_S v4f32:$src)>; 2272def : Pat<(loongarch_vfrecipe v2f64:$src), 2273 (VFRECIPE_D v2f64:$src)>; 2274def : Pat<(loongarch_vfrsqrte v4f32:$src), 2275 (VFRSQRTE_S v4f32:$src)>; 2276def : Pat<(loongarch_vfrsqrte v2f64:$src), 2277 (VFRSQRTE_D v2f64:$src)>; 2278} 2279 2280// Vector floating-point conversion 2281def : Pat<(f32 (fceil FPR32:$fj)), 2282 (f32 (EXTRACT_SUBREG (VFRINTRP_S (VREPLVEI_W 2283 (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>; 2284def : Pat<(f64 (fceil FPR64:$fj)), 2285 (f64 (EXTRACT_SUBREG (VFRINTRP_D (VREPLVEI_D 2286 (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>; 2287def : Pat<(f32 (ffloor FPR32:$fj)), 2288 (f32 (EXTRACT_SUBREG (VFRINTRM_S (VREPLVEI_W 2289 (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>; 2290def : Pat<(f64 (ffloor FPR64:$fj)), 2291 (f64 (EXTRACT_SUBREG (VFRINTRM_D (VREPLVEI_D 2292 (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>; 2293def : Pat<(f32 (ftrunc FPR32:$fj)), 2294 (f32 (EXTRACT_SUBREG (VFRINTRZ_S (VREPLVEI_W 2295 (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>; 2296def : Pat<(f64 (ftrunc FPR64:$fj)), 2297 (f64 (EXTRACT_SUBREG (VFRINTRZ_D (VREPLVEI_D 2298 (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>; 2299def : Pat<(f32 (froundeven FPR32:$fj)), 2300 (f32 (EXTRACT_SUBREG (VFRINTRNE_S (VREPLVEI_W 2301 (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>; 2302def : Pat<(f64 (froundeven FPR64:$fj)), 2303 (f64 (EXTRACT_SUBREG (VFRINTRNE_D (VREPLVEI_D 2304 (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>; 2305 2306// load 2307def : Pat<(int_loongarch_lsx_vld GPR:$rj, timm:$imm), 2308 (VLD GPR:$rj, (to_valid_timm timm:$imm))>; 2309def : Pat<(int_loongarch_lsx_vldx GPR:$rj, GPR:$rk), 2310 (VLDX GPR:$rj, GPR:$rk)>; 2311 2312def : Pat<(int_loongarch_lsx_vldrepl_b GPR:$rj, timm:$imm), 2313 (VLDREPL_B GPR:$rj, (to_valid_timm timm:$imm))>; 2314def : Pat<(int_loongarch_lsx_vldrepl_h GPR:$rj, timm:$imm), 2315 (VLDREPL_H GPR:$rj, (to_valid_timm timm:$imm))>; 2316def : Pat<(int_loongarch_lsx_vldrepl_w GPR:$rj, timm:$imm), 2317 (VLDREPL_W GPR:$rj, (to_valid_timm timm:$imm))>; 2318def : Pat<(int_loongarch_lsx_vldrepl_d GPR:$rj, timm:$imm), 2319 (VLDREPL_D GPR:$rj, (to_valid_timm timm:$imm))>; 2320 2321// store 2322def : Pat<(int_loongarch_lsx_vst LSX128:$vd, GPR:$rj, timm:$imm), 2323 (VST LSX128:$vd, GPR:$rj, (to_valid_timm timm:$imm))>; 2324def : Pat<(int_loongarch_lsx_vstx LSX128:$vd, GPR:$rj, GPR:$rk), 2325 (VSTX LSX128:$vd, GPR:$rj, GPR:$rk)>; 2326 2327def : Pat<(int_loongarch_lsx_vstelm_b v16i8:$vd, GPR:$rj, timm:$imm, timm:$idx), 2328 (VSTELM_B v16i8:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2329 (to_valid_timm timm:$idx))>; 2330def : Pat<(int_loongarch_lsx_vstelm_h v8i16:$vd, GPR:$rj, timm:$imm, timm:$idx), 2331 (VSTELM_H v8i16:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2332 (to_valid_timm timm:$idx))>; 2333def : Pat<(int_loongarch_lsx_vstelm_w v4i32:$vd, GPR:$rj, timm:$imm, timm:$idx), 2334 (VSTELM_W v4i32:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2335 (to_valid_timm timm:$idx))>; 2336def : Pat<(int_loongarch_lsx_vstelm_d v2i64:$vd, GPR:$rj, timm:$imm, timm:$idx), 2337 (VSTELM_D v2i64:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2338 (to_valid_timm timm:$idx))>; 2339 2340} // Predicates = [HasExtLSX] 2341