1//===-- LoongArch.td - Describe the LoongArch Target -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/Target/Target.td" 10 11//===----------------------------------------------------------------------===// 12// LoongArch subtarget features and instruction predicates. 13//===----------------------------------------------------------------------===// 14 15// LoongArch is divided into two versions, the 32-bit version (LA32) and the 16// 64-bit version (LA64). 17def Feature64Bit 18 : SubtargetFeature<"64bit", "HasLA64", "true", 19 "LA64 Basic Integer and Privilege Instruction Set">; 20def Feature32Bit 21 : SubtargetFeature<"32bit", "HasLA32", "true", 22 "LA32 Basic Integer and Privilege Instruction Set">; 23def IsLA64 24 : Predicate<"Subtarget->is64Bit()">, 25 AssemblerPredicate<(all_of Feature64Bit), 26 "LA64 Basic Integer and Privilege Instruction Set">; 27def IsLA32 28 : Predicate<"!Subtarget->is64Bit()">, 29 AssemblerPredicate<(all_of(not Feature64Bit)), 30 "LA32 Basic Integer and Privilege Instruction Set">; 31 32defvar LA32 = DefaultMode; 33def LA64 : HwMode<"+64bit", [IsLA64]>; 34 35// Single Precision floating point 36def FeatureBasicF 37 : SubtargetFeature<"f", "HasBasicF", "true", 38 "'F' (Single-Precision Floating-Point)">; 39def HasBasicF : Predicate<"Subtarget->hasBasicF()">; 40 41// Double Precision floating point 42def FeatureBasicD 43 : SubtargetFeature<"d", "HasBasicD", "true", 44 "'D' (Double-Precision Floating-Point)", 45 [FeatureBasicF]>; 46def HasBasicD : Predicate<"Subtarget->hasBasicD()">; 47 48// Loongson SIMD eXtension (LSX) 49def FeatureExtLSX 50 : SubtargetFeature<"lsx", "HasExtLSX", "true", 51 "'LSX' (Loongson SIMD Extension)", [FeatureBasicD]>; 52def HasExtLSX : Predicate<"Subtarget->hasExtLSX()">; 53 54// Loongson Advanced SIMD eXtension (LASX) 55def FeatureExtLASX 56 : SubtargetFeature<"lasx", "HasExtLASX", "true", 57 "'LASX' (Loongson Advanced SIMD Extension)", 58 [FeatureExtLSX]>; 59def HasExtLASX : Predicate<"Subtarget->hasExtLASX()">; 60 61// Loongson VirtualiZation (LVZ) 62def FeatureExtLVZ 63 : SubtargetFeature<"lvz", "HasExtLVZ", "true", 64 "'LVZ' (Loongson Virtualization Extension)">; 65def HasExtLVZ : Predicate<"Subtarget->hasExtLVZ()">; 66 67// Loongson Binary Translation (LBT) 68def FeatureExtLBT 69 : SubtargetFeature<"lbt", "HasExtLBT", "true", 70 "'LBT' (Loongson Binary Translation Extension)">; 71def HasExtLBT : Predicate<"Subtarget->hasExtLBT()">; 72 73// Expand la.global as la.pcrel 74def LaGlobalWithPcrel 75 : SubtargetFeature<"la-global-with-pcrel", "HasLaGlobalWithPcrel", "true", 76 "Expand la.global as la.pcrel">; 77def HasLaGlobalWithPcrel 78 : Predicate<"Subtarget->hasLaGlobalWithPcrel()">, 79 AssemblerPredicate<(all_of LaGlobalWithPcrel), 80 "Expand la.global as la.pcrel">; 81 82// Expand la.global as la.abs 83def LaGlobalWithAbs 84 : SubtargetFeature<"la-global-with-abs", "HasLaGlobalWithAbs", "true", 85 "Expand la.global as la.abs">; 86def HasLaGlobalWithAbs 87 : Predicate<"Subtarget->hasLaGlobalWithAbs()">, 88 AssemblerPredicate<(all_of LaGlobalWithAbs), 89 "Expand la.global as la.abs">; 90 91// Expand la.local as la.abs 92def LaLocalWithAbs 93 : SubtargetFeature<"la-local-with-abs", "HasLaLocalWithAbs", "true", 94 "Expand la.local as la.abs">; 95def HasLaLocalWithAbs 96 : Predicate<"Subtarget->hasLaLocalWithAbs()">, 97 AssemblerPredicate<(all_of LaLocalWithAbs), 98 "Expand la.local as la.abs">; 99 100// Unaligned memory access 101def FeatureUAL 102 : SubtargetFeature<"ual", "HasUAL", "true", 103 "Allow memory accesses to be unaligned">; 104 105def FeatureRelax 106 : SubtargetFeature<"relax", "HasLinkerRelax", "true", 107 "Enable Linker relaxation">; 108 109// Floating point approximation operation 110def FeatureFrecipe 111 : SubtargetFeature<"frecipe", "HasFrecipe", "true", 112 "Support frecipe.{s/d} and frsqrte.{s/d} instructions.">; 113def HasFrecipe : Predicate<"Subtarget->hasFrecipe()">; 114 115// Atomic memory swap and add instructions for byte and half word 116def FeatureLAM_BH 117 : SubtargetFeature<"lam-bh", "HasLAM_BH", "true", 118 "Support amswap[_db].{b/h} and amadd[_db].{b/h} instructions.">; 119def HasLAM_BH : Predicate<"Subtarget->hasLAM_BH()">; 120 121// Atomic memory compare and swap instructions for byte, half word, word and double word 122def FeatureLAMCAS 123 : SubtargetFeature<"lamcas", "HasLAMCAS", "true", 124 "Support amcas[_db].{b/h/w/d}.">; 125def HasLAMCAS : Predicate<"Subtarget->hasLAMCAS()">; 126 127def FeatureLD_SEQ_SA 128 : SubtargetFeature<"ld-seq-sa", "HasLD_SEQ_SA", "true", 129 "Don't use load-load barrier (dbar 0x700).">; 130def HasLD_SEQ_SA : Predicate<"Subtarget->hasLD_SEQ_SA()">; 131 132// Assume div.w[u] and mod.w[u] can handle inputs that are not sign-extended. 133def FeatureDiv32 134 : SubtargetFeature<"div32", "HasDiv32", "true", 135 "Assume div.w[u] and mod.w[u] can handle inputs that are not sign-extended">; 136def HasDiv32 : Predicate<"Subtarget->hasDiv32()">; 137 138// Support SC.Q instruction 139def FeatureSCQ 140 : SubtargetFeature<"scq", "HasSCQ", "true", 141 "Support sc.q instruction">; 142def HasSCQ : Predicate<"Subtarget->hasSCQ()">; 143 144def TunePreferWInst 145 : SubtargetFeature<"prefer-w-inst", "PreferWInst", "true", 146 "Prefer instructions with W suffix">; 147 148//===----------------------------------------------------------------------===// 149// Registers, instruction descriptions ... 150//===----------------------------------------------------------------------===// 151 152include "LoongArchRegisterInfo.td" 153include "LoongArchCallingConv.td" 154include "LoongArchInstrInfo.td" 155 156//===----------------------------------------------------------------------===// 157// LoongArch processors supported. 158//===----------------------------------------------------------------------===// 159 160def : ProcessorModel<"generic-la32", NoSchedModel, [Feature32Bit]>; 161def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit, 162 FeatureUAL, 163 FeatureExtLSX]>; 164 165// Generic 64-bit processor with double-precision floating-point support. 166def : ProcessorModel<"loongarch64", NoSchedModel, [Feature64Bit, 167 FeatureUAL, 168 FeatureBasicD]>; 169 170// Support generic for compatibility with other targets. The triple will be used 171// to change to the appropriate la32/la64 version. 172def : ProcessorModel<"generic", NoSchedModel, []>; 173 174def : ProcessorModel<"la464", NoSchedModel, [Feature64Bit, 175 FeatureUAL, 176 FeatureExtLASX, 177 FeatureExtLVZ, 178 FeatureExtLBT]>; 179 180def : ProcessorModel<"la664", NoSchedModel, [Feature64Bit, 181 FeatureUAL, 182 FeatureExtLASX, 183 FeatureExtLVZ, 184 FeatureExtLBT, 185 FeatureFrecipe, 186 FeatureLAM_BH, 187 FeatureLAMCAS, 188 FeatureLD_SEQ_SA, 189 FeatureDiv32, 190 FeatureSCQ]>; 191 192//===----------------------------------------------------------------------===// 193// Define the LoongArch target. 194//===----------------------------------------------------------------------===// 195 196def LoongArchInstrInfo : InstrInfo { 197 let guessInstructionProperties = 0; 198} 199 200def LoongArchAsmParser : AsmParser { 201 let ShouldEmitMatchRegisterAltName = 1; 202 let AllowDuplicateRegisterNames = 1; 203} 204 205def LoongArchAsmParserVariant : AsmParserVariant { 206 int Variant = 0; 207 // Recognize hard coded registers. 208 string RegisterPrefix = "$"; 209} 210 211def LoongArchAsmWriter : AsmWriter { 212 int PassSubtarget = 1; 213} 214 215def LoongArch : Target { 216 let InstructionSet = LoongArchInstrInfo; 217 let AssemblyParsers = [LoongArchAsmParser]; 218 let AssemblyParserVariants = [LoongArchAsmParserVariant]; 219 let AssemblyWriters = [LoongArchAsmWriter]; 220 let AllowRegisterRenaming = 1; 221} 222