1//===- HexagonPatterns.td - Selection Patterns for Hexagon -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// Table of contents: 10// (0) Definitions 11// (1) Immediates 12// (2) Type casts 13// (3) Extend/truncate/saturate 14// (4) Logical 15// (5) Compare 16// (6) Select 17// (7) Insert/extract 18// (8) Shift/permute 19// (9) Arithmetic/bitwise 20// (10) Bit 21// (11) PIC 22// (12) Load 23// (13) Store 24// (14) Memop 25// (15) Call 26// (16) Branch 27// (17) Misc 28 29// Guidelines (in no particular order): 30// 1. Avoid relying on pattern ordering to give preference to one pattern 31// over another, prefer using AddedComplexity instead. The reason for 32// this is to avoid unintended conseqeuences (caused by altering the 33// order) when making changes. The current order of patterns in this 34// file obviously does play some role, but none of the ordering was 35// deliberately chosen (other than to create a logical structure of 36// this file). When making changes, adding AddedComplexity to existing 37// patterns may be needed. 38// 2. Maintain the logical structure of the file, try to put new patterns 39// in designated sections. 40// 3. Do not use A2_combinew instruction directly, use Combinew fragment 41// instead. It uses REG_SEQUENCE, which is more amenable to optimizations. 42// 4. Most selection macros are based on PatFrags. For DAGs that involve 43// SDNodes, use pf1/pf2 to convert them to PatFrags. Use common frags 44// whenever possible (see the Definitions section). When adding new 45// macro, try to make is general to enable reuse across sections. 46// 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition 47// that the nested operation has only one use. Having it separated in case 48// of multiple uses avoids duplication of (processor) work. 49// 6. The v4 vector instructions (64-bit) are treated as core instructions, 50// for example, A2_vaddh is in the "arithmetic" section with A2_add. 51// 7. When adding a pattern for an instruction with a constant-extendable 52// operand, allow all possible kinds of inputs for the immediate value 53// (see AnyImm/anyimm and their variants in the Definitions section). 54 55 56// --(0) Definitions ----------------------------------------------------- 57// 58 59// This complex pattern exists only to create a machine instruction operand 60// of type "frame index". There doesn't seem to be a way to do that directly 61// in the patterns. 62def AddrFI: ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>; 63 64// These complex patterns are not strictly necessary, since global address 65// folding will happen during DAG combining. For distinguishing between GA 66// and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used. 67def AddrGA: ComplexPattern<i32, 1, "SelectAddrGA", [], []>; 68def AddrGP: ComplexPattern<i32, 1, "SelectAddrGP", [], []>; 69def AnyImm: ComplexPattern<i32, 1, "SelectAnyImm", [], []>; 70def AnyInt: ComplexPattern<i32, 1, "SelectAnyInt", [], []>; 71 72// Global address or a constant being a multiple of 2^n. 73def AnyImm0: ComplexPattern<i32, 1, "SelectAnyImm0", [], []>; 74def AnyImm1: ComplexPattern<i32, 1, "SelectAnyImm1", [], []>; 75def AnyImm2: ComplexPattern<i32, 1, "SelectAnyImm2", [], []>; 76def AnyImm3: ComplexPattern<i32, 1, "SelectAnyImm3", [], []>; 77 78 79// Type helper frags. 80def V2I1: PatLeaf<(v2i1 PredRegs:$R)>; 81def V4I1: PatLeaf<(v4i1 PredRegs:$R)>; 82def V8I1: PatLeaf<(v8i1 PredRegs:$R)>; 83def V4I8: PatLeaf<(v4i8 IntRegs:$R)>; 84def V2I16: PatLeaf<(v2i16 IntRegs:$R)>; 85 86def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>; 87def V4I16: PatLeaf<(v4i16 DoubleRegs:$R)>; 88def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>; 89 90def SDTVecLeaf: 91 SDTypeProfile<1, 0, [SDTCisVec<0>]>; 92def SDTVecVecIntOp: 93 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>, 94 SDTCisVT<3,i32>]>; 95 96def HexagonPTRUE: SDNode<"HexagonISD::PTRUE", SDTVecLeaf>; 97def HexagonPFALSE: SDNode<"HexagonISD::PFALSE", SDTVecLeaf>; 98def HexagonVALIGN: SDNode<"HexagonISD::VALIGN", SDTVecVecIntOp>; 99def HexagonVALIGNADDR: SDNode<"HexagonISD::VALIGNADDR", SDTIntUnaryOp>; 100def HexagonMULHUS: SDNode<"HexagonISD::MULHUS", SDTIntBinOp>; 101 102def SDTSaturate: 103 SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, SDTCisVT<2, OtherVT>]>; 104def HexagonSSAT: SDNode<"HexagonISD::SSAT", SDTSaturate>; 105def HexagonUSAT: SDNode<"HexagonISD::USAT", SDTSaturate>; 106 107def ptrue: PatFrag<(ops), (HexagonPTRUE)>; 108def pfalse: PatFrag<(ops), (HexagonPFALSE)>; 109def pnot: PatFrag<(ops node:$Pu), (xor node:$Pu, ptrue)>; 110 111def: Pat<(v8i1 (HexagonPFALSE)), (C2_tfrrp (A2_tfrsi (i32 0)))>; 112def: Pat<(v8i1 (HexagonPTRUE)), (C2_tfrrp (A2_tfrsi (i32 -1)))>; 113 114def valign: PatFrag<(ops node:$Vt, node:$Vs, node:$Ru), 115 (HexagonVALIGN node:$Vt, node:$Vs, node:$Ru)>; 116def valignaddr: PatFrag<(ops node:$Addr), (HexagonVALIGNADDR node:$Addr)>; 117 118def ssat: PatFrag<(ops node:$V, node:$Ty), (HexagonSSAT node:$V, node:$Ty)>; 119def usat: PatFrag<(ops node:$V, node:$Ty), (HexagonUSAT node:$V, node:$Ty)>; 120 121// Pattern fragments to extract the low and high subregisters from a 122// 64-bit value. 123def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_lo)>; 124def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_hi)>; 125 126def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{ 127 return isOrEquivalentToAdd(N); 128}]>; 129 130def IsPow2_32: PatLeaf<(i32 imm), [{ 131 uint32_t V = N->getZExtValue(); 132 return isPowerOf2_32(V); 133}]>; 134 135def IsPow2_64: PatLeaf<(i64 imm), [{ 136 uint64_t V = N->getZExtValue(); 137 return isPowerOf2_64(V); 138}]>; 139 140def IsNPow2_32: PatLeaf<(i32 imm), [{ 141 uint32_t NV = ~N->getZExtValue(); 142 return isPowerOf2_32(NV); 143}]>; 144 145def IsPow2_64L: PatLeaf<(i64 imm), [{ 146 uint64_t V = N->getZExtValue(); 147 return isPowerOf2_64(V) && Log2_64(V) < 32; 148}]>; 149 150def IsPow2_64H: PatLeaf<(i64 imm), [{ 151 uint64_t V = N->getZExtValue(); 152 return isPowerOf2_64(V) && Log2_64(V) >= 32; 153}]>; 154 155def IsNPow2_64L: PatLeaf<(i64 imm), [{ 156 uint64_t NV = ~N->getZExtValue(); 157 return isPowerOf2_64(NV) && Log2_64(NV) < 32; 158}]>; 159 160def IsNPow2_64H: PatLeaf<(i64 imm), [{ 161 uint64_t NV = ~N->getZExtValue(); 162 return isPowerOf2_64(NV) && Log2_64(NV) >= 32; 163}]>; 164 165class IsULE<int Width, int Arg>: PatLeaf<(i32 imm), 166 "uint64_t V = N->getZExtValue();" # 167 "return isUInt<" # Width # ">(V) && V <= " # Arg # ";" 168>; 169 170class IsUGT<int Width, int Arg>: PatLeaf<(i32 imm), 171 "uint64_t V = N->getZExtValue();" # 172 "return isUInt<" # Width # ">(V) && V > " # Arg # ";" 173>; 174 175def SDEC1: SDNodeXForm<imm, [{ 176 int32_t V = N->getSExtValue(); 177 return CurDAG->getSignedTargetConstant(V-1, SDLoc(N), MVT::i32); 178}]>; 179 180def UDEC1: SDNodeXForm<imm, [{ 181 uint32_t V = N->getZExtValue(); 182 assert(V >= 1); 183 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32); 184}]>; 185 186def UDEC32: SDNodeXForm<imm, [{ 187 uint32_t V = N->getZExtValue(); 188 assert(V >= 32); 189 return CurDAG->getTargetConstant(V-32, SDLoc(N), MVT::i32); 190}]>; 191 192class Subi<int From>: SDNodeXForm<imm, 193 "int32_t V = " # From # " - N->getSExtValue();" # 194 "return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);" 195>; 196 197def Log2_32: SDNodeXForm<imm, [{ 198 uint32_t V = N->getZExtValue(); 199 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 200}]>; 201 202def Log2_64: SDNodeXForm<imm, [{ 203 uint64_t V = N->getZExtValue(); 204 return CurDAG->getTargetConstant(Log2_64(V), SDLoc(N), MVT::i32); 205}]>; 206 207def LogN2_32: SDNodeXForm<imm, [{ 208 uint32_t NV = ~N->getZExtValue(); 209 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 210}]>; 211 212def LogN2_64: SDNodeXForm<imm, [{ 213 uint64_t NV = ~N->getZExtValue(); 214 return CurDAG->getTargetConstant(Log2_64(NV), SDLoc(N), MVT::i32); 215}]>; 216 217def NegImm8: SDNodeXForm<imm, [{ 218 int8_t NV = -N->getSExtValue(); 219 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 220}]>; 221 222def NegImm16: SDNodeXForm<imm, [{ 223 int16_t NV = -N->getSExtValue(); 224 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 225}]>; 226 227def NegImm32: SDNodeXForm<imm, [{ 228 int32_t NV = -N->getSExtValue(); 229 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 230}]>; 231 232def SplatB: SDNodeXForm<imm, [{ 233 uint32_t V = N->getZExtValue(); 234 assert(isUInt<8>(V) || V >> 8 == 0xFFFFFF); 235 V &= 0xFF; 236 uint32_t S = V << 24 | V << 16 | V << 8 | V; 237 return CurDAG->getTargetConstant(S, SDLoc(N), MVT::i32); 238}]>; 239 240def SplatH: SDNodeXForm<imm, [{ 241 uint32_t V = N->getZExtValue(); 242 assert(isUInt<16>(V) || V >> 16 == 0xFFFF); 243 V &= 0xFFFF; 244 return CurDAG->getTargetConstant(V << 16 | V, SDLoc(N), MVT::i32); 245}]>; 246 247 248// Helpers for type promotions/contractions. 249def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>; 250def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>; 251def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>; 252def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>; 253def ToAext64: OutPatFrag<(ops node:$Rs), 254 (REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>; 255 256def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt), 257 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>; 258 259def addrga: PatLeaf<(i32 AddrGA:$Addr)>; 260def addrgp: PatLeaf<(i32 AddrGP:$Addr)>; 261def anyimm: PatLeaf<(i32 AnyImm:$Imm)>; 262def anyint: PatLeaf<(i32 AnyInt:$Imm)>; 263 264// Global address or an aligned constant. 265def anyimm0: PatLeaf<(i32 AnyImm0:$Addr)>; 266def anyimm1: PatLeaf<(i32 AnyImm1:$Addr)>; 267def anyimm2: PatLeaf<(i32 AnyImm2:$Addr)>; 268def anyimm3: PatLeaf<(i32 AnyImm3:$Addr)>; 269 270def f32ImmPred : PatLeaf<(f32 fpimm:$F)>; 271def f64ImmPred : PatLeaf<(f64 fpimm:$F)>; 272def f32zero: PatLeaf<(f32 fpimm:$F), [{ 273 return N->isExactlyValue(APFloat::getZero(APFloat::IEEEsingle(), false)); 274}]>; 275 276// This complex pattern is really only to detect various forms of 277// sign-extension i32->i64. The selected value will be of type i64 278// whose low word is the value being extended. The high word is 279// unspecified. 280def Usxtw: ComplexPattern<i64, 1, "DetectUseSxtw", [], []>; 281 282def Aext64: PatFrag<(ops node:$Rs), (i64 (anyext node:$Rs))>; 283def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>; 284def Sext64: PatLeaf<(i64 Usxtw:$Rs)>; 285 286def azext: PatFrags<(ops node:$Rs), [(zext node:$Rs), (anyext node:$Rs)]>; 287def asext: PatFrags<(ops node:$Rs), [(sext node:$Rs), (anyext node:$Rs)]>; 288 289def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off), 290 (PS_fi (i32 AddrFI:$Rs), imm:$off)>; 291 292 293// Converters from unary/binary SDNode to PatFrag. 294class pf1<SDNode Op> : PatFrag<(ops node:$a), (Op node:$a)>; 295class pf2<SDNode Op> : PatFrag<(ops node:$a, node:$b), (Op node:$a, node:$b)>; 296 297class Not2<PatFrag P> 298 : PatFrag<(ops node:$A, node:$B), (P node:$A, (not node:$B))>; 299class VNot2<PatFrag P, PatFrag Not> 300 : PatFrag<(ops node:$A, node:$B), (P node:$A, (Not node:$B))>; 301 302// If there is a constant operand that feeds the and/or instruction, 303// do not generate the compound instructions. 304// It is not always profitable, as some times we end up with a transfer. 305// Check the below example. 306// ra = #65820; rb = lsr(rb, #8); rc ^= and (rb, ra) 307// Instead this is preferable. 308// ra = and (#65820, lsr(ra, #8)); rb = xor(rb, ra) 309class Su_ni1<PatFrag Op> 310 : PatFrag<Op.Operands, !head(Op.Fragments), [{ 311 if (hasOneUse(N)){ 312 // Check if Op1 is an immediate operand. 313 SDValue Op1 = N->getOperand(1); 314 return !isa<ConstantSDNode>(Op1); 315 } 316 return false;}], 317 Op.OperandTransform>; 318 319class Su<PatFrag Op> 320 : PatFrag<Op.Operands, !head(Op.Fragments), [{ return hasOneUse(N); }], 321 Op.OperandTransform>; 322 323// Main selection macros. 324 325class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred> 326 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>; 327 328class OpR_RI_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 329 PatFrag RegPred, PatFrag ImmPred> 330 : Pat<(ResType (Op RegPred:$Rs, ImmPred:$I)), 331 (MI RegPred:$Rs, imm:$I)>; 332 333class OpR_RR_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 334 PatFrag RsPred, PatFrag RtPred = RsPred> 335 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 336 (MI RsPred:$Rs, RtPred:$Rt)>; 337 338class AccRRI_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 339 PatFrag RegPred, PatFrag ImmPred> 340 : Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)), 341 (MI RegPred:$Rx, RegPred:$Rs, imm:$I)>; 342 343class AccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 344 PatFrag RxPred, PatFrag RsPred, PatFrag RtPred> 345 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)), 346 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>; 347 348multiclass SelMinMax_pats<PatFrag CmpOp, PatFrag Val, 349 InstHexagon InstA, InstHexagon InstB> { 350 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$A, Val:$B), 351 (InstA Val:$A, Val:$B)>; 352 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$B, Val:$A), 353 (InstB Val:$A, Val:$B)>; 354} 355 356multiclass MinMax_pats<InstHexagon PickT, InstHexagon PickS, 357 SDPatternOperator Sel, SDPatternOperator CmpOp, 358 ValueType CmpType, PatFrag CmpPred> { 359 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), 360 CmpPred:$Vt, CmpPred:$Vs), 361 (PickT CmpPred:$Vs, CmpPred:$Vt)>; 362 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), 363 CmpPred:$Vs, CmpPred:$Vt), 364 (PickS CmpPred:$Vs, CmpPred:$Vt)>; 365} 366 367// Bitcasts between same-size vector types are no-ops, except for the 368// actual type change. 369multiclass NopCast_pat<ValueType Ty1, ValueType Ty2, RegisterClass RC> { 370 def: Pat<(Ty1 (bitconvert (Ty2 RC:$Val))), (Ty1 RC:$Val)>; 371 def: Pat<(Ty2 (bitconvert (Ty1 RC:$Val))), (Ty2 RC:$Val)>; 372} 373 374// Frags for commonly used SDNodes. 375def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>; 376def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>; 377def Mul: pf2<mul>; def Xor: pf2<xor>; def Shl: pf2<shl>; 378 379def Smin: pf2<smin>; def Smax: pf2<smax>; 380def Umin: pf2<umin>; def Umax: pf2<umax>; 381 382def Rol: pf2<rotl>; 383 384def Fptosi: pf1<fp_to_sint>; 385def Fptoui: pf1<fp_to_uint>; 386def Sitofp: pf1<sint_to_fp>; 387def Uitofp: pf1<uint_to_fp>; 388 389 390// --(1) Immediate ------------------------------------------------------- 391// 392 393def Imm64Lo: SDNodeXForm<imm, [{ 394 return CurDAG->getSignedTargetConstant(int32_t(N->getSExtValue()), 395 SDLoc(N), MVT::i32); 396}]>; 397def Imm64Hi: SDNodeXForm<imm, [{ 398 return CurDAG->getSignedTargetConstant(int32_t(N->getSExtValue()>>32), 399 SDLoc(N), MVT::i32); 400}]>; 401 402 403def SDTHexagonCONST32 404 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<0>]>; 405 406def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>; 407def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>; 408def HexagonCONST32: SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>; 409def HexagonCONST32_GP: SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>; 410 411def TruncI64ToI32: SDNodeXForm<imm, [{ 412 return CurDAG->getSignedTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); 413}]>; 414 415def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>; 416def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>; 417 418def: Pat<(HexagonCONST32 tglobaltlsaddr:$A), (A2_tfrsi imm:$A)>; 419def: Pat<(HexagonCONST32 bbl:$A), (A2_tfrsi imm:$A)>; 420def: Pat<(HexagonCONST32 tglobaladdr:$A), (A2_tfrsi imm:$A)>; 421def: Pat<(HexagonCONST32_GP tblockaddress:$A), (A2_tfrsi imm:$A)>; 422def: Pat<(HexagonCONST32_GP tglobaladdr:$A), (A2_tfrsi imm:$A)>; 423def: Pat<(HexagonJT tjumptable:$A), (A2_tfrsi imm:$A)>; 424def: Pat<(HexagonCP tconstpool:$A), (A2_tfrsi imm:$A)>; 425// The HVX load patterns also match CP directly. Make sure that if 426// the selection of this opcode changes, it's updated in all places. 427 428def: Pat<(i1 0), (PS_false)>; 429def: Pat<(i1 1), (PS_true)>; 430def: Pat<(i64 imm:$v), (CONST64 imm:$v)>, 431 Requires<[UseSmallData,NotOptTinyCore]>; 432def: Pat<(i64 imm:$v), 433 (Combinew (A2_tfrsi (Imm64Hi $v)), (A2_tfrsi (Imm64Lo $v)))>; 434 435def ftoi : SDNodeXForm<fpimm, [{ 436 APInt I = N->getValueAPF().bitcastToAPInt(); 437 return CurDAG->getTargetConstant(I.getZExtValue(), SDLoc(N), 438 MVT::getIntegerVT(I.getBitWidth())); 439}]>; 440 441def: Pat<(f32ImmPred:$f), (A2_tfrsi (ftoi $f))>; 442def: Pat<(f64ImmPred:$f), (CONST64 (ftoi $f))>; 443 444def ToI32: OutPatFrag<(ops node:$V), (A2_tfrsi $V)>; 445 446// --(2) Type cast ------------------------------------------------------- 447// 448 449def: OpR_R_pat<F2_conv_sf2df, pf1<fpextend>, f64, F32>; 450def: OpR_R_pat<F2_conv_df2sf, pf1<fpround>, f32, F64>; 451 452def: OpR_R_pat<F2_conv_w2sf, pf1<sint_to_fp>, f32, I32>; 453def: OpR_R_pat<F2_conv_d2sf, pf1<sint_to_fp>, f32, I64>; 454def: OpR_R_pat<F2_conv_w2df, pf1<sint_to_fp>, f64, I32>; 455def: OpR_R_pat<F2_conv_d2df, pf1<sint_to_fp>, f64, I64>; 456 457def: OpR_R_pat<F2_conv_uw2sf, pf1<uint_to_fp>, f32, I32>; 458def: OpR_R_pat<F2_conv_ud2sf, pf1<uint_to_fp>, f32, I64>; 459def: OpR_R_pat<F2_conv_uw2df, pf1<uint_to_fp>, f64, I32>; 460def: OpR_R_pat<F2_conv_ud2df, pf1<uint_to_fp>, f64, I64>; 461 462def: OpR_R_pat<F2_conv_sf2w_chop, pf1<fp_to_sint>, i32, F32>; 463def: OpR_R_pat<F2_conv_df2w_chop, pf1<fp_to_sint>, i32, F64>; 464def: OpR_R_pat<F2_conv_sf2d_chop, pf1<fp_to_sint>, i64, F32>; 465def: OpR_R_pat<F2_conv_df2d_chop, pf1<fp_to_sint>, i64, F64>; 466 467def: OpR_R_pat<F2_conv_sf2uw_chop, pf1<fp_to_uint>, i32, F32>; 468def: OpR_R_pat<F2_conv_df2uw_chop, pf1<fp_to_uint>, i32, F64>; 469def: OpR_R_pat<F2_conv_sf2ud_chop, pf1<fp_to_uint>, i64, F32>; 470def: OpR_R_pat<F2_conv_df2ud_chop, pf1<fp_to_uint>, i64, F64>; 471 472// Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp]. 473def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>; 474def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>; 475def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>; 476def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>; 477 478// Bit convert 32- and 64-bit types. 479// All of these are bitcastable to one another: i32, v2i16, v4i8. 480defm: NopCast_pat<i32, v2i16, IntRegs>; 481defm: NopCast_pat<i32, v4i8, IntRegs>; 482defm: NopCast_pat<v2i16, v4i8, IntRegs>; 483// All of these are bitcastable to one another: i64, v2i32, v4i16, v8i8. 484defm: NopCast_pat<i64, v2i32, DoubleRegs>; 485defm: NopCast_pat<i64, v4i16, DoubleRegs>; 486defm: NopCast_pat<i64, v8i8, DoubleRegs>; 487defm: NopCast_pat<v2i32, v4i16, DoubleRegs>; 488defm: NopCast_pat<v2i32, v8i8, DoubleRegs>; 489defm: NopCast_pat<v4i16, v8i8, DoubleRegs>; 490 491 492// --(3) Extend/truncate/saturate ---------------------------------------- 493// 494 495def: Pat<(sext_inreg I32:$Rs, i8), (A2_sxtb I32:$Rs)>; 496def: Pat<(sext_inreg I32:$Rs, i16), (A2_sxth I32:$Rs)>; 497def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>; 498def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>; 499def: Pat<(sext_inreg I64:$Rs, i8), (A2_sxtw (A2_sxtb (LoReg $Rs)))>; 500 501def: Pat<(i64 (sext I32:$Rs)), (A2_sxtw I32:$Rs)>; 502def: Pat<(Zext64 I32:$Rs), (ToZext64 $Rs)>; 503def: Pat<(Aext64 I32:$Rs), (ToZext64 $Rs)>; 504 505def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>; 506def: Pat<(i1 (trunc I32:$Rs)), (S2_tstbit_i I32:$Rs, 0)>; 507def: Pat<(i1 (trunc I64:$Rs)), (S2_tstbit_i (LoReg $Rs), 0)>; 508 509let AddedComplexity = 20 in { 510 def: Pat<(and I32:$Rs, 255), (A2_zxtb I32:$Rs)>; 511 def: Pat<(and I32:$Rs, 65535), (A2_zxth I32:$Rs)>; 512} 513 514// Extensions from i1 or vectors of i1. 515def: Pat<(i32 (azext I1:$Pu)), (C2_muxii I1:$Pu, 1, 0)>; 516def: Pat<(i64 (azext I1:$Pu)), (ToZext64 (C2_muxii I1:$Pu, 1, 0))>; 517def: Pat<(i32 (sext I1:$Pu)), (C2_muxii I1:$Pu, -1, 0)>; 518def: Pat<(i64 (sext I1:$Pu)), (Combinew (C2_muxii PredRegs:$Pu, -1, 0), 519 (C2_muxii PredRegs:$Pu, -1, 0))>; 520 521def: Pat<(v2i16 (sext V2I1:$Pu)), (S2_vtrunehb (C2_mask V2I1:$Pu))>; 522def: Pat<(v2i32 (sext V2I1:$Pu)), (C2_mask V2I1:$Pu)>; 523def: Pat<(v4i8 (sext V4I1:$Pu)), (S2_vtrunehb (C2_mask V4I1:$Pu))>; 524def: Pat<(v4i16 (sext V4I1:$Pu)), (C2_mask V4I1:$Pu)>; 525def: Pat<(v8i8 (sext V8I1:$Pu)), (C2_mask V8I1:$Pu)>; 526 527def Vsplatpi: OutPatFrag<(ops node:$V), 528 (Combinew (A2_tfrsi $V), (A2_tfrsi $V))>; 529 530def: Pat<(v2i16 (azext V2I1:$Pu)), 531 (A2_andir (S2_vtrunehb (C2_mask V2I1:$Pu)), (i32 0x00010001))>; 532def: Pat<(v2i32 (azext V2I1:$Pu)), 533 (A2_andp (C2_mask V2I1:$Pu), (A2_combineii (i32 1), (i32 1)))>; 534def: Pat<(v4i8 (azext V4I1:$Pu)), 535 (A2_andir (S2_vtrunehb (C2_mask V4I1:$Pu)), (i32 0x01010101))>; 536def: Pat<(v4i16 (azext V4I1:$Pu)), 537 (A2_andp (C2_mask V4I1:$Pu), (Vsplatpi (i32 0x00010001)))>; 538def: Pat<(v8i8 (azext V8I1:$Pu)), 539 (A2_andp (C2_mask V8I1:$Pu), (Vsplatpi (i32 0x01010101)))>; 540 541def: Pat<(v4i16 (azext V4I8:$Rs)), (S2_vzxtbh V4I8:$Rs)>; 542def: Pat<(v2i32 (azext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>; 543def: Pat<(v4i16 (sext V4I8:$Rs)), (S2_vsxtbh V4I8:$Rs)>; 544def: Pat<(v2i32 (sext V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>; 545 546def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)), 547 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>; 548 549def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)), 550 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>; 551 552// Truncate: from vector B copy all 'E'ven 'B'yte elements: 553// A[0] = B[0]; A[1] = B[2]; A[2] = B[4]; A[3] = B[6]; 554def: Pat<(v4i8 (trunc V4I16:$Rs)), 555 (S2_vtrunehb V4I16:$Rs)>; 556 557// Truncate: from vector B copy all 'O'dd 'B'yte elements: 558// A[0] = B[1]; A[1] = B[3]; A[2] = B[5]; A[3] = B[7]; 559// S2_vtrunohb 560 561// Truncate: from vectors B and C copy all 'E'ven 'H'alf-word elements: 562// A[0] = B[0]; A[1] = B[2]; A[2] = C[0]; A[3] = C[2]; 563// S2_vtruneh 564 565def: Pat<(v2i16 (trunc V2I32:$Rs)), 566 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>; 567 568// Truncate to vNi1 569def: Pat<(v2i1 (trunc V2I32:$Rs)), 570 (A4_vcmpweqi (A2_andp V2I32:$Rs, (A2_combineii (i32 1), (i32 1))), 571 (i32 1))>; 572def: Pat<(v4i1 (trunc V4I16:$Rs)), 573 (A4_vcmpheqi (Combinew (A2_andir (HiReg $Rs), (i32 0x00010001)), 574 (A2_andir (LoReg $Rs), (i32 0x00010001))), 575 (i32 1))>; 576def: Pat<(v8i1 (trunc V8I8:$Rs)), 577 (A4_vcmpbeqi (Combinew (A2_andir (HiReg $Rs), (i32 0x01010101)), 578 (A2_andir (LoReg $Rs), (i32 0x01010101))), 579 (i32 1))>; 580 581 582// Saturation: 583// Note: saturation assumes the same signed-ness for the input and the 584// output. 585def: Pat<(i32 (ssat I32:$Rs, i8)), (A2_satb I32:$Rs)>; 586def: Pat<(i32 (ssat I32:$Rs, i16)), (A2_sath I32:$Rs)>; 587def: Pat<(i32 (ssat I64:$Rs, i32)), (A2_sat I64:$Rs)>; 588def: Pat<(i32 (usat I32:$Rs, i8)), (A2_satub I32:$Rs)>; 589def: Pat<(i32 (usat I32:$Rs, i16)), (A2_satuh I32:$Rs)>; 590def: Pat<(i32 (usat I64:$Rs, i32)), 591 (C2_mux (C2_cmpeqi (HiReg $Rs), (i32 0)), (LoReg $Rs), (i32 -1))>; 592 593def: Pat<(v4i8 (ssat V4I16:$Rs, v4i8)), (S2_vsathb V4I16:$Rs)>; 594def: Pat<(v2i16 (ssat V2I32:$Rs, v2i16)), (S2_vsatwh V2I32:$Rs)>; 595def: Pat<(v4i8 (usat V4I16:$Rs, v4i8)), (S2_vsathub V4I16:$Rs)>; 596def: Pat<(v2i16 (usat V2I32:$Rs, v2i16)), (S2_vsatwuh V2I32:$Rs)>; 597 598 599// --(4) Logical --------------------------------------------------------- 600// 601 602def: Pat<(not I1:$Ps), (C2_not I1:$Ps)>; 603def: Pat<(pnot V2I1:$Ps), (C2_not V2I1:$Ps)>; 604def: Pat<(pnot V4I1:$Ps), (C2_not V4I1:$Ps)>; 605def: Pat<(pnot V8I1:$Ps), (C2_not V8I1:$Ps)>; 606def: Pat<(add I1:$Ps, -1), (C2_not I1:$Ps)>; 607 608def: OpR_RR_pat<C2_and, And, i1, I1>; 609def: OpR_RR_pat<C2_or, Or, i1, I1>; 610def: OpR_RR_pat<C2_xor, Xor, i1, I1>; 611def: OpR_RR_pat<C2_andn, Not2<And>, i1, I1>; 612def: OpR_RR_pat<C2_orn, Not2<Or>, i1, I1>; 613 614def: AccRRR_pat<C4_and_and, And, Su<And>, I1, I1, I1>; 615def: AccRRR_pat<C4_and_or, And, Su< Or>, I1, I1, I1>; 616def: AccRRR_pat<C4_or_and, Or, Su<And>, I1, I1, I1>; 617def: AccRRR_pat<C4_or_or, Or, Su< Or>, I1, I1, I1>; 618def: AccRRR_pat<C4_and_andn, And, Su<Not2<And>>, I1, I1, I1>; 619def: AccRRR_pat<C4_and_orn, And, Su<Not2< Or>>, I1, I1, I1>; 620def: AccRRR_pat<C4_or_andn, Or, Su<Not2<And>>, I1, I1, I1>; 621def: AccRRR_pat<C4_or_orn, Or, Su<Not2< Or>>, I1, I1, I1>; 622 623multiclass BoolvOpR_RR_pat<InstHexagon MI, PatFrag VOp> { 624 def: OpR_RR_pat<MI, VOp, v2i1, V2I1>; 625 def: OpR_RR_pat<MI, VOp, v4i1, V4I1>; 626 def: OpR_RR_pat<MI, VOp, v8i1, V8I1>; 627} 628 629multiclass BoolvAccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag VOp> { 630 def: AccRRR_pat<MI, AccOp, VOp, V2I1, V2I1, V2I1>; 631 def: AccRRR_pat<MI, AccOp, VOp, V4I1, V4I1, V4I1>; 632 def: AccRRR_pat<MI, AccOp, VOp, V8I1, V8I1, V8I1>; 633} 634 635defm: BoolvOpR_RR_pat<C2_and, And>; 636defm: BoolvOpR_RR_pat<C2_or, Or>; 637defm: BoolvOpR_RR_pat<C2_xor, Xor>; 638defm: BoolvOpR_RR_pat<C2_andn, VNot2<And, pnot>>; 639defm: BoolvOpR_RR_pat<C2_orn, VNot2< Or, pnot>>; 640 641// op(Ps, op(Pt, Pu)) 642defm: BoolvAccRRR_pat<C4_and_and, And, Su<And>>; 643defm: BoolvAccRRR_pat<C4_and_or, And, Su<Or>>; 644defm: BoolvAccRRR_pat<C4_or_and, Or, Su<And>>; 645defm: BoolvAccRRR_pat<C4_or_or, Or, Su<Or>>; 646 647// op(Ps, op(Pt, !Pu)) 648defm: BoolvAccRRR_pat<C4_and_andn, And, Su<VNot2<And, pnot>>>; 649defm: BoolvAccRRR_pat<C4_and_orn, And, Su<VNot2< Or, pnot>>>; 650defm: BoolvAccRRR_pat<C4_or_andn, Or, Su<VNot2<And, pnot>>>; 651defm: BoolvAccRRR_pat<C4_or_orn, Or, Su<VNot2< Or, pnot>>>; 652 653 654// --(5) Compare --------------------------------------------------------- 655// 656 657// Avoid negated comparisons, i.e. those of form "Pd = !cmp(...)". 658// These cannot form compounds (e.g. J4_cmpeqi_tp0_jump_nt). 659 660def: OpR_RI_pat<C2_cmpeqi, seteq, i1, I32, anyimm>; 661def: OpR_RI_pat<C2_cmpgti, setgt, i1, I32, anyimm>; 662def: OpR_RI_pat<C2_cmpgtui, setugt, i1, I32, anyimm>; 663 664def: Pat<(i1 (setge I32:$Rs, s32_0ImmPred:$s10)), 665 (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10))>; 666def: Pat<(i1 (setuge I32:$Rs, u32_0ImmPred:$u9)), 667 (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9))>; 668 669def: Pat<(i1 (setlt I32:$Rs, s32_0ImmPred:$s10)), 670 (C2_not (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10)))>; 671def: Pat<(i1 (setult I32:$Rs, u32_0ImmPred:$u9)), 672 (C2_not (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9)))>; 673 674// Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones 675// that reverse the order of the operands. 676class RevCmp<PatFrag F> 677 : PatFrag<(ops node:$rhs, node:$lhs), !head(F.Fragments), F.PredicateCode, 678 F.OperandTransform>; 679 680def: OpR_RR_pat<C2_cmpeq, seteq, i1, I32>; 681def: OpR_RR_pat<C2_cmpgt, setgt, i1, I32>; 682def: OpR_RR_pat<C2_cmpgtu, setugt, i1, I32>; 683def: OpR_RR_pat<C2_cmpgt, RevCmp<setlt>, i1, I32>; 684def: OpR_RR_pat<C2_cmpgtu, RevCmp<setult>, i1, I32>; 685def: OpR_RR_pat<C2_cmpeqp, seteq, i1, I64>; 686def: OpR_RR_pat<C2_cmpgtp, setgt, i1, I64>; 687def: OpR_RR_pat<C2_cmpgtup, setugt, i1, I64>; 688def: OpR_RR_pat<C2_cmpgtp, RevCmp<setlt>, i1, I64>; 689def: OpR_RR_pat<C2_cmpgtup, RevCmp<setult>, i1, I64>; 690def: OpR_RR_pat<A2_vcmpbeq, seteq, i1, V8I8>; 691def: OpR_RR_pat<A2_vcmpbeq, seteq, v8i1, V8I8>; 692def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, i1, V8I8>; 693def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, v8i1, V8I8>; 694def: OpR_RR_pat<A4_vcmpbgt, setgt, i1, V8I8>; 695def: OpR_RR_pat<A4_vcmpbgt, setgt, v8i1, V8I8>; 696def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, i1, V8I8>; 697def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, v8i1, V8I8>; 698def: OpR_RR_pat<A2_vcmpbgtu, setugt, i1, V8I8>; 699def: OpR_RR_pat<A2_vcmpbgtu, setugt, v8i1, V8I8>; 700def: OpR_RR_pat<A2_vcmpheq, seteq, i1, V4I16>; 701def: OpR_RR_pat<A2_vcmpheq, seteq, v4i1, V4I16>; 702def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, i1, V4I16>; 703def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, v4i1, V4I16>; 704def: OpR_RR_pat<A2_vcmphgt, setgt, i1, V4I16>; 705def: OpR_RR_pat<A2_vcmphgt, setgt, v4i1, V4I16>; 706def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, i1, V4I16>; 707def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, v4i1, V4I16>; 708def: OpR_RR_pat<A2_vcmphgtu, setugt, i1, V4I16>; 709def: OpR_RR_pat<A2_vcmphgtu, setugt, v4i1, V4I16>; 710def: OpR_RR_pat<A2_vcmpweq, seteq, i1, V2I32>; 711def: OpR_RR_pat<A2_vcmpweq, seteq, v2i1, V2I32>; 712def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, i1, V2I32>; 713def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, v2i1, V2I32>; 714def: OpR_RR_pat<A2_vcmpwgt, setgt, i1, V2I32>; 715def: OpR_RR_pat<A2_vcmpwgt, setgt, v2i1, V2I32>; 716def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, i1, V2I32>; 717def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, v2i1, V2I32>; 718def: OpR_RR_pat<A2_vcmpwgtu, setugt, i1, V2I32>; 719def: OpR_RR_pat<A2_vcmpwgtu, setugt, v2i1, V2I32>; 720 721def: OpR_RR_pat<F2_sfcmpeq, seteq, i1, F32>; 722def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>; 723def: OpR_RR_pat<F2_sfcmpge, setge, i1, F32>; 724def: OpR_RR_pat<F2_sfcmpeq, setoeq, i1, F32>; 725def: OpR_RR_pat<F2_sfcmpgt, setogt, i1, F32>; 726def: OpR_RR_pat<F2_sfcmpge, setoge, i1, F32>; 727def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setolt>, i1, F32>; 728def: OpR_RR_pat<F2_sfcmpge, RevCmp<setole>, i1, F32>; 729def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setlt>, i1, F32>; 730def: OpR_RR_pat<F2_sfcmpge, RevCmp<setle>, i1, F32>; 731def: OpR_RR_pat<F2_sfcmpuo, setuo, i1, F32>; 732 733def: OpR_RR_pat<F2_dfcmpeq, seteq, i1, F64>; 734def: OpR_RR_pat<F2_dfcmpgt, setgt, i1, F64>; 735def: OpR_RR_pat<F2_dfcmpge, setge, i1, F64>; 736def: OpR_RR_pat<F2_dfcmpeq, setoeq, i1, F64>; 737def: OpR_RR_pat<F2_dfcmpgt, setogt, i1, F64>; 738def: OpR_RR_pat<F2_dfcmpge, setoge, i1, F64>; 739def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setolt>, i1, F64>; 740def: OpR_RR_pat<F2_dfcmpge, RevCmp<setole>, i1, F64>; 741def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setlt>, i1, F64>; 742def: OpR_RR_pat<F2_dfcmpge, RevCmp<setle>, i1, F64>; 743def: OpR_RR_pat<F2_dfcmpuo, setuo, i1, F64>; 744 745// Avoid C4_cmpneqi, C4_cmpltei, C4_cmplteui, since they cannot form compounds. 746 747def: Pat<(i1 (setne I32:$Rs, anyimm:$u5)), 748 (C2_not (C2_cmpeqi I32:$Rs, imm:$u5))>; 749def: Pat<(i1 (setle I32:$Rs, anyimm:$u5)), 750 (C2_not (C2_cmpgti I32:$Rs, imm:$u5))>; 751def: Pat<(i1 (setule I32:$Rs, anyimm:$u5)), 752 (C2_not (C2_cmpgtui I32:$Rs, imm:$u5))>; 753 754class OpmR_RR_pat<PatFrag Output, PatFrag Op, ValueType ResType, 755 PatFrag RsPred, PatFrag RtPred = RsPred> 756 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 757 (Output RsPred:$Rs, RtPred:$Rt)>; 758 759class Outn<InstHexagon MI> 760 : OutPatFrag<(ops node:$Rs, node:$Rt), 761 (C2_not (MI $Rs, $Rt))>; 762 763def: OpmR_RR_pat<Outn<C2_cmpeq>, setne, i1, I32>; 764def: OpmR_RR_pat<Outn<C2_cmpgt>, setle, i1, I32>; 765def: OpmR_RR_pat<Outn<C2_cmpgtu>, setule, i1, I32>; 766def: OpmR_RR_pat<Outn<C2_cmpgt>, RevCmp<setge>, i1, I32>; 767def: OpmR_RR_pat<Outn<C2_cmpgtu>, RevCmp<setuge>, i1, I32>; 768def: OpmR_RR_pat<Outn<C2_cmpeqp>, setne, i1, I64>; 769def: OpmR_RR_pat<Outn<C2_cmpgtp>, setle, i1, I64>; 770def: OpmR_RR_pat<Outn<C2_cmpgtup>, setule, i1, I64>; 771def: OpmR_RR_pat<Outn<C2_cmpgtp>, RevCmp<setge>, i1, I64>; 772def: OpmR_RR_pat<Outn<C2_cmpgtup>, RevCmp<setuge>, i1, I64>; 773def: OpmR_RR_pat<Outn<A2_vcmpbeq>, setne, v8i1, V8I8>; 774def: OpmR_RR_pat<Outn<A4_vcmpbgt>, setle, v8i1, V8I8>; 775def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, setule, v8i1, V8I8>; 776def: OpmR_RR_pat<Outn<A4_vcmpbgt>, RevCmp<setge>, v8i1, V8I8>; 777def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, RevCmp<setuge>, v8i1, V8I8>; 778def: OpmR_RR_pat<Outn<A2_vcmpheq>, setne, v4i1, V4I16>; 779def: OpmR_RR_pat<Outn<A2_vcmphgt>, setle, v4i1, V4I16>; 780def: OpmR_RR_pat<Outn<A2_vcmphgtu>, setule, v4i1, V4I16>; 781def: OpmR_RR_pat<Outn<A2_vcmphgt>, RevCmp<setge>, v4i1, V4I16>; 782def: OpmR_RR_pat<Outn<A2_vcmphgtu>, RevCmp<setuge>, v4i1, V4I16>; 783def: OpmR_RR_pat<Outn<A2_vcmpweq>, setne, v2i1, V2I32>; 784def: OpmR_RR_pat<Outn<A2_vcmpwgt>, setle, v2i1, V2I32>; 785def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, setule, v2i1, V2I32>; 786def: OpmR_RR_pat<Outn<A2_vcmpwgt>, RevCmp<setge>, v2i1, V2I32>; 787def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, RevCmp<setuge>, v2i1, V2I32>; 788 789let AddedComplexity = 100 in { 790 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 255), 0)), 791 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>; 792 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 255), 0)), 793 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>; 794 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 795 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>; 796 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 797 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>; 798} 799 800// PatFrag for AsserZext which takes the original type as a parameter. 801def SDTAssertZext: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,1>]>; 802def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>; 803class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>; 804 805multiclass Cmpb_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 806 PatLeaf ImmPred, int Mask> { 807 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 808 (MI I32:$Rs, imm:$I)>; 809 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 810 (MI I32:$Rs, imm:$I)>; 811} 812 813multiclass CmpbN_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 814 PatLeaf ImmPred, int Mask> { 815 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 816 (C2_not (MI I32:$Rs, imm:$I))>; 817 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 818 (C2_not (MI I32:$Rs, imm:$I))>; 819} 820 821multiclass CmpbND_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 822 PatLeaf ImmPred, int Mask> { 823 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 824 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 825 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 826 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 827} 828 829let AddedComplexity = 200 in { 830 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>; 831 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>; 832 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>; 833 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>; 834 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>; 835 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>; 836 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>; 837 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>; 838} 839 840def: Pat<(i32 (zext (i1 (seteq I32:$Rs, I32:$Rt)))), 841 (A4_rcmpeq I32:$Rs, I32:$Rt)>; 842def: Pat<(i32 (zext (i1 (setne I32:$Rs, I32:$Rt)))), 843 (A4_rcmpneq I32:$Rs, I32:$Rt)>; 844def: Pat<(i32 (zext (i1 (seteq I32:$Rs, anyimm:$s8)))), 845 (A4_rcmpeqi I32:$Rs, imm:$s8)>; 846def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))), 847 (A4_rcmpneqi I32:$Rs, imm:$s8)>; 848 849def: Pat<(i1 (seteq I1:$Ps, (i1 -1))), (I1:$Ps)>; 850def: Pat<(i1 (setne I1:$Ps, (i1 -1))), (C2_not I1:$Ps)>; 851def: Pat<(i1 (seteq I1:$Ps, I1:$Pt)), (C2_not (C2_xor I1:$Ps, I1:$Pt))>; 852def: Pat<(i1 (setne I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>; 853 854multiclass BoolE_pat<PatFrag OpPred, ValueType ResTy> { 855 def: Pat<(ResTy (seteq OpPred:$Ps, OpPred:$Pt)), (C2_not (C2_xor $Ps, $Pt))>; 856 def: Pat<(ResTy (setne OpPred:$Ps, OpPred:$Pt)), (C2_xor $Ps, $Pt)>; 857} 858 859defm: BoolE_pat<I1, i1>; 860defm: BoolE_pat<V2I1, v2i1>; 861defm: BoolE_pat<V4I1, v4i1>; 862defm: BoolE_pat<V8I1, v8i1>; 863 864multiclass BoolL_pat<PatFrag OpPred, ValueType ResTy> { 865 // Signed "true" == -1 866 def: Pat<(ResTy (setlt OpPred:$Ps, OpPred:$Pt)), (C2_andn $Ps, $Pt)>; 867 def: Pat<(ResTy (setle OpPred:$Ps, OpPred:$Pt)), (C2_orn $Ps, $Pt)>; 868 def: Pat<(ResTy (setult OpPred:$Ps, OpPred:$Pt)), (C2_andn $Pt, $Ps)>; 869 def: Pat<(ResTy (setule OpPred:$Ps, OpPred:$Pt)), (C2_orn $Pt, $Ps)>; 870} 871 872defm: BoolL_pat<I1, i1>; 873defm: BoolL_pat<V2I1, v2i1>; 874defm: BoolL_pat<V4I1, v4i1>; 875defm: BoolL_pat<V8I1, v8i1>; 876 877// Floating-point comparisons with checks for ordered/unordered status. 878 879class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3> 880 : OutPatFrag<(ops node:$Rs, node:$Rt), 881 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>; 882 883class Cmpuf<InstHexagon MI>: T3<C2_or, F2_sfcmpuo, MI>; 884class Cmpud<InstHexagon MI>: T3<C2_or, F2_dfcmpuo, MI>; 885 886class Cmpufn<InstHexagon MI>: T3<C2_orn, F2_sfcmpuo, MI>; 887class Cmpudn<InstHexagon MI>: T3<C2_orn, F2_dfcmpuo, MI>; 888 889def: OpmR_RR_pat<Cmpuf<F2_sfcmpeq>, setueq, i1, F32>; 890def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, setuge, i1, F32>; 891def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, setugt, i1, F32>; 892def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, RevCmp<setule>, i1, F32>; 893def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, RevCmp<setult>, i1, F32>; 894def: OpmR_RR_pat<Cmpufn<F2_sfcmpeq>, setune, i1, F32>; 895 896def: OpmR_RR_pat<Cmpud<F2_dfcmpeq>, setueq, i1, F64>; 897def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, setuge, i1, F64>; 898def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, setugt, i1, F64>; 899def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, RevCmp<setule>, i1, F64>; 900def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, RevCmp<setult>, i1, F64>; 901def: OpmR_RR_pat<Cmpudn<F2_dfcmpeq>, setune, i1, F64>; 902 903def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setone, i1, F32>; 904def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setne, i1, F32>; 905 906def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setone, i1, F64>; 907def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setne, i1, F64>; 908 909def: OpmR_RR_pat<Outn<F2_sfcmpuo>, seto, i1, F32>; 910def: OpmR_RR_pat<Outn<F2_dfcmpuo>, seto, i1, F64>; 911 912 913// --(6) Select ---------------------------------------------------------- 914// 915 916def: Pat<(select I1:$Pu, I32:$Rs, I32:$Rt), 917 (C2_mux I1:$Pu, I32:$Rs, I32:$Rt)>; 918def: Pat<(select I1:$Pu, v4i8:$Rs, v4i8:$Rt), 919 (C2_mux I1:$Pu, v4i8:$Rs, v4i8:$Rt)>; 920def: Pat<(select I1:$Pu, v2i16:$Rs, v2i16:$Rt), 921 (C2_mux I1:$Pu, v2i16:$Rs, v2i16:$Rt)>; 922def: Pat<(select I1:$Pu, anyimm:$s8, I32:$Rs), 923 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 924def: Pat<(select I1:$Pu, I32:$Rs, anyimm:$s8), 925 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 926def: Pat<(select I1:$Pu, anyimm:$s8, s8_0ImmPred:$S8), 927 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 928 929def: Pat<(select (not I1:$Pu), I32:$Rs, I32:$Rt), 930 (C2_mux I1:$Pu, I32:$Rt, I32:$Rs)>; 931def: Pat<(select (not I1:$Pu), s8_0ImmPred:$S8, anyimm:$s8), 932 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 933def: Pat<(select (not I1:$Pu), anyimm:$s8, I32:$Rs), 934 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 935def: Pat<(select (not I1:$Pu), I32:$Rs, anyimm:$s8), 936 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 937 938// Map from a 64-bit select to an emulated 64-bit mux. 939// Hexagon does not support 64-bit MUXes; so emulate with combines. 940def: Pat<(select I1:$Pu, I64:$Rs, I64:$Rt), 941 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 942 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 943 944def: Pat<(select I1:$Pu, v2i32:$Rs, v2i32:$Rt), 945 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 946 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 947 948def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I), 949 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 950def: Pat<(select I1:$Pu, f32ImmPred:$I, F32:$Rt), 951 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 952def: Pat<(select I1:$Pu, F32:$Rs, F32:$Rt), 953 (C2_mux I1:$Pu, F32:$Rs, F32:$Rt)>; 954def: Pat<(select I1:$Pu, F64:$Rs, F64:$Rt), 955 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 956 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 957 958def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt), 959 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>; 960def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt), 961 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>; 962 963def: Pat<(select (not I1:$Pu), f32ImmPred:$I, F32:$Rs), 964 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 965def: Pat<(select (not I1:$Pu), F32:$Rt, f32ImmPred:$I), 966 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 967 968def: Pat<(vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt), 969 (C2_vmux V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)>; 970def: Pat<(vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt), 971 (C2_vmux V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)>; 972def: Pat<(vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt), 973 (C2_vmux V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)>; 974 975def: Pat<(vselect (pnot V8I1:$Pu), V8I8:$Rs, V8I8:$Rt), 976 (C2_vmux V8I1:$Pu, V8I8:$Rt, V8I8:$Rs)>; 977def: Pat<(vselect (pnot V4I1:$Pu), V4I16:$Rs, V4I16:$Rt), 978 (C2_vmux V4I1:$Pu, V4I16:$Rt, V4I16:$Rs)>; 979def: Pat<(vselect (pnot V2I1:$Pu), V2I32:$Rs, V2I32:$Rt), 980 (C2_vmux V2I1:$Pu, V2I32:$Rt, V2I32:$Rs)>; 981 982 983// From LegalizeDAG.cpp: (Pu ? Pv : Pw) <=> (Pu & Pv) | (!Pu & Pw). 984def: Pat<(select I1:$Pu, I1:$Ps, I1:$Pt), 985 (C4_or_andn (C2_and $Ps, $Pu), $Pt, $Pu)>; 986 987def: Pat<(vselect V2I1:$Pu, V2I1:$Ps, V2I1:$Pt), 988 (C4_or_andn (C2_and $Ps, $Pu), $Pt, $Pu)>; 989def: Pat<(vselect V4I1:$Pu, V4I1:$Ps, V4I1:$Pt), 990 (C4_or_andn (C2_and $Ps, $Pu), $Pt, $Pu)>; 991def: Pat<(vselect V8I1:$Pu, V8I1:$Ps, V8I1:$Pt), 992 (C4_or_andn (C2_and $Ps, $Pu), $Pt, $Pu)>; 993 994def: Pat<(select I1:$Pu, V2I1:$Ps, V2I1:$Pt), 995 (C2_tfrrp (C2_mux $Pu, (C2_tfrpr $Ps), (C2_tfrpr $Pt)))>; 996def: Pat<(select I1:$Pu, V4I1:$Ps, V4I1:$Pt), 997 (C2_tfrrp (C2_mux $Pu, (C2_tfrpr $Ps), (C2_tfrpr $Pt)))>; 998def: Pat<(select I1:$Pu, V8I1:$Ps, V8I1:$Pt), 999 (C2_tfrrp (C2_mux $Pu, (C2_tfrpr $Ps), (C2_tfrpr $Pt)))>; 1000 1001def IsPosHalf : PatLeaf<(i32 IntRegs:$a), [{ 1002 return isPositiveHalfWord(N); 1003}]>; 1004 1005multiclass SelMinMax16_pats<PatFrag CmpOp, InstHexagon InstA, 1006 InstHexagon InstB> { 1007 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 1008 IsPosHalf:$Rs, IsPosHalf:$Rt), i16), 1009 (InstA IntRegs:$Rs, IntRegs:$Rt)>; 1010 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 1011 IsPosHalf:$Rt, IsPosHalf:$Rs), i16), 1012 (InstB IntRegs:$Rs, IntRegs:$Rt)>; 1013} 1014 1015let AddedComplexity = 200 in { 1016 defm: SelMinMax16_pats<setge, A2_max, A2_min>; 1017 defm: SelMinMax16_pats<setgt, A2_max, A2_min>; 1018 defm: SelMinMax16_pats<setle, A2_min, A2_max>; 1019 defm: SelMinMax16_pats<setlt, A2_min, A2_max>; 1020 defm: SelMinMax16_pats<setuge, A2_maxu, A2_minu>; 1021 defm: SelMinMax16_pats<setugt, A2_maxu, A2_minu>; 1022 defm: SelMinMax16_pats<setule, A2_minu, A2_maxu>; 1023 defm: SelMinMax16_pats<setult, A2_minu, A2_maxu>; 1024} 1025 1026def: OpR_RR_pat<A2_min, Smin, i32, I32, I32>; 1027def: OpR_RR_pat<A2_max, Smax, i32, I32, I32>; 1028def: OpR_RR_pat<A2_minu, Umin, i32, I32, I32>; 1029def: OpR_RR_pat<A2_maxu, Umax, i32, I32, I32>; 1030def: OpR_RR_pat<A2_minp, Smin, i64, I64, I64>; 1031def: OpR_RR_pat<A2_maxp, Smax, i64, I64, I64>; 1032def: OpR_RR_pat<A2_minup, Umin, i64, I64, I64>; 1033def: OpR_RR_pat<A2_maxup, Umax, i64, I64, I64>; 1034 1035let AddedComplexity = 100 in { 1036 defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setogt, i1, F32>; 1037 defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setoge, i1, F32>; 1038 defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setolt, i1, F32>; 1039 defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setole, i1, F32>; 1040} 1041 1042let AddedComplexity = 100, Predicates = [HasV67] in { 1043 defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setogt, i1, F64>; 1044 defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setoge, i1, F64>; 1045 defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setolt, i1, F64>; 1046 defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setole, i1, F64>; 1047} 1048 1049def: OpR_RR_pat<A2_vminb, Smin, v8i8, V8I8>; 1050def: OpR_RR_pat<A2_vmaxb, Smax, v8i8, V8I8>; 1051def: OpR_RR_pat<A2_vminub, Umin, v8i8, V8I8>; 1052def: OpR_RR_pat<A2_vmaxub, Umax, v8i8, V8I8>; 1053 1054def: OpR_RR_pat<A2_vminh, Smin, v4i16, V4I16>; 1055def: OpR_RR_pat<A2_vmaxh, Smax, v4i16, V4I16>; 1056def: OpR_RR_pat<A2_vminuh, Umin, v4i16, V4I16>; 1057def: OpR_RR_pat<A2_vmaxuh, Umax, v4i16, V4I16>; 1058 1059def: OpR_RR_pat<A2_vminw, Smin, v2i32, V2I32>; 1060def: OpR_RR_pat<A2_vmaxw, Smax, v2i32, V2I32>; 1061def: OpR_RR_pat<A2_vminuw, Umin, v2i32, V2I32>; 1062def: OpR_RR_pat<A2_vmaxuw, Umax, v2i32, V2I32>; 1063 1064// --(7) Insert/extract -------------------------------------------------- 1065// 1066 1067def SDTHexagonINSERT: 1068 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 1069 SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>; 1070def HexagonINSERT: SDNode<"HexagonISD::INSERT", SDTHexagonINSERT>; 1071 1072let AddedComplexity = 10 in { 1073 def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2), 1074 (S2_insert I32:$Rs, I32:$Rt, imm:$u1, imm:$u2)>; 1075 def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2), 1076 (S2_insertp I64:$Rs, I64:$Rt, imm:$u1, imm:$u2)>; 1077} 1078def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, I32:$Width, I32:$Off), 1079 (S2_insert_rp I32:$Rs, I32:$Rt, (Combinew $Width, $Off))>; 1080def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, I32:$Width, I32:$Off), 1081 (S2_insertp_rp I64:$Rs, I64:$Rt, (Combinew $Width, $Off))>; 1082 1083def SDTHexagonEXTRACTU 1084 : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>, 1085 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 1086def HexagonEXTRACTU: SDNode<"HexagonISD::EXTRACTU", SDTHexagonEXTRACTU>; 1087 1088let AddedComplexity = 10 in { 1089 def: Pat<(HexagonEXTRACTU I32:$Rs, u5_0ImmPred:$u5, u5_0ImmPred:$U5), 1090 (S2_extractu I32:$Rs, imm:$u5, imm:$U5)>; 1091 def: Pat<(HexagonEXTRACTU I64:$Rs, u6_0ImmPred:$u6, u6_0ImmPred:$U6), 1092 (S2_extractup I64:$Rs, imm:$u6, imm:$U6)>; 1093} 1094def: Pat<(HexagonEXTRACTU I32:$Rs, I32:$Width, I32:$Off), 1095 (S2_extractu_rp I32:$Rs, (Combinew $Width, $Off))>; 1096def: Pat<(HexagonEXTRACTU I64:$Rs, I32:$Width, I32:$Off), 1097 (S2_extractup_rp I64:$Rs, (Combinew $Width, $Off))>; 1098 1099def: Pat<(v4i8 (splat_vector anyint:$V)), (ToI32 (SplatB $V))>; 1100def: Pat<(v2i16 (splat_vector anyint:$V)), (ToI32 (SplatH $V))>; 1101def: Pat<(v8i8 (splat_vector anyint:$V)), 1102 (Combinew (ToI32 (SplatB $V)), (ToI32 (SplatB $V)))>; 1103def: Pat<(v4i16 (splat_vector anyint:$V)), 1104 (Combinew (ToI32 (SplatH $V)), (ToI32 (SplatH $V)))>; 1105let AddedComplexity = 10 in 1106def: Pat<(v2i32 (splat_vector s8_0ImmPred:$s8)), 1107 (A2_combineii imm:$s8, imm:$s8)>; 1108def: Pat<(v2i32 (splat_vector anyimm:$V)), (Combinew (ToI32 $V), (ToI32 $V))>; 1109 1110def: Pat<(v4i8 (splat_vector I32:$Rs)), (S2_vsplatrb I32:$Rs)>; 1111def: Pat<(v2i16 (splat_vector I32:$Rs)), (LoReg (S2_vsplatrh I32:$Rs))>; 1112def: Pat<(v4i16 (splat_vector I32:$Rs)), (S2_vsplatrh I32:$Rs)>; 1113def: Pat<(v2i32 (splat_vector I32:$Rs)), (Combinew I32:$Rs, I32:$Rs)>; 1114 1115let AddedComplexity = 10 in 1116def: Pat<(v8i8 (splat_vector I32:$Rs)), (S6_vsplatrbp I32:$Rs)>, 1117 Requires<[HasV62]>; 1118def: Pat<(v8i8 (splat_vector I32:$Rs)), 1119 (Combinew (S2_vsplatrb I32:$Rs), (S2_vsplatrb I32:$Rs))>; 1120 1121let AddedComplexity = 10 in { 1122 def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 8, u5_0ImmPred:$U5), i8), 1123 (S4_extract I32:$Rs, 8, imm:$U5)>; 1124 def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 16, u5_0ImmPred:$U5), i16), 1125 (S4_extract I32:$Rs, 16, imm:$U5)>; 1126 def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 8, u6_0ImmPred:$U6), i8), 1127 (S4_extractp I64:$Rs, 8, imm:$U6)>; 1128 def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 16, u6_0ImmPred:$U6), i16), 1129 (S4_extractp I64:$Rs, 16, imm:$U6)>; 1130 def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 32, u6_0ImmPred:$U6), i32), 1131 (S4_extractp I64:$Rs, 32, imm:$U6)>; 1132} 1133 1134def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 8, I32:$Off), i8), 1135 (S4_extract_rp I32:$Rs, (Combinew (ToI32 8), I32:$Off))>; 1136def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 16, I32:$Off), i16), 1137 (S4_extract_rp I32:$Rs, (Combinew (ToI32 16), I32:$Off))>; 1138def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 8, I32:$Off), i8), 1139 (S4_extractp_rp I64:$Rs, (Combinew (ToI32 8), I32:$Off))>; 1140def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 16, I32:$Off), i16), 1141 (S4_extractp_rp I64:$Rs, (Combinew (ToI32 16), I32:$Off))>; 1142def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 32, I32:$Off), i32), 1143 (S4_extractp_rp I64:$Rs, (Combinew (ToI32 32), I32:$Off))>; 1144 1145 1146// --(8) Shift/permute --------------------------------------------------- 1147// 1148 1149def SDTHexagonI64I32I32: SDTypeProfile<1, 2, 1150 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 1151 1152def HexagonCOMBINE: SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>; 1153 1154def: Pat<(HexagonCOMBINE I32:$Rs, I32:$Rt), (Combinew $Rs, $Rt)>; 1155 1156// The complexity of the combines involving immediates should be greater 1157// than the complexity of the combine with two registers. 1158let AddedComplexity = 50 in { 1159 def: Pat<(HexagonCOMBINE I32:$Rs, anyimm:$s8), 1160 (A4_combineri IntRegs:$Rs, imm:$s8)>; 1161 def: Pat<(HexagonCOMBINE anyimm:$s8, I32:$Rs), 1162 (A4_combineir imm:$s8, IntRegs:$Rs)>; 1163} 1164 1165// The complexity of the combine with two immediates should be greater than 1166// the complexity of a combine involving a register. 1167let AddedComplexity = 75 in { 1168 def: Pat<(HexagonCOMBINE s8_0ImmPred:$s8, anyimm:$u6), 1169 (A4_combineii imm:$s8, imm:$u6)>; 1170 def: Pat<(HexagonCOMBINE anyimm:$s8, s8_0ImmPred:$S8), 1171 (A2_combineii imm:$s8, imm:$S8)>; 1172} 1173 1174def: Pat<(bswap I32:$Rs), (A2_swiz I32:$Rs)>; 1175def: Pat<(bswap I64:$Rss), (Combinew (A2_swiz (LoReg $Rss)), 1176 (A2_swiz (HiReg $Rss)))>; 1177 1178def: Pat<(bswap V2I16:$Rs), (A2_combine_lh (A2_swiz $Rs), (A2_swiz $Rs))>; 1179def: Pat<(bswap V2I32:$Rs), (Combinew (A2_swiz (HiReg $Rs)), 1180 (A2_swiz (LoReg $Rs)))>; 1181def: Pat<(bswap V4I16:$Rs), (A2_orp (S2_lsr_i_vh $Rs, 8), 1182 (S2_asl_i_vh $Rs, 8))>; 1183 1184def: Pat<(shl s6_0ImmPred:$s6, I32:$Rt), (S4_lsli imm:$s6, I32:$Rt)>; 1185def: Pat<(shl I32:$Rs, (i32 16)), (A2_aslh I32:$Rs)>; 1186def: Pat<(sra I32:$Rs, (i32 16)), (A2_asrh I32:$Rs)>; 1187 1188def: OpR_RI_pat<S2_asr_i_r, Sra, i32, I32, u5_0ImmPred>; 1189def: OpR_RI_pat<S2_lsr_i_r, Srl, i32, I32, u5_0ImmPred>; 1190def: OpR_RI_pat<S2_asl_i_r, Shl, i32, I32, u5_0ImmPred>; 1191def: OpR_RI_pat<S2_asr_i_p, Sra, i64, I64, u6_0ImmPred>; 1192def: OpR_RI_pat<S2_lsr_i_p, Srl, i64, I64, u6_0ImmPred>; 1193def: OpR_RI_pat<S2_asl_i_p, Shl, i64, I64, u6_0ImmPred>; 1194def: OpR_RI_pat<S2_asr_i_vh, Sra, v4i16, V4I16, u4_0ImmPred>; 1195def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>; 1196def: OpR_RI_pat<S2_asl_i_vh, Shl, v4i16, V4I16, u4_0ImmPred>; 1197def: OpR_RI_pat<S2_asr_i_vh, Sra, v2i32, V2I32, u5_0ImmPred>; 1198def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>; 1199def: OpR_RI_pat<S2_asl_i_vh, Shl, v2i32, V2I32, u5_0ImmPred>; 1200 1201def: OpR_RR_pat<S2_asr_r_r, Sra, i32, I32, I32>; 1202def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>; 1203def: OpR_RR_pat<S2_asl_r_r, Shl, i32, I32, I32>; 1204def: OpR_RR_pat<S2_asr_r_p, Sra, i64, I64, I32>; 1205def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>; 1206def: OpR_RR_pat<S2_asl_r_p, Shl, i64, I64, I32>; 1207 1208// Funnel shifts. 1209def IsMul8_U3: PatLeaf<(i32 imm), [{ 1210 uint64_t V = N->getZExtValue(); 1211 return V % 8 == 0 && isUInt<3>(V / 8); 1212}]>; 1213 1214def Divu8: SDNodeXForm<imm, [{ 1215 return CurDAG->getTargetConstant(N->getZExtValue() / 8, SDLoc(N), MVT::i32); 1216}]>; 1217 1218// Funnel shift-left. 1219def FShl32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1220 (HiReg (S2_asl_i_p (Combinew $Rs, $Rt), $S))>; 1221def FShl32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1222 (HiReg (S2_asl_r_p (Combinew $Rs, $Rt), $Ru))>; 1223 1224def FShl64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1225 (S2_lsr_i_p_or (S2_asl_i_p $Rs, $S), $Rt, (Subi<64> $S))>; 1226def FShl64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1227 (S2_lsr_r_p_or (S2_asl_r_p $Rs, $Ru), $Rt, (A2_subri 64, $Ru))>; 1228 1229// Combined SDNodeXForm: (Divu8 (Subi<64> $S)) 1230def Divu64_8: SDNodeXForm<imm, [{ 1231 return CurDAG->getTargetConstant((64 - N->getSExtValue()) / 8, 1232 SDLoc(N), MVT::i32); 1233}]>; 1234 1235// Special cases: 1236let AddedComplexity = 100 in { 1237 def: Pat<(fshl I32:$Rs, I32:$Rt, (i32 16)), 1238 (A2_combine_lh I32:$Rs, I32:$Rt)>; 1239 def: Pat<(fshl I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1240 (S2_valignib I64:$Rs, I64:$Rt, (Divu64_8 $S))>; 1241} 1242 1243let Predicates = [HasV60], AddedComplexity = 50 in { 1244 def: OpR_RI_pat<S6_rol_i_r, Rol, i32, I32, u5_0ImmPred>; 1245 def: OpR_RI_pat<S6_rol_i_p, Rol, i64, I64, u6_0ImmPred>; 1246} 1247let AddedComplexity = 30 in { 1248 def: Pat<(rotl I32:$Rs, u5_0ImmPred:$S), (FShl32i $Rs, $Rs, imm:$S)>; 1249 def: Pat<(rotl I64:$Rs, u6_0ImmPred:$S), (FShl64i $Rs, $Rs, imm:$S)>; 1250 def: Pat<(fshl I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShl32i $Rs, $Rt, imm:$S)>; 1251 def: Pat<(fshl I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShl64i $Rs, $Rt, imm:$S)>; 1252} 1253def: Pat<(rotl I32:$Rs, I32:$Rt), (FShl32r $Rs, $Rs, $Rt)>; 1254def: Pat<(rotl I64:$Rs, I32:$Rt), (FShl64r $Rs, $Rs, $Rt)>; 1255def: Pat<(fshl I32:$Rs, I32:$Rt, I32:$Ru), (FShl32r $Rs, $Rt, $Ru)>; 1256def: Pat<(fshl I64:$Rs, I64:$Rt, I32:$Ru), (FShl64r $Rs, $Rt, $Ru)>; 1257 1258// Funnel shift-right. 1259def FShr32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1260 (LoReg (S2_lsr_i_p (Combinew $Rs, $Rt), $S))>; 1261def FShr32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1262 (LoReg (S2_lsr_r_p (Combinew $Rs, $Rt), $Ru))>; 1263 1264def FShr64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1265 (S2_asl_i_p_or (S2_lsr_i_p $Rt, $S), $Rs, (Subi<64> $S))>; 1266def FShr64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1267 (S2_asl_r_p_or (S2_lsr_r_p $Rt, $Ru), $Rs, (A2_subri 64, $Ru))>; 1268 1269// Special cases: 1270let AddedComplexity = 100 in { 1271 def: Pat<(fshr I32:$Rs, I32:$Rt, (i32 16)), 1272 (A2_combine_lh I32:$Rs, I32:$Rt)>; 1273 def: Pat<(fshr I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1274 (S2_valignib I64:$Rs, I64:$Rt, (Divu8 $S))>; 1275} 1276 1277let Predicates = [HasV60], AddedComplexity = 50 in { 1278 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (S6_rol_i_r I32:$Rs, (Subi<32> $S))>; 1279 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (S6_rol_i_p I64:$Rs, (Subi<64> $S))>; 1280} 1281let AddedComplexity = 30 in { 1282 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (FShr32i $Rs, $Rs, imm:$S)>; 1283 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (FShr64i $Rs, $Rs, imm:$S)>; 1284 def: Pat<(fshr I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShr32i $Rs, $Rt, imm:$S)>; 1285 def: Pat<(fshr I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShr64i $Rs, $Rt, imm:$S)>; 1286} 1287def: Pat<(rotr I32:$Rs, I32:$Rt), (FShr32r $Rs, $Rs, $Rt)>; 1288def: Pat<(rotr I64:$Rs, I32:$Rt), (FShr64r $Rs, $Rs, $Rt)>; 1289def: Pat<(fshr I32:$Rs, I32:$Rt, I32:$Ru), (FShr32r $Rs, $Rt, $Ru)>; 1290def: Pat<(fshr I64:$Rs, I64:$Rt, I32:$Ru), (FShr64r $Rs, $Rt, $Ru)>; 1291 1292 1293def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)), 1294 (S2_asr_i_r_rnd I32:$Rs, imm:$u5)>; 1295def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)), 1296 (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>; 1297 1298// Prefer S2_addasl_rrri over S2_asl_i_r_acc. 1299let AddedComplexity = 120 in 1300def: Pat<(add I32:$Rt, (shl I32:$Rs, u3_0ImmPred:$u3)), 1301 (S2_addasl_rrri IntRegs:$Rt, IntRegs:$Rs, imm:$u3)>; 1302 1303let AddedComplexity = 100 in { 1304 def: AccRRI_pat<S2_asr_i_r_acc, Add, Su<Sra>, I32, u5_0ImmPred>; 1305 def: AccRRI_pat<S2_asr_i_r_nac, Sub, Su<Sra>, I32, u5_0ImmPred>; 1306 def: AccRRI_pat<S2_asr_i_r_and, And, Su<Sra>, I32, u5_0ImmPred>; 1307 def: AccRRI_pat<S2_asr_i_r_or, Or, Su<Sra>, I32, u5_0ImmPred>; 1308 1309 def: AccRRI_pat<S2_asr_i_p_acc, Add, Su<Sra>, I64, u6_0ImmPred>; 1310 def: AccRRI_pat<S2_asr_i_p_nac, Sub, Su<Sra>, I64, u6_0ImmPred>; 1311 def: AccRRI_pat<S2_asr_i_p_and, And, Su<Sra>, I64, u6_0ImmPred>; 1312 def: AccRRI_pat<S2_asr_i_p_or, Or, Su<Sra>, I64, u6_0ImmPred>; 1313 1314 def: AccRRI_pat<S2_lsr_i_r_acc, Add, Su<Srl>, I32, u5_0ImmPred>; 1315 def: AccRRI_pat<S2_lsr_i_r_nac, Sub, Su<Srl>, I32, u5_0ImmPred>; 1316 def: AccRRI_pat<S2_lsr_i_r_and, And, Su<Srl>, I32, u5_0ImmPred>; 1317 def: AccRRI_pat<S2_lsr_i_r_or, Or, Su<Srl>, I32, u5_0ImmPred>; 1318 def: AccRRI_pat<S2_lsr_i_r_xacc, Xor, Su<Srl>, I32, u5_0ImmPred>; 1319 1320 def: AccRRI_pat<S2_lsr_i_p_acc, Add, Su<Srl>, I64, u6_0ImmPred>; 1321 def: AccRRI_pat<S2_lsr_i_p_nac, Sub, Su<Srl>, I64, u6_0ImmPred>; 1322 def: AccRRI_pat<S2_lsr_i_p_and, And, Su<Srl>, I64, u6_0ImmPred>; 1323 def: AccRRI_pat<S2_lsr_i_p_or, Or, Su<Srl>, I64, u6_0ImmPred>; 1324 def: AccRRI_pat<S2_lsr_i_p_xacc, Xor, Su<Srl>, I64, u6_0ImmPred>; 1325 1326 def: AccRRI_pat<S2_asl_i_r_acc, Add, Su<Shl>, I32, u5_0ImmPred>; 1327 def: AccRRI_pat<S2_asl_i_r_nac, Sub, Su<Shl>, I32, u5_0ImmPred>; 1328 def: AccRRI_pat<S2_asl_i_r_and, And, Su<Shl>, I32, u5_0ImmPred>; 1329 def: AccRRI_pat<S2_asl_i_r_or, Or, Su<Shl>, I32, u5_0ImmPred>; 1330 def: AccRRI_pat<S2_asl_i_r_xacc, Xor, Su<Shl>, I32, u5_0ImmPred>; 1331 1332 def: AccRRI_pat<S2_asl_i_p_acc, Add, Su<Shl>, I64, u6_0ImmPred>; 1333 def: AccRRI_pat<S2_asl_i_p_nac, Sub, Su<Shl>, I64, u6_0ImmPred>; 1334 def: AccRRI_pat<S2_asl_i_p_and, And, Su<Shl>, I64, u6_0ImmPred>; 1335 def: AccRRI_pat<S2_asl_i_p_or, Or, Su<Shl>, I64, u6_0ImmPred>; 1336 def: AccRRI_pat<S2_asl_i_p_xacc, Xor, Su<Shl>, I64, u6_0ImmPred>; 1337 1338 let Predicates = [HasV60] in { 1339 def: AccRRI_pat<S6_rol_i_r_acc, Add, Su<Rol>, I32, u5_0ImmPred>; 1340 def: AccRRI_pat<S6_rol_i_r_nac, Sub, Su<Rol>, I32, u5_0ImmPred>; 1341 def: AccRRI_pat<S6_rol_i_r_and, And, Su<Rol>, I32, u5_0ImmPred>; 1342 def: AccRRI_pat<S6_rol_i_r_or, Or, Su<Rol>, I32, u5_0ImmPred>; 1343 def: AccRRI_pat<S6_rol_i_r_xacc, Xor, Su<Rol>, I32, u5_0ImmPred>; 1344 1345 def: AccRRI_pat<S6_rol_i_p_acc, Add, Su<Rol>, I64, u6_0ImmPred>; 1346 def: AccRRI_pat<S6_rol_i_p_nac, Sub, Su<Rol>, I64, u6_0ImmPred>; 1347 def: AccRRI_pat<S6_rol_i_p_and, And, Su<Rol>, I64, u6_0ImmPred>; 1348 def: AccRRI_pat<S6_rol_i_p_or, Or, Su<Rol>, I64, u6_0ImmPred>; 1349 def: AccRRI_pat<S6_rol_i_p_xacc, Xor, Su<Rol>, I64, u6_0ImmPred>; 1350 } 1351} 1352 1353let AddedComplexity = 100 in { 1354 def: AccRRR_pat<S2_asr_r_r_acc, Add, Su<Sra>, I32, I32, I32>; 1355 def: AccRRR_pat<S2_asr_r_r_nac, Sub, Su<Sra>, I32, I32, I32>; 1356 def: AccRRR_pat<S2_asr_r_r_and, And, Su<Sra>, I32, I32, I32>; 1357 def: AccRRR_pat<S2_asr_r_r_or, Or, Su<Sra>, I32, I32, I32>; 1358 1359 def: AccRRR_pat<S2_asr_r_p_acc, Add, Su<Sra>, I64, I64, I32>; 1360 def: AccRRR_pat<S2_asr_r_p_nac, Sub, Su<Sra>, I64, I64, I32>; 1361 def: AccRRR_pat<S2_asr_r_p_and, And, Su<Sra>, I64, I64, I32>; 1362 def: AccRRR_pat<S2_asr_r_p_or, Or, Su<Sra>, I64, I64, I32>; 1363 def: AccRRR_pat<S2_asr_r_p_xor, Xor, Su<Sra>, I64, I64, I32>; 1364 1365 def: AccRRR_pat<S2_lsr_r_r_acc, Add, Su<Srl>, I32, I32, I32>; 1366 def: AccRRR_pat<S2_lsr_r_r_nac, Sub, Su<Srl>, I32, I32, I32>; 1367 def: AccRRR_pat<S2_lsr_r_r_and, And, Su<Srl>, I32, I32, I32>; 1368 def: AccRRR_pat<S2_lsr_r_r_or, Or, Su<Srl>, I32, I32, I32>; 1369 1370 def: AccRRR_pat<S2_lsr_r_p_acc, Add, Su<Srl>, I64, I64, I32>; 1371 def: AccRRR_pat<S2_lsr_r_p_nac, Sub, Su<Srl>, I64, I64, I32>; 1372 def: AccRRR_pat<S2_lsr_r_p_and, And, Su<Srl>, I64, I64, I32>; 1373 def: AccRRR_pat<S2_lsr_r_p_or, Or, Su<Srl>, I64, I64, I32>; 1374 def: AccRRR_pat<S2_lsr_r_p_xor, Xor, Su<Srl>, I64, I64, I32>; 1375 1376 def: AccRRR_pat<S2_asl_r_r_acc, Add, Su<Shl>, I32, I32, I32>; 1377 def: AccRRR_pat<S2_asl_r_r_nac, Sub, Su<Shl>, I32, I32, I32>; 1378 def: AccRRR_pat<S2_asl_r_r_and, And, Su<Shl>, I32, I32, I32>; 1379 def: AccRRR_pat<S2_asl_r_r_or, Or, Su<Shl>, I32, I32, I32>; 1380 1381 def: AccRRR_pat<S2_asl_r_p_acc, Add, Su<Shl>, I64, I64, I32>; 1382 def: AccRRR_pat<S2_asl_r_p_nac, Sub, Su<Shl>, I64, I64, I32>; 1383 def: AccRRR_pat<S2_asl_r_p_and, And, Su<Shl>, I64, I64, I32>; 1384 def: AccRRR_pat<S2_asl_r_p_or, Or, Su<Shl>, I64, I64, I32>; 1385 def: AccRRR_pat<S2_asl_r_p_xor, Xor, Su<Shl>, I64, I64, I32>; 1386} 1387 1388 1389class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp, 1390 PatFrag RegPred, PatFrag ImmPred> 1391 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)), 1392 (MI anyimm:$u8, RegPred:$Rs, imm:$U5)>; 1393 1394let AddedComplexity = 200, Predicates = [UseCompound] in { 1395 def: OpshIRI_pat<S4_addi_asl_ri, Add, Su<Shl>, I32, u5_0ImmPred>; 1396 def: OpshIRI_pat<S4_addi_lsr_ri, Add, Su<Srl>, I32, u5_0ImmPred>; 1397 def: OpshIRI_pat<S4_subi_asl_ri, Sub, Su<Shl>, I32, u5_0ImmPred>; 1398 def: OpshIRI_pat<S4_subi_lsr_ri, Sub, Su<Srl>, I32, u5_0ImmPred>; 1399 def: OpshIRI_pat<S4_andi_asl_ri, And, Su<Shl>, I32, u5_0ImmPred>; 1400 def: OpshIRI_pat<S4_andi_lsr_ri, And, Su<Srl>, I32, u5_0ImmPred>; 1401 def: OpshIRI_pat<S4_ori_asl_ri, Or, Su<Shl>, I32, u5_0ImmPred>; 1402 def: OpshIRI_pat<S4_ori_lsr_ri, Or, Su<Srl>, I32, u5_0ImmPred>; 1403} 1404 1405// Prefer this pattern to S2_asl_i_p_or for the special case of joining 1406// two 32-bit words into a 64-bit word. 1407let AddedComplexity = 200 in 1408def: Pat<(or (shl (Aext64 I32:$a), (i32 32)), (Zext64 I32:$b)), 1409 (Combinew I32:$a, I32:$b)>; 1410 1411def: Pat<(or (or (or (shl (Zext64 (and I32:$b, (i32 65535))), (i32 16)), 1412 (Zext64 (and I32:$a, (i32 65535)))), 1413 (shl (Aext64 (and I32:$c, (i32 65535))), (i32 32))), 1414 (shl (Aext64 I32:$d), (i32 48))), 1415 (Combinew (A2_combine_ll I32:$d, I32:$c), 1416 (A2_combine_ll I32:$b, I32:$a))>; 1417 1418let AddedComplexity = 200 in { 1419 def: Pat<(or (shl I32:$Rt, (i32 16)), (and I32:$Rs, (i32 65535))), 1420 (A2_combine_ll I32:$Rt, I32:$Rs)>; 1421 def: Pat<(or (shl I32:$Rt, (i32 16)), (srl I32:$Rs, (i32 16))), 1422 (A2_combine_lh I32:$Rt, I32:$Rs)>; 1423 def: Pat<(or (and I32:$Rt, (i32 268431360)), (and I32:$Rs, (i32 65535))), 1424 (A2_combine_hl I32:$Rt, I32:$Rs)>; 1425 def: Pat<(or (and I32:$Rt, (i32 268431360)), (srl I32:$Rs, (i32 16))), 1426 (A2_combine_hh I32:$Rt, I32:$Rs)>; 1427} 1428 1429def SDTHexagonVShift 1430 : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVec<0>, SDTCisVT<2, i32>]>; 1431 1432def HexagonVASL: SDNode<"HexagonISD::VASL", SDTHexagonVShift>; 1433def HexagonVASR: SDNode<"HexagonISD::VASR", SDTHexagonVShift>; 1434def HexagonVLSR: SDNode<"HexagonISD::VLSR", SDTHexagonVShift>; 1435 1436// Funnel shifts with the shift amount module element bit width. 1437def HexagonMFSHL: SDNode<"HexagonISD::MFSHL", SDTIntShiftDOp>; 1438def HexagonMFSHR: SDNode<"HexagonISD::MFSHR", SDTIntShiftDOp>; 1439 1440def: OpR_RI_pat<S2_asl_i_vw, pf2<HexagonVASL>, v2i32, V2I32, u5_0ImmPred>; 1441def: OpR_RI_pat<S2_asl_i_vh, pf2<HexagonVASL>, v4i16, V4I16, u4_0ImmPred>; 1442def: OpR_RI_pat<S2_asr_i_vw, pf2<HexagonVASR>, v2i32, V2I32, u5_0ImmPred>; 1443def: OpR_RI_pat<S2_asr_i_vh, pf2<HexagonVASR>, v4i16, V4I16, u4_0ImmPred>; 1444def: OpR_RI_pat<S2_lsr_i_vw, pf2<HexagonVLSR>, v2i32, V2I32, u5_0ImmPred>; 1445def: OpR_RI_pat<S2_lsr_i_vh, pf2<HexagonVLSR>, v4i16, V4I16, u4_0ImmPred>; 1446 1447def: OpR_RR_pat<S2_asl_r_vw, pf2<HexagonVASL>, v2i32, V2I32, I32>; 1448def: OpR_RR_pat<S2_asl_r_vh, pf2<HexagonVASL>, v4i16, V4I16, I32>; 1449def: OpR_RR_pat<S2_asr_r_vw, pf2<HexagonVASR>, v2i32, V2I32, I32>; 1450def: OpR_RR_pat<S2_asr_r_vh, pf2<HexagonVASR>, v4i16, V4I16, I32>; 1451def: OpR_RR_pat<S2_lsr_r_vw, pf2<HexagonVLSR>, v2i32, V2I32, I32>; 1452def: OpR_RR_pat<S2_lsr_r_vh, pf2<HexagonVLSR>, v4i16, V4I16, I32>; 1453 1454def: Pat<(sra V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1455 (S2_asr_i_vw V2I32:$b, imm:$c)>; 1456def: Pat<(srl V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1457 (S2_lsr_i_vw V2I32:$b, imm:$c)>; 1458def: Pat<(shl V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1459 (S2_asl_i_vw V2I32:$b, imm:$c)>; 1460def: Pat<(sra V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1461 (S2_asr_i_vh V4I16:$b, imm:$c)>; 1462def: Pat<(srl V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1463 (S2_lsr_i_vh V4I16:$b, imm:$c)>; 1464def: Pat<(shl V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1465 (S2_asl_i_vh V4I16:$b, imm:$c)>; 1466 1467def: Pat<(HexagonVASR V2I16:$Rs, u4_0ImmPred:$S), 1468 (LoReg (S2_asr_i_vh (ToAext64 $Rs), imm:$S))>; 1469def: Pat<(HexagonVASL V2I16:$Rs, u4_0ImmPred:$S), 1470 (LoReg (S2_asl_i_vh (ToAext64 $Rs), imm:$S))>; 1471def: Pat<(HexagonVLSR V2I16:$Rs, u4_0ImmPred:$S), 1472 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), imm:$S))>; 1473def: Pat<(HexagonVASR V2I16:$Rs, I32:$Rt), 1474 (LoReg (S2_asr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1475def: Pat<(HexagonVASL V2I16:$Rs, I32:$Rt), 1476 (LoReg (S2_asl_i_vh (ToAext64 $Rs), I32:$Rt))>; 1477def: Pat<(HexagonVLSR V2I16:$Rs, I32:$Rt), 1478 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1479 1480 1481// --(9) Arithmetic/bitwise ---------------------------------------------- 1482// 1483 1484def: Pat<(abs I32:$Rs), (A2_abs I32:$Rs)>; 1485def: Pat<(abs I64:$Rs), (A2_absp I64:$Rs)>; 1486def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>; 1487def: Pat<(not I64:$Rs), (A2_notp I64:$Rs)>; 1488def: Pat<(ineg I64:$Rs), (A2_negp I64:$Rs)>; 1489 1490def: Pat<(fabs F32:$Rs), (S2_clrbit_i F32:$Rs, 31)>; 1491def: Pat<(fneg F32:$Rs), (S2_togglebit_i F32:$Rs, 31)>; 1492 1493def: Pat<(fabs F64:$Rs), 1494 (Combinew (S2_clrbit_i (HiReg $Rs), 31), 1495 (i32 (LoReg $Rs)))>; 1496def: Pat<(fneg F64:$Rs), 1497 (Combinew (S2_togglebit_i (HiReg $Rs), 31), 1498 (i32 (LoReg $Rs)))>; 1499 1500def: Pat<(add I32:$Rs, anyimm:$s16), (A2_addi I32:$Rs, imm:$s16)>; 1501def: Pat<(or I32:$Rs, anyimm:$s10), (A2_orir I32:$Rs, imm:$s10)>; 1502def: Pat<(and I32:$Rs, anyimm:$s10), (A2_andir I32:$Rs, imm:$s10)>; 1503def: Pat<(sub anyimm:$s10, I32:$Rs), (A2_subri imm:$s10, I32:$Rs)>; 1504 1505def: OpR_RR_pat<A2_add, Add, i32, I32>; 1506def: OpR_RR_pat<A2_sub, Sub, i32, I32>; 1507def: OpR_RR_pat<A2_and, And, i32, I32>; 1508def: OpR_RR_pat<A2_or, Or, i32, I32>; 1509def: OpR_RR_pat<A2_xor, Xor, i32, I32>; 1510def: OpR_RR_pat<A2_addp, Add, i64, I64>; 1511def: OpR_RR_pat<A2_subp, Sub, i64, I64>; 1512def: OpR_RR_pat<A2_andp, And, i64, I64>; 1513def: OpR_RR_pat<A2_orp, Or, i64, I64>; 1514def: OpR_RR_pat<A2_xorp, Xor, i64, I64>; 1515def: OpR_RR_pat<A4_andnp, Not2<And>, i64, I64>; 1516def: OpR_RR_pat<A4_ornp, Not2<Or>, i64, I64>; 1517 1518def: OpR_RR_pat<A2_svaddh, Add, v2i16, V2I16>; 1519def: OpR_RR_pat<A2_svsubh, Sub, v2i16, V2I16>; 1520 1521def: OpR_RR_pat<A2_vaddub, Add, v8i8, V8I8>; 1522def: OpR_RR_pat<A2_vaddh, Add, v4i16, V4I16>; 1523def: OpR_RR_pat<A2_vaddw, Add, v2i32, V2I32>; 1524def: OpR_RR_pat<A2_vsubub, Sub, v8i8, V8I8>; 1525def: OpR_RR_pat<A2_vsubh, Sub, v4i16, V4I16>; 1526def: OpR_RR_pat<A2_vsubw, Sub, v2i32, V2I32>; 1527 1528def: OpR_RR_pat<A2_and, And, v4i8, V4I8>; 1529def: OpR_RR_pat<A2_xor, Xor, v4i8, V4I8>; 1530def: OpR_RR_pat<A2_or, Or, v4i8, V4I8>; 1531def: OpR_RR_pat<A2_and, And, v2i16, V2I16>; 1532def: OpR_RR_pat<A2_xor, Xor, v2i16, V2I16>; 1533def: OpR_RR_pat<A2_or, Or, v2i16, V2I16>; 1534def: OpR_RR_pat<A2_andp, And, v8i8, V8I8>; 1535def: OpR_RR_pat<A2_orp, Or, v8i8, V8I8>; 1536def: OpR_RR_pat<A2_xorp, Xor, v8i8, V8I8>; 1537def: OpR_RR_pat<A2_andp, And, v4i16, V4I16>; 1538def: OpR_RR_pat<A2_orp, Or, v4i16, V4I16>; 1539def: OpR_RR_pat<A2_xorp, Xor, v4i16, V4I16>; 1540def: OpR_RR_pat<A2_andp, And, v2i32, V2I32>; 1541def: OpR_RR_pat<A2_orp, Or, v2i32, V2I32>; 1542def: OpR_RR_pat<A2_xorp, Xor, v2i32, V2I32>; 1543 1544def: OpR_RR_pat<M2_mpyi, Mul, i32, I32>; 1545def: OpR_RR_pat<M2_mpy_up, pf2<mulhs>, i32, I32>; 1546def: OpR_RR_pat<M2_mpyu_up, pf2<mulhu>, i32, I32>; 1547def: OpR_RI_pat<M2_mpysip, Mul, i32, I32, u32_0ImmPred>; 1548def: OpR_RI_pat<M2_mpysmi, Mul, i32, I32, s32_0ImmPred>; 1549 1550// Arithmetic on predicates. 1551def: OpR_RR_pat<C2_xor, Add, i1, I1>; 1552def: OpR_RR_pat<C2_xor, Add, v2i1, V2I1>; 1553def: OpR_RR_pat<C2_xor, Add, v4i1, V4I1>; 1554def: OpR_RR_pat<C2_xor, Add, v8i1, V8I1>; 1555def: OpR_RR_pat<C2_xor, Sub, i1, I1>; 1556def: OpR_RR_pat<C2_xor, Sub, v2i1, V2I1>; 1557def: OpR_RR_pat<C2_xor, Sub, v4i1, V4I1>; 1558def: OpR_RR_pat<C2_xor, Sub, v8i1, V8I1>; 1559def: OpR_RR_pat<C2_and, Mul, i1, I1>; 1560def: OpR_RR_pat<C2_and, Mul, v2i1, V2I1>; 1561def: OpR_RR_pat<C2_and, Mul, v4i1, V4I1>; 1562def: OpR_RR_pat<C2_and, Mul, v8i1, V8I1>; 1563 1564def: OpR_RR_pat<F2_sfadd, pf2<fadd>, f32, F32>; 1565def: OpR_RR_pat<F2_sfsub, pf2<fsub>, f32, F32>; 1566def: OpR_RR_pat<F2_sfmpy, pf2<fmul>, f32, F32>; 1567def: OpR_RR_pat<F2_sfmin, pf2<fminnum>, f32, F32>; 1568def: OpR_RR_pat<F2_sfmax, pf2<fmaxnum>, f32, F32>; 1569 1570let Predicates = [HasV66] in { 1571 def: OpR_RR_pat<F2_dfadd, pf2<fadd>, f64, F64>; 1572 def: OpR_RR_pat<F2_dfsub, pf2<fsub>, f64, F64>; 1573} 1574 1575def DfMpy: OutPatFrag<(ops node:$Rs, node:$Rt), 1576 (F2_dfmpyhh 1577 (F2_dfmpylh 1578 (F2_dfmpylh 1579 (F2_dfmpyll $Rs, $Rt), 1580 $Rs, $Rt), 1581 $Rt, $Rs), 1582 $Rs, $Rt)>; 1583 1584let Predicates = [HasV67,UseUnsafeMath], AddedComplexity = 50 in { 1585 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy $Rs, $Rt)>; 1586} 1587let Predicates = [HasV67] in { 1588 def: OpR_RR_pat<F2_dfmin, pf2<fminnum>, f64, F64>; 1589 def: OpR_RR_pat<F2_dfmax, pf2<fmaxnum>, f64, F64>; 1590 1591 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy (F2_dfmpyfix $Rs, $Rt), 1592 (F2_dfmpyfix $Rt, $Rs))>; 1593} 1594 1595// In expressions like a0*b0 + a1*b1 + ..., prefer to generate multiply-add, 1596// over add-add with individual multiplies as inputs. 1597let AddedComplexity = 10 in { 1598 def: AccRRI_pat<M2_macsip, Add, Su<Mul>, I32, u32_0ImmPred>; 1599 def: AccRRI_pat<M2_macsin, Sub, Su<Mul>, I32, u32_0ImmPred>; 1600 def: AccRRR_pat<M2_maci, Add, Su<Mul>, I32, I32, I32>; 1601 let Predicates = [HasV66] in 1602 def: AccRRR_pat<M2_mnaci, Sub, Su<Mul>, I32, I32, I32>; 1603} 1604 1605def: AccRRI_pat<M2_naccii, Sub, Su<Add>, I32, s32_0ImmPred>; 1606def: AccRRI_pat<M2_accii, Add, Su<Add>, I32, s32_0ImmPred>; 1607def: AccRRR_pat<M2_acci, Add, Su<Add>, I32, I32, I32>; 1608 1609// Mulh for vectors 1610// 1611def: Pat<(v2i32 (mulhu V2I32:$Rss, V2I32:$Rtt)), 1612 (Combinew (M2_mpyu_up (HiReg $Rss), (HiReg $Rtt)), 1613 (M2_mpyu_up (LoReg $Rss), (LoReg $Rtt)))>; 1614 1615def: Pat<(v2i32 (mulhs V2I32:$Rss, V2I32:$Rtt)), 1616 (Combinew (M2_mpy_up (HiReg $Rss), (HiReg $Rtt)), 1617 (M2_mpy_up (LoReg $Rss), (LoReg $Rtt)))>; 1618 1619def Mulhub4: 1620 OutPatFrag<(ops node:$Rs, node:$Rt), (S2_vtrunohb (M5_vmpybuu $Rs, $Rt))>; 1621def Mulhub8: 1622 OutPatFrag<(ops node:$Rss, node:$Rtt), 1623 (Combinew (Mulhub4 (HiReg $Rss), (HiReg $Rtt)), 1624 (Mulhub4 (LoReg $Rss), (LoReg $Rtt)))>; 1625 1626// (mux (x >= 0), 0, y) 1627def Negbytes8: 1628 OutPatFrag<(ops node:$Rss, node:$Rtt), 1629 (C2_vmux (A4_vcmpbgti $Rss, -1), (A2_tfrpi 0), $Rtt)>; 1630 1631def: Pat<(v4i8 (mulhu V4I8:$Rs, V4I8:$Rt)), (Mulhub4 $Rs, $Rt)>; 1632def: Pat<(v8i8 (mulhu V8I8:$Rss, V8I8:$Rtt)), (Mulhub8 $Rss, $Rtt)>; 1633 1634// (Mulhs x, y) = (Mulhu x, y) - (x < 0 ? y : 0) - (y < 0 ? x : 0) 1635def Mulhsb8: 1636 OutPatFrag<(ops node:$Rss, node:$Rtt), 1637 (A2_vsubub (Mulhub8 $Rss, $Rtt), 1638 (A2_vaddub (Negbytes8 $Rss, $Rtt), 1639 (Negbytes8 $Rtt, $Rss)))>; 1640 1641def: Pat<(v4i8 (mulhs V4I8:$Rs, V4I8:$Rt)), 1642 (LoReg (Mulhsb8 (v8i8 (ToAext64 $Rs)), (v8i8 (ToAext64 $Rt))))>; 1643def: Pat<(v8i8 (mulhs V8I8:$Rss, V8I8:$Rtt)), (Mulhsb8 $Rss, $Rtt)>; 1644 1645// v2i16 *s v2i16 -> v2i32 1646def Muli16: 1647 OutPatFrag<(ops node:$Rs, node:$Rt), (M2_vmpy2s_s0 $Rs, $Rt)>; 1648 1649def Mulhsh2: 1650 OutPatFrag<(ops node:$Rs, node:$Rt), 1651 (A2_combine_hh (HiReg (Muli16 $Rs, $Rt)), 1652 (LoReg (Muli16 $Rs, $Rt)))>; 1653def Mulhsh4: 1654 OutPatFrag<(ops node:$Rss, node:$Rtt), 1655 (Combinew (Mulhsh2 (HiReg $Rss), (HiReg $Rtt)), 1656 (Mulhsh2 (LoReg $Rss), (LoReg $Rtt)))>; 1657 1658def: Pat<(v2i16 (mulhs V2I16:$Rs, V2I16:$Rt)), (Mulhsh2 $Rs, $Rt)>; 1659def: Pat<(v4i16 (mulhs V4I16:$Rss, V4I16:$Rtt)), (Mulhsh4 $Rss, $Rtt)>; 1660 1661def: Pat<(v2i16 (mulhu V2I16:$Rs, V2I16:$Rt)), 1662 (A2_svaddh 1663 (Mulhsh2 $Rs, $Rt), 1664 (A2_svaddh (LoReg (A2_andp (Combinew $Rt, $Rs), 1665 (S2_asr_i_vh (Combinew $Rs, $Rt), 15))), 1666 (HiReg (A2_andp (Combinew $Rt, $Rs), 1667 (S2_asr_i_vh (Combinew $Rs, $Rt), 15)))))>; 1668 1669def: Pat<(v4i16 (mulhu V4I16:$Rss, V4I16:$Rtt)), 1670 (A2_vaddh 1671 (Mulhsh4 $Rss, $Rtt), 1672 (A2_vaddh (A2_andp V4I16:$Rss, (S2_asr_i_vh $Rtt, 15)), 1673 (A2_andp V4I16:$Rtt, (S2_asr_i_vh $Rss, 15))))>; 1674 1675 1676def: Pat<(ineg (mul I32:$Rs, u8_0ImmPred:$u8)), 1677 (M2_mpysin IntRegs:$Rs, imm:$u8)>; 1678 1679def n8_0ImmPred: PatLeaf<(i32 imm), [{ 1680 int64_t V = N->getSExtValue(); 1681 return -255 <= V && V <= 0; 1682}]>; 1683 1684// Change the sign of the immediate for Rd=-mpyi(Rs,#u8) 1685def: Pat<(mul I32:$Rs, n8_0ImmPred:$n8), 1686 (M2_mpysin I32:$Rs, (NegImm8 imm:$n8))>; 1687 1688def: Pat<(add Sext64:$Rs, I64:$Rt), 1689 (A2_addsp (LoReg Sext64:$Rs), I64:$Rt)>; 1690 1691def: AccRRR_pat<M4_and_and, And, Su_ni1<And>, I32, I32, I32>; 1692def: AccRRR_pat<M4_and_or, And, Su_ni1<Or>, I32, I32, I32>; 1693def: AccRRR_pat<M4_and_xor, And, Su<Xor>, I32, I32, I32>; 1694def: AccRRR_pat<M4_or_and, Or, Su_ni1<And>, I32, I32, I32>; 1695def: AccRRR_pat<M4_or_or, Or, Su_ni1<Or>, I32, I32, I32>; 1696def: AccRRR_pat<M4_or_xor, Or, Su<Xor>, I32, I32, I32>; 1697def: AccRRR_pat<M4_xor_and, Xor, Su_ni1<And>, I32, I32, I32>; 1698def: AccRRR_pat<M4_xor_or, Xor, Su_ni1<Or>, I32, I32, I32>; 1699def: AccRRR_pat<M2_xor_xacc, Xor, Su<Xor>, I32, I32, I32>; 1700def: AccRRR_pat<M4_xor_xacc, Xor, Su<Xor>, I64, I64, I64>; 1701 1702// For dags like (or (and (not _), _), (shl _, _)) where the "or" with 1703// one argument matches the patterns below, and with the other argument 1704// matches S2_asl_r_r_or, etc, prefer the patterns below. 1705let AddedComplexity = 110 in { // greater than S2_asl_r_r_and/or/xor. 1706 def: AccRRR_pat<M4_and_andn, And, Su<Not2<And>>, I32, I32, I32>; 1707 def: AccRRR_pat<M4_or_andn, Or, Su<Not2<And>>, I32, I32, I32>; 1708 def: AccRRR_pat<M4_xor_andn, Xor, Su<Not2<And>>, I32, I32, I32>; 1709} 1710 1711// S4_addaddi and S4_subaddi don't have tied operands, so give them 1712// a bit of preference. 1713let AddedComplexity = 30, Predicates = [UseCompound] in { 1714 def: Pat<(add I32:$Rs, (Su<Add> I32:$Ru, anyimm:$s6)), 1715 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1716 def: Pat<(add anyimm:$s6, (Su<Add> I32:$Rs, I32:$Ru)), 1717 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1718 def: Pat<(add I32:$Rs, (Su<Sub> anyimm:$s6, I32:$Ru)), 1719 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1720 def: Pat<(sub (Su<Add> I32:$Rs, anyimm:$s6), I32:$Ru), 1721 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1722 def: Pat<(add (Su<Sub> I32:$Rs, I32:$Ru), anyimm:$s6), 1723 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1724} 1725 1726let Predicates = [UseCompound] in 1727def: Pat<(or I32:$Ru, (Su<And> I32:$Rx, anyimm:$s10)), 1728 (S4_or_andix IntRegs:$Ru, IntRegs:$Rx, imm:$s10)>; 1729 1730def: Pat<(or I32:$Rx, (Su<And> I32:$Rs, anyimm:$s10)), 1731 (S4_or_andi IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1732def: Pat<(or I32:$Rx, (Su<Or> I32:$Rs, anyimm:$s10)), 1733 (S4_or_ori IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1734 1735 1736def: Pat<(i32 (trunc (sra (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1737 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1738def: Pat<(i32 (trunc (srl (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1739 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1740 1741def: Pat<(mul (Zext64 I32:$Rs), (Zext64 I32:$Rt)), 1742 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1743def: Pat<(mul (Aext64 I32:$Rs), (Aext64 I32:$Rt)), 1744 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1745def: Pat<(mul Sext64:$Rs, Sext64:$Rt), 1746 (M2_dpmpyss_s0 (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1747 1748def: Pat<(add I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1749 (M2_dpmpyss_acc_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1750def: Pat<(sub I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1751 (M2_dpmpyss_nac_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1752def: Pat<(add I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1753 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1754def: Pat<(add I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1755 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1756def: Pat<(sub I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1757 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1758def: Pat<(sub I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1759 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1760 1761// Add halfword. 1762def: Pat<(sext_inreg (add I32:$Rt, I32:$Rs), i16), 1763 (A2_addh_l16_ll I32:$Rt, I32:$Rs)>; 1764def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1765 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1766def: Pat<(shl (add I32:$Rt, I32:$Rs), (i32 16)), 1767 (A2_addh_h16_ll I32:$Rt, I32:$Rs)>; 1768 1769// Subtract halfword. 1770def: Pat<(sext_inreg (sub I32:$Rt, I32:$Rs), i16), 1771 (A2_subh_l16_ll I32:$Rt, I32:$Rs)>; 1772def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1773 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1774def: Pat<(shl (sub I32:$Rt, I32:$Rs), (i32 16)), 1775 (A2_subh_h16_ll I32:$Rt, I32:$Rs)>; 1776 1777def: Pat<(mul I64:$Rss, I64:$Rtt), 1778 (Combinew 1779 (M2_maci (M2_maci (HiReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt))), 1780 (LoReg $Rss), 1781 (HiReg $Rtt)), 1782 (LoReg $Rtt), 1783 (HiReg $Rss)), 1784 (i32 (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)))))>; 1785 1786def MulHU : OutPatFrag<(ops node:$Rss, node:$Rtt), 1787 (A2_addp 1788 (M2_dpmpyuu_acc_s0 1789 (S2_lsr_i_p 1790 (A2_addp 1791 (M2_dpmpyuu_acc_s0 1792 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)), 32), 1793 (HiReg $Rss), 1794 (LoReg $Rtt)), 1795 (A4_combineir 0, (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt))))), 1796 32), 1797 (HiReg $Rss), 1798 (HiReg $Rtt)), 1799 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt)), 32))>; 1800 1801// Multiply 64-bit unsigned and use upper result. 1802def : Pat <(mulhu I64:$Rss, I64:$Rtt), (MulHU $Rss, $Rtt)>; 1803 1804// Multiply 64-bit signed and use upper result. 1805// 1806// For two signed 64-bit integers A and B, let A' and B' denote A and B 1807// with the sign bit cleared. Then A = -2^63*s(A) + A', where s(A) is the 1808// sign bit of A (and identically for B). With this notation, the signed 1809// product A*B can be written as: 1810// AB = (-2^63 s(A) + A') * (-2^63 s(B) + B') 1811// = 2^126 s(A)s(B) - 2^63 [s(A)B'+s(B)A'] + A'B' 1812// = 2^126 s(A)s(B) + 2^63 [s(A)B'+s(B)A'] + A'B' - 2*2^63 [s(A)B'+s(B)A'] 1813// = (unsigned product AB) - 2^64 [s(A)B'+s(B)A'] 1814 1815// Clear the sign bit in a 64-bit register. 1816def ClearSign : OutPatFrag<(ops node:$Rss), 1817 (Combinew (S2_clrbit_i (HiReg $Rss), 31), (i32 (LoReg $Rss)))>; 1818 1819def : Pat <(mulhs I64:$Rss, I64:$Rtt), 1820 (A2_subp 1821 (MulHU $Rss, $Rtt), 1822 (A2_addp 1823 (A2_andp (S2_asr_i_p $Rss, 63), (ClearSign $Rtt)), 1824 (A2_andp (S2_asr_i_p $Rtt, 63), (ClearSign $Rss))))>; 1825 1826// Prefer these instructions over M2_macsip/M2_macsin: the macsi* instructions 1827// will put the immediate addend into a register, while these instructions will 1828// use it directly. Such a construct does not appear in the middle of a gep, 1829// where M2_macsip would be preferable. 1830let AddedComplexity = 20, Predicates = [UseCompound] in { 1831 def: Pat<(add (Su<Mul> I32:$Rs, u6_0ImmPred:$U6), anyimm:$u6), 1832 (M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>; 1833 def: Pat<(add (Su<Mul> I32:$Rs, I32:$Rt), anyimm:$u6), 1834 (M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>; 1835} 1836 1837// Keep these instructions less preferable to M2_macsip/M2_macsin. 1838let Predicates = [UseCompound] in { 1839 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)), 1840 (M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>; 1841 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)), 1842 (M4_mpyri_addr IntRegs:$Ru, IntRegs:$Rs, imm:$u6)>; 1843 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)), 1844 (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>; 1845} 1846 1847def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx), 1848 (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>; 1849def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx), 1850 (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; 1851 1852def: Pat<(mul V2I32:$Rs, V2I32:$Rt), 1853 (PS_vmulw V2I32:$Rs, V2I32:$Rt)>; 1854def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)), 1855 (PS_vmulw_acc V2I32:$Rx, V2I32:$Rs, V2I32:$Rt)>; 1856 1857// Add/subtract two v4i8: Hexagon does not have an insn for this one, so 1858// we use the double add v8i8, and use only the low part of the result. 1859def: Pat<(add V4I8:$Rs, V4I8:$Rt), 1860 (LoReg (A2_vaddub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1861def: Pat<(sub V4I8:$Rs, V4I8:$Rt), 1862 (LoReg (A2_vsubub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1863 1864// Use M2_vmpy2s_s0 for half-word vector multiply. It multiplies two 1865// half-words, and saturates the result to a 32-bit value, except the 1866// saturation never happens (it can only occur with scaling). 1867def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)), 1868 (LoReg (S2_vtrunewh (IMPLICIT_DEF), 1869 (M2_vmpy2s_s0 V2I16:$Rs, V2I16:$Rt)))>; 1870def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)), 1871 (S2_vtrunewh (M2_vmpy2s_s0 (HiReg $Rs), (HiReg $Rt)), 1872 (M2_vmpy2s_s0 (LoReg $Rs), (LoReg $Rt)))>; 1873 1874// Multiplies two v4i8 vectors. 1875def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)), 1876 (S2_vtrunehb (M5_vmpybuu V4I8:$Rs, V4I8:$Rt))>; 1877 1878// Multiplies two v8i8 vectors. 1879def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)), 1880 (Combinew (S2_vtrunehb (M5_vmpybuu (HiReg $Rs), (HiReg $Rt))), 1881 (S2_vtrunehb (M5_vmpybuu (LoReg $Rs), (LoReg $Rt))))>; 1882 1883 1884// --(10) Bit ------------------------------------------------------------ 1885// 1886 1887// Count leading zeros. 1888def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>; 1889def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>; 1890 1891// Count trailing zeros. 1892def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>; 1893def: Pat<(i32 (trunc (cttz I64:$Rss))), (S2_ct0p I64:$Rss)>; 1894 1895// Count leading ones. 1896def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>; 1897def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>; 1898 1899// Count trailing ones. 1900def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>; 1901def: Pat<(i32 (trunc (cttz (not I64:$Rss)))), (S2_ct1p I64:$Rss)>; 1902 1903// Define leading/trailing patterns that require zero-extensions to 64 bits. 1904def: Pat<(i64 (ctlz I64:$Rss)), (ToZext64 (S2_cl0p I64:$Rss))>; 1905def: Pat<(i64 (cttz I64:$Rss)), (ToZext64 (S2_ct0p I64:$Rss))>; 1906def: Pat<(i64 (ctlz (not I64:$Rss))), (ToZext64 (S2_cl1p I64:$Rss))>; 1907def: Pat<(i64 (cttz (not I64:$Rss))), (ToZext64 (S2_ct1p I64:$Rss))>; 1908 1909def: Pat<(i64 (ctpop I64:$Rss)), (ToZext64 (S5_popcountp I64:$Rss))>; 1910def: Pat<(i32 (ctpop I32:$Rs)), (S5_popcountp (A4_combineir 0, I32:$Rs))>; 1911 1912def: Pat<(bitreverse I32:$Rs), (S2_brev I32:$Rs)>; 1913def: Pat<(bitreverse I64:$Rss), (S2_brevp I64:$Rss)>; 1914 1915def: Pat<(bitreverse V4I8:$Rs), (A2_swiz (S2_brev $Rs))>; 1916def: Pat<(bitreverse V8I8:$Rs), (Combinew (A2_swiz (LoReg (S2_brevp $Rs))), 1917 (A2_swiz (HiReg (S2_brevp $Rs))))>; 1918def: Pat<(bitreverse V2I16:$Rs), (A2_combine_lh (S2_brev $Rs), 1919 (S2_brev $Rs))>; 1920def: Pat<(bitreverse V4I16:$Rs), 1921 (Combinew (A2_combine_lh (LoReg (S2_brevp $Rs)), 1922 (LoReg (S2_brevp $Rs))), 1923 (A2_combine_lh (HiReg (S2_brevp $Rs)), 1924 (HiReg (S2_brevp $Rs))))>; 1925def: Pat<(bitreverse V2I32:$Rs), 1926 (Combinew (i32 (LoReg (S2_brevp $Rs))), 1927 (i32 (HiReg (S2_brevp $Rs))))>; 1928 1929let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1930 def: Pat<(and I32:$Rs, IsNPow2_32:$V), 1931 (S2_clrbit_i IntRegs:$Rs, (LogN2_32 $V))>; 1932 def: Pat<(or I32:$Rs, IsPow2_32:$V), 1933 (S2_setbit_i IntRegs:$Rs, (Log2_32 $V))>; 1934 def: Pat<(xor I32:$Rs, IsPow2_32:$V), 1935 (S2_togglebit_i IntRegs:$Rs, (Log2_32 $V))>; 1936 1937 def: Pat<(and I32:$Rs, (not (shl 1, I32:$Rt))), 1938 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1939 def: Pat<(or I32:$Rs, (shl 1, I32:$Rt)), 1940 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1941 def: Pat<(xor I32:$Rs, (shl 1, I32:$Rt)), 1942 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>; 1943} 1944 1945// Clr/set/toggle bit for 64-bit values with immediate bit index. 1946let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1947 def: Pat<(and I64:$Rss, IsNPow2_64L:$V), 1948 (Combinew (i32 (HiReg $Rss)), 1949 (S2_clrbit_i (LoReg $Rss), (LogN2_64 $V)))>; 1950 def: Pat<(and I64:$Rss, IsNPow2_64H:$V), 1951 (Combinew (S2_clrbit_i (HiReg $Rss), (UDEC32 (i32 (LogN2_64 $V)))), 1952 (i32 (LoReg $Rss)))>; 1953 1954 def: Pat<(or I64:$Rss, IsPow2_64L:$V), 1955 (Combinew (i32 (HiReg $Rss)), 1956 (S2_setbit_i (LoReg $Rss), (Log2_64 $V)))>; 1957 def: Pat<(or I64:$Rss, IsPow2_64H:$V), 1958 (Combinew (S2_setbit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1959 (i32 (LoReg $Rss)))>; 1960 1961 def: Pat<(xor I64:$Rss, IsPow2_64L:$V), 1962 (Combinew (i32 (HiReg $Rss)), 1963 (S2_togglebit_i (LoReg $Rss), (Log2_64 $V)))>; 1964 def: Pat<(xor I64:$Rss, IsPow2_64H:$V), 1965 (Combinew (S2_togglebit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1966 (i32 (LoReg $Rss)))>; 1967} 1968 1969 1970let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1971 def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)), 1972 (S2_tstbit_i IntRegs:$Rs, imm:$u5)>; 1973 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1974 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1975 def: Pat<(i1 (trunc I32:$Rs)), 1976 (S2_tstbit_i IntRegs:$Rs, 0)>; 1977 def: Pat<(i1 (trunc I64:$Rs)), 1978 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>; 1979} 1980 1981def: Pat<(and (srl I32:$Rs, u5_0ImmPred:$u5), 1), 1982 (I1toI32 (S2_tstbit_i I32:$Rs, imm:$u5))>; 1983def: Pat<(and (srl I64:$Rss, IsULE<32,31>:$u6), 1), 1984 (ToZext64 (I1toI32 (S2_tstbit_i (LoReg $Rss), imm:$u6)))>; 1985def: Pat<(and (srl I64:$Rss, IsUGT<32,31>:$u6), 1), 1986 (ToZext64 (I1toI32 (S2_tstbit_i (HiReg $Rss), (UDEC32 $u6))))>; 1987 1988def: Pat<(and (not (srl I32:$Rs, u5_0ImmPred:$u5)), 1), 1989 (I1toI32 (S4_ntstbit_i I32:$Rs, imm:$u5))>; 1990def: Pat<(and (not (srl I64:$Rss, IsULE<32,31>:$u6)), 1), 1991 (ToZext64 (I1toI32 (S4_ntstbit_i (LoReg $Rss), imm:$u6)))>; 1992def: Pat<(and (not (srl I64:$Rss, IsUGT<32,31>:$u6)), 1), 1993 (ToZext64 (I1toI32 (S4_ntstbit_i (HiReg $Rss), (UDEC32 $u6))))>; 1994 1995let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1996 def: Pat<(i1 (seteq (and I32:$Rs, u6_0ImmPred:$u6), 0)), 1997 (C2_bitsclri IntRegs:$Rs, imm:$u6)>; 1998 def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), 0)), 1999 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>; 2000} 2001 2002let AddedComplexity = 10 in // Complexity greater than compare reg-reg. 2003def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), IntRegs:$Rt)), 2004 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>; 2005 2006def SDTTestBit: 2007 SDTypeProfile<1, 2, [SDTCisVT<0, i1>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 2008def HexagonTSTBIT: SDNode<"HexagonISD::TSTBIT", SDTTestBit>; 2009 2010def: Pat<(HexagonTSTBIT I32:$Rs, u5_0ImmPred:$u5), 2011 (S2_tstbit_i I32:$Rs, imm:$u5)>; 2012def: Pat<(HexagonTSTBIT I32:$Rs, I32:$Rt), 2013 (S2_tstbit_r I32:$Rs, I32:$Rt)>; 2014 2015// Add extra complexity to prefer these instructions over bitsset/bitsclr. 2016// The reason is that tstbit/ntstbit can be folded into a compound instruction: 2017// if ([!]tstbit(...)) jump ... 2018let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 2019 def: Pat<(i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)), 2020 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 2021 def: Pat<(i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)), 2022 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 2023 def: Pat<(i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)), 2024 (S4_ntstbit_r I32:$Rs, I32:$Rt)>; 2025 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), 2026 (S2_tstbit_r I32:$Rs, I32:$Rt)>; 2027} 2028 2029def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64L:$u6), 0)), 2030 (S4_ntstbit_i (LoReg $Rs), (Log2_64 $u6))>; 2031def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64H:$u6), 0)), 2032 (S4_ntstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 $u6))))>; 2033def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64L:$u6), 0)), 2034 (S2_tstbit_i (LoReg $Rs), (Log2_64 imm:$u6))>; 2035def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64H:$u6), 0)), 2036 (S2_tstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 imm:$u6))))>; 2037 2038// Do not increase complexity of these patterns. In the DAG, "cmp i8" may be 2039// represented as a compare against "value & 0xFF", which is an exact match 2040// for cmpb (same for cmph). The patterns below do not contain any additional 2041// complexity that would make them preferable, and if they were actually used 2042// instead of cmpb/cmph, they would result in a compare against register that 2043// is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF). 2044def: Pat<(i1 (setne (and I32:$Rs, u6_0ImmPred:$u6), 0)), 2045 (C4_nbitsclri I32:$Rs, imm:$u6)>; 2046def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)), 2047 (C4_nbitsclr I32:$Rs, I32:$Rt)>; 2048def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)), 2049 (C4_nbitsset I32:$Rs, I32:$Rt)>; 2050 2051// Special patterns to address certain cases where the "top-down" matching 2052// algorithm would cause suboptimal selection. 2053 2054let AddedComplexity = 100 in { 2055 // Avoid A4_rcmp[n]eqi in these cases: 2056 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 2057 (I1toI32 (S4_ntstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 2058 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 2059 (I1toI32 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 2060 def: Pat<(i32 (zext (i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)))), 2061 (I1toI32 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5)))>; 2062 def: Pat<(i32 (zext (i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)))), 2063 (I1toI32 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5)))>; 2064 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 2065 (I1toI32 (S4_ntstbit_r I32:$Rs, I32:$Rt))>; 2066 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 2067 (I1toI32 (S2_tstbit_r I32:$Rs, I32:$Rt))>; 2068} 2069 2070// --(11) PIC ------------------------------------------------------------ 2071// 2072 2073def SDT_HexagonAtGot 2074 : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 2075def SDT_HexagonAtPcrel 2076 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 2077 2078// AT_GOT address-of-GOT, address-of-global, offset-in-global 2079def HexagonAtGot : SDNode<"HexagonISD::AT_GOT", SDT_HexagonAtGot>; 2080// AT_PCREL address-of-global 2081def HexagonAtPcrel : SDNode<"HexagonISD::AT_PCREL", SDT_HexagonAtPcrel>; 2082 2083def: Pat<(HexagonAtGot I32:$got, I32:$addr, (i32 0)), 2084 (L2_loadri_io I32:$got, imm:$addr)>; 2085def: Pat<(HexagonAtGot I32:$got, I32:$addr, s30_2ImmPred:$off), 2086 (A2_addi (L2_loadri_io I32:$got, imm:$addr), imm:$off)>; 2087def: Pat<(HexagonAtPcrel I32:$addr), 2088 (C4_addipc imm:$addr)>; 2089 2090// The HVX load patterns also match AT_PCREL directly. Make sure that 2091// if the selection of this opcode changes, it's updated in all places. 2092 2093 2094// --(12) Load ----------------------------------------------------------- 2095// 2096 2097def L1toI32: OutPatFrag<(ops node:$Rs), (A2_subri 0, (i32 $Rs))>; 2098def L1toI64: OutPatFrag<(ops node:$Rs), (ToSext64 (L1toI32 $Rs))>; 2099 2100def extloadv2i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 2101 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 2102}]>; 2103def extloadv4i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 2104 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 2105}]>; 2106 2107def zextloadv2i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 2108 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 2109}]>; 2110def zextloadv4i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 2111 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 2112}]>; 2113 2114def sextloadv2i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 2115 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 2116}]>; 2117def sextloadv4i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 2118 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 2119}]>; 2120 2121// Patterns to select load-indexed: Rs + Off. 2122// - frameindex [+ imm], 2123multiclass Loadxfi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 2124 InstHexagon MI> { 2125 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 2126 (VT (MI AddrFI:$fi, imm:$Off))>; 2127 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 2128 (VT (MI AddrFI:$fi, imm:$Off))>; 2129 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>; 2130} 2131 2132// Patterns to select load-indexed: Rs + Off. 2133// - base reg [+ imm] 2134multiclass Loadxgi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 2135 InstHexagon MI> { 2136 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 2137 (VT (MI IntRegs:$Rs, imm:$Off))>; 2138 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 2139 (VT (MI IntRegs:$Rs, imm:$Off))>; 2140 def: Pat<(VT (Load I32:$Rs)), (VT (MI IntRegs:$Rs, 0))>; 2141} 2142 2143// Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi. 2144multiclass Loadxi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 2145 InstHexagon MI> { 2146 defm: Loadxfi_pat<Load, VT, ImmPred, MI>; 2147 defm: Loadxgi_pat<Load, VT, ImmPred, MI>; 2148} 2149 2150// Patterns to select load reg indexed: Rs + Off with a value modifier. 2151// - frameindex [+ imm] 2152multiclass Loadxfim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2153 PatLeaf ImmPred, InstHexagon MI> { 2154 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 2155 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 2156 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 2157 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 2158 def: Pat<(VT (Load AddrFI:$fi)), (VT (ValueMod (MI AddrFI:$fi, 0)))>; 2159} 2160 2161// Patterns to select load reg indexed: Rs + Off with a value modifier. 2162// - base reg [+ imm] 2163multiclass Loadxgim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2164 PatLeaf ImmPred, InstHexagon MI> { 2165 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 2166 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 2167 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 2168 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 2169 def: Pat<(VT (Load I32:$Rs)), (VT (ValueMod (MI IntRegs:$Rs, 0)))>; 2170} 2171 2172// Patterns to select load reg indexed: Rs + Off with a value modifier. 2173// Combines Loadxfim + Loadxgim. 2174multiclass Loadxim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2175 PatLeaf ImmPred, InstHexagon MI> { 2176 defm: Loadxfim_pat<Load, VT, ValueMod, ImmPred, MI>; 2177 defm: Loadxgim_pat<Load, VT, ValueMod, ImmPred, MI>; 2178} 2179 2180// Pattern to select load reg reg-indexed: Rs + Rt<<u2. 2181class Loadxr_shl_pat<PatFrag Load, ValueType VT, InstHexagon MI> 2182 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 2183 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>; 2184 2185// Pattern to select load reg reg-indexed: Rs + Rt<<0. 2186class Loadxr_add_pat<PatFrag Load, ValueType VT, InstHexagon MI> 2187 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 2188 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>; 2189 2190// Pattern to select load reg reg-indexed: Rs + Rt<<u2 with value modifier. 2191class Loadxrm_shl_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2192 InstHexagon MI> 2193 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 2194 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2)))>; 2195 2196// Pattern to select load reg reg-indexed: Rs + Rt<<0 with value modifier. 2197class Loadxrm_add_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2198 InstHexagon MI> 2199 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 2200 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, 0)))>; 2201 2202// Pattern to select load long-offset reg-indexed: Addr + Rt<<u2. 2203// Don't match for u2==0, instead use reg+imm for those cases. 2204class Loadxu_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, InstHexagon MI> 2205 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 2206 (VT (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr))>; 2207 2208class Loadxum_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, PatFrag ValueMod, 2209 InstHexagon MI> 2210 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 2211 (VT (ValueMod (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr)))>; 2212 2213// Pattern to select load absolute. 2214class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI> 2215 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>; 2216 2217// Pattern to select load absolute with value modifier. 2218class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod, 2219 InstHexagon MI> 2220 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>; 2221 2222 2223let AddedComplexity = 20 in { 2224 defm: Loadxi_pat<extloadi1, i32, anyimm0, L2_loadrub_io>; 2225 defm: Loadxi_pat<extloadi8, i32, anyimm0, L2_loadrub_io>; 2226 defm: Loadxi_pat<extloadi16, i32, anyimm1, L2_loadruh_io>; 2227 defm: Loadxi_pat<extloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 2228 defm: Loadxi_pat<extloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2229 defm: Loadxi_pat<sextloadi8, i32, anyimm0, L2_loadrb_io>; 2230 defm: Loadxi_pat<sextloadi16, i32, anyimm1, L2_loadrh_io>; 2231 defm: Loadxi_pat<sextloadv2i8, v2i16, anyimm1, L2_loadbsw2_io>; 2232 defm: Loadxi_pat<sextloadv4i8, v4i16, anyimm2, L2_loadbsw4_io>; 2233 defm: Loadxi_pat<zextloadi1, i32, anyimm0, L2_loadrub_io>; 2234 defm: Loadxi_pat<zextloadi8, i32, anyimm0, L2_loadrub_io>; 2235 defm: Loadxi_pat<zextloadi16, i32, anyimm1, L2_loadruh_io>; 2236 defm: Loadxi_pat<zextloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 2237 defm: Loadxi_pat<zextloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2238 defm: Loadxi_pat<load, i32, anyimm2, L2_loadri_io>; 2239 defm: Loadxi_pat<load, v2i16, anyimm2, L2_loadri_io>; 2240 defm: Loadxi_pat<load, v4i8, anyimm2, L2_loadri_io>; 2241 defm: Loadxi_pat<load, i64, anyimm3, L2_loadrd_io>; 2242 defm: Loadxi_pat<load, v2i32, anyimm3, L2_loadrd_io>; 2243 defm: Loadxi_pat<load, v4i16, anyimm3, L2_loadrd_io>; 2244 defm: Loadxi_pat<load, v8i8, anyimm3, L2_loadrd_io>; 2245 defm: Loadxi_pat<load, f32, anyimm2, L2_loadri_io>; 2246 defm: Loadxi_pat<load, f64, anyimm3, L2_loadrd_io>; 2247 // No sextloadi1. 2248 2249 defm: Loadxi_pat<atomic_load_8 , i32, anyimm0, L2_loadrub_io>; 2250 defm: Loadxi_pat<atomic_load_16, i32, anyimm1, L2_loadruh_io>; 2251 defm: Loadxi_pat<atomic_load_32, i32, anyimm2, L2_loadri_io>; 2252 defm: Loadxi_pat<atomic_load_64, i64, anyimm3, L2_loadrd_io>; 2253} 2254 2255let AddedComplexity = 30 in { 2256 // Loads of i1 are loading a byte, and the byte should be either 0 or 1. 2257 // It doesn't matter if it's sign- or zero-extended, so use zero-extension 2258 // everywhere. 2259 defm: Loadxim_pat<sextloadi1, i32, L1toI32, anyimm0, L2_loadrub_io>; 2260 defm: Loadxim_pat<extloadi1, i64, ToAext64, anyimm0, L2_loadrub_io>; 2261 defm: Loadxim_pat<sextloadi1, i64, L1toI64, anyimm0, L2_loadrub_io>; 2262 defm: Loadxim_pat<zextloadi1, i64, ToZext64, anyimm0, L2_loadrub_io>; 2263 2264 defm: Loadxim_pat<extloadi8, i64, ToAext64, anyimm0, L2_loadrub_io>; 2265 defm: Loadxim_pat<extloadi16, i64, ToAext64, anyimm1, L2_loadruh_io>; 2266 defm: Loadxim_pat<extloadi32, i64, ToAext64, anyimm2, L2_loadri_io>; 2267 defm: Loadxim_pat<zextloadi8, i64, ToZext64, anyimm0, L2_loadrub_io>; 2268 defm: Loadxim_pat<zextloadi16, i64, ToZext64, anyimm1, L2_loadruh_io>; 2269 defm: Loadxim_pat<zextloadi32, i64, ToZext64, anyimm2, L2_loadri_io>; 2270 defm: Loadxim_pat<sextloadi8, i64, ToSext64, anyimm0, L2_loadrb_io>; 2271 defm: Loadxim_pat<sextloadi16, i64, ToSext64, anyimm1, L2_loadrh_io>; 2272 defm: Loadxim_pat<sextloadi32, i64, ToSext64, anyimm2, L2_loadri_io>; 2273} 2274 2275let AddedComplexity = 60 in { 2276 def: Loadxu_pat<extloadi1, i32, anyimm0, L4_loadrub_ur>; 2277 def: Loadxu_pat<extloadi8, i32, anyimm0, L4_loadrub_ur>; 2278 def: Loadxu_pat<extloadi16, i32, anyimm1, L4_loadruh_ur>; 2279 def: Loadxu_pat<extloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 2280 def: Loadxu_pat<extloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2281 def: Loadxu_pat<sextloadi8, i32, anyimm0, L4_loadrb_ur>; 2282 def: Loadxu_pat<sextloadi16, i32, anyimm1, L4_loadrh_ur>; 2283 def: Loadxu_pat<sextloadv2i8, v2i16, anyimm1, L4_loadbsw2_ur>; 2284 def: Loadxu_pat<sextloadv4i8, v4i16, anyimm2, L4_loadbsw4_ur>; 2285 def: Loadxu_pat<zextloadi1, i32, anyimm0, L4_loadrub_ur>; 2286 def: Loadxu_pat<zextloadi8, i32, anyimm0, L4_loadrub_ur>; 2287 def: Loadxu_pat<zextloadi16, i32, anyimm1, L4_loadruh_ur>; 2288 def: Loadxu_pat<zextloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 2289 def: Loadxu_pat<zextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2290 def: Loadxu_pat<load, i32, anyimm2, L4_loadri_ur>; 2291 def: Loadxu_pat<load, v2i16, anyimm2, L4_loadri_ur>; 2292 def: Loadxu_pat<load, v4i8, anyimm2, L4_loadri_ur>; 2293 def: Loadxu_pat<load, i64, anyimm3, L4_loadrd_ur>; 2294 def: Loadxu_pat<load, v2i32, anyimm3, L4_loadrd_ur>; 2295 def: Loadxu_pat<load, v4i16, anyimm3, L4_loadrd_ur>; 2296 def: Loadxu_pat<load, v8i8, anyimm3, L4_loadrd_ur>; 2297 def: Loadxu_pat<load, f32, anyimm2, L4_loadri_ur>; 2298 def: Loadxu_pat<load, f64, anyimm3, L4_loadrd_ur>; 2299 2300 def: Loadxum_pat<sextloadi1, i32, anyimm0, L1toI32, L4_loadrub_ur>; 2301 def: Loadxum_pat<extloadi1, i64, anyimm0, ToAext64, L4_loadrub_ur>; 2302 def: Loadxum_pat<sextloadi1, i64, anyimm0, L1toI64, L4_loadrub_ur>; 2303 def: Loadxum_pat<zextloadi1, i64, anyimm0, ToZext64, L4_loadrub_ur>; 2304 2305 def: Loadxum_pat<sextloadi8, i64, anyimm0, ToSext64, L4_loadrb_ur>; 2306 def: Loadxum_pat<zextloadi8, i64, anyimm0, ToZext64, L4_loadrub_ur>; 2307 def: Loadxum_pat<extloadi8, i64, anyimm0, ToAext64, L4_loadrub_ur>; 2308 def: Loadxum_pat<sextloadi16, i64, anyimm1, ToSext64, L4_loadrh_ur>; 2309 def: Loadxum_pat<zextloadi16, i64, anyimm1, ToZext64, L4_loadruh_ur>; 2310 def: Loadxum_pat<extloadi16, i64, anyimm1, ToAext64, L4_loadruh_ur>; 2311 def: Loadxum_pat<sextloadi32, i64, anyimm2, ToSext64, L4_loadri_ur>; 2312 def: Loadxum_pat<zextloadi32, i64, anyimm2, ToZext64, L4_loadri_ur>; 2313 def: Loadxum_pat<extloadi32, i64, anyimm2, ToAext64, L4_loadri_ur>; 2314} 2315 2316let AddedComplexity = 40 in { 2317 def: Loadxr_shl_pat<extloadi1, i32, L4_loadrub_rr>; 2318 def: Loadxr_shl_pat<extloadi8, i32, L4_loadrub_rr>; 2319 def: Loadxr_shl_pat<zextloadi1, i32, L4_loadrub_rr>; 2320 def: Loadxr_shl_pat<zextloadi8, i32, L4_loadrub_rr>; 2321 def: Loadxr_shl_pat<sextloadi8, i32, L4_loadrb_rr>; 2322 def: Loadxr_shl_pat<extloadi16, i32, L4_loadruh_rr>; 2323 def: Loadxr_shl_pat<zextloadi16, i32, L4_loadruh_rr>; 2324 def: Loadxr_shl_pat<sextloadi16, i32, L4_loadrh_rr>; 2325 def: Loadxr_shl_pat<load, i32, L4_loadri_rr>; 2326 def: Loadxr_shl_pat<load, v2i16, L4_loadri_rr>; 2327 def: Loadxr_shl_pat<load, v4i8, L4_loadri_rr>; 2328 def: Loadxr_shl_pat<load, i64, L4_loadrd_rr>; 2329 def: Loadxr_shl_pat<load, v2i32, L4_loadrd_rr>; 2330 def: Loadxr_shl_pat<load, v4i16, L4_loadrd_rr>; 2331 def: Loadxr_shl_pat<load, v8i8, L4_loadrd_rr>; 2332 def: Loadxr_shl_pat<load, f32, L4_loadri_rr>; 2333 def: Loadxr_shl_pat<load, f64, L4_loadrd_rr>; 2334} 2335 2336let AddedComplexity = 20 in { 2337 def: Loadxr_add_pat<extloadi1, i32, L4_loadrub_rr>; 2338 def: Loadxr_add_pat<extloadi8, i32, L4_loadrub_rr>; 2339 def: Loadxr_add_pat<zextloadi8, i32, L4_loadrub_rr>; 2340 def: Loadxr_add_pat<zextloadi1, i32, L4_loadrub_rr>; 2341 def: Loadxr_add_pat<sextloadi8, i32, L4_loadrb_rr>; 2342 def: Loadxr_add_pat<extloadi16, i32, L4_loadruh_rr>; 2343 def: Loadxr_add_pat<zextloadi16, i32, L4_loadruh_rr>; 2344 def: Loadxr_add_pat<sextloadi16, i32, L4_loadrh_rr>; 2345 def: Loadxr_add_pat<load, i32, L4_loadri_rr>; 2346 def: Loadxr_add_pat<load, v2i16, L4_loadri_rr>; 2347 def: Loadxr_add_pat<load, v4i8, L4_loadri_rr>; 2348 def: Loadxr_add_pat<load, i64, L4_loadrd_rr>; 2349 def: Loadxr_add_pat<load, v2i32, L4_loadrd_rr>; 2350 def: Loadxr_add_pat<load, v4i16, L4_loadrd_rr>; 2351 def: Loadxr_add_pat<load, v8i8, L4_loadrd_rr>; 2352 def: Loadxr_add_pat<load, f32, L4_loadri_rr>; 2353 def: Loadxr_add_pat<load, f64, L4_loadrd_rr>; 2354} 2355 2356let AddedComplexity = 40 in { 2357 def: Loadxrm_shl_pat<sextloadi1, i32, L1toI32, L4_loadrub_rr>; 2358 def: Loadxrm_shl_pat<extloadi1, i64, ToAext64, L4_loadrub_rr>; 2359 def: Loadxrm_shl_pat<sextloadi1, i64, L1toI64, L4_loadrub_rr>; 2360 def: Loadxrm_shl_pat<zextloadi1, i64, ToZext64, L4_loadrub_rr>; 2361 2362 def: Loadxrm_shl_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2363 def: Loadxrm_shl_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2364 def: Loadxrm_shl_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2365 def: Loadxrm_shl_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2366 def: Loadxrm_shl_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2367 def: Loadxrm_shl_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2368 def: Loadxrm_shl_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2369 def: Loadxrm_shl_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2370 def: Loadxrm_shl_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2371} 2372 2373let AddedComplexity = 30 in { 2374 def: Loadxrm_add_pat<sextloadi1, i32, L1toI32, L4_loadrub_rr>; 2375 def: Loadxrm_add_pat<extloadi1, i64, ToAext64, L4_loadrub_rr>; 2376 def: Loadxrm_add_pat<sextloadi1, i64, L1toI64, L4_loadrub_rr>; 2377 def: Loadxrm_add_pat<zextloadi1, i64, ToZext64, L4_loadrub_rr>; 2378 2379 def: Loadxrm_add_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2380 def: Loadxrm_add_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2381 def: Loadxrm_add_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2382 def: Loadxrm_add_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2383 def: Loadxrm_add_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2384 def: Loadxrm_add_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2385 def: Loadxrm_add_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2386 def: Loadxrm_add_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2387 def: Loadxrm_add_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2388} 2389 2390// Absolute address 2391 2392let AddedComplexity = 60 in { 2393 def: Loada_pat<extloadi1, i32, anyimm0, PS_loadrubabs>; 2394 def: Loada_pat<zextloadi1, i32, anyimm0, PS_loadrubabs>; 2395 def: Loada_pat<extloadi8, i32, anyimm0, PS_loadrubabs>; 2396 def: Loada_pat<sextloadi8, i32, anyimm0, PS_loadrbabs>; 2397 def: Loada_pat<zextloadi8, i32, anyimm0, PS_loadrubabs>; 2398 def: Loada_pat<extloadi16, i32, anyimm1, PS_loadruhabs>; 2399 def: Loada_pat<sextloadi16, i32, anyimm1, PS_loadrhabs>; 2400 def: Loada_pat<zextloadi16, i32, anyimm1, PS_loadruhabs>; 2401 def: Loada_pat<load, i32, anyimm2, PS_loadriabs>; 2402 def: Loada_pat<load, v2i16, anyimm2, PS_loadriabs>; 2403 def: Loada_pat<load, v4i8, anyimm2, PS_loadriabs>; 2404 def: Loada_pat<load, i64, anyimm3, PS_loadrdabs>; 2405 def: Loada_pat<load, v2i32, anyimm3, PS_loadrdabs>; 2406 def: Loada_pat<load, v4i16, anyimm3, PS_loadrdabs>; 2407 def: Loada_pat<load, v8i8, anyimm3, PS_loadrdabs>; 2408 def: Loada_pat<load, f32, anyimm2, PS_loadriabs>; 2409 def: Loada_pat<load, f64, anyimm3, PS_loadrdabs>; 2410 2411 def: Loada_pat<atomic_load_8, i32, anyimm0, PS_loadrubabs>; 2412 def: Loada_pat<atomic_load_16, i32, anyimm1, PS_loadruhabs>; 2413 def: Loada_pat<atomic_load_32, i32, anyimm2, PS_loadriabs>; 2414 def: Loada_pat<atomic_load_64, i64, anyimm3, PS_loadrdabs>; 2415} 2416 2417let AddedComplexity = 30 in { 2418 def: Loadam_pat<load, i1, anyimm0, I32toI1, PS_loadrubabs>; 2419 def: Loadam_pat<sextloadi1, i32, anyimm0, L1toI32, PS_loadrubabs>; 2420 def: Loadam_pat<extloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>; 2421 def: Loadam_pat<sextloadi1, i64, anyimm0, L1toI64, PS_loadrubabs>; 2422 def: Loadam_pat<zextloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>; 2423 2424 def: Loadam_pat<extloadi8, i64, anyimm0, ToAext64, PS_loadrubabs>; 2425 def: Loadam_pat<sextloadi8, i64, anyimm0, ToSext64, PS_loadrbabs>; 2426 def: Loadam_pat<zextloadi8, i64, anyimm0, ToZext64, PS_loadrubabs>; 2427 def: Loadam_pat<extloadi16, i64, anyimm1, ToAext64, PS_loadruhabs>; 2428 def: Loadam_pat<sextloadi16, i64, anyimm1, ToSext64, PS_loadrhabs>; 2429 def: Loadam_pat<zextloadi16, i64, anyimm1, ToZext64, PS_loadruhabs>; 2430 def: Loadam_pat<extloadi32, i64, anyimm2, ToAext64, PS_loadriabs>; 2431 def: Loadam_pat<sextloadi32, i64, anyimm2, ToSext64, PS_loadriabs>; 2432 def: Loadam_pat<zextloadi32, i64, anyimm2, ToZext64, PS_loadriabs>; 2433} 2434 2435// GP-relative address 2436 2437let AddedComplexity = 100 in { 2438 def: Loada_pat<extloadi1, i32, addrgp, L2_loadrubgp>; 2439 def: Loada_pat<zextloadi1, i32, addrgp, L2_loadrubgp>; 2440 def: Loada_pat<extloadi8, i32, addrgp, L2_loadrubgp>; 2441 def: Loada_pat<sextloadi8, i32, addrgp, L2_loadrbgp>; 2442 def: Loada_pat<zextloadi8, i32, addrgp, L2_loadrubgp>; 2443 def: Loada_pat<extloadi16, i32, addrgp, L2_loadruhgp>; 2444 def: Loada_pat<sextloadi16, i32, addrgp, L2_loadrhgp>; 2445 def: Loada_pat<zextloadi16, i32, addrgp, L2_loadruhgp>; 2446 def: Loada_pat<load, i32, addrgp, L2_loadrigp>; 2447 def: Loada_pat<load, v2i16, addrgp, L2_loadrigp>; 2448 def: Loada_pat<load, v4i8, addrgp, L2_loadrigp>; 2449 def: Loada_pat<load, i64, addrgp, L2_loadrdgp>; 2450 def: Loada_pat<load, v2i32, addrgp, L2_loadrdgp>; 2451 def: Loada_pat<load, v4i16, addrgp, L2_loadrdgp>; 2452 def: Loada_pat<load, v8i8, addrgp, L2_loadrdgp>; 2453 def: Loada_pat<load, f32, addrgp, L2_loadrigp>; 2454 def: Loada_pat<load, f64, addrgp, L2_loadrdgp>; 2455 2456 def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>; 2457 def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>; 2458 def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>; 2459 def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>; 2460} 2461 2462let AddedComplexity = 70 in { 2463 def: Loadam_pat<sextloadi1, i32, addrgp, L1toI32, L2_loadrubgp>; 2464 def: Loadam_pat<extloadi1, i64, addrgp, ToAext64, L2_loadrubgp>; 2465 def: Loadam_pat<sextloadi1, i64, addrgp, L1toI64, L2_loadrubgp>; 2466 def: Loadam_pat<zextloadi1, i64, addrgp, ToZext64, L2_loadrubgp>; 2467 2468 def: Loadam_pat<extloadi8, i64, addrgp, ToAext64, L2_loadrubgp>; 2469 def: Loadam_pat<sextloadi8, i64, addrgp, ToSext64, L2_loadrbgp>; 2470 def: Loadam_pat<zextloadi8, i64, addrgp, ToZext64, L2_loadrubgp>; 2471 def: Loadam_pat<extloadi16, i64, addrgp, ToAext64, L2_loadruhgp>; 2472 def: Loadam_pat<sextloadi16, i64, addrgp, ToSext64, L2_loadrhgp>; 2473 def: Loadam_pat<zextloadi16, i64, addrgp, ToZext64, L2_loadruhgp>; 2474 def: Loadam_pat<extloadi32, i64, addrgp, ToAext64, L2_loadrigp>; 2475 def: Loadam_pat<sextloadi32, i64, addrgp, ToSext64, L2_loadrigp>; 2476 def: Loadam_pat<zextloadi32, i64, addrgp, ToZext64, L2_loadrigp>; 2477 2478 def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>; 2479} 2480 2481// Patterns for loads of i1: 2482def: Pat<(i1 (load AddrFI:$fi)), 2483 (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>; 2484def: Pat<(i1 (load (add I32:$Rs, anyimm0:$Off))), 2485 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>; 2486def: Pat<(i1 (load I32:$Rs)), 2487 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>; 2488 2489 2490// --(13) Store ---------------------------------------------------------- 2491// 2492 2493class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset, InstHexagon MI> 2494 : Pat<(Store Value:$Rt, I32:$Rx, Offset:$s4), 2495 (MI I32:$Rx, imm:$s4, Value:$Rt)>; 2496 2497def: Storepi_pat<post_truncsti8, I32, s4_0ImmPred, S2_storerb_pi>; 2498def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>; 2499def: Storepi_pat<post_store, I32, s4_2ImmPred, S2_storeri_pi>; 2500def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>; 2501 2502// Patterns for generating stores, where the address takes different forms: 2503// - frameindex, 2504// - frameindex + offset, 2505// - base + offset, 2506// - simple (base address without offset). 2507// These would usually be used together (via Storexi_pat defined below), but 2508// in some cases one may want to apply different properties (such as 2509// AddedComplexity) to the individual patterns. 2510class Storexi_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2511 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>; 2512 2513multiclass Storexi_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2514 InstHexagon MI> { 2515 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2516 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2517 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2518 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2519} 2520 2521multiclass Storexi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2522 InstHexagon MI> { 2523 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2524 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2525 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2526 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2527} 2528 2529class Storexi_base_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2530 : Pat<(Store Value:$Rt, I32:$Rs), 2531 (MI IntRegs:$Rs, 0, Value:$Rt)>; 2532 2533// Patterns for generating stores, where the address takes different forms, 2534// and where the value being stored is transformed through the value modifier 2535// ValueMod. The address forms are same as above. 2536class Storexim_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2537 InstHexagon MI> 2538 : Pat<(Store Value:$Rs, AddrFI:$fi), 2539 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>; 2540 2541multiclass Storexim_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2542 PatFrag ValueMod, InstHexagon MI> { 2543 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2544 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2545 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2546 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2547} 2548 2549multiclass Storexim_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2550 PatFrag ValueMod, InstHexagon MI> { 2551 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2552 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2553 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2554 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2555} 2556 2557class Storexim_base_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2558 InstHexagon MI> 2559 : Pat<(Store Value:$Rt, I32:$Rs), 2560 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>; 2561 2562multiclass Storexi_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2563 InstHexagon MI> { 2564 defm: Storexi_fi_add_pat <Store, Value, ImmPred, MI>; 2565 def: Storexi_fi_pat <Store, Value, MI>; 2566 defm: Storexi_add_pat <Store, Value, ImmPred, MI>; 2567} 2568 2569multiclass Storexim_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2570 PatFrag ValueMod, InstHexagon MI> { 2571 defm: Storexim_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2572 def: Storexim_fi_pat <Store, Value, ValueMod, MI>; 2573 defm: Storexim_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2574} 2575 2576// Reg<<S + Imm 2577class Storexu_shl_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, InstHexagon MI> 2578 : Pat<(Store Value:$Rt, (add (shl I32:$Ru, u2_0ImmPred:$u2), ImmPred:$A)), 2579 (MI IntRegs:$Ru, imm:$u2, ImmPred:$A, Value:$Rt)>; 2580 2581// Reg<<S + Reg 2582class Storexr_shl_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2583 : Pat<(Store Value:$Ru, (add I32:$Rs, (shl I32:$Rt, u2_0ImmPred:$u2))), 2584 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>; 2585 2586// Reg + Reg 2587class Storexr_add_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2588 : Pat<(Store Value:$Ru, (add I32:$Rs, I32:$Rt)), 2589 (MI IntRegs:$Rs, IntRegs:$Rt, 0, Value:$Ru)>; 2590 2591class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI> 2592 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>; 2593 2594class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod, 2595 InstHexagon MI> 2596 : Pat<(Store Value:$val, Addr:$addr), 2597 (MI Addr:$addr, (ValueMod Value:$val))>; 2598 2599def IMM_BYTE : SDNodeXForm<imm, [{ 2600 // -1 can be represented as 255, etc. 2601 // assigning to a byte restores our desired signed value. 2602 int8_t imm = N->getSExtValue(); 2603 return CurDAG->getSignedTargetConstant(imm, SDLoc(N), MVT::i32); 2604}]>; 2605 2606def IMM_HALF : SDNodeXForm<imm, [{ 2607 // -1 can be represented as 65535, etc. 2608 // assigning to a short restores our desired signed value. 2609 int16_t imm = N->getSExtValue(); 2610 return CurDAG->getSignedTargetConstant(imm, SDLoc(N), MVT::i32); 2611}]>; 2612 2613def IMM_WORD : SDNodeXForm<imm, [{ 2614 // -1 can be represented as 4294967295, etc. 2615 // Currently, it's not doing this. But some optimization 2616 // might convert -1 to a large +ve number. 2617 // assigning to a word restores our desired signed value. 2618 int32_t imm = N->getSExtValue(); 2619 return CurDAG->getSignedTargetConstant(imm, SDLoc(N), MVT::i32); 2620}]>; 2621 2622def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>; 2623def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>; 2624def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>; 2625 2626// Even though the offset is not extendable in the store-immediate, we 2627// can still generate the fi# in the base address. If the final offset 2628// is not valid for the instruction, we will replace it with a scratch 2629// register. 2630class SmallStackStore<PatFrag Store> 2631 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2632 return isSmallStackStore(cast<StoreSDNode>(N)); 2633}]>; 2634 2635// This is the complement of SmallStackStore. 2636class LargeStackStore<PatFrag Store> 2637 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2638 return !isSmallStackStore(cast<StoreSDNode>(N)); 2639}]>; 2640 2641// Preferred addressing modes for various combinations of stored value 2642// and address computation. 2643// For stores where the address and value are both immediates, prefer 2644// store-immediate. The reason is that the constant-extender optimization 2645// can replace store-immediate with a store-register, but there is nothing 2646// to generate a store-immediate out of a store-register. 2647// 2648// C R F F+C R+C R+R R<<S+C R<<S+R 2649// --+-------+-----+-----+------+-----+-----+--------+-------- 2650// C | imm | imm | imm | imm | imm | rr | ur | rr 2651// R | abs* | io | io | io | io | rr | ur | rr 2652// 2653// (*) Absolute or GP-relative. 2654// 2655// Note that any expression can be matched by Reg. In particular, an immediate 2656// can always be placed in a register, so patterns checking for Imm should 2657// have a higher priority than the ones involving Reg that could also match. 2658// For example, *(p+4) could become r1=#4; memw(r0+r1<<#0) instead of the 2659// preferred memw(r0+#4). Similarly Reg+Imm or Reg+Reg should be tried before 2660// Reg alone. 2661// 2662// The order in which the different combinations are tried: 2663// 2664// C F R F+C R+C R+R R<<S+C R<<S+R 2665// --+-------+-----+-----+------+-----+-----+--------+-------- 2666// C | 1 | 6 | - | 5 | 9 | - | - | - 2667// R | 2 | 8 | 12 | 7 | 10 | 11 | 3 | 4 2668 2669 2670// First, match the unusual case of doubleword store into Reg+Imm4, i.e. 2671// a store where the offset Imm4 is a multiple of 4, but not of 8. This 2672// implies that Reg is also a proper multiple of 4. To still generate a 2673// doubleword store, add 4 to Reg, and subtract 4 from the offset. 2674 2675def s30_2ProperPred : PatLeaf<(i32 imm), [{ 2676 int64_t v = (int64_t)N->getSExtValue(); 2677 return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v); 2678}]>; 2679def RoundTo8 : SDNodeXForm<imm, [{ 2680 int32_t Imm = N->getSExtValue(); 2681 return CurDAG->getSignedTargetConstant(Imm & -8, SDLoc(N), MVT::i32); 2682}]>; 2683 2684let AddedComplexity = 150 in 2685def: Pat<(store I64:$Ru, (add I32:$Rs, s30_2ProperPred:$Off)), 2686 (S2_storerd_io (A2_addi I32:$Rs, 4), (RoundTo8 $Off), I64:$Ru)>; 2687 2688class Storexi_abs_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2689 : Pat<(Store Value:$val, anyimm:$addr), 2690 (MI (ToI32 $addr), 0, Value:$val)>; 2691class Storexim_abs_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2692 InstHexagon MI> 2693 : Pat<(Store Value:$val, anyimm:$addr), 2694 (MI (ToI32 $addr), 0, (ValueMod Value:$val))>; 2695 2696let AddedComplexity = 140 in { 2697 def: Storexim_abs_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2698 def: Storexim_abs_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2699 def: Storexim_abs_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2700 2701 def: Storexi_abs_pat<truncstorei8, anyimm, S4_storeirb_io>; 2702 def: Storexi_abs_pat<truncstorei16, anyimm, S4_storeirh_io>; 2703 def: Storexi_abs_pat<store, anyimm, S4_storeiri_io>; 2704} 2705 2706// GP-relative address 2707let AddedComplexity = 120 in { 2708 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbgp>; 2709 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhgp>; 2710 def: Storea_pat<store, I32, addrgp, S2_storerigp>; 2711 def: Storea_pat<store, V4I8, addrgp, S2_storerigp>; 2712 def: Storea_pat<store, V2I16, addrgp, S2_storerigp>; 2713 def: Storea_pat<store, I64, addrgp, S2_storerdgp>; 2714 def: Storea_pat<store, V8I8, addrgp, S2_storerdgp>; 2715 def: Storea_pat<store, V4I16, addrgp, S2_storerdgp>; 2716 def: Storea_pat<store, V2I32, addrgp, S2_storerdgp>; 2717 def: Storea_pat<store, F32, addrgp, S2_storerigp>; 2718 def: Storea_pat<store, F64, addrgp, S2_storerdgp>; 2719 def: Storea_pat<atomic_store_8, I32, addrgp, S2_storerbgp>; 2720 def: Storea_pat<atomic_store_16, I32, addrgp, S2_storerhgp>; 2721 def: Storea_pat<atomic_store_32, I32, addrgp, S2_storerigp>; 2722 def: Storea_pat<atomic_store_32, V4I8, addrgp, S2_storerigp>; 2723 def: Storea_pat<atomic_store_32, V2I16, addrgp, S2_storerigp>; 2724 def: Storea_pat<atomic_store_64, I64, addrgp, S2_storerdgp>; 2725 def: Storea_pat<atomic_store_64, V8I8, addrgp, S2_storerdgp>; 2726 def: Storea_pat<atomic_store_64, V4I16, addrgp, S2_storerdgp>; 2727 def: Storea_pat<atomic_store_64, V2I32, addrgp, S2_storerdgp>; 2728 2729 def: Stoream_pat<truncstorei8, I64, addrgp, LoReg, S2_storerbgp>; 2730 def: Stoream_pat<truncstorei16, I64, addrgp, LoReg, S2_storerhgp>; 2731 def: Stoream_pat<truncstorei32, I64, addrgp, LoReg, S2_storerigp>; 2732 def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>; 2733} 2734 2735// Absolute address 2736let AddedComplexity = 110 in { 2737 def: Storea_pat<truncstorei8, I32, anyimm0, PS_storerbabs>; 2738 def: Storea_pat<truncstorei16, I32, anyimm1, PS_storerhabs>; 2739 def: Storea_pat<store, I32, anyimm2, PS_storeriabs>; 2740 def: Storea_pat<store, V4I8, anyimm2, PS_storeriabs>; 2741 def: Storea_pat<store, V2I16, anyimm2, PS_storeriabs>; 2742 def: Storea_pat<store, I64, anyimm3, PS_storerdabs>; 2743 def: Storea_pat<store, V8I8, anyimm3, PS_storerdabs>; 2744 def: Storea_pat<store, V4I16, anyimm3, PS_storerdabs>; 2745 def: Storea_pat<store, V2I32, anyimm3, PS_storerdabs>; 2746 def: Storea_pat<store, F32, anyimm2, PS_storeriabs>; 2747 def: Storea_pat<store, F64, anyimm3, PS_storerdabs>; 2748 def: Storea_pat<atomic_store_8, I32, anyimm0, PS_storerbabs>; 2749 def: Storea_pat<atomic_store_16, I32, anyimm1, PS_storerhabs>; 2750 def: Storea_pat<atomic_store_32, I32, anyimm2, PS_storeriabs>; 2751 def: Storea_pat<atomic_store_32, V4I8, anyimm2, PS_storeriabs>; 2752 def: Storea_pat<atomic_store_32, V2I16, anyimm2, PS_storeriabs>; 2753 def: Storea_pat<atomic_store_64, I64, anyimm3, PS_storerdabs>; 2754 def: Storea_pat<atomic_store_64, V8I8, anyimm3, PS_storerdabs>; 2755 def: Storea_pat<atomic_store_64, V4I16, anyimm3, PS_storerdabs>; 2756 def: Storea_pat<atomic_store_64, V2I32, anyimm3, PS_storerdabs>; 2757 2758 def: Stoream_pat<truncstorei8, I64, anyimm0, LoReg, PS_storerbabs>; 2759 def: Stoream_pat<truncstorei16, I64, anyimm1, LoReg, PS_storerhabs>; 2760 def: Stoream_pat<truncstorei32, I64, anyimm2, LoReg, PS_storeriabs>; 2761 def: Stoream_pat<store, I1, anyimm0, I1toI32, PS_storerbabs>; 2762} 2763 2764// Reg<<S + Imm 2765let AddedComplexity = 100 in { 2766 def: Storexu_shl_pat<truncstorei8, I32, anyimm0, S4_storerb_ur>; 2767 def: Storexu_shl_pat<truncstorei16, I32, anyimm1, S4_storerh_ur>; 2768 def: Storexu_shl_pat<store, I32, anyimm2, S4_storeri_ur>; 2769 def: Storexu_shl_pat<store, V4I8, anyimm2, S4_storeri_ur>; 2770 def: Storexu_shl_pat<store, V2I16, anyimm2, S4_storeri_ur>; 2771 def: Storexu_shl_pat<store, I64, anyimm3, S4_storerd_ur>; 2772 def: Storexu_shl_pat<store, V8I8, anyimm3, S4_storerd_ur>; 2773 def: Storexu_shl_pat<store, V4I16, anyimm3, S4_storerd_ur>; 2774 def: Storexu_shl_pat<store, V2I32, anyimm3, S4_storerd_ur>; 2775 def: Storexu_shl_pat<store, F32, anyimm2, S4_storeri_ur>; 2776 def: Storexu_shl_pat<store, F64, anyimm3, S4_storerd_ur>; 2777 2778 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), anyimm:$A)), 2779 (S4_storerb_ur IntRegs:$Rs, imm:$u2, imm:$A, (I1toI32 I1:$Pu))>; 2780} 2781 2782// Reg<<S + Reg 2783let AddedComplexity = 90 in { 2784 def: Storexr_shl_pat<truncstorei8, I32, S4_storerb_rr>; 2785 def: Storexr_shl_pat<truncstorei16, I32, S4_storerh_rr>; 2786 def: Storexr_shl_pat<store, I32, S4_storeri_rr>; 2787 def: Storexr_shl_pat<store, V4I8, S4_storeri_rr>; 2788 def: Storexr_shl_pat<store, V2I16, S4_storeri_rr>; 2789 def: Storexr_shl_pat<store, I64, S4_storerd_rr>; 2790 def: Storexr_shl_pat<store, V8I8, S4_storerd_rr>; 2791 def: Storexr_shl_pat<store, V4I16, S4_storerd_rr>; 2792 def: Storexr_shl_pat<store, V2I32, S4_storerd_rr>; 2793 def: Storexr_shl_pat<store, F32, S4_storeri_rr>; 2794 def: Storexr_shl_pat<store, F64, S4_storerd_rr>; 2795 2796 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), I32:$Rt)), 2797 (S4_storerb_rr IntRegs:$Rt, IntRegs:$Rs, imm:$u2, (I1toI32 I1:$Pu))>; 2798} 2799 2800class SS_<PatFrag F> : SmallStackStore<F>; 2801class LS_<PatFrag F> : LargeStackStore<F>; 2802 2803multiclass IMFA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2804 defm: Storexim_fi_add_pat<S, V, O, M, I>; 2805} 2806multiclass IFA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2807 defm: Storexi_fi_add_pat<S, V, O, I>; 2808} 2809 2810// Fi+Imm, store-immediate 2811let AddedComplexity = 80 in { 2812 defm: IMFA_<SS_<truncstorei8>, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2813 defm: IMFA_<SS_<truncstorei16>, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2814 defm: IMFA_<SS_<store>, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2815 2816 defm: IFA_<SS_<truncstorei8>, anyimm, u6_0ImmPred, S4_storeirb_io>; 2817 defm: IFA_<SS_<truncstorei16>, anyimm, u6_1ImmPred, S4_storeirh_io>; 2818 defm: IFA_<SS_<store>, anyimm, u6_2ImmPred, S4_storeiri_io>; 2819 2820 // For large-stack stores, generate store-register (prefer explicit Fi 2821 // in the address). 2822 defm: IMFA_<LS_<truncstorei8>, anyimm, u6_0ImmPred, ToI32, S2_storerb_io>; 2823 defm: IMFA_<LS_<truncstorei16>, anyimm, u6_1ImmPred, ToI32, S2_storerh_io>; 2824 defm: IMFA_<LS_<store>, anyimm, u6_2ImmPred, ToI32, S2_storeri_io>; 2825} 2826 2827// Fi, store-immediate 2828let AddedComplexity = 70 in { 2829 def: Storexim_fi_pat<SS_<truncstorei8>, anyint, ToImmByte, S4_storeirb_io>; 2830 def: Storexim_fi_pat<SS_<truncstorei16>, anyint, ToImmHalf, S4_storeirh_io>; 2831 def: Storexim_fi_pat<SS_<store>, anyint, ToImmWord, S4_storeiri_io>; 2832 2833 def: Storexi_fi_pat<SS_<truncstorei8>, anyimm, S4_storeirb_io>; 2834 def: Storexi_fi_pat<SS_<truncstorei16>, anyimm, S4_storeirh_io>; 2835 def: Storexi_fi_pat<SS_<store>, anyimm, S4_storeiri_io>; 2836 2837 // For large-stack stores, generate store-register (prefer explicit Fi 2838 // in the address). 2839 def: Storexim_fi_pat<LS_<truncstorei8>, anyimm, ToI32, S2_storerb_io>; 2840 def: Storexim_fi_pat<LS_<truncstorei16>, anyimm, ToI32, S2_storerh_io>; 2841 def: Storexim_fi_pat<LS_<store>, anyimm, ToI32, S2_storeri_io>; 2842} 2843 2844// Fi+Imm, Fi, store-register 2845let AddedComplexity = 60 in { 2846 defm: Storexi_fi_add_pat<truncstorei8, I32, anyimm, S2_storerb_io>; 2847 defm: Storexi_fi_add_pat<truncstorei16, I32, anyimm, S2_storerh_io>; 2848 defm: Storexi_fi_add_pat<store, I32, anyimm, S2_storeri_io>; 2849 defm: Storexi_fi_add_pat<store, V4I8, anyimm, S2_storeri_io>; 2850 defm: Storexi_fi_add_pat<store, V2I16, anyimm, S2_storeri_io>; 2851 defm: Storexi_fi_add_pat<store, I64, anyimm, S2_storerd_io>; 2852 defm: Storexi_fi_add_pat<store, V8I8, anyimm, S2_storerd_io>; 2853 defm: Storexi_fi_add_pat<store, V4I16, anyimm, S2_storerd_io>; 2854 defm: Storexi_fi_add_pat<store, V2I32, anyimm, S2_storerd_io>; 2855 defm: Storexi_fi_add_pat<store, F32, anyimm, S2_storeri_io>; 2856 defm: Storexi_fi_add_pat<store, F64, anyimm, S2_storerd_io>; 2857 defm: Storexim_fi_add_pat<store, I1, anyimm, I1toI32, S2_storerb_io>; 2858 2859 def: Storexi_fi_pat<truncstorei8, I32, S2_storerb_io>; 2860 def: Storexi_fi_pat<truncstorei16, I32, S2_storerh_io>; 2861 def: Storexi_fi_pat<store, I32, S2_storeri_io>; 2862 def: Storexi_fi_pat<store, V4I8, S2_storeri_io>; 2863 def: Storexi_fi_pat<store, V2I16, S2_storeri_io>; 2864 def: Storexi_fi_pat<store, I64, S2_storerd_io>; 2865 def: Storexi_fi_pat<store, V8I8, S2_storerd_io>; 2866 def: Storexi_fi_pat<store, V4I16, S2_storerd_io>; 2867 def: Storexi_fi_pat<store, V2I32, S2_storerd_io>; 2868 def: Storexi_fi_pat<store, F32, S2_storeri_io>; 2869 def: Storexi_fi_pat<store, F64, S2_storerd_io>; 2870 def: Storexim_fi_pat<store, I1, I1toI32, S2_storerb_io>; 2871} 2872 2873 2874multiclass IMRA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2875 defm: Storexim_add_pat<S, V, O, M, I>; 2876} 2877multiclass IRA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2878 defm: Storexi_add_pat<S, V, O, I>; 2879} 2880 2881// Reg+Imm, store-immediate 2882let AddedComplexity = 50 in { 2883 defm: IMRA_<truncstorei8, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2884 defm: IMRA_<truncstorei16, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2885 defm: IMRA_<store, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2886 2887 defm: IRA_<truncstorei8, anyimm, u6_0ImmPred, S4_storeirb_io>; 2888 defm: IRA_<truncstorei16, anyimm, u6_1ImmPred, S4_storeirh_io>; 2889 defm: IRA_<store, anyimm, u6_2ImmPred, S4_storeiri_io>; 2890} 2891 2892// Reg+Imm, store-register 2893let AddedComplexity = 40 in { 2894 defm: Storexi_pat<truncstorei8, I32, anyimm0, S2_storerb_io>; 2895 defm: Storexi_pat<truncstorei16, I32, anyimm1, S2_storerh_io>; 2896 defm: Storexi_pat<store, I32, anyimm2, S2_storeri_io>; 2897 defm: Storexi_pat<store, V4I8, anyimm2, S2_storeri_io>; 2898 defm: Storexi_pat<store, V2I16, anyimm2, S2_storeri_io>; 2899 defm: Storexi_pat<store, I64, anyimm3, S2_storerd_io>; 2900 defm: Storexi_pat<store, V8I8, anyimm3, S2_storerd_io>; 2901 defm: Storexi_pat<store, V4I16, anyimm3, S2_storerd_io>; 2902 defm: Storexi_pat<store, V2I32, anyimm3, S2_storerd_io>; 2903 defm: Storexi_pat<store, F32, anyimm2, S2_storeri_io>; 2904 defm: Storexi_pat<store, F64, anyimm3, S2_storerd_io>; 2905 2906 defm: Storexim_pat<truncstorei8, I64, anyimm0, LoReg, S2_storerb_io>; 2907 defm: Storexim_pat<truncstorei16, I64, anyimm1, LoReg, S2_storerh_io>; 2908 defm: Storexim_pat<truncstorei32, I64, anyimm2, LoReg, S2_storeri_io>; 2909 defm: Storexim_pat<store, I1, anyimm0, I1toI32, S2_storerb_io>; 2910 2911 defm: Storexi_pat<atomic_store_8, I32, anyimm0, S2_storerb_io>; 2912 defm: Storexi_pat<atomic_store_16, I32, anyimm1, S2_storerh_io>; 2913 defm: Storexi_pat<atomic_store_32, I32, anyimm2, S2_storeri_io>; 2914 defm: Storexi_pat<atomic_store_32, V4I8, anyimm2, S2_storeri_io>; 2915 defm: Storexi_pat<atomic_store_32, V2I16, anyimm2, S2_storeri_io>; 2916 defm: Storexi_pat<atomic_store_64, I64, anyimm3, S2_storerd_io>; 2917 defm: Storexi_pat<atomic_store_64, V8I8, anyimm3, S2_storerd_io>; 2918 defm: Storexi_pat<atomic_store_64, V4I16, anyimm3, S2_storerd_io>; 2919 defm: Storexi_pat<atomic_store_64, V2I32, anyimm3, S2_storerd_io>; 2920} 2921 2922// Reg+Reg 2923let AddedComplexity = 30 in { 2924 def: Storexr_add_pat<truncstorei8, I32, S4_storerb_rr>; 2925 def: Storexr_add_pat<truncstorei16, I32, S4_storerh_rr>; 2926 def: Storexr_add_pat<store, I32, S4_storeri_rr>; 2927 def: Storexr_add_pat<store, V4I8, S4_storeri_rr>; 2928 def: Storexr_add_pat<store, V2I16, S4_storeri_rr>; 2929 def: Storexr_add_pat<store, I64, S4_storerd_rr>; 2930 def: Storexr_add_pat<store, V8I8, S4_storerd_rr>; 2931 def: Storexr_add_pat<store, V4I16, S4_storerd_rr>; 2932 def: Storexr_add_pat<store, V2I32, S4_storerd_rr>; 2933 def: Storexr_add_pat<store, F32, S4_storeri_rr>; 2934 def: Storexr_add_pat<store, F64, S4_storerd_rr>; 2935 2936 def: Pat<(store I1:$Pu, (add I32:$Rs, I32:$Rt)), 2937 (S4_storerb_rr IntRegs:$Rs, IntRegs:$Rt, 0, (I1toI32 I1:$Pu))>; 2938} 2939 2940// Reg, store-immediate 2941let AddedComplexity = 20 in { 2942 def: Storexim_base_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2943 def: Storexim_base_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2944 def: Storexim_base_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2945 2946 def: Storexi_base_pat<truncstorei8, anyimm, S4_storeirb_io>; 2947 def: Storexi_base_pat<truncstorei16, anyimm, S4_storeirh_io>; 2948 def: Storexi_base_pat<store, anyimm, S4_storeiri_io>; 2949} 2950 2951// Reg, store-register 2952let AddedComplexity = 10 in { 2953 def: Storexi_base_pat<truncstorei8, I32, S2_storerb_io>; 2954 def: Storexi_base_pat<truncstorei16, I32, S2_storerh_io>; 2955 def: Storexi_base_pat<store, I32, S2_storeri_io>; 2956 def: Storexi_base_pat<store, V4I8, S2_storeri_io>; 2957 def: Storexi_base_pat<store, V2I16, S2_storeri_io>; 2958 def: Storexi_base_pat<store, I64, S2_storerd_io>; 2959 def: Storexi_base_pat<store, V8I8, S2_storerd_io>; 2960 def: Storexi_base_pat<store, V4I16, S2_storerd_io>; 2961 def: Storexi_base_pat<store, V2I32, S2_storerd_io>; 2962 def: Storexi_base_pat<store, F32, S2_storeri_io>; 2963 def: Storexi_base_pat<store, F64, S2_storerd_io>; 2964 2965 def: Storexim_base_pat<truncstorei8, I64, LoReg, S2_storerb_io>; 2966 def: Storexim_base_pat<truncstorei16, I64, LoReg, S2_storerh_io>; 2967 def: Storexim_base_pat<truncstorei32, I64, LoReg, S2_storeri_io>; 2968 def: Storexim_base_pat<store, I1, I1toI32, S2_storerb_io>; 2969 2970 def: Storexi_base_pat<atomic_store_8, I32, S2_storerb_io>; 2971 def: Storexi_base_pat<atomic_store_16, I32, S2_storerh_io>; 2972 def: Storexi_base_pat<atomic_store_32, I32, S2_storeri_io>; 2973 def: Storexi_base_pat<atomic_store_32, V4I8, S2_storeri_io>; 2974 def: Storexi_base_pat<atomic_store_32, V2I16, S2_storeri_io>; 2975 def: Storexi_base_pat<atomic_store_64, I64, S2_storerd_io>; 2976 def: Storexi_base_pat<atomic_store_64, V8I8, S2_storerd_io>; 2977 def: Storexi_base_pat<atomic_store_64, V4I16, S2_storerd_io>; 2978 def: Storexi_base_pat<atomic_store_64, V2I32, S2_storerd_io>; 2979} 2980 2981 2982// --(14) Memop ---------------------------------------------------------- 2983// 2984 2985def m5_0Imm8Pred : PatLeaf<(i32 imm), [{ 2986 int8_t V = N->getSExtValue(); 2987 return -32 < V && V <= -1; 2988}]>; 2989 2990def m5_0Imm16Pred : PatLeaf<(i32 imm), [{ 2991 int16_t V = N->getSExtValue(); 2992 return -32 < V && V <= -1; 2993}]>; 2994 2995def m5_0ImmPred : PatLeaf<(i32 imm), [{ 2996 int64_t V = N->getSExtValue(); 2997 return -31 <= V && V <= -1; 2998}]>; 2999 3000def IsNPow2_8 : PatLeaf<(i32 imm), [{ 3001 uint8_t NV = ~N->getZExtValue(); 3002 return isPowerOf2_32(NV); 3003}]>; 3004 3005def IsNPow2_16 : PatLeaf<(i32 imm), [{ 3006 uint16_t NV = ~N->getZExtValue(); 3007 return isPowerOf2_32(NV); 3008}]>; 3009 3010def Log2_8 : SDNodeXForm<imm, [{ 3011 uint8_t V = N->getZExtValue(); 3012 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 3013}]>; 3014 3015def Log2_16 : SDNodeXForm<imm, [{ 3016 uint16_t V = N->getZExtValue(); 3017 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 3018}]>; 3019 3020def LogN2_8 : SDNodeXForm<imm, [{ 3021 uint8_t NV = ~N->getZExtValue(); 3022 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 3023}]>; 3024 3025def LogN2_16 : SDNodeXForm<imm, [{ 3026 uint16_t NV = ~N->getZExtValue(); 3027 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 3028}]>; 3029 3030def IdImm : SDNodeXForm<imm, [{ return SDValue(N, 0); }]>; 3031 3032multiclass Memopxr_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 3033 InstHexagon MI> { 3034 // Addr: i32 3035 def: Pat<(Store (Oper (Load I32:$Rs), I32:$A), I32:$Rs), 3036 (MI I32:$Rs, 0, I32:$A)>; 3037 // Addr: fi 3038 def: Pat<(Store (Oper (Load AddrFI:$Rs), I32:$A), AddrFI:$Rs), 3039 (MI AddrFI:$Rs, 0, I32:$A)>; 3040} 3041 3042multiclass Memopxr_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3043 SDNode Oper, InstHexagon MI> { 3044 // Addr: i32 3045 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), I32:$A), 3046 (add I32:$Rs, ImmPred:$Off)), 3047 (MI I32:$Rs, imm:$Off, I32:$A)>; 3048 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), I32:$A), 3049 (IsOrAdd I32:$Rs, ImmPred:$Off)), 3050 (MI I32:$Rs, imm:$Off, I32:$A)>; 3051 // Addr: fi 3052 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), I32:$A), 3053 (add AddrFI:$Rs, ImmPred:$Off)), 3054 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 3055 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), I32:$A), 3056 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 3057 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 3058} 3059 3060multiclass Memopxr_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3061 SDNode Oper, InstHexagon MI> { 3062 let Predicates = [UseMEMOPS] in { 3063 defm: Memopxr_base_pat <Load, Store, Oper, MI>; 3064 defm: Memopxr_add_pat <Load, Store, ImmPred, Oper, MI>; 3065 } 3066} 3067 3068let AddedComplexity = 200 in { 3069 // add reg 3070 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, add, 3071 /*anyext*/ L4_add_memopb_io>; 3072 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, 3073 /*sext*/ L4_add_memopb_io>; 3074 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, 3075 /*zext*/ L4_add_memopb_io>; 3076 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, add, 3077 /*anyext*/ L4_add_memoph_io>; 3078 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, 3079 /*sext*/ L4_add_memoph_io>; 3080 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, 3081 /*zext*/ L4_add_memoph_io>; 3082 defm: Memopxr_pat<load, store, u6_2ImmPred, add, L4_add_memopw_io>; 3083 3084 // sub reg 3085 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, 3086 /*anyext*/ L4_sub_memopb_io>; 3087 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, 3088 /*sext*/ L4_sub_memopb_io>; 3089 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, 3090 /*zext*/ L4_sub_memopb_io>; 3091 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, 3092 /*anyext*/ L4_sub_memoph_io>; 3093 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, 3094 /*sext*/ L4_sub_memoph_io>; 3095 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, 3096 /*zext*/ L4_sub_memoph_io>; 3097 defm: Memopxr_pat<load, store, u6_2ImmPred, sub, L4_sub_memopw_io>; 3098 3099 // and reg 3100 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, and, 3101 /*anyext*/ L4_and_memopb_io>; 3102 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, 3103 /*sext*/ L4_and_memopb_io>; 3104 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, 3105 /*zext*/ L4_and_memopb_io>; 3106 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, and, 3107 /*anyext*/ L4_and_memoph_io>; 3108 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, 3109 /*sext*/ L4_and_memoph_io>; 3110 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, 3111 /*zext*/ L4_and_memoph_io>; 3112 defm: Memopxr_pat<load, store, u6_2ImmPred, and, L4_and_memopw_io>; 3113 3114 // or reg 3115 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, or, 3116 /*anyext*/ L4_or_memopb_io>; 3117 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, 3118 /*sext*/ L4_or_memopb_io>; 3119 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, 3120 /*zext*/ L4_or_memopb_io>; 3121 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, or, 3122 /*anyext*/ L4_or_memoph_io>; 3123 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, 3124 /*sext*/ L4_or_memoph_io>; 3125 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, 3126 /*zext*/ L4_or_memoph_io>; 3127 defm: Memopxr_pat<load, store, u6_2ImmPred, or, L4_or_memopw_io>; 3128} 3129 3130 3131multiclass Memopxi_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 3132 PatFrag Arg, SDNodeXForm ArgMod, InstHexagon MI> { 3133 // Addr: i32 3134 def: Pat<(Store (Oper (Load I32:$Rs), Arg:$A), I32:$Rs), 3135 (MI I32:$Rs, 0, (ArgMod Arg:$A))>; 3136 // Addr: fi 3137 def: Pat<(Store (Oper (Load AddrFI:$Rs), Arg:$A), AddrFI:$Rs), 3138 (MI AddrFI:$Rs, 0, (ArgMod Arg:$A))>; 3139} 3140 3141multiclass Memopxi_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3142 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 3143 InstHexagon MI> { 3144 // Addr: i32 3145 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), Arg:$A), 3146 (add I32:$Rs, ImmPred:$Off)), 3147 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3148 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), Arg:$A), 3149 (IsOrAdd I32:$Rs, ImmPred:$Off)), 3150 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3151 // Addr: fi 3152 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 3153 (add AddrFI:$Rs, ImmPred:$Off)), 3154 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3155 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 3156 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 3157 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3158} 3159 3160multiclass Memopxi_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3161 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 3162 InstHexagon MI> { 3163 let Predicates = [UseMEMOPS] in { 3164 defm: Memopxi_base_pat <Load, Store, Oper, Arg, ArgMod, MI>; 3165 defm: Memopxi_add_pat <Load, Store, ImmPred, Oper, Arg, ArgMod, MI>; 3166 } 3167} 3168 3169let AddedComplexity = 220 in { 3170 // add imm 3171 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 3172 /*anyext*/ IdImm, L4_iadd_memopb_io>; 3173 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 3174 /*sext*/ IdImm, L4_iadd_memopb_io>; 3175 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 3176 /*zext*/ IdImm, L4_iadd_memopb_io>; 3177 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3178 /*anyext*/ IdImm, L4_iadd_memoph_io>; 3179 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3180 /*sext*/ IdImm, L4_iadd_memoph_io>; 3181 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3182 /*zext*/ IdImm, L4_iadd_memoph_io>; 3183 defm: Memopxi_pat<load, store, u6_2ImmPred, add, u5_0ImmPred, IdImm, 3184 L4_iadd_memopw_io>; 3185 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3186 /*anyext*/ NegImm8, L4_iadd_memopb_io>; 3187 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3188 /*sext*/ NegImm8, L4_iadd_memopb_io>; 3189 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3190 /*zext*/ NegImm8, L4_iadd_memopb_io>; 3191 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3192 /*anyext*/ NegImm16, L4_iadd_memoph_io>; 3193 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3194 /*sext*/ NegImm16, L4_iadd_memoph_io>; 3195 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3196 /*zext*/ NegImm16, L4_iadd_memoph_io>; 3197 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, m5_0ImmPred, NegImm32, 3198 L4_iadd_memopw_io>; 3199 3200 // sub imm 3201 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3202 /*anyext*/ IdImm, L4_isub_memopb_io>; 3203 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3204 /*sext*/ IdImm, L4_isub_memopb_io>; 3205 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3206 /*zext*/ IdImm, L4_isub_memopb_io>; 3207 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3208 /*anyext*/ IdImm, L4_isub_memoph_io>; 3209 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3210 /*sext*/ IdImm, L4_isub_memoph_io>; 3211 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3212 /*zext*/ IdImm, L4_isub_memoph_io>; 3213 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, u5_0ImmPred, IdImm, 3214 L4_isub_memopw_io>; 3215 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3216 /*anyext*/ NegImm8, L4_isub_memopb_io>; 3217 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3218 /*sext*/ NegImm8, L4_isub_memopb_io>; 3219 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3220 /*zext*/ NegImm8, L4_isub_memopb_io>; 3221 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3222 /*anyext*/ NegImm16, L4_isub_memoph_io>; 3223 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3224 /*sext*/ NegImm16, L4_isub_memoph_io>; 3225 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3226 /*zext*/ NegImm16, L4_isub_memoph_io>; 3227 defm: Memopxi_pat<load, store, u6_2ImmPred, add, m5_0ImmPred, NegImm32, 3228 L4_isub_memopw_io>; 3229 3230 // clrbit imm 3231 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3232 /*anyext*/ LogN2_8, L4_iand_memopb_io>; 3233 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3234 /*sext*/ LogN2_8, L4_iand_memopb_io>; 3235 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3236 /*zext*/ LogN2_8, L4_iand_memopb_io>; 3237 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3238 /*anyext*/ LogN2_16, L4_iand_memoph_io>; 3239 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3240 /*sext*/ LogN2_16, L4_iand_memoph_io>; 3241 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3242 /*zext*/ LogN2_16, L4_iand_memoph_io>; 3243 defm: Memopxi_pat<load, store, u6_2ImmPred, and, IsNPow2_32, 3244 LogN2_32, L4_iand_memopw_io>; 3245 3246 // setbit imm 3247 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3248 /*anyext*/ Log2_8, L4_ior_memopb_io>; 3249 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3250 /*sext*/ Log2_8, L4_ior_memopb_io>; 3251 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3252 /*zext*/ Log2_8, L4_ior_memopb_io>; 3253 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3254 /*anyext*/ Log2_16, L4_ior_memoph_io>; 3255 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3256 /*sext*/ Log2_16, L4_ior_memoph_io>; 3257 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3258 /*zext*/ Log2_16, L4_ior_memoph_io>; 3259 defm: Memopxi_pat<load, store, u6_2ImmPred, or, IsPow2_32, 3260 Log2_32, L4_ior_memopw_io>; 3261} 3262 3263 3264// --(15) Call ----------------------------------------------------------- 3265// 3266 3267// Pseudo instructions. 3268def SDT_SPCallSeqStart 3269 : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3270def SDT_SPCallSeqEnd 3271 : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3272 3273def callseq_start: SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 3274 [SDNPHasChain, SDNPOutGlue]>; 3275def callseq_end: SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 3276 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 3277 3278def SDT_SPCall: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 3279 3280def HexagonTCRet: SDNode<"HexagonISD::TC_RETURN", SDT_SPCall, 3281 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 3282def callv3: SDNode<"HexagonISD::CALL", SDT_SPCall, 3283 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 3284def callv3nr: SDNode<"HexagonISD::CALLnr", SDT_SPCall, 3285 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 3286 3287def: Pat<(callseq_start timm:$amt, timm:$amt2), 3288 (ADJCALLSTACKDOWN imm:$amt, imm:$amt2)>; 3289def: Pat<(callseq_end timm:$amt1, timm:$amt2), 3290 (ADJCALLSTACKUP imm:$amt1, imm:$amt2)>; 3291 3292def: Pat<(HexagonTCRet tglobaladdr:$dst), (PS_tailcall_i tglobaladdr:$dst)>; 3293def: Pat<(HexagonTCRet texternalsym:$dst), (PS_tailcall_i texternalsym:$dst)>; 3294def: Pat<(HexagonTCRet I32:$dst), (PS_tailcall_r I32:$dst)>; 3295 3296def: Pat<(callv3 I32:$dst), (J2_callr I32:$dst)>; 3297def: Pat<(callv3 tglobaladdr:$dst), (J2_call tglobaladdr:$dst)>; 3298def: Pat<(callv3 texternalsym:$dst), (J2_call texternalsym:$dst)>; 3299def: Pat<(callv3 tglobaltlsaddr:$dst), (J2_call tglobaltlsaddr:$dst)>; 3300 3301def: Pat<(callv3nr I32:$dst), (PS_callr_nr I32:$dst)>; 3302def: Pat<(callv3nr tglobaladdr:$dst), (PS_call_nr tglobaladdr:$dst)>; 3303def: Pat<(callv3nr texternalsym:$dst), (PS_call_nr texternalsym:$dst)>; 3304 3305def retglue : SDNode<"HexagonISD::RET_GLUE", SDTNone, 3306 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 3307def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>; 3308 3309def: Pat<(retglue), (PS_jmpret (i32 R31))>; 3310def: Pat<(eh_return), (EH_RETURN_JMPR (i32 R31))>; 3311 3312 3313// --(16) Branch --------------------------------------------------------- 3314// 3315 3316def: Pat<(br bb:$dst), (J2_jump b30_2Imm:$dst)>; 3317def: Pat<(brind I32:$dst), (J2_jumpr I32:$dst)>; 3318 3319def: Pat<(brcond I1:$Pu, bb:$dst), 3320 (J2_jumpt I1:$Pu, bb:$dst)>; 3321def: Pat<(brcond (not I1:$Pu), bb:$dst), 3322 (J2_jumpf I1:$Pu, bb:$dst)>; 3323def: Pat<(brcond (i1 (setne I1:$Pu, -1)), bb:$dst), 3324 (J2_jumpf I1:$Pu, bb:$dst)>; 3325def: Pat<(brcond (i1 (seteq I1:$Pu, 0)), bb:$dst), 3326 (J2_jumpf I1:$Pu, bb:$dst)>; 3327def: Pat<(brcond (i1 (setne I1:$Pu, 0)), bb:$dst), 3328 (J2_jumpt I1:$Pu, bb:$dst)>; 3329 3330 3331// --(17) Misc ----------------------------------------------------------- 3332 3333 3334// Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)' 3335// for C code of the form r = (c>='0' && c<='9') ? 1 : 0. 3336// The isdigit transformation relies on two 'clever' aspects: 3337// 1) The data type is unsigned which allows us to eliminate a zero test after 3338// biasing the expression by 48. We are depending on the representation of 3339// the unsigned types, and semantics. 3340// 2) The front end has converted <= 9 into < 10 on entry to LLVM. 3341// 3342// For the C code: 3343// retval = (c >= '0' && c <= '9') ? 1 : 0; 3344// The code is transformed upstream of llvm into 3345// retval = (c-48) < 10 ? 1 : 0; 3346 3347def u7_0PosImmPred : ImmLeaf<i32, [{ 3348 // True if the immediate fits in an 7-bit unsigned field and is positive. 3349 return Imm > 0 && isUInt<7>(Imm); 3350}]>; 3351 3352let AddedComplexity = 139 in 3353def: Pat<(i32 (zext (i1 (setult (and I32:$Rs, 255), u7_0PosImmPred:$u7)))), 3354 (C2_muxii (A4_cmpbgtui IntRegs:$Rs, (UDEC1 imm:$u7)), 0, 1)>; 3355 3356let AddedComplexity = 100 in 3357def: Pat<(or (or (shl (HexagonINSERT (i32 (zextloadi8 (add I32:$b, 2))), 3358 (i32 (extloadi8 (add I32:$b, 3))), 3359 24, 8), 3360 (i32 16)), 3361 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))), 3362 (zextloadi8 I32:$b)), 3363 (A2_swiz (L2_loadri_io I32:$b, 0))>; 3364 3365 3366// We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH 3367// because the SDNode ISD::PREFETCH has properties MayLoad and MayStore. 3368// We don't really want either one here. 3369def SDTHexagonDCFETCH: SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>; 3370def HexagonDCFETCH: SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH, 3371 [SDNPHasChain]>; 3372 3373def: Pat<(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3), 3374 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3375def: Pat<(HexagonDCFETCH (i32 (add IntRegs:$Rs, u11_3ImmPred:$u11_3)), (i32 0)), 3376 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3377 3378def SDTHexagonALLOCA 3379 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3380def HexagonALLOCA 3381 : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA, [SDNPHasChain]>; 3382 3383def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)), 3384 (PS_alloca IntRegs:$Rs, imm:$A)>; 3385 3386def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>; 3387def: Pat<(HexagonBARRIER), (Y2_barrier)>; 3388 3389def: Pat<(trap), (PS_crash)>; 3390def: Pat<(debugtrap), (Y2_break)>; 3391 3392// Read cycle counter. 3393def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; 3394def HexagonREADCYCLE: SDNode<"HexagonISD::READCYCLE", SDTInt64Leaf, 3395 [SDNPHasChain]>; 3396 3397def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>; 3398 3399// Read time counter. 3400def HexagonREADTIMER: SDNode<"HexagonISD::READTIMER", SDTInt64Leaf, 3401 [SDNPHasChain]>; 3402 3403def: Pat<(HexagonREADTIMER), (A4_tfrcpp UTIMER)>; 3404 3405// The declared return value of the store-locked intrinsics is i32, but 3406// the instructions actually define i1. To avoid register copies from 3407// IntRegs to PredRegs and back, fold the entire pattern checking the 3408// result against true/false. 3409let AddedComplexity = 100 in { 3410 def: Pat<(i1 (setne (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3411 (S2_storew_locked I32:$Rs, I32:$Rt)>; 3412 def: Pat<(i1 (seteq (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3413 (C2_not (S2_storew_locked I32:$Rs, I32:$Rt))>; 3414 def: Pat<(i1 (setne (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3415 (S4_stored_locked I32:$Rs, I64:$Rt)>; 3416 def: Pat<(i1 (seteq (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3417 (C2_not (S4_stored_locked I32:$Rs, I64:$Rt))>; 3418} 3419 3420def: Pat<(int_hexagon_instrprof_custom (HexagonAtPcrel tglobaladdr:$addr), u32_0ImmPred:$I), 3421 (PS_call_instrprof_custom tglobaladdr:$addr, imm:$I)>; 3422 3423def: Pat<(int_hexagon_instrprof_custom (HexagonCONST32 tglobaladdr:$addr), u32_0ImmPred:$I), 3424 (PS_call_instrprof_custom tglobaladdr:$addr, imm:$I)>; 3425