xref: /llvm-project/llvm/lib/Target/ARM/ARMTargetMachine.cpp (revision bb3f5e1fed7c6ba733b7f273e93f5d3930976185) 
1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "ARMTargetMachine.h"
13 #include "ARM.h"
14 #include "ARMLatencyMutations.h"
15 #include "ARMMachineFunctionInfo.h"
16 #include "ARMMacroFusion.h"
17 #include "ARMSubtarget.h"
18 #include "ARMTargetObjectFile.h"
19 #include "ARMTargetTransformInfo.h"
20 #include "MCTargetDesc/ARMMCTargetDesc.h"
21 #include "TargetInfo/ARMTargetInfo.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/CodeGen/ExecutionDomainFix.h"
25 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
26 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
30 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
31 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
32 #include "llvm/CodeGen/MIRParser/MIParser.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineScheduler.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/CodeGen/TargetPassConfig.h"
37 #include "llvm/IR/Attributes.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/MC/TargetRegistry.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Target/TargetLoweringObjectFile.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/TargetParser/ARMTargetParser.h"
48 #include "llvm/TargetParser/TargetParser.h"
49 #include "llvm/TargetParser/Triple.h"
50 #include "llvm/Transforms/CFGuard.h"
51 #include "llvm/Transforms/IPO.h"
52 #include "llvm/Transforms/Scalar.h"
53 #include <cassert>
54 #include <memory>
55 #include <optional>
56 #include <string>
57 
58 using namespace llvm;
59 
60 static cl::opt<bool>
61 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
62                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
63                    cl::init(false));
64 
65 static cl::opt<bool>
66 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
67                  cl::desc("Run SimplifyCFG after expanding atomic operations"
68                           " to make use of cmpxchg flow-based information"),
69                  cl::init(true));
70 
71 static cl::opt<bool>
72 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
73                       cl::desc("Enable ARM load/store optimization pass"),
74                       cl::init(true));
75 
76 // FIXME: Unify control over GlobalMerge.
77 static cl::opt<cl::boolOrDefault>
78 EnableGlobalMerge("arm-global-merge", cl::Hidden,
79                   cl::desc("Enable the global merge pass"));
80 
81 namespace llvm {
82   void initializeARMExecutionDomainFixPass(PassRegistry&);
83 }
84 
85 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() {
86   // Register the target.
87   RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
88   RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
89   RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
90   RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
91 
92   PassRegistry &Registry = *PassRegistry::getPassRegistry();
93   initializeGlobalISel(Registry);
94   initializeARMLoadStoreOptPass(Registry);
95   initializeARMPreAllocLoadStoreOptPass(Registry);
96   initializeARMParallelDSPPass(Registry);
97   initializeARMBranchTargetsPass(Registry);
98   initializeARMConstantIslandsPass(Registry);
99   initializeARMExecutionDomainFixPass(Registry);
100   initializeARMExpandPseudoPass(Registry);
101   initializeThumb2SizeReducePass(Registry);
102   initializeMVEVPTBlockPass(Registry);
103   initializeMVETPAndVPTOptimisationsPass(Registry);
104   initializeMVETailPredicationPass(Registry);
105   initializeARMLowOverheadLoopsPass(Registry);
106   initializeARMBlockPlacementPass(Registry);
107   initializeMVEGatherScatterLoweringPass(Registry);
108   initializeARMSLSHardeningPass(Registry);
109   initializeMVELaneInterleavingPass(Registry);
110   initializeARMFixCortexA57AES1742098Pass(Registry);
111   initializeARMDAGToDAGISelLegacyPass(Registry);
112 }
113 
114 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
115   if (TT.isOSBinFormatMachO())
116     return std::make_unique<TargetLoweringObjectFileMachO>();
117   if (TT.isOSWindows())
118     return std::make_unique<TargetLoweringObjectFileCOFF>();
119   return std::make_unique<ARMElfTargetObjectFile>();
120 }
121 
122 static ARMBaseTargetMachine::ARMABI
123 computeTargetABI(const Triple &TT, StringRef CPU,
124                  const TargetOptions &Options) {
125   StringRef ABIName = Options.MCOptions.getABIName();
126 
127   if (ABIName.empty())
128     ABIName = ARM::computeDefaultTargetABI(TT, CPU);
129 
130   if (ABIName == "aapcs16")
131     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
132   else if (ABIName.starts_with("aapcs"))
133     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
134   else if (ABIName.starts_with("apcs"))
135     return ARMBaseTargetMachine::ARM_ABI_APCS;
136 
137   llvm_unreachable("Unhandled/unknown ABI Name!");
138   return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
139 }
140 
141 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
142                                      const TargetOptions &Options,
143                                      bool isLittle) {
144   auto ABI = computeTargetABI(TT, CPU, Options);
145   std::string Ret;
146 
147   if (isLittle)
148     // Little endian.
149     Ret += "e";
150   else
151     // Big endian.
152     Ret += "E";
153 
154   Ret += DataLayout::getManglingComponent(TT);
155 
156   // Pointers are 32 bits and aligned to 32 bits.
157   Ret += "-p:32:32";
158 
159   // Function pointers are aligned to 8 bits (because the LSB stores the
160   // ARM/Thumb state).
161   Ret += "-Fi8";
162 
163   // ABIs other than APCS have 64 bit integers with natural alignment.
164   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
165     Ret += "-i64:64";
166 
167   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
168   // bits, others to 64 bits. We always try to align to 64 bits.
169   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
170     Ret += "-f64:32:64";
171 
172   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
173   // to 64. We always ty to give them natural alignment.
174   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
175     Ret += "-v64:32:64-v128:32:128";
176   else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
177     Ret += "-v128:64:128";
178 
179   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
180   // particular hardware support on 32-bit ARM).
181   Ret += "-a:0:32";
182 
183   // Integer registers are 32 bits.
184   Ret += "-n32";
185 
186   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
187   // aligned everywhere else.
188   if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
189     Ret += "-S128";
190   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
191     Ret += "-S64";
192   else
193     Ret += "-S32";
194 
195   return Ret;
196 }
197 
198 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
199                                            std::optional<Reloc::Model> RM) {
200   if (!RM)
201     // Default relocation model on Darwin is PIC.
202     return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
203 
204   if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
205     assert(TT.isOSBinFormatELF() &&
206            "ROPI/RWPI currently only supported for ELF");
207 
208   // DynamicNoPIC is only used on darwin.
209   if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
210     return Reloc::Static;
211 
212   return *RM;
213 }
214 
215 /// Create an ARM architecture model.
216 ///
217 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
218                                            StringRef CPU, StringRef FS,
219                                            const TargetOptions &Options,
220                                            std::optional<Reloc::Model> RM,
221                                            std::optional<CodeModel::Model> CM,
222                                            CodeGenOptLevel OL, bool isLittle)
223     : CodeGenTargetMachineImpl(T, computeDataLayout(TT, CPU, Options, isLittle),
224                                TT, CPU, FS, Options,
225                                getEffectiveRelocModel(TT, RM),
226                                getEffectiveCodeModel(CM, CodeModel::Small), OL),
227       TargetABI(computeTargetABI(TT, CPU, Options)),
228       TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
229 
230   // Default to triple-appropriate float ABI
231   if (Options.FloatABIType == FloatABI::Default) {
232     if (isTargetHardFloat())
233       this->Options.FloatABIType = FloatABI::Hard;
234     else
235       this->Options.FloatABIType = FloatABI::Soft;
236   }
237 
238   // Default to triple-appropriate EABI
239   if (Options.EABIVersion == EABI::Default ||
240       Options.EABIVersion == EABI::Unknown) {
241     // musl is compatible with glibc with regard to EABI version
242     if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
243          TargetTriple.getEnvironment() == Triple::GNUEABIT64 ||
244          TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
245          TargetTriple.getEnvironment() == Triple::GNUEABIHFT64 ||
246          TargetTriple.getEnvironment() == Triple::MuslEABI ||
247          TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
248          TargetTriple.getEnvironment() == Triple::OpenHOS) &&
249         !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
250       this->Options.EABIVersion = EABI::GNU;
251     else
252       this->Options.EABIVersion = EABI::EABI5;
253   }
254 
255   if (TT.isOSBinFormatMachO()) {
256     this->Options.TrapUnreachable = true;
257     this->Options.NoTrapAfterNoreturn = true;
258   }
259 
260   // ARM supports the debug entry values.
261   setSupportsDebugEntryValues(true);
262 
263   initAsmInfo();
264 
265   // ARM supports the MachineOutliner.
266   setMachineOutliner(true);
267   setSupportsDefaultOutlining(true);
268 }
269 
270 ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
271 
272 MachineFunctionInfo *ARMBaseTargetMachine::createMachineFunctionInfo(
273     BumpPtrAllocator &Allocator, const Function &F,
274     const TargetSubtargetInfo *STI) const {
275   return ARMFunctionInfo::create<ARMFunctionInfo>(
276       Allocator, F, static_cast<const ARMSubtarget *>(STI));
277 }
278 
279 const ARMSubtarget *
280 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
281   Attribute CPUAttr = F.getFnAttribute("target-cpu");
282   Attribute FSAttr = F.getFnAttribute("target-features");
283 
284   std::string CPU =
285       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
286   std::string FS =
287       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
288 
289   // FIXME: This is related to the code below to reset the target options,
290   // we need to know whether or not the soft float flag is set on the
291   // function before we can generate a subtarget. We also need to use
292   // it as a key for the subtarget since that can be the only difference
293   // between two functions.
294   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
295   // If the soft float attribute is set on the function turn on the soft float
296   // subtarget feature.
297   if (SoftFloat)
298     FS += FS.empty() ? "+soft-float" : ",+soft-float";
299 
300   // Use the optminsize to identify the subtarget, but don't use it in the
301   // feature string.
302   std::string Key = CPU + FS;
303   if (F.hasMinSize())
304     Key += "+minsize";
305 
306   auto &I = SubtargetMap[Key];
307   if (!I) {
308     // This needs to be done before we create a new subtarget since any
309     // creation will depend on the TM and the code generation flags on the
310     // function that reside in TargetOptions.
311     resetTargetOptions(F);
312     I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
313                                         F.hasMinSize());
314 
315     if (!I->isThumb() && !I->hasARMOps())
316       F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
317           "instructions, but the target does not support ARM mode execution.");
318   }
319 
320   return I.get();
321 }
322 
323 TargetTransformInfo
324 ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) const {
325   return TargetTransformInfo(ARMTTIImpl(this, F));
326 }
327 
328 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
329                                        StringRef CPU, StringRef FS,
330                                        const TargetOptions &Options,
331                                        std::optional<Reloc::Model> RM,
332                                        std::optional<CodeModel::Model> CM,
333                                        CodeGenOptLevel OL, bool JIT)
334     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
335 
336 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
337                                        StringRef CPU, StringRef FS,
338                                        const TargetOptions &Options,
339                                        std::optional<Reloc::Model> RM,
340                                        std::optional<CodeModel::Model> CM,
341                                        CodeGenOptLevel OL, bool JIT)
342     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
343 
344 namespace {
345 
346 /// ARM Code Generator Pass Configuration Options.
347 class ARMPassConfig : public TargetPassConfig {
348 public:
349   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
350       : TargetPassConfig(TM, PM) {}
351 
352   ARMBaseTargetMachine &getARMTargetMachine() const {
353     return getTM<ARMBaseTargetMachine>();
354   }
355 
356   ScheduleDAGInstrs *
357   createMachineScheduler(MachineSchedContext *C) const override {
358     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
359     // add DAG Mutations here.
360     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
361     if (ST.hasFusion())
362       DAG->addMutation(createARMMacroFusionDAGMutation());
363     return DAG;
364   }
365 
366   ScheduleDAGInstrs *
367   createPostMachineScheduler(MachineSchedContext *C) const override {
368     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
369     // add DAG Mutations here.
370     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
371     if (ST.hasFusion())
372       DAG->addMutation(createARMMacroFusionDAGMutation());
373     if (auto Mutation = createARMLatencyMutations(ST, C->AA))
374       DAG->addMutation(std::move(Mutation));
375     return DAG;
376   }
377 
378   void addIRPasses() override;
379   void addCodeGenPrepare() override;
380   bool addPreISel() override;
381   bool addInstSelector() override;
382   bool addIRTranslator() override;
383   bool addLegalizeMachineIR() override;
384   bool addRegBankSelect() override;
385   bool addGlobalInstructionSelect() override;
386   void addPreRegAlloc() override;
387   void addPreSched2() override;
388   void addPreEmitPass() override;
389   void addPreEmitPass2() override;
390 
391   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
392 };
393 
394 class ARMExecutionDomainFix : public ExecutionDomainFix {
395 public:
396   static char ID;
397   ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
398   StringRef getPassName() const override {
399     return "ARM Execution Domain Fix";
400   }
401 };
402 char ARMExecutionDomainFix::ID;
403 
404 } // end anonymous namespace
405 
406 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
407   "ARM Execution Domain Fix", false, false)
408 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
409 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
410   "ARM Execution Domain Fix", false, false)
411 
412 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
413   return new ARMPassConfig(*this, PM);
414 }
415 
416 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
417   return getStandardCSEConfigForOpt(TM->getOptLevel());
418 }
419 
420 void ARMPassConfig::addIRPasses() {
421   if (TM->Options.ThreadModel == ThreadModel::Single)
422     addPass(createLowerAtomicPass());
423   else
424     addPass(createAtomicExpandLegacyPass());
425 
426   // Cmpxchg instructions are often used with a subsequent comparison to
427   // determine whether it succeeded. We can exploit existing control-flow in
428   // ldrex/strex loops to simplify this, but it needs tidying up.
429   if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAtomicTidy)
430     addPass(createCFGSimplificationPass(
431         SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
432         [this](const Function &F) {
433           const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
434           return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
435         }));
436 
437   addPass(createMVEGatherScatterLoweringPass());
438   addPass(createMVELaneInterleavingPass());
439 
440   TargetPassConfig::addIRPasses();
441 
442   // Run the parallel DSP pass.
443   if (getOptLevel() == CodeGenOptLevel::Aggressive)
444     addPass(createARMParallelDSPPass());
445 
446   // Match complex arithmetic patterns
447   if (TM->getOptLevel() >= CodeGenOptLevel::Default)
448     addPass(createComplexDeinterleavingPass(TM));
449 
450   // Match interleaved memory accesses to ldN/stN intrinsics.
451   if (TM->getOptLevel() != CodeGenOptLevel::None)
452     addPass(createInterleavedAccessPass());
453 
454   // Add Control Flow Guard checks.
455   if (TM->getTargetTriple().isOSWindows())
456     addPass(createCFGuardCheckPass());
457 
458   if (TM->Options.JMCInstrument)
459     addPass(createJMCInstrumenterPass());
460 }
461 
462 void ARMPassConfig::addCodeGenPrepare() {
463   if (getOptLevel() != CodeGenOptLevel::None)
464     addPass(createTypePromotionLegacyPass());
465   TargetPassConfig::addCodeGenPrepare();
466 }
467 
468 bool ARMPassConfig::addPreISel() {
469   if ((TM->getOptLevel() != CodeGenOptLevel::None &&
470        EnableGlobalMerge == cl::BOU_UNSET) ||
471       EnableGlobalMerge == cl::BOU_TRUE) {
472     // FIXME: This is using the thumb1 only constant value for
473     // maximal global offset for merging globals. We may want
474     // to look into using the old value for non-thumb1 code of
475     // 4095 based on the TargetMachine, but this starts to become
476     // tricky when doing code gen per function.
477     bool OnlyOptimizeForSize =
478         (TM->getOptLevel() < CodeGenOptLevel::Aggressive) &&
479         (EnableGlobalMerge == cl::BOU_UNSET);
480     // Merging of extern globals is enabled by default on non-Mach-O as we
481     // expect it to be generally either beneficial or harmless. On Mach-O it
482     // is disabled as we emit the .subsections_via_symbols directive which
483     // means that merging extern globals is not safe.
484     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
485     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
486                                   MergeExternalByDefault));
487   }
488 
489   if (TM->getOptLevel() != CodeGenOptLevel::None) {
490     addPass(createHardwareLoopsLegacyPass());
491     addPass(createMVETailPredicationPass());
492     // FIXME: IR passes can delete address-taken basic blocks, deleting
493     // corresponding blockaddresses. ARMConstantPoolConstant holds references to
494     // address-taken basic blocks which can be invalidated if the function
495     // containing the blockaddress has already been codegen'd and the basic
496     // block is removed. Work around this by forcing all IR passes to run before
497     // any ISel takes place. We should have a more principled way of handling
498     // this. See D99707 for more details.
499     addPass(createBarrierNoopPass());
500   }
501 
502   return false;
503 }
504 
505 bool ARMPassConfig::addInstSelector() {
506   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
507   return false;
508 }
509 
510 bool ARMPassConfig::addIRTranslator() {
511   addPass(new IRTranslator(getOptLevel()));
512   return false;
513 }
514 
515 bool ARMPassConfig::addLegalizeMachineIR() {
516   addPass(new Legalizer());
517   return false;
518 }
519 
520 bool ARMPassConfig::addRegBankSelect() {
521   addPass(new RegBankSelect());
522   return false;
523 }
524 
525 bool ARMPassConfig::addGlobalInstructionSelect() {
526   addPass(new InstructionSelect(getOptLevel()));
527   return false;
528 }
529 
530 void ARMPassConfig::addPreRegAlloc() {
531   if (getOptLevel() != CodeGenOptLevel::None) {
532     if (getOptLevel() == CodeGenOptLevel::Aggressive)
533       addPass(&MachinePipelinerID);
534 
535     addPass(createMVETPAndVPTOptimisationsPass());
536 
537     addPass(createMLxExpansionPass());
538 
539     if (EnableARMLoadStoreOpt)
540       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
541 
542     if (!DisableA15SDOptimization)
543       addPass(createA15SDOptimizerPass());
544   }
545 }
546 
547 void ARMPassConfig::addPreSched2() {
548   if (getOptLevel() != CodeGenOptLevel::None) {
549     if (EnableARMLoadStoreOpt)
550       addPass(createARMLoadStoreOptimizationPass());
551 
552     addPass(new ARMExecutionDomainFix());
553     addPass(createBreakFalseDeps());
554   }
555 
556   // Expand some pseudo instructions into multiple instructions to allow
557   // proper scheduling.
558   addPass(createARMExpandPseudoPass());
559 
560   if (getOptLevel() != CodeGenOptLevel::None) {
561     // When optimising for size, always run the Thumb2SizeReduction pass before
562     // IfConversion. Otherwise, check whether IT blocks are restricted
563     // (e.g. in v8, IfConversion depends on Thumb instruction widths)
564     addPass(createThumb2SizeReductionPass([this](const Function &F) {
565       return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
566              this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
567     }));
568 
569     addPass(createIfConverter([](const MachineFunction &MF) {
570       return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
571     }));
572   }
573   addPass(createThumb2ITBlockPass());
574 
575   // Add both scheduling passes to give the subtarget an opportunity to pick
576   // between them.
577   if (getOptLevel() != CodeGenOptLevel::None) {
578     addPass(&PostMachineSchedulerID);
579     addPass(&PostRASchedulerID);
580   }
581 
582   addPass(createMVEVPTBlockPass());
583   addPass(createARMIndirectThunks());
584   addPass(createARMSLSHardeningPass());
585 }
586 
587 void ARMPassConfig::addPreEmitPass() {
588   addPass(createThumb2SizeReductionPass());
589 
590   // Constant island pass work on unbundled instructions.
591   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
592     return MF.getSubtarget<ARMSubtarget>().isThumb2();
593   }));
594 
595   // Don't optimize barriers or block placement at -O0.
596   if (getOptLevel() != CodeGenOptLevel::None) {
597     addPass(createARMBlockPlacementPass());
598     addPass(createARMOptimizeBarriersPass());
599   }
600 }
601 
602 void ARMPassConfig::addPreEmitPass2() {
603   // Inserts fixup instructions before unsafe AES operations. Instructions may
604   // be inserted at the start of blocks and at within blocks so this pass has to
605   // come before those below.
606   addPass(createARMFixCortexA57AES1742098Pass());
607   // Inserts BTIs at the start of functions and indirectly-called basic blocks,
608   // so passes cannot add to the start of basic blocks once this has run.
609   addPass(createARMBranchTargetsPass());
610   // Inserts Constant Islands. Block sizes cannot be increased after this point,
611   // as this may push the branch ranges and load offsets of accessing constant
612   // pools out of range..
613   addPass(createARMConstantIslandPass());
614   // Finalises Low-Overhead Loops. This replaces pseudo instructions with real
615   // instructions, but the pseudos all have conservative sizes so that block
616   // sizes will only be decreased by this pass.
617   addPass(createARMLowOverheadLoopsPass());
618 
619   if (TM->getTargetTriple().isOSWindows()) {
620     // Identify valid longjmp targets for Windows Control Flow Guard.
621     addPass(createCFGuardLongjmpPass());
622     // Identify valid eh continuation targets for Windows EHCont Guard.
623     addPass(createEHContGuardCatchretPass());
624   }
625 }
626 
627 yaml::MachineFunctionInfo *
628 ARMBaseTargetMachine::createDefaultFuncInfoYAML() const {
629   return new yaml::ARMFunctionInfo();
630 }
631 
632 yaml::MachineFunctionInfo *
633 ARMBaseTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
634   const auto *MFI = MF.getInfo<ARMFunctionInfo>();
635   return new yaml::ARMFunctionInfo(*MFI);
636 }
637 
638 bool ARMBaseTargetMachine::parseMachineFunctionInfo(
639     const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
640     SMDiagnostic &Error, SMRange &SourceRange) const {
641   const auto &YamlMFI = static_cast<const yaml::ARMFunctionInfo &>(MFI);
642   MachineFunction &MF = PFS.MF;
643   MF.getInfo<ARMFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
644   return false;
645 }
646 
647 void ARMBaseTargetMachine::reset() { SubtargetMap.clear(); }
648