1 //===- AMDKernelCodeTUtils.cpp --------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file - utility functions to parse/print AMDGPUMCKernelCodeT structure 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDKernelCodeTUtils.h" 14 #include "AMDKernelCodeT.h" 15 #include "SIDefines.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/SIDefinesUtils.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCParser/MCAsmLexer.h" 22 #include "llvm/MC/MCParser/MCAsmParser.h" 23 #include "llvm/MC/MCStreamer.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 using namespace llvm; 28 using namespace llvm::AMDGPU; 29 30 // Generates the following for AMDGPUMCKernelCodeT struct members: 31 // - HasMemberXXXXX class 32 // A check to see if AMDGPUMCKernelCodeT has a specific member so it can 33 // determine which of the original amd_kernel_code_t members are duplicated 34 // (if the names don't match, the table driven strategy won't work). 35 // - IsMCExprXXXXX class 36 // Check whether a AMDGPUMCKernelcodeT struct member is MCExpr-ified or not. 37 // - GetMemberXXXXX class 38 // A retrieval helper for said member (of type const MCExpr *&). Will return 39 // a `Phony` const MCExpr * initialized to nullptr to preserve reference 40 // returns. 41 #define GEN_HAS_MEMBER(member) \ 42 class HasMember##member { \ 43 private: \ 44 struct KnownWithMember { \ 45 int member; \ 46 }; \ 47 class AmbiguousDerived : public AMDGPUMCKernelCodeT, \ 48 public KnownWithMember {}; \ 49 template <typename U> \ 50 static constexpr std::false_type Test(decltype(U::member) *); \ 51 template <typename U> static constexpr std::true_type Test(...); \ 52 \ 53 public: \ 54 static constexpr bool RESULT = \ 55 std::is_same_v<decltype(Test<AmbiguousDerived>(nullptr)), \ 56 std::true_type>; \ 57 }; \ 58 class IsMCExpr##member { \ 59 template <typename U, \ 60 typename std::enable_if_t< \ 61 HasMember##member::RESULT && \ 62 std::is_same_v<decltype(U::member), const MCExpr *>, \ 63 U> * = nullptr> \ 64 static constexpr std::true_type HasMCExprType(decltype(U::member) *); \ 65 template <typename U> static constexpr std::false_type HasMCExprType(...); \ 66 \ 67 public: \ 68 static constexpr bool RESULT = \ 69 std::is_same_v<decltype(HasMCExprType<AMDGPUMCKernelCodeT>(nullptr)), \ 70 std::true_type>; \ 71 }; \ 72 class GetMember##member { \ 73 public: \ 74 static const MCExpr *Phony; \ 75 template <typename U, typename std::enable_if_t<IsMCExpr##member::RESULT, \ 76 U> * = nullptr> \ 77 static const MCExpr *&Get(U &C) { \ 78 assert(IsMCExpr##member::RESULT && \ 79 "Trying to retrieve member that does not exist."); \ 80 return C.member; \ 81 } \ 82 template <typename U, typename std::enable_if_t<!IsMCExpr##member::RESULT, \ 83 U> * = nullptr> \ 84 static const MCExpr *&Get(U &C) { \ 85 return Phony; \ 86 } \ 87 }; \ 88 const MCExpr *GetMember##member::Phony = nullptr; 89 90 // Cannot generate class declarations using the table driver approach (see table 91 // in AMDKernelCodeTInfo.h). Luckily, if any are missing here or eventually 92 // added to the table, an error should occur when trying to retrieve the table 93 // in getMCExprIndexTable. 94 GEN_HAS_MEMBER(amd_code_version_major) 95 GEN_HAS_MEMBER(amd_code_version_minor) 96 GEN_HAS_MEMBER(amd_machine_kind) 97 GEN_HAS_MEMBER(amd_machine_version_major) 98 GEN_HAS_MEMBER(amd_machine_version_minor) 99 GEN_HAS_MEMBER(amd_machine_version_stepping) 100 101 GEN_HAS_MEMBER(kernel_code_entry_byte_offset) 102 GEN_HAS_MEMBER(kernel_code_prefetch_byte_size) 103 104 GEN_HAS_MEMBER(granulated_workitem_vgpr_count) 105 GEN_HAS_MEMBER(granulated_wavefront_sgpr_count) 106 GEN_HAS_MEMBER(priority) 107 GEN_HAS_MEMBER(float_mode) 108 GEN_HAS_MEMBER(priv) 109 GEN_HAS_MEMBER(enable_dx10_clamp) 110 GEN_HAS_MEMBER(debug_mode) 111 GEN_HAS_MEMBER(enable_ieee_mode) 112 GEN_HAS_MEMBER(enable_wgp_mode) 113 GEN_HAS_MEMBER(enable_mem_ordered) 114 GEN_HAS_MEMBER(enable_fwd_progress) 115 116 GEN_HAS_MEMBER(enable_sgpr_private_segment_wave_byte_offset) 117 GEN_HAS_MEMBER(user_sgpr_count) 118 GEN_HAS_MEMBER(enable_trap_handler) 119 GEN_HAS_MEMBER(enable_sgpr_workgroup_id_x) 120 GEN_HAS_MEMBER(enable_sgpr_workgroup_id_y) 121 GEN_HAS_MEMBER(enable_sgpr_workgroup_id_z) 122 GEN_HAS_MEMBER(enable_sgpr_workgroup_info) 123 GEN_HAS_MEMBER(enable_vgpr_workitem_id) 124 GEN_HAS_MEMBER(enable_exception_msb) 125 GEN_HAS_MEMBER(granulated_lds_size) 126 GEN_HAS_MEMBER(enable_exception) 127 128 GEN_HAS_MEMBER(enable_sgpr_private_segment_buffer) 129 GEN_HAS_MEMBER(enable_sgpr_dispatch_ptr) 130 GEN_HAS_MEMBER(enable_sgpr_queue_ptr) 131 GEN_HAS_MEMBER(enable_sgpr_kernarg_segment_ptr) 132 GEN_HAS_MEMBER(enable_sgpr_dispatch_id) 133 GEN_HAS_MEMBER(enable_sgpr_flat_scratch_init) 134 GEN_HAS_MEMBER(enable_sgpr_private_segment_size) 135 GEN_HAS_MEMBER(enable_sgpr_grid_workgroup_count_x) 136 GEN_HAS_MEMBER(enable_sgpr_grid_workgroup_count_y) 137 GEN_HAS_MEMBER(enable_sgpr_grid_workgroup_count_z) 138 GEN_HAS_MEMBER(enable_wavefront_size32) 139 GEN_HAS_MEMBER(enable_ordered_append_gds) 140 GEN_HAS_MEMBER(private_element_size) 141 GEN_HAS_MEMBER(is_ptr64) 142 GEN_HAS_MEMBER(is_dynamic_callstack) 143 GEN_HAS_MEMBER(is_debug_enabled) 144 GEN_HAS_MEMBER(is_xnack_enabled) 145 146 GEN_HAS_MEMBER(workitem_private_segment_byte_size) 147 GEN_HAS_MEMBER(workgroup_group_segment_byte_size) 148 GEN_HAS_MEMBER(gds_segment_byte_size) 149 GEN_HAS_MEMBER(kernarg_segment_byte_size) 150 GEN_HAS_MEMBER(workgroup_fbarrier_count) 151 GEN_HAS_MEMBER(wavefront_sgpr_count) 152 GEN_HAS_MEMBER(workitem_vgpr_count) 153 GEN_HAS_MEMBER(reserved_vgpr_first) 154 GEN_HAS_MEMBER(reserved_vgpr_count) 155 GEN_HAS_MEMBER(reserved_sgpr_first) 156 GEN_HAS_MEMBER(reserved_sgpr_count) 157 GEN_HAS_MEMBER(debug_wavefront_private_segment_offset_sgpr) 158 GEN_HAS_MEMBER(debug_private_segment_buffer_sgpr) 159 GEN_HAS_MEMBER(kernarg_segment_alignment) 160 GEN_HAS_MEMBER(group_segment_alignment) 161 GEN_HAS_MEMBER(private_segment_alignment) 162 GEN_HAS_MEMBER(wavefront_size) 163 GEN_HAS_MEMBER(call_convention) 164 GEN_HAS_MEMBER(runtime_loader_kernel_symbol) 165 166 static ArrayRef<StringLiteral> get_amd_kernel_code_t_FldNames() { 167 static constexpr StringLiteral const Table[] = { 168 "", // not found placeholder 169 #define RECORD(name, altName, print, parse) #name 170 #include "Utils/AMDKernelCodeTInfo.h" 171 #undef RECORD 172 }; 173 return ArrayRef(Table); 174 } 175 176 static ArrayRef<StringLiteral> get_amd_kernel_code_t_FldAltNames() { 177 static constexpr StringLiteral const Table[] = { 178 "", // not found placeholder 179 #define RECORD(name, altName, print, parse) #altName 180 #include "Utils/AMDKernelCodeTInfo.h" 181 #undef RECORD 182 }; 183 return ArrayRef(Table); 184 } 185 186 static ArrayRef<bool> hasMCExprVersionTable() { 187 static bool const Table[] = { 188 #define RECORD(name, altName, print, parse) (IsMCExpr##name::RESULT) 189 #include "Utils/AMDKernelCodeTInfo.h" 190 #undef RECORD 191 }; 192 return ArrayRef(Table); 193 } 194 195 using RetrieveFx = const MCExpr *&(*)(AMDGPUMCKernelCodeT &); 196 197 static ArrayRef<RetrieveFx> getMCExprIndexTable() { 198 static const RetrieveFx Table[] = { 199 #define RECORD(name, altName, print, parse) GetMember##name::Get 200 #include "Utils/AMDKernelCodeTInfo.h" 201 #undef RECORD 202 }; 203 return ArrayRef(Table); 204 } 205 206 static StringMap<int> createIndexMap(ArrayRef<StringLiteral> names, 207 ArrayRef<StringLiteral> altNames) { 208 StringMap<int> map; 209 assert(names.size() == altNames.size()); 210 for (unsigned i = 0; i < names.size(); ++i) { 211 map.insert(std::pair(names[i], i)); 212 map.insert(std::pair(altNames[i], i)); 213 } 214 return map; 215 } 216 217 static int get_amd_kernel_code_t_FieldIndex(StringRef name) { 218 static const auto map = createIndexMap(get_amd_kernel_code_t_FldNames(), 219 get_amd_kernel_code_t_FldAltNames()); 220 return map.lookup(name) - 1; // returns -1 if not found 221 } 222 223 class PrintField { 224 public: 225 template <typename T, T AMDGPUMCKernelCodeT::*ptr, 226 typename std::enable_if_t<!std::is_integral_v<T>, T> * = nullptr> 227 static void printField(StringRef Name, const AMDGPUMCKernelCodeT &C, 228 raw_ostream &OS, MCContext &Ctx, 229 AMDGPUMCKernelCodeT::PrintHelper Helper) { 230 OS << Name << " = "; 231 const MCExpr *Value = C.*ptr; 232 Helper(Value, OS, Ctx.getAsmInfo()); 233 } 234 235 template <typename T, T AMDGPUMCKernelCodeT::*ptr, 236 typename std::enable_if_t<std::is_integral_v<T>, T> * = nullptr> 237 static void printField(StringRef Name, const AMDGPUMCKernelCodeT &C, 238 raw_ostream &OS, MCContext &, 239 AMDGPUMCKernelCodeT::PrintHelper) { 240 OS << Name << " = " << (int)(C.*ptr); 241 } 242 }; 243 244 template <typename T, T AMDGPUMCKernelCodeT::*ptr, int shift, int width = 1> 245 static void printBitField(StringRef Name, const AMDGPUMCKernelCodeT &C, 246 raw_ostream &OS, MCContext &, 247 AMDGPUMCKernelCodeT::PrintHelper) { 248 const auto Mask = (static_cast<T>(1) << width) - 1; 249 OS << Name << " = " << (int)((C.*ptr >> shift) & Mask); 250 } 251 252 using PrintFx = void (*)(StringRef, const AMDGPUMCKernelCodeT &, raw_ostream &, 253 MCContext &, AMDGPUMCKernelCodeT::PrintHelper Helper); 254 255 static ArrayRef<PrintFx> 256 getPrinterTable(AMDGPUMCKernelCodeT::PrintHelper Helper) { 257 static const PrintFx Table[] = { 258 #define COMPPGM1(name, aname, AccMacro) \ 259 COMPPGM(name, aname, C_00B848_##AccMacro, S_00B848_##AccMacro, 0) 260 #define COMPPGM2(name, aname, AccMacro) \ 261 COMPPGM(name, aname, C_00B84C_##AccMacro, S_00B84C_##AccMacro, 32) 262 #define PRINTFIELD(sname, aname, name) PrintField::printField<FLD_T(name)> 263 #define PRINTCOMP(Complement, PGMType) \ 264 [](StringRef Name, const AMDGPUMCKernelCodeT &C, raw_ostream &OS, \ 265 MCContext &Ctx, AMDGPUMCKernelCodeT::PrintHelper Helper) { \ 266 OS << Name << " = "; \ 267 auto [Shift, Mask] = getShiftMask(Complement); \ 268 const MCExpr *Value; \ 269 if (PGMType == 0) { \ 270 Value = \ 271 maskShiftGet(C.compute_pgm_resource1_registers, Mask, Shift, Ctx); \ 272 } else { \ 273 Value = \ 274 maskShiftGet(C.compute_pgm_resource2_registers, Mask, Shift, Ctx); \ 275 } \ 276 Helper(Value, OS, Ctx.getAsmInfo()); \ 277 } 278 #define RECORD(name, altName, print, parse) print 279 #include "Utils/AMDKernelCodeTInfo.h" 280 #undef RECORD 281 }; 282 return ArrayRef(Table); 283 } 284 285 static bool expectAbsExpression(MCAsmParser &MCParser, int64_t &Value, 286 raw_ostream &Err) { 287 288 if (MCParser.getLexer().isNot(AsmToken::Equal)) { 289 Err << "expected '='"; 290 return false; 291 } 292 MCParser.getLexer().Lex(); 293 294 if (MCParser.parseAbsoluteExpression(Value)) { 295 Err << "integer absolute expression expected"; 296 return false; 297 } 298 return true; 299 } 300 301 template <typename T, T AMDGPUMCKernelCodeT::*ptr> 302 static bool parseField(AMDGPUMCKernelCodeT &C, MCAsmParser &MCParser, 303 raw_ostream &Err) { 304 int64_t Value = 0; 305 if (!expectAbsExpression(MCParser, Value, Err)) 306 return false; 307 C.*ptr = (T)Value; 308 return true; 309 } 310 311 template <typename T, T AMDGPUMCKernelCodeT::*ptr, int shift, int width = 1> 312 static bool parseBitField(AMDGPUMCKernelCodeT &C, MCAsmParser &MCParser, 313 raw_ostream &Err) { 314 int64_t Value = 0; 315 if (!expectAbsExpression(MCParser, Value, Err)) 316 return false; 317 const uint64_t Mask = ((UINT64_C(1) << width) - 1) << shift; 318 C.*ptr &= (T)~Mask; 319 C.*ptr |= (T)((Value << shift) & Mask); 320 return true; 321 } 322 323 static bool parseExpr(MCAsmParser &MCParser, const MCExpr *&Value, 324 raw_ostream &Err) { 325 if (MCParser.getLexer().isNot(AsmToken::Equal)) { 326 Err << "expected '='"; 327 return false; 328 } 329 MCParser.getLexer().Lex(); 330 331 if (MCParser.parseExpression(Value)) { 332 Err << "Could not parse expression"; 333 return false; 334 } 335 return true; 336 } 337 338 using ParseFx = bool (*)(AMDGPUMCKernelCodeT &, MCAsmParser &, raw_ostream &); 339 340 static ArrayRef<ParseFx> getParserTable() { 341 static const ParseFx Table[] = { 342 #define COMPPGM1(name, aname, AccMacro) \ 343 COMPPGM(name, aname, G_00B848_##AccMacro, C_00B848_##AccMacro, 0) 344 #define COMPPGM2(name, aname, AccMacro) \ 345 COMPPGM(name, aname, G_00B84C_##AccMacro, C_00B84C_##AccMacro, 32) 346 #define PARSECOMP(Complement, PGMType) \ 347 [](AMDGPUMCKernelCodeT &C, MCAsmParser &MCParser, \ 348 raw_ostream &Err) -> bool { \ 349 MCContext &Ctx = MCParser.getContext(); \ 350 const MCExpr *Value; \ 351 if (!parseExpr(MCParser, Value, Err)) \ 352 return false; \ 353 auto [Shift, Mask] = getShiftMask(Complement); \ 354 Value = maskShiftSet(Value, Mask, Shift, Ctx); \ 355 const MCExpr *Compl = MCConstantExpr::create(Complement, Ctx); \ 356 if (PGMType == 0) { \ 357 C.compute_pgm_resource1_registers = MCBinaryExpr::createAnd( \ 358 C.compute_pgm_resource1_registers, Compl, Ctx); \ 359 C.compute_pgm_resource1_registers = MCBinaryExpr::createOr( \ 360 C.compute_pgm_resource1_registers, Value, Ctx); \ 361 } else { \ 362 C.compute_pgm_resource2_registers = MCBinaryExpr::createAnd( \ 363 C.compute_pgm_resource2_registers, Compl, Ctx); \ 364 C.compute_pgm_resource2_registers = MCBinaryExpr::createOr( \ 365 C.compute_pgm_resource2_registers, Value, Ctx); \ 366 } \ 367 return true; \ 368 } 369 #define RECORD(name, altName, print, parse) parse 370 #include "Utils/AMDKernelCodeTInfo.h" 371 #undef RECORD 372 }; 373 return ArrayRef(Table); 374 } 375 376 static void printAmdKernelCodeField(const AMDGPUMCKernelCodeT &C, int FldIndex, 377 raw_ostream &OS, MCContext &Ctx, 378 AMDGPUMCKernelCodeT::PrintHelper Helper) { 379 auto Printer = getPrinterTable(Helper)[FldIndex]; 380 if (Printer) 381 Printer(get_amd_kernel_code_t_FldNames()[FldIndex + 1], C, OS, Ctx, Helper); 382 } 383 384 void AMDGPUMCKernelCodeT::initDefault(const MCSubtargetInfo *STI, 385 MCContext &Ctx, bool InitMCExpr) { 386 AMDGPUMCKernelCodeT(); 387 388 AMDGPU::initDefaultAMDKernelCodeT(*this, STI); 389 390 if (InitMCExpr) { 391 const MCExpr *ZeroExpr = MCConstantExpr::create(0, Ctx); 392 compute_pgm_resource1_registers = 393 MCConstantExpr::create(Lo_32(compute_pgm_resource_registers), Ctx); 394 compute_pgm_resource2_registers = 395 MCConstantExpr::create(Hi_32(compute_pgm_resource_registers), Ctx); 396 is_dynamic_callstack = ZeroExpr; 397 wavefront_sgpr_count = ZeroExpr; 398 workitem_vgpr_count = ZeroExpr; 399 workitem_private_segment_byte_size = ZeroExpr; 400 } 401 } 402 403 void AMDGPUMCKernelCodeT::validate(const MCSubtargetInfo *STI, MCContext &Ctx) { 404 int64_t Value; 405 if (!compute_pgm_resource1_registers->evaluateAsAbsolute(Value)) 406 return; 407 408 if (G_00B848_DX10_CLAMP(Value) && AMDGPU::isGFX12Plus(*STI)) { 409 Ctx.reportError({}, "enable_dx10_clamp=1 is not allowed on GFX12+"); 410 return; 411 } 412 413 if (G_00B848_IEEE_MODE(Value) && AMDGPU::isGFX12Plus(*STI)) { 414 Ctx.reportError({}, "enable_ieee_mode=1 is not allowed on GFX12+"); 415 return; 416 } 417 418 if (G_00B848_WGP_MODE(Value) && !AMDGPU::isGFX10Plus(*STI)) { 419 Ctx.reportError({}, "enable_wgp_mode=1 is only allowed on GFX10+"); 420 return; 421 } 422 423 if (G_00B848_MEM_ORDERED(Value) && !AMDGPU::isGFX10Plus(*STI)) { 424 Ctx.reportError({}, "enable_mem_ordered=1 is only allowed on GFX10+"); 425 return; 426 } 427 428 if (G_00B848_FWD_PROGRESS(Value) && !AMDGPU::isGFX10Plus(*STI)) { 429 Ctx.reportError({}, "enable_fwd_progress=1 is only allowed on GFX10+"); 430 return; 431 } 432 } 433 434 const MCExpr *&AMDGPUMCKernelCodeT::getMCExprForIndex(int Index) { 435 static const auto IndexTable = getMCExprIndexTable(); 436 return IndexTable[Index](*this); 437 } 438 439 bool AMDGPUMCKernelCodeT::ParseKernelCodeT(StringRef ID, MCAsmParser &MCParser, 440 raw_ostream &Err) { 441 const int Idx = get_amd_kernel_code_t_FieldIndex(ID); 442 if (Idx < 0) { 443 Err << "unexpected amd_kernel_code_t field name " << ID; 444 return false; 445 } 446 447 if (hasMCExprVersionTable()[Idx]) { 448 const MCExpr *Value; 449 if (!parseExpr(MCParser, Value, Err)) 450 return false; 451 getMCExprForIndex(Idx) = Value; 452 return true; 453 } 454 auto Parser = getParserTable()[Idx]; 455 return Parser ? Parser(*this, MCParser, Err) : false; 456 } 457 458 void AMDGPUMCKernelCodeT::EmitKernelCodeT(raw_ostream &OS, MCContext &Ctx, 459 PrintHelper Helper) { 460 const int Size = hasMCExprVersionTable().size(); 461 for (int i = 0; i < Size; ++i) { 462 OS << "\t\t"; 463 if (hasMCExprVersionTable()[i]) { 464 OS << get_amd_kernel_code_t_FldNames()[i + 1] << " = "; 465 const MCExpr *Value = getMCExprForIndex(i); 466 Helper(Value, OS, Ctx.getAsmInfo()); 467 } else { 468 printAmdKernelCodeField(*this, i, OS, Ctx, Helper); 469 } 470 OS << '\n'; 471 } 472 } 473 474 void AMDGPUMCKernelCodeT::EmitKernelCodeT(MCStreamer &OS, MCContext &Ctx) { 475 OS.emitIntValue(amd_kernel_code_version_major, /*Size=*/4); 476 OS.emitIntValue(amd_kernel_code_version_minor, /*Size=*/4); 477 OS.emitIntValue(amd_machine_kind, /*Size=*/2); 478 OS.emitIntValue(amd_machine_version_major, /*Size=*/2); 479 OS.emitIntValue(amd_machine_version_minor, /*Size=*/2); 480 OS.emitIntValue(amd_machine_version_stepping, /*Size=*/2); 481 OS.emitIntValue(kernel_code_entry_byte_offset, /*Size=*/8); 482 OS.emitIntValue(kernel_code_prefetch_byte_offset, /*Size=*/8); 483 OS.emitIntValue(kernel_code_prefetch_byte_size, /*Size=*/8); 484 OS.emitIntValue(reserved0, /*Size=*/8); 485 486 if (compute_pgm_resource1_registers != nullptr) 487 OS.emitValue(compute_pgm_resource1_registers, /*Size=*/4); 488 else 489 OS.emitIntValue(Lo_32(compute_pgm_resource_registers), 490 /*Size=*/4); 491 492 if (compute_pgm_resource2_registers != nullptr) 493 OS.emitValue(compute_pgm_resource2_registers, /*Size=*/4); 494 else 495 OS.emitIntValue(Hi_32(compute_pgm_resource_registers), 496 /*Size=*/4); 497 498 if (is_dynamic_callstack != nullptr) { 499 const MCExpr *CodeProps = MCConstantExpr::create(code_properties, Ctx); 500 CodeProps = MCBinaryExpr::createOr( 501 CodeProps, 502 maskShiftSet(is_dynamic_callstack, 503 (1 << AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK_WIDTH) - 1, 504 AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK_SHIFT, Ctx), 505 Ctx); 506 OS.emitValue(CodeProps, /*Size=*/4); 507 } else 508 OS.emitIntValue(code_properties, /*Size=*/4); 509 510 if (workitem_private_segment_byte_size != nullptr) 511 OS.emitValue(workitem_private_segment_byte_size, /*Size=*/4); 512 else 513 OS.emitIntValue(0, /*Size=*/4); 514 515 OS.emitIntValue(workgroup_group_segment_byte_size, /*Size=*/4); 516 OS.emitIntValue(gds_segment_byte_size, /*Size=*/4); 517 OS.emitIntValue(kernarg_segment_byte_size, /*Size=*/8); 518 OS.emitIntValue(workgroup_fbarrier_count, /*Size=*/4); 519 520 if (wavefront_sgpr_count != nullptr) 521 OS.emitValue(wavefront_sgpr_count, /*Size=*/2); 522 else 523 OS.emitIntValue(0, /*Size=*/2); 524 525 if (workitem_vgpr_count != nullptr) 526 OS.emitValue(workitem_vgpr_count, /*Size=*/2); 527 else 528 OS.emitIntValue(0, /*Size=*/2); 529 530 OS.emitIntValue(reserved_vgpr_first, /*Size=*/2); 531 OS.emitIntValue(reserved_vgpr_count, /*Size=*/2); 532 OS.emitIntValue(reserved_sgpr_first, /*Size=*/2); 533 OS.emitIntValue(reserved_sgpr_count, /*Size=*/2); 534 OS.emitIntValue(debug_wavefront_private_segment_offset_sgpr, 535 /*Size=*/2); 536 OS.emitIntValue(debug_private_segment_buffer_sgpr, /*Size=*/2); 537 OS.emitIntValue(kernarg_segment_alignment, /*Size=*/1); 538 OS.emitIntValue(group_segment_alignment, /*Size=*/1); 539 OS.emitIntValue(private_segment_alignment, /*Size=*/1); 540 OS.emitIntValue(wavefront_size, /*Size=*/1); 541 542 OS.emitIntValue(call_convention, /*Size=*/4); 543 OS.emitBytes(StringRef((const char *)reserved3, /*Size=*/12)); 544 OS.emitIntValue(runtime_loader_kernel_symbol, /*Size=*/8); 545 OS.emitBytes(StringRef((const char *)control_directives, /*Size=*/16 * 8)); 546 } 547