1//===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Subregister declarations 11//===----------------------------------------------------------------------===// 12 13let Namespace = "AMDGPU" in { 14 15def lo16 : SubRegIndex<16, 0>; 16def hi16 : SubRegIndex<16, 16>; 17 18foreach Index = 0...31 in { 19 def sub#Index : SubRegIndex<32, !shl(Index, 5)>; 20} 21 22foreach Index = 1...31 in { 23 def sub#Index#_lo16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), lo16>; 24 def sub#Index#_hi16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), hi16>; 25} 26 27foreach Size = {2...6,8,16} in { 28 foreach Index = !range(!sub(33, Size)) in { 29 def !interleave(!foreach(cur, !range(Size), "sub"#!add(cur, Index)), "_") : 30 SubRegIndex<!mul(Size, 32), !shl(Index, 5)> { 31 let CoveringSubRegIndices = 32 !foreach(cur, !range(Size), !cast<SubRegIndex>(sub#!add(cur, Index))); 33 } 34 } 35} 36 37} 38 39//===----------------------------------------------------------------------===// 40// Helpers 41//===----------------------------------------------------------------------===// 42 43class getSubRegs<int size> { 44 list<SubRegIndex> ret2 = [sub0, sub1]; 45 list<SubRegIndex> ret3 = [sub0, sub1, sub2]; 46 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3]; 47 list<SubRegIndex> ret5 = [sub0, sub1, sub2, sub3, sub4]; 48 list<SubRegIndex> ret6 = [sub0, sub1, sub2, sub3, sub4, sub5]; 49 list<SubRegIndex> ret7 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6]; 50 list<SubRegIndex> ret8 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; 51 list<SubRegIndex> ret9 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, sub8]; 52 list<SubRegIndex> ret10 = [sub0, sub1, sub2, sub3, 53 sub4, sub5, sub6, sub7, 54 sub8, sub9]; 55 list<SubRegIndex> ret11 = [sub0, sub1, sub2, sub3, 56 sub4, sub5, sub6, sub7, 57 sub8, sub9, sub10]; 58 list<SubRegIndex> ret12 = [sub0, sub1, sub2, sub3, 59 sub4, sub5, sub6, sub7, 60 sub8, sub9, sub10, sub11]; 61 list<SubRegIndex> ret16 = [sub0, sub1, sub2, sub3, 62 sub4, sub5, sub6, sub7, 63 sub8, sub9, sub10, sub11, 64 sub12, sub13, sub14, sub15]; 65 list<SubRegIndex> ret32 = [sub0, sub1, sub2, sub3, 66 sub4, sub5, sub6, sub7, 67 sub8, sub9, sub10, sub11, 68 sub12, sub13, sub14, sub15, 69 sub16, sub17, sub18, sub19, 70 sub20, sub21, sub22, sub23, 71 sub24, sub25, sub26, sub27, 72 sub28, sub29, sub30, sub31]; 73 74 list<SubRegIndex> ret = !if(!eq(size, 2), ret2, 75 !if(!eq(size, 3), ret3, 76 !if(!eq(size, 4), ret4, 77 !if(!eq(size, 5), ret5, 78 !if(!eq(size, 6), ret6, 79 !if(!eq(size, 7), ret7, 80 !if(!eq(size, 8), ret8, 81 !if(!eq(size, 9), ret9, 82 !if(!eq(size, 10), ret10, 83 !if(!eq(size, 11), ret11, 84 !if(!eq(size, 12), ret12, 85 !if(!eq(size, 16), ret16, 86 ret32)))))))))))); 87} 88 89// Generates list of sequential register tuple names. 90// E.g. RegSeq<3,2,2,"s">.ret -> [ "s[0:1]", "s[2:3]" ] 91class RegSeqNames<int last_reg, int stride, int size, string prefix> { 92 defvar numtuples = !div(!sub(!add(last_reg, stride, 1), size), stride); 93 defvar range = !range(0, !mul(numtuples, stride), stride); 94 list<string> ret = !foreach(n, range, prefix # "[" # n # ":" # !add(n, size, -1) # "]"); 95} 96 97// Generates list of dags for register tuples. 98class RegSeqDags<RegisterClass RC, int last_reg, int stride, int size, 99 int start = 0> { 100 dag trunc_rc = (trunc RC, 101 !if(!and(!eq(stride, 1), !eq(start, 0)), 102 !sub(!add(last_reg, 2), size), 103 !add(last_reg, 1))); 104 list<dag> ret = 105 !if(!lt(start, size), 106 !listconcat([(add (decimate (shl trunc_rc, start), stride))], 107 RegSeqDags<RC, last_reg, stride, size, !add(start, 1)>.ret), 108 []); 109} 110 111class SIRegisterTuples<list<SubRegIndex> Indices, RegisterClass RC, 112 int last_reg, int stride, int size, string prefix> : 113 RegisterTuples<Indices, 114 RegSeqDags<RC, last_reg, stride, size>.ret, 115 RegSeqNames<last_reg, stride, size, prefix>.ret>; 116 117//===----------------------------------------------------------------------===// 118// Declarations that describe the SI registers 119//===----------------------------------------------------------------------===// 120class SIReg <string n, bits<8> regIdx = 0, bit isVGPR = 0, 121 bit isAGPR = 0, bit isHi16 = 0> : Register<n> { 122 let Namespace = "AMDGPU"; 123 124 // These are generic helper values we use to form actual register 125 // codes. They should not be assumed to match any particular register 126 // encodings on any particular subtargets. 127 let HWEncoding{7-0} = regIdx; 128 let HWEncoding{8} = isVGPR; 129 let HWEncoding{9} = isAGPR; 130 let HWEncoding{10} = isHi16; 131 132 int Index = !cast<int>(regIdx); 133} 134 135// For register classes that use TSFlags. 136class SIRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList> 137 : RegisterClass <n, rTypes, Align, rList> { 138 // For vector register classes. 139 field bit HasVGPR = 0; 140 field bit HasAGPR = 0; 141 142 // For scalar register classes. 143 field bit HasSGPR = 0; 144 145 // Alignment of the first register in tuple (in 32-bit units). 146 field int RegTupleAlignUnits = 1; 147 148 // These need to be kept in sync with the enum SIRCFlags. 149 let TSFlags{1-0} = RegTupleAlignUnits; 150 let TSFlags{2} = HasVGPR; 151 let TSFlags{3} = HasAGPR; 152 let TSFlags{4} = HasSGPR; 153} 154 155multiclass SIRegLoHi16 <string n, bits<8> regIdx, bit ArtificialHigh = 1, 156 bit isVGPR = 0, bit isAGPR = 0, 157 list<int> DwarfEncodings = [-1, -1]> { 158 def _LO16 : SIReg<n#".l", regIdx, isVGPR, isAGPR>; 159 def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx, isVGPR, isAGPR, 160 /* isHi16 */ 1> { 161 let isArtificial = ArtificialHigh; 162 } 163 def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"), 164 !cast<Register>(NAME#"_HI16")]>, 165 DwarfRegNum<DwarfEncodings> { 166 let Namespace = "AMDGPU"; 167 let SubRegIndices = [lo16, hi16]; 168 let CoveredBySubRegs = !not(ArtificialHigh); 169 let HWEncoding{7-0} = regIdx; 170 let HWEncoding{8} = isVGPR; 171 let HWEncoding{9} = isAGPR; 172 173 int Index = !cast<int>(regIdx); 174 } 175} 176 177// Special Registers 178defm VCC_LO : SIRegLoHi16<"vcc_lo", 106>; 179defm VCC_HI : SIRegLoHi16<"vcc_hi", 107>; 180 181// Pseudo-registers: Used as placeholders during isel and immediately 182// replaced, never seeing the verifier. 183def PRIVATE_RSRC_REG : SIReg<"private_rsrc", 0>; 184def FP_REG : SIReg<"fp", 0>; 185def SP_REG : SIReg<"sp", 0>; 186 187// Pseudo-register to represent the program-counter DWARF register. 188def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 16]> { 189 // There is no physical register corresponding to a "program counter", but 190 // we need to encode the concept in debug information in order to represent 191 // things like the return value in unwind information. 192 let isArtificial = 1; 193} 194 195// VCC for 64-bit instructions 196def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> { 197 let Namespace = "AMDGPU"; 198 let SubRegIndices = [sub0, sub1]; 199 let HWEncoding = VCC_LO.HWEncoding; 200} 201 202defm EXEC_LO : SIRegLoHi16<"exec_lo", 126, /*ArtificialHigh=*/1, /*isVGPR=*/0, 203 /*isAGPR=*/0, /*DwarfEncodings=*/[1, 1]>; 204defm EXEC_HI : SIRegLoHi16<"exec_hi", 127>; 205 206def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> { 207 let Namespace = "AMDGPU"; 208 let SubRegIndices = [sub0, sub1]; 209 let HWEncoding = EXEC_LO.HWEncoding; 210} 211 212// 32-bit real registers, for MC only. 213// May be used with both 32-bit and 64-bit operands. 214defm SRC_VCCZ : SIRegLoHi16<"src_vccz", 251>; 215defm SRC_EXECZ : SIRegLoHi16<"src_execz", 252>; 216defm SRC_SCC : SIRegLoHi16<"src_scc", 253>; 217 218// 1-bit pseudo register, for codegen only. 219// Should never be emitted. 220def SCC : SIReg<"scc">; 221 222// Encoding changes between subtarget generations. 223// See also Utils/AMDGPUBaseInfo.cpp MAP_REG2REG. 224defm M0_gfxpre11 : SIRegLoHi16 <"m0", 124>; 225defm M0_gfx11plus : SIRegLoHi16 <"m0", 125>; 226defm M0 : SIRegLoHi16 <"m0", 0>; 227 228defm SGPR_NULL_gfxpre11 : SIRegLoHi16 <"null", 125>; 229defm SGPR_NULL_gfx11plus : SIRegLoHi16 <"null", 124>; 230let isConstant = true in { 231defm SGPR_NULL : SIRegLoHi16 <"null", 0>; 232defm SGPR_NULL_HI : SIRegLoHi16 <"", 0>; 233} // isConstant = true 234 235def SGPR_NULL64 : 236 RegisterWithSubRegs<"null", [SGPR_NULL, SGPR_NULL_HI]> { 237 let Namespace = "AMDGPU"; 238 let SubRegIndices = [sub0, sub1]; 239 let HWEncoding = SGPR_NULL.HWEncoding; 240 let isConstant = true; 241} 242 243// Aperture registers are 64 bit registers with a LO/HI 32 bit. 244// HI 32 bit cannot be used, and LO 32 is used by instructions 245// with 32 bit sources. 246// 247// Note that the low 32 bits are essentially useless as they 248// don't contain the lower 32 bits of the address - they are in 249// the high 32 bits. The lower 32 bits are always zero (for base) or 250// -1 (for limit). Since we cannot access the high 32 bits, when we 251// need them, we need to do a 64 bit load and extract the bits manually. 252multiclass ApertureRegister<string name, bits<8> regIdx> { 253 let isConstant = true in { 254 // FIXME: We shouldn't need to define subregisters for these (nor add them to any 16 bit 255 // register classes), but if we don't it seems to confuse the TableGen 256 // backend and we end up with a lot of weird register pressure sets and classes. 257 defm _LO : SIRegLoHi16 <name, regIdx>; 258 defm _HI : SIRegLoHi16 <"", regIdx>; 259 260 def "" : RegisterWithSubRegs<name, [!cast<Register>(NAME#_LO), !cast<Register>(NAME#_HI)]> { 261 let Namespace = "AMDGPU"; 262 let SubRegIndices = [sub0, sub1]; 263 let HWEncoding = !cast<Register>(NAME#_LO).HWEncoding; 264 } 265 } // isConstant = true 266} 267 268defm SRC_SHARED_BASE : ApertureRegister<"src_shared_base", 235>; 269defm SRC_SHARED_LIMIT : ApertureRegister<"src_shared_limit", 236>; 270defm SRC_PRIVATE_BASE : ApertureRegister<"src_private_base", 237>; 271defm SRC_PRIVATE_LIMIT : ApertureRegister<"src_private_limit", 238>; 272 273defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>; 274 275// Not addressable 276def MODE : SIReg <"mode", 0>; 277 278def LDS_DIRECT : SIReg <"src_lds_direct", 254> { 279 // There is no physical register corresponding to this. This is an 280 // encoding value in a source field, which will ultimately trigger a 281 // read from m0. 282 let isArtificial = 1; 283} 284 285defm XNACK_MASK_LO : SIRegLoHi16<"xnack_mask_lo", 104>; 286defm XNACK_MASK_HI : SIRegLoHi16<"xnack_mask_hi", 105>; 287 288def XNACK_MASK : 289 RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]> { 290 let Namespace = "AMDGPU"; 291 let SubRegIndices = [sub0, sub1]; 292 let HWEncoding = XNACK_MASK_LO.HWEncoding; 293} 294 295// Trap handler registers 296defm TBA_LO : SIRegLoHi16<"tba_lo", 108>; 297defm TBA_HI : SIRegLoHi16<"tba_hi", 109>; 298 299def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]> { 300 let Namespace = "AMDGPU"; 301 let SubRegIndices = [sub0, sub1]; 302 let HWEncoding = TBA_LO.HWEncoding; 303} 304 305defm TMA_LO : SIRegLoHi16<"tma_lo", 110>; 306defm TMA_HI : SIRegLoHi16<"tma_hi", 111>; 307 308def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]> { 309 let Namespace = "AMDGPU"; 310 let SubRegIndices = [sub0, sub1]; 311 let HWEncoding = TMA_LO.HWEncoding; 312} 313 314foreach Index = 0...15 in { 315 defm TTMP#Index#_vi : SIRegLoHi16<"ttmp"#Index, !add(112, Index)>; 316 defm TTMP#Index#_gfx9plus : SIRegLoHi16<"ttmp"#Index, !add(108, Index)>; 317 defm TTMP#Index : SIRegLoHi16<"ttmp"#Index, 0>; 318} 319 320multiclass FLAT_SCR_LOHI_m <string n, bits<8> ci_e, bits<8> vi_e> { 321 defm _ci : SIRegLoHi16<n, ci_e>; 322 defm _vi : SIRegLoHi16<n, vi_e>; 323 defm "" : SIRegLoHi16<n, 0>; 324} 325 326class FlatReg <Register lo, Register hi, bits<16> encoding> : 327 RegisterWithSubRegs<"flat_scratch", [lo, hi]> { 328 let Namespace = "AMDGPU"; 329 let SubRegIndices = [sub0, sub1]; 330 let HWEncoding = encoding; 331} 332 333defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes. 334defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes. 335 336def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>; 337def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>; 338def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>; 339 340// SGPR registers 341foreach Index = 0...105 in { 342 defm SGPR#Index : 343 SIRegLoHi16 <"s"#Index, Index, /*ArtificialHigh=*/1, 344 /*isVGPR=*/0, /*isAGPR=*/0, /*DwarfEncodings=*/ 345 [!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)), 346 !if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>; 347} 348 349// VGPR registers 350foreach Index = 0...255 in { 351 defm VGPR#Index : 352 SIRegLoHi16 <"v"#Index, Index, /*ArtificialHigh=*/ 0, 353 /*isVGPR=*/ 1, /*isAGPR=*/ 0, /*DwarfEncodings=*/ 354 [!add(Index, 2560), !add(Index, 1536)]>; 355} 356 357// AccVGPR registers 358foreach Index = 0...255 in { 359 defm AGPR#Index : 360 SIRegLoHi16 <"a"#Index, Index, /*ArtificialHigh=*/ 1, 361 /*isVGPR=*/ 0, /*isAGPR=*/ 1, /*DwarfEncodings=*/ 362 [!add(Index, 3072), !add(Index, 2048)]>; 363} 364 365//===----------------------------------------------------------------------===// 366// Groupings using register classes and tuples 367//===----------------------------------------------------------------------===// 368 369def SCC_CLASS : SIRegisterClass<"AMDGPU", [i1], 1, (add SCC)> { 370 let CopyCost = -1; 371 let isAllocatable = 0; 372 let HasSGPR = 1; 373 let BaseClassOrder = 10000; 374} 375 376def M0_CLASS : SIRegisterClass<"AMDGPU", [i32], 32, (add M0)> { 377 let CopyCost = 1; 378 let isAllocatable = 0; 379 let HasSGPR = 1; 380} 381 382def M0_CLASS_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16, (add M0_LO16)> { 383 let CopyCost = 1; 384 let Size = 16; 385 let isAllocatable = 0; 386 let HasSGPR = 1; 387} 388 389// TODO: Do we need to set DwarfRegAlias on register tuples? 390 391def SGPR_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16, 392 (add (sequence "SGPR%u_LO16", 0, 105))> { 393 let AllocationPriority = 0; 394 let Size = 16; 395 let GeneratePressureSet = 0; 396 let HasSGPR = 1; 397} 398 399def SGPR_HI16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16, 400 (add (sequence "SGPR%u_HI16", 0, 105))> { 401 let isAllocatable = 0; 402 let Size = 16; 403 let GeneratePressureSet = 0; 404 let HasSGPR = 1; 405} 406 407// SGPR 32-bit registers 408def SGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32, 409 (add (sequence "SGPR%u", 0, 105))> { 410 // Give all SGPR classes higher priority than VGPR classes, because 411 // we want to spill SGPRs to VGPRs. 412 let AllocationPriority = 0; 413 let GeneratePressureSet = 0; 414 let HasSGPR = 1; 415} 416 417// SGPR 64-bit registers 418def SGPR_64Regs : SIRegisterTuples<getSubRegs<2>.ret, SGPR_32, 105, 2, 2, "s">; 419 420// SGPR 96-bit registers. 421def SGPR_96Regs : SIRegisterTuples<getSubRegs<3>.ret, SGPR_32, 105, 4, 3, "s">; 422 423// SGPR 128-bit registers 424def SGPR_128Regs : SIRegisterTuples<getSubRegs<4>.ret, SGPR_32, 105, 4, 4, "s">; 425 426// SGPR 160-bit registers. No operations use these, but for symmetry with 160-bit VGPRs. 427def SGPR_160Regs : SIRegisterTuples<getSubRegs<5>.ret, SGPR_32, 105, 4, 5, "s">; 428 429// SGPR 192-bit registers. No operations use these, but for symmetry with 192-bit VGPRs. 430def SGPR_192Regs : SIRegisterTuples<getSubRegs<6>.ret, SGPR_32, 105, 4, 6, "s">; 431 432// SGPR 224-bit registers. No operations use these, but for symmetry with 224-bit VGPRs. 433def SGPR_224Regs : SIRegisterTuples<getSubRegs<7>.ret, SGPR_32, 105, 4, 7, "s">; 434 435// SGPR 256-bit registers 436def SGPR_256Regs : SIRegisterTuples<getSubRegs<8>.ret, SGPR_32, 105, 4, 8, "s">; 437 438// SGPR 288-bit registers. No operations use these, but for symmetry with 288-bit VGPRs. 439def SGPR_288Regs : SIRegisterTuples<getSubRegs<9>.ret, SGPR_32, 105, 4, 9, "s">; 440 441// SGPR 320-bit registers. No operations use these, but for symmetry with 320-bit VGPRs. 442def SGPR_320Regs : SIRegisterTuples<getSubRegs<10>.ret, SGPR_32, 105, 4, 10, "s">; 443 444// SGPR 352-bit registers. No operations use these, but for symmetry with 352-bit VGPRs. 445def SGPR_352Regs : SIRegisterTuples<getSubRegs<11>.ret, SGPR_32, 105, 4, 11, "s">; 446 447// SGPR 384-bit registers. No operations use these, but for symmetry with 384-bit VGPRs. 448def SGPR_384Regs : SIRegisterTuples<getSubRegs<12>.ret, SGPR_32, 105, 4, 12, "s">; 449 450// SGPR 512-bit registers 451def SGPR_512Regs : SIRegisterTuples<getSubRegs<16>.ret, SGPR_32, 105, 4, 16, "s">; 452 453// SGPR 1024-bit registers 454def SGPR_1024Regs : SIRegisterTuples<getSubRegs<32>.ret, SGPR_32, 105, 4, 32, "s">; 455 456// Trap handler TMP 32-bit registers 457def TTMP_32 : SIRegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16, v2bf16], 32, 458 (add (sequence "TTMP%u", 0, 15))> { 459 let isAllocatable = 0; 460 let HasSGPR = 1; 461} 462 463// Trap handler TMP 16-bit registers 464def TTMP_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16, 465 (add (sequence "TTMP%u_LO16", 0, 15))> { 466 let Size = 16; 467 let isAllocatable = 0; 468 let HasSGPR = 1; 469} 470 471// Trap handler TMP 64-bit registers 472def TTMP_64Regs : SIRegisterTuples<getSubRegs<2>.ret, TTMP_32, 15, 2, 2, "ttmp">; 473 474// Trap handler TMP 96-bit registers 475def TTMP_96Regs : SIRegisterTuples<getSubRegs<3>.ret, TTMP_32, 15, 3, 3, "ttmp">; 476 477// Trap handler TMP 128-bit registers 478def TTMP_128Regs : SIRegisterTuples<getSubRegs<4>.ret, TTMP_32, 15, 4, 4, "ttmp">; 479 480// Trap handler TMP 160-bit registers 481def TTMP_160Regs : SIRegisterTuples<getSubRegs<5>.ret, TTMP_32, 15, 4, 5, "ttmp">; 482 483// Trap handler TMP 192-bit registers 484def TTMP_192Regs : SIRegisterTuples<getSubRegs<6>.ret, TTMP_32, 15, 4, 6, "ttmp">; 485 486// Trap handler TMP 224-bit registers 487def TTMP_224Regs : SIRegisterTuples<getSubRegs<7>.ret, TTMP_32, 15, 4, 7, "ttmp">; 488 489// Trap handler TMP 256-bit registers 490def TTMP_256Regs : SIRegisterTuples<getSubRegs<8>.ret, TTMP_32, 15, 4, 8, "ttmp">; 491 492// Trap handler TMP 288-bit registers 493def TTMP_288Regs : SIRegisterTuples<getSubRegs<9>.ret, TTMP_32, 15, 4, 9, "ttmp">; 494 495// Trap handler TMP 320-bit registers 496def TTMP_320Regs : SIRegisterTuples<getSubRegs<10>.ret, TTMP_32, 15, 4, 10, "ttmp">; 497 498// Trap handler TMP 352-bit registers 499def TTMP_352Regs : SIRegisterTuples<getSubRegs<11>.ret, TTMP_32, 15, 4, 11, "ttmp">; 500 501// Trap handler TMP 384-bit registers 502def TTMP_384Regs : SIRegisterTuples<getSubRegs<12>.ret, TTMP_32, 15, 4, 12, "ttmp">; 503 504// Trap handler TMP 512-bit registers 505def TTMP_512Regs : SIRegisterTuples<getSubRegs<16>.ret, TTMP_32, 15, 4, 16, "ttmp">; 506 507class TmpRegTuplesBase<int index, int size, 508 list<Register> subRegs, 509 list<SubRegIndex> indices = getSubRegs<size>.ret, 510 int index1 = !add(index, size, -1), 511 string name = "ttmp["#index#":"#index1#"]"> : 512 RegisterWithSubRegs<name, subRegs> { 513 let HWEncoding = subRegs[0].HWEncoding; 514 let SubRegIndices = indices; 515} 516 517class TmpRegTuples<string tgt, 518 int size, 519 int index0, 520 int index1 = !add(index0, 1), 521 int index2 = !add(index0, !if(!eq(size, 2), 1, 2)), 522 int index3 = !add(index0, !if(!eq(size, 2), 1, 3)), 523 int index4 = !add(index0, !if(!eq(size, 8), 4, 1)), 524 int index5 = !add(index0, !if(!eq(size, 8), 5, 1)), 525 int index6 = !add(index0, !if(!eq(size, 8), 6, 1)), 526 int index7 = !add(index0, !if(!eq(size, 8), 7, 1)), 527 Register r0 = !cast<Register>("TTMP"#index0#tgt), 528 Register r1 = !cast<Register>("TTMP"#index1#tgt), 529 Register r2 = !cast<Register>("TTMP"#index2#tgt), 530 Register r3 = !cast<Register>("TTMP"#index3#tgt), 531 Register r4 = !cast<Register>("TTMP"#index4#tgt), 532 Register r5 = !cast<Register>("TTMP"#index5#tgt), 533 Register r6 = !cast<Register>("TTMP"#index6#tgt), 534 Register r7 = !cast<Register>("TTMP"#index7#tgt)> : 535 TmpRegTuplesBase<index0, size, 536 !if(!eq(size, 2), [r0, r1], 537 !if(!eq(size, 4), [r0, r1, r2, r3], 538 [r0, r1, r2, r3, r4, r5, r6, r7])), 539 getSubRegs<size>.ret>; 540 541foreach Index = {0, 2, 4, 6, 8, 10, 12, 14} in { 542 def TTMP#Index#_TTMP#!add(Index,1)#_vi : TmpRegTuples<"_vi", 2, Index>; 543 def TTMP#Index#_TTMP#!add(Index,1)#_gfx9plus : TmpRegTuples<"_gfx9plus", 2, Index>; 544} 545 546foreach Index = {0, 4, 8, 12} in { 547 def TTMP#Index#_TTMP#!add(Index,1)# 548 _TTMP#!add(Index,2)# 549 _TTMP#!add(Index,3)#_vi : TmpRegTuples<"_vi", 4, Index>; 550 def TTMP#Index#_TTMP#!add(Index,1)# 551 _TTMP#!add(Index,2)# 552 _TTMP#!add(Index,3)#_gfx9plus : TmpRegTuples<"_gfx9plus", 4, Index>; 553} 554 555foreach Index = {0, 4, 8} in { 556 def TTMP#Index#_TTMP#!add(Index,1)# 557 _TTMP#!add(Index,2)# 558 _TTMP#!add(Index,3)# 559 _TTMP#!add(Index,4)# 560 _TTMP#!add(Index,5)# 561 _TTMP#!add(Index,6)# 562 _TTMP#!add(Index,7)#_vi : TmpRegTuples<"_vi", 8, Index>; 563 def TTMP#Index#_TTMP#!add(Index,1)# 564 _TTMP#!add(Index,2)# 565 _TTMP#!add(Index,3)# 566 _TTMP#!add(Index,4)# 567 _TTMP#!add(Index,5)# 568 _TTMP#!add(Index,6)# 569 _TTMP#!add(Index,7)#_gfx9plus : TmpRegTuples<"_gfx9plus", 8, Index>; 570} 571 572def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_vi : 573 TmpRegTuplesBase<0, 16, 574 [TTMP0_vi, TTMP1_vi, TTMP2_vi, TTMP3_vi, 575 TTMP4_vi, TTMP5_vi, TTMP6_vi, TTMP7_vi, 576 TTMP8_vi, TTMP9_vi, TTMP10_vi, TTMP11_vi, 577 TTMP12_vi, TTMP13_vi, TTMP14_vi, TTMP15_vi]>; 578 579def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_gfx9plus : 580 TmpRegTuplesBase<0, 16, 581 [TTMP0_gfx9plus, TTMP1_gfx9plus, TTMP2_gfx9plus, TTMP3_gfx9plus, 582 TTMP4_gfx9plus, TTMP5_gfx9plus, TTMP6_gfx9plus, TTMP7_gfx9plus, 583 TTMP8_gfx9plus, TTMP9_gfx9plus, TTMP10_gfx9plus, TTMP11_gfx9plus, 584 TTMP12_gfx9plus, TTMP13_gfx9plus, TTMP14_gfx9plus, TTMP15_gfx9plus]>; 585 586class RegisterTypes<list<ValueType> reg_types> { 587 list<ValueType> types = reg_types; 588} 589 590def Reg16Types : RegisterTypes<[i16, f16, bf16]>; 591def Reg32Types : RegisterTypes<[i32, f32, v2i16, v2f16, v2bf16, p2, p3, p5, p6]>; 592def Reg64Types : RegisterTypes<[i64, f64, v2i32, v2f32, p0, p1, p4, v4i16, v4f16, v4bf16]>; 593def Reg96Types : RegisterTypes<[v3i32, v3f32]>; 594def Reg128Types : RegisterTypes<[v4i32, v4f32, v2i64, v2f64, v8i16, v8f16, v8bf16]>; 595 596let HasVGPR = 1 in { 597// VOP3 and VINTERP can access 256 lo and 256 hi registers. 598def VGPR_16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 599 (add (interleave (sequence "VGPR%u_LO16", 0, 255), 600 (sequence "VGPR%u_HI16", 0, 255)))> { 601 let AllocationPriority = 2; 602 let Size = 16; 603 let GeneratePressureSet = 0; 604 605 // This is the base class for VGPR{128..255}_{LO16,HI16}. 606 let BaseClassOrder = 17; 607} 608 609// VOP1/2/C can access the First 128 lo and 128 hi registers. 610// The order of registers in the class determines order of allocation, so it is 611// important to interleave lo and hi registers. 612def VGPR_16_Lo128 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 613 (add (interleave (sequence "VGPR%u_LO16", 0, 127), 614 (sequence "VGPR%u_HI16", 0, 127)))> { 615 let Size = 16; 616 let GeneratePressureSet = 0; 617 let isAllocatable = 0; 618 619 // This is the base class for VGPR{0..127}_{LO16,HI16}. 620 let BaseClassOrder = 16; 621} 622 623// VGPR 32-bit registers 624// i16/f16 only on VI+ 625def VGPR_32 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32, 626 (add (sequence "VGPR%u", 0, 255))> { 627 let AllocationPriority = 0; 628 let Size = 32; 629 let Weight = 1; 630 let BaseClassOrder = 32; 631} 632 633// Identical to VGPR_32 except it only contains the low 128 (Lo128) registers. 634def VGPR_32_Lo128 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32, 635 (add (sequence "VGPR%u", 0, 127))> { 636 let AllocationPriority = 0; 637 let GeneratePressureSet = 0; 638 let Size = 32; 639 let Weight = 1; 640} 641} // End HasVGPR = 1 642 643// VGPR 64-bit registers 644def VGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, VGPR_32, 255, 1, 2, "v">; 645 646// VGPR 96-bit registers 647def VGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, VGPR_32, 255, 1, 3, "v">; 648 649// VGPR 128-bit registers 650def VGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, VGPR_32, 255, 1, 4, "v">; 651 652// VGPR 160-bit registers 653def VGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, VGPR_32, 255, 1, 5, "v">; 654 655// VGPR 192-bit registers 656def VGPR_192 : SIRegisterTuples<getSubRegs<6>.ret, VGPR_32, 255, 1, 6, "v">; 657 658// VGPR 224-bit registers 659def VGPR_224 : SIRegisterTuples<getSubRegs<7>.ret, VGPR_32, 255, 1, 7, "v">; 660 661// VGPR 256-bit registers 662def VGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, VGPR_32, 255, 1, 8, "v">; 663 664// VGPR 288-bit registers 665def VGPR_288 : SIRegisterTuples<getSubRegs<9>.ret, VGPR_32, 255, 1, 9, "v">; 666 667// VGPR 320-bit registers 668def VGPR_320 : SIRegisterTuples<getSubRegs<10>.ret, VGPR_32, 255, 1, 10, "v">; 669 670// VGPR 352-bit registers 671def VGPR_352 : SIRegisterTuples<getSubRegs<11>.ret, VGPR_32, 255, 1, 11, "v">; 672 673// VGPR 384-bit registers 674def VGPR_384 : SIRegisterTuples<getSubRegs<12>.ret, VGPR_32, 255, 1, 12, "v">; 675 676// VGPR 512-bit registers 677def VGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, VGPR_32, 255, 1, 16, "v">; 678 679// VGPR 1024-bit registers 680def VGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, VGPR_32, 255, 1, 32, "v">; 681 682let HasAGPR = 1 in { 683def AGPR_LO16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 684 (add (sequence "AGPR%u_LO16", 0, 255))> { 685 let isAllocatable = 0; 686 let Size = 16; 687 let GeneratePressureSet = 0; 688 let BaseClassOrder = 16; 689} 690 691// AccVGPR 32-bit registers 692def AGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32, 693 (add (sequence "AGPR%u", 0, 255))> { 694 let AllocationPriority = 0; 695 let Size = 32; 696 let Weight = 1; 697 let BaseClassOrder = 32; 698} 699} // End HasAGPR = 1 700 701// AGPR 64-bit registers 702def AGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, AGPR_32, 255, 1, 2, "a">; 703 704// AGPR 96-bit registers 705def AGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, AGPR_32, 255, 1, 3, "a">; 706 707// AGPR 128-bit registers 708def AGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, AGPR_32, 255, 1, 4, "a">; 709 710// AGPR 160-bit registers 711def AGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, AGPR_32, 255, 1, 5, "a">; 712 713// AGPR 192-bit registers 714def AGPR_192 : SIRegisterTuples<getSubRegs<6>.ret, AGPR_32, 255, 1, 6, "a">; 715 716// AGPR 224-bit registers 717def AGPR_224 : SIRegisterTuples<getSubRegs<7>.ret, AGPR_32, 255, 1, 7, "a">; 718 719// AGPR 256-bit registers 720def AGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, AGPR_32, 255, 1, 8, "a">; 721 722// AGPR 288-bit registers 723def AGPR_288 : SIRegisterTuples<getSubRegs<9>.ret, AGPR_32, 255, 1, 9, "a">; 724 725// AGPR 320-bit registers 726def AGPR_320 : SIRegisterTuples<getSubRegs<10>.ret, AGPR_32, 255, 1, 10, "a">; 727 728// AGPR 352-bit registers 729def AGPR_352 : SIRegisterTuples<getSubRegs<11>.ret, AGPR_32, 255, 1, 11, "a">; 730 731// AGPR 384-bit registers 732def AGPR_384 : SIRegisterTuples<getSubRegs<12>.ret, AGPR_32, 255, 1, 12, "a">; 733 734// AGPR 512-bit registers 735def AGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, AGPR_32, 255, 1, 16, "a">; 736 737// AGPR 1024-bit registers 738def AGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, AGPR_32, 255, 1, 32, "a">; 739 740//===----------------------------------------------------------------------===// 741// Register classes used as source and destination 742//===----------------------------------------------------------------------===// 743 744def Pseudo_SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32, 745 (add FP_REG, SP_REG)> { 746 let isAllocatable = 0; 747 let CopyCost = -1; 748 let HasSGPR = 1; 749 let BaseClassOrder = 10000; 750} 751 752def Pseudo_SReg_128 : SIRegisterClass<"AMDGPU", Reg128Types.types, 32, 753 (add PRIVATE_RSRC_REG)> { 754 let isAllocatable = 0; 755 let CopyCost = -1; 756 let HasSGPR = 1; 757 let BaseClassOrder = 10000; 758} 759 760def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32], 32, 761 (add LDS_DIRECT)> { 762 let isAllocatable = 0; 763 let CopyCost = -1; 764} 765 766let GeneratePressureSet = 0, HasSGPR = 1 in { 767// Subset of SReg_32 without M0 for SMRD instructions and alike. 768// See comments in SIInstructions.td for more info. 769def SReg_32_XM0_XEXEC : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32, 770 (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI, 771 SGPR_NULL, SGPR_NULL_HI, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE_LO, 772 SRC_SHARED_LIMIT_LO, SRC_PRIVATE_BASE_LO, SRC_PRIVATE_LIMIT_LO, SRC_SHARED_BASE_HI, 773 SRC_SHARED_LIMIT_HI, SRC_PRIVATE_BASE_HI, SRC_PRIVATE_LIMIT_HI, SRC_POPS_EXITING_WAVE_ID, 774 SRC_VCCZ, SRC_EXECZ, SRC_SCC)> { 775 let AllocationPriority = 0; 776} 777 778def SReg_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16, 779 (add SGPR_LO16, VCC_LO_LO16, VCC_HI_LO16, FLAT_SCR_LO_LO16, FLAT_SCR_HI_LO16, 780 XNACK_MASK_LO_LO16, XNACK_MASK_HI_LO16, SGPR_NULL_LO16, SGPR_NULL_HI_LO16, TTMP_LO16, 781 TMA_LO_LO16, TMA_HI_LO16, TBA_LO_LO16, TBA_HI_LO16, SRC_SHARED_BASE_LO_LO16, 782 SRC_SHARED_LIMIT_LO_LO16, SRC_PRIVATE_BASE_LO_LO16, SRC_PRIVATE_LIMIT_LO_LO16, 783 SRC_SHARED_BASE_HI_LO16, SRC_SHARED_LIMIT_HI_LO16, SRC_PRIVATE_BASE_HI_LO16, 784 SRC_PRIVATE_LIMIT_HI_LO16, SRC_POPS_EXITING_WAVE_ID_LO16, SRC_VCCZ_LO16, 785 SRC_EXECZ_LO16, SRC_SCC_LO16, EXEC_LO_LO16, EXEC_HI_LO16, M0_CLASS_LO16)> { 786 let Size = 16; 787 let isAllocatable = 0; 788 let BaseClassOrder = 16; 789} 790 791def SReg_32_XEXEC : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32, 792 (add SReg_32_XM0_XEXEC, M0_CLASS)> { 793 let AllocationPriority = 0; 794} 795 796def SReg_32_XEXEC_HI : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32, 797 (add SReg_32_XEXEC, EXEC_LO)> { 798 let AllocationPriority = 0; 799} 800 801def SReg_32_XM0 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32, 802 (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> { 803 let AllocationPriority = 0; 804} 805 806} // End GeneratePressureSet = 0 807 808// Register class for all scalar registers (SGPRs + Special Registers) 809def SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32, 810 (add SReg_32_XM0, M0_CLASS)> { 811 let AllocationPriority = 0; 812 let HasSGPR = 1; 813 let BaseClassOrder = 32; 814} 815 816def SGPR_NULL128 : SIReg<"null">; 817def SGPR_NULL256 : SIReg<"null">; 818 819let GeneratePressureSet = 0 in { 820def SRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32, 821 (add SReg_32, LDS_DIRECT_CLASS)> { 822 let isAllocatable = 0; 823 let HasSGPR = 1; 824} 825 826def SGPR_64 : SIRegisterClass<"AMDGPU", Reg64Types.types, 32, 827 (add SGPR_64Regs)> { 828 let CopyCost = 1; 829 let AllocationPriority = 1; 830 let HasSGPR = 1; 831} 832 833// CCR (call clobbered registers) SGPR 64-bit registers 834def CCR_SGPR_64 : SIRegisterClass<"AMDGPU", SGPR_64.RegTypes, 32, (add (trunc SGPR_64, 15))> { 835 let CopyCost = SGPR_64.CopyCost; 836 let AllocationPriority = SGPR_64.AllocationPriority; 837 let HasSGPR = 1; 838} 839 840// Call clobbered 64-bit SGPRs for AMDGPU_Gfx CC 841def Gfx_CCR_SGPR_64 : SIRegisterClass<"AMDGPU", SGPR_64.RegTypes, 32, 842 (add (trunc (shl SGPR_64, 18), 14))> { // s[36:37]-s[s62:63] 843 let CopyCost = SGPR_64.CopyCost; 844 let AllocationPriority = SGPR_64.AllocationPriority; 845 let HasSGPR = 1; 846} 847 848def TTMP_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16, v4bf16], 32, 849 (add TTMP_64Regs)> { 850 let isAllocatable = 0; 851 let HasSGPR = 1; 852} 853 854def SReg_64_XEXEC_XNULL : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16, v4bf16], 32, 855 (add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, SRC_SHARED_BASE, 856 SRC_SHARED_LIMIT, SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, TTMP_64, TBA, TMA)> { 857 let CopyCost = 1; 858 let AllocationPriority = 1; 859 let HasSGPR = 1; 860} 861 862def SReg_64_XEXEC : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16, v4bf16], 32, 863 (add SReg_64_XEXEC_XNULL, SGPR_NULL64)> { 864 let CopyCost = 1; 865 let AllocationPriority = 1; 866 let HasSGPR = 1; 867} 868 869def SReg_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16, v4bf16], 32, 870 (add SReg_64_XEXEC, EXEC)> { 871 let CopyCost = 1; 872 let AllocationPriority = 1; 873 let HasSGPR = 1; 874 let BaseClassOrder = 64; 875} 876 877def SReg_1_XEXEC : SIRegisterClass<"AMDGPU", [i1], 32, 878 (add SReg_64_XEXEC, SReg_32_XEXEC)> { 879 let CopyCost = 1; 880 let isAllocatable = 0; 881 let HasSGPR = 1; 882} 883 884def SReg_1 : SIRegisterClass<"AMDGPU", [i1], 32, 885 (add SReg_1_XEXEC, EXEC, EXEC_LO, EXEC_HI)> { 886 let CopyCost = 1; 887 let isAllocatable = 0; 888 let HasSGPR = 1; 889} 890 891multiclass SRegClass<int numRegs, 892 list<ValueType> regTypes, 893 SIRegisterTuples regList, 894 SIRegisterTuples ttmpList = regList, 895 bit hasNull = 0, 896 int copyCost = !sra(!add(numRegs, 1), 1)> { 897 defvar hasTTMP = !ne(regList, ttmpList); 898 defvar suffix = !cast<string>(!mul(numRegs, 32)); 899 defvar sgprName = !strconcat("SGPR_", suffix); 900 defvar ttmpName = !strconcat("TTMP_", suffix); 901 902 let AllocationPriority = !sub(numRegs, 1), CopyCost = copyCost, HasSGPR = 1 in { 903 def "" # sgprName : SIRegisterClass<"AMDGPU", regTypes, 32, (add regList)> { 904 } 905 906 if hasTTMP then { 907 def "" # ttmpName : SIRegisterClass<"AMDGPU", regTypes, 32, (add ttmpList)> { 908 let isAllocatable = 0; 909 } 910 } 911 912 def SReg_ # suffix # !if(hasNull, "_XNULL", ""): 913 SIRegisterClass<"AMDGPU", regTypes, 32, 914 !con((add !cast<RegisterClass>(sgprName)), 915 !if(hasTTMP, 916 (add !cast<RegisterClass>(ttmpName)), 917 (add)))> { 918 let isAllocatable = 0; 919 let BaseClassOrder = !mul(numRegs, 32); 920 } 921 922 if hasNull then { 923 def SReg_ # suffix : 924 SIRegisterClass<"AMDGPU", regTypes, 32, 925 (add !cast<RegisterClass>("SReg_" # suffix # "_XNULL"), !cast<Register>("SGPR_NULL" # suffix))> { 926 let isAllocatable = 0; 927 let BaseClassOrder = !mul(numRegs, 32); 928 } 929 } 930 } 931} 932 933defm "" : SRegClass<3, Reg96Types.types, SGPR_96Regs, TTMP_96Regs>; 934defm "" : SRegClass<4, Reg128Types.types, SGPR_128Regs, TTMP_128Regs, /*hasNull*/ true>; 935defm "" : SRegClass<5, [v5i32, v5f32], SGPR_160Regs, TTMP_160Regs>; 936defm "" : SRegClass<6, [v6i32, v6f32, v3i64, v3f64], SGPR_192Regs, TTMP_192Regs>; 937defm "" : SRegClass<7, [v7i32, v7f32], SGPR_224Regs, TTMP_224Regs>; 938defm "" : SRegClass<8, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16, v16bf16], SGPR_256Regs, TTMP_256Regs, /*hasNull*/ true>; 939defm "" : SRegClass<9, [v9i32, v9f32], SGPR_288Regs, TTMP_288Regs>; 940defm "" : SRegClass<10, [v10i32, v10f32], SGPR_320Regs, TTMP_320Regs>; 941defm "" : SRegClass<11, [v11i32, v11f32], SGPR_352Regs, TTMP_352Regs>; 942defm "" : SRegClass<12, [v12i32, v12f32], SGPR_384Regs, TTMP_384Regs>; 943 944let GlobalPriority = true in { 945defm "" : SRegClass<16, [v16i32, v16f32, v8i64, v8f64, v32i16, v32f16, v32bf16], SGPR_512Regs, TTMP_512Regs>; 946defm "" : SRegClass<32, [v32i32, v32f32, v16i64, v16f64], SGPR_1024Regs>; 947} 948 949def VRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32, 950 (add VGPR_32, LDS_DIRECT_CLASS)> { 951 let isAllocatable = 0; 952 let HasVGPR = 1; 953} 954 955// Register class for all vector registers (VGPRs + Interpolation Registers) 956class VRegClassBase<int numRegs, list<ValueType> regTypes, dag regList> : 957 SIRegisterClass<"AMDGPU", regTypes, 32, regList> { 958 let Size = !mul(numRegs, 32); 959 960 // Requires n v_mov_b32 to copy 961 let CopyCost = numRegs; 962 let AllocationPriority = !sub(numRegs, 1); 963 let Weight = numRegs; 964} 965 966// Define a register tuple class, along with one requiring an even 967// aligned base register. 968multiclass VRegClass<int numRegs, list<ValueType> regTypes, dag regList> { 969 let HasVGPR = 1 in { 970 // Define the regular class. 971 def "" : VRegClassBase<numRegs, regTypes, regList> { 972 let BaseClassOrder = !mul(numRegs, 32); 973 } 974 975 // Define 2-aligned variant 976 def _Align2 : VRegClassBase<numRegs, regTypes, (decimate regList, 2)> { 977 // Give aligned class higher priority in base class resolution 978 let BaseClassOrder = !sub(!mul(numRegs, 32), 1); 979 let RegTupleAlignUnits = 2; 980 } 981 } 982} 983 984defm VReg_64 : VRegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4bf16, v4i16, p0, p1, p4], 985 (add VGPR_64)>; 986defm VReg_96 : VRegClass<3, Reg96Types.types, (add VGPR_96)>; 987defm VReg_128 : VRegClass<4, Reg128Types.types, (add VGPR_128)>; 988defm VReg_160 : VRegClass<5, [v5i32, v5f32], (add VGPR_160)>; 989 990defm VReg_192 : VRegClass<6, [v6i32, v6f32, v3i64, v3f64], (add VGPR_192)>; 991defm VReg_224 : VRegClass<7, [v7i32, v7f32], (add VGPR_224)>; 992defm VReg_256 : VRegClass<8, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16, v16bf16], (add VGPR_256)>; 993defm VReg_288 : VRegClass<9, [v9i32, v9f32], (add VGPR_288)>; 994defm VReg_320 : VRegClass<10, [v10i32, v10f32], (add VGPR_320)>; 995defm VReg_352 : VRegClass<11, [v11i32, v11f32], (add VGPR_352)>; 996defm VReg_384 : VRegClass<12, [v12i32, v12f32], (add VGPR_384)>; 997 998let GlobalPriority = true in { 999defm VReg_512 : VRegClass<16, [v16i32, v16f32, v8i64, v8f64, v32i16, v32f16, v32bf16], (add VGPR_512)>; 1000defm VReg_1024 : VRegClass<32, [v32i32, v32f32, v16i64, v16f64], (add VGPR_1024)>; 1001} 1002 1003multiclass ARegClass<int numRegs, list<ValueType> regTypes, dag regList> { 1004 let CopyCost = !add(numRegs, numRegs, 1), HasAGPR = 1 in { 1005 // Define the regular class. 1006 def "" : VRegClassBase<numRegs, regTypes, regList> { 1007 let BaseClassOrder = !mul(numRegs, 32); 1008 } 1009 1010 // Define 2-aligned variant 1011 def _Align2 : VRegClassBase<numRegs, regTypes, (decimate regList, 2)> { 1012 // Give aligned class higher priority in base class resolution 1013 let BaseClassOrder = !sub(!mul(numRegs, 32), 1); 1014 let RegTupleAlignUnits = 2; 1015 } 1016 } 1017} 1018 1019defm AReg_64 : ARegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16], 1020 (add AGPR_64)>; 1021defm AReg_96 : ARegClass<3, [v3i32, v3f32], (add AGPR_96)>; 1022defm AReg_128 : ARegClass<4, [v4i32, v4f32, v2i64, v2f64, v8i16, v8f16, v8bf16], (add AGPR_128)>; 1023defm AReg_160 : ARegClass<5, [v5i32, v5f32], (add AGPR_160)>; 1024defm AReg_192 : ARegClass<6, [v6i32, v6f32, v3i64, v3f64], (add AGPR_192)>; 1025defm AReg_224 : ARegClass<7, [v7i32, v7f32], (add AGPR_224)>; 1026defm AReg_256 : ARegClass<8, [v8i32, v8f32, v4i64, v4f64], (add AGPR_256)>; 1027defm AReg_288 : ARegClass<9, [v9i32, v9f32], (add AGPR_288)>; 1028defm AReg_320 : ARegClass<10, [v10i32, v10f32], (add AGPR_320)>; 1029defm AReg_352 : ARegClass<11, [v11i32, v11f32], (add AGPR_352)>; 1030defm AReg_384 : ARegClass<12, [v12i32, v12f32], (add AGPR_384)>; 1031 1032let GlobalPriority = true in { 1033defm AReg_512 : ARegClass<16, [v16i32, v16f32, v8i64, v8f64], (add AGPR_512)>; 1034defm AReg_1024 : ARegClass<32, [v32i32, v32f32, v16i64, v16f64], (add AGPR_1024)>; 1035} 1036 1037} // End GeneratePressureSet = 0 1038 1039let GeneratePressureSet = 0 in { 1040// No register should ever be allocated using VReg_1. This is a hack for 1041// SelectionDAG that should always be lowered by SILowerI1Copies. TableGen 1042// sorts register classes based on the number of registers in them so this is 1043// sorted to the end and not preferred over VGPR_32. 1044def VReg_1 : SIRegisterClass<"AMDGPU", [i1], 32, (add)> { 1045 let Size = 1; 1046 let HasVGPR = 1; 1047} 1048 1049def VS_16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 1050 (add VGPR_16, SReg_32, LDS_DIRECT_CLASS)> { 1051 let isAllocatable = 0; 1052 let HasVGPR = 1; 1053} 1054 1055def VS_16_Lo128 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 1056 (add VGPR_16_Lo128, SReg_32, LDS_DIRECT_CLASS)> { 1057 let isAllocatable = 0; 1058 let HasVGPR = 1; 1059} 1060 1061def VS_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32, 1062 (add VGPR_32, SReg_32, LDS_DIRECT_CLASS)> { 1063 let isAllocatable = 0; 1064 let HasVGPR = 1; 1065 let HasSGPR = 1; 1066} 1067 1068def VS_32_Lo128 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32, 1069 (add VGPR_32_Lo128, SReg_32, LDS_DIRECT_CLASS)> { 1070 let isAllocatable = 0; 1071 let HasVGPR = 1; 1072 let HasSGPR = 1; 1073} 1074 1075def VS_64 : SIRegisterClass<"AMDGPU", VReg_64.RegTypes, 32, (add VReg_64, SReg_64)> { 1076 let isAllocatable = 0; 1077 let HasVGPR = 1; 1078 let HasSGPR = 1; 1079} 1080 1081def AV_32 : SIRegisterClass<"AMDGPU", VGPR_32.RegTypes, 32, (add VGPR_32, AGPR_32)> { 1082 let HasVGPR = 1; 1083 let HasAGPR = 1; 1084} 1085} // End GeneratePressureSet = 0 1086 1087// Define a register tuple class, along with one requiring an even 1088// aligned base register. 1089multiclass AVRegClass<int numRegs, list<ValueType> regTypes, 1090 dag vregList, dag aregList> { 1091 let HasVGPR = 1, HasAGPR = 1 in { 1092 // Define the regular class. 1093 def "" : VRegClassBase<numRegs, regTypes, (add vregList, aregList)>; 1094 1095 // Define 2-aligned variant 1096 def _Align2 : VRegClassBase<numRegs, regTypes, 1097 (add (decimate vregList, 2), 1098 (decimate aregList, 2))> { 1099 let RegTupleAlignUnits = 2; 1100 } 1101 } 1102} 1103 1104defm AV_64 : AVRegClass<2, VReg_64.RegTypes, (add VGPR_64), (add AGPR_64)>; 1105defm AV_96 : AVRegClass<3, VReg_96.RegTypes, (add VGPR_96), (add AGPR_96)>; 1106defm AV_128 : AVRegClass<4, VReg_128.RegTypes, (add VGPR_128), (add AGPR_128)>; 1107defm AV_160 : AVRegClass<5, VReg_160.RegTypes, (add VGPR_160), (add AGPR_160)>; 1108defm AV_192 : AVRegClass<6, VReg_192.RegTypes, (add VGPR_192), (add AGPR_192)>; 1109defm AV_224 : AVRegClass<7, VReg_224.RegTypes, (add VGPR_224), (add AGPR_224)>; 1110defm AV_256 : AVRegClass<8, VReg_256.RegTypes, (add VGPR_256), (add AGPR_256)>; 1111defm AV_288 : AVRegClass<9, VReg_288.RegTypes, (add VGPR_288), (add AGPR_288)>; 1112defm AV_320 : AVRegClass<10, VReg_320.RegTypes, (add VGPR_320), (add AGPR_320)>; 1113defm AV_352 : AVRegClass<11, VReg_352.RegTypes, (add VGPR_352), (add AGPR_352)>; 1114defm AV_384 : AVRegClass<12, VReg_384.RegTypes, (add VGPR_384), (add AGPR_384)>; 1115 1116let GlobalPriority = true in { 1117defm AV_512 : AVRegClass<16, VReg_512.RegTypes, (add VGPR_512), (add AGPR_512)>; 1118defm AV_1024 : AVRegClass<32, VReg_1024.RegTypes, (add VGPR_1024), (add AGPR_1024)>; 1119} 1120 1121//===----------------------------------------------------------------------===// 1122// Register operands 1123//===----------------------------------------------------------------------===// 1124 1125class RegImmMatcher<string name> : AsmOperandClass { 1126 let Name = name; 1127 let RenderMethod = "addRegOrImmOperands"; 1128} 1129 1130class RegOrImmOperand <RegisterClass RegClass, string OperandTypeName> 1131 : RegisterOperand<RegClass> { 1132 let OperandNamespace = "AMDGPU"; 1133 let OperandType = OperandTypeName; 1134 let ParserMatchClass = RegImmMatcher<!subst("_Deferred", "", NAME)>; 1135} 1136 1137// Should be in sync with the OperandSemantics defined in SIDefines.h 1138def OperandSemantics { 1139 int INT = 0; 1140 int FP16 = 1; 1141 int BF16 = 2; 1142 int FP32 = 3; 1143 int FP64 = 4; 1144} 1145 1146//===----------------------------------------------------------------------===// 1147// SSrc_* Operands with an SGPR or a 32-bit immediate 1148//===----------------------------------------------------------------------===// 1149 1150class SrcRegOrImm9<RegisterClass regClass, string opWidth, string operandType, 1151 int immWidth, int OperandSemantics> 1152 : RegOrImmOperand<regClass, operandType> { 1153 string DecoderMethodName = "decodeSrcRegOrImm9"; 1154 let DecoderMethod = DecoderMethodName # "<AMDGPUDisassembler::" # opWidth # 1155 ", " # immWidth # ", " # OperandSemantics # ">"; 1156} 1157 1158class SrcRegOrImm9_t16<string operandType, int OperandSemantics, RegisterClass regClass = VS_16> 1159 : SrcRegOrImm9<regClass, "OPW16", operandType, 16, OperandSemantics> { 1160 let DecoderMethodName = "decodeOperand_VSrcT16"; 1161 let EncoderMethod = "getMachineOpValueT16"; 1162} 1163 1164def SSrc_b16 : SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_INT16", 16, OperandSemantics.INT>; 1165def SSrc_bf16: SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_BF16", 16, OperandSemantics.BF16>; 1166def SSrc_f16 : SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_FP16", 16, OperandSemantics.FP16>; 1167def SSrc_b32 : SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_INT32", 32, OperandSemantics.INT>; 1168def SSrc_f32 : SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_FP32", 32, OperandSemantics.FP32>; 1169def SSrc_b64 : SrcRegOrImm9 <SReg_64, "OPW64", "OPERAND_REG_IMM_INT64", 64, OperandSemantics.INT>; 1170 1171def SSrcOrLds_b32 : SrcRegOrImm9 <SRegOrLds_32, "OPW32", "OPERAND_REG_IMM_INT32", 32, OperandSemantics.INT>; 1172 1173//===----------------------------------------------------------------------===// 1174// SSrc_32_Deferred Operands with an SGPR or a 32-bit immediate for use with 1175// FMAMK/FMAAK 1176//===----------------------------------------------------------------------===// 1177 1178class SrcRegOrImmDeferred9<RegisterClass regClass, string opWidth, 1179 string operandType, int immWidth, int OperandSemantics> 1180 : RegOrImmOperand<regClass, operandType> { 1181 string DecoderMethodName = "decodeSrcRegOrImmDeferred9"; 1182 let DecoderMethod = DecoderMethodName # "<AMDGPUDisassembler::" # 1183 opWidth # ", " # immWidth # ", " # OperandSemantics # ">"; 1184} 1185 1186def SSrc_f32_Deferred : SrcRegOrImmDeferred9<SReg_32, "OPW32", "OPERAND_REG_IMM_FP32_DEFERRED", 32, OperandSemantics.FP32>; 1187 1188//===----------------------------------------------------------------------===// 1189// SCSrc_* Operands with an SGPR or a inline constant 1190//===----------------------------------------------------------------------===// 1191 1192def SCSrc_b32 : SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_INLINE_C_INT32", 32, OperandSemantics.INT>; 1193def SCSrc_b64 : SrcRegOrImm9 <SReg_64, "OPW64", "OPERAND_REG_INLINE_C_INT64", 64, OperandSemantics.INT>; 1194 1195//===----------------------------------------------------------------------===// 1196// VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate 1197//===----------------------------------------------------------------------===// 1198 1199// The current and temporary future default used case for VOP3. 1200def VSrc_b16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_IMM_INT16", 16, OperandSemantics.INT>; 1201def VSrc_bf16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_IMM_BF16", 16, OperandSemantics.BF16>; 1202def VSrc_f16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_IMM_FP16", 16, OperandSemantics.FP16>; 1203 1204// True16 VOP3 operands. 1205def VSrcT_b16 : SrcRegOrImm9_t16 <"OPERAND_REG_IMM_INT16", OperandSemantics.INT>; 1206def VSrcT_bf16 : SrcRegOrImm9_t16 <"OPERAND_REG_IMM_BF16", OperandSemantics.BF16>; 1207def VSrcT_f16 : SrcRegOrImm9_t16 <"OPERAND_REG_IMM_FP16", OperandSemantics.FP16>; 1208 1209// True16 VOP1/2/C operands. 1210let DecoderMethodName = "decodeOperand_VSrcT16_Lo128", EncoderMethod = "getMachineOpValueT16Lo128" in { 1211 def VSrcT_b16_Lo128 : SrcRegOrImm9_t16 <"OPERAND_REG_IMM_INT16", OperandSemantics.INT, VS_16_Lo128>; 1212 def VSrcT_bf16_Lo128 : SrcRegOrImm9_t16 <"OPERAND_REG_IMM_BF16", OperandSemantics.BF16, VS_16_Lo128>; 1213 def VSrcT_f16_Lo128 : SrcRegOrImm9_t16 <"OPERAND_REG_IMM_FP16",OperandSemantics.FP16, VS_16_Lo128>; 1214} // End DecoderMethodName = "decodeOperand_VSrcT16_Lo128", EncoderMethod = "getMachineOpValueT16Lo128" 1215 1216// The current and temporary future default used case for fake VOP1/2/C. 1217// For VOP1,2,C True16 instructions. _Lo128 use first 128 32-bit VGPRs only. 1218def VSrcFake16_b16_Lo128 : SrcRegOrImm9 <VS_32_Lo128, "OPW16", "OPERAND_REG_IMM_INT16", 16, OperandSemantics.INT>; 1219def VSrcFake16_bf16_Lo128 : SrcRegOrImm9 <VS_32_Lo128, "OPW16", "OPERAND_REG_IMM_BF16", 16, OperandSemantics.BF16>; 1220def VSrcFake16_f16_Lo128 : SrcRegOrImm9 <VS_32_Lo128, "OPW16", "OPERAND_REG_IMM_FP16", 16, OperandSemantics.FP16>; 1221 1222def VSrc_b32 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_IMM_INT32", 32, OperandSemantics.INT>; 1223def VSrc_f32 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_IMM_FP32", 32, OperandSemantics.FP32>; 1224def VSrc_v2b16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_IMM_V2INT16", 32, OperandSemantics.INT>; 1225def VSrc_v2bf16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_IMM_V2BF16", 16, OperandSemantics.BF16>; 1226def VSrc_v2f16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_IMM_V2FP16", 16, OperandSemantics.FP16>; 1227def VSrc_b64 : SrcRegOrImm9 <VS_64, "OPW64", "OPERAND_REG_IMM_INT64", 64, OperandSemantics.INT>; 1228def VSrc_f64 : SrcRegOrImm9 <VS_64, "OPW64", "OPERAND_REG_IMM_FP64", 64, OperandSemantics.FP64> { 1229 let DecoderMethod = "decodeOperand_VSrc_f64"; 1230} 1231def VSrc_v2b32 : SrcRegOrImm9 <VS_64, "OPW64", "OPERAND_REG_IMM_V2INT32", 32, OperandSemantics.INT>; 1232def VSrc_v2f32 : SrcRegOrImm9 <VS_64, "OPW64", "OPERAND_REG_IMM_V2FP32", 32, OperandSemantics.FP32>; 1233 1234//===----------------------------------------------------------------------===// 1235// VSrc_*_Deferred Operands with an SGPR, VGPR or a 32-bit immediate for use 1236// with FMAMK/FMAAK 1237//===----------------------------------------------------------------------===// 1238 1239def VSrc_bf16_Deferred : SrcRegOrImmDeferred9<VS_32, "OPW16", "OPERAND_REG_IMM_BF16_DEFERRED", 16, OperandSemantics.BF16>; 1240def VSrc_f16_Deferred : SrcRegOrImmDeferred9<VS_32, "OPW16", "OPERAND_REG_IMM_FP16_DEFERRED", 16, OperandSemantics.FP16>; 1241def VSrc_f32_Deferred : SrcRegOrImmDeferred9<VS_32, "OPW32", "OPERAND_REG_IMM_FP32_DEFERRED", 32, OperandSemantics.FP32>; 1242 1243// True 16 Operands 1244def VSrcT_f16_Lo128_Deferred : SrcRegOrImmDeferred9<VS_16_Lo128, "OPW16", 1245 "OPERAND_REG_IMM_FP16_DEFERRED", 16, OperandSemantics.FP16> { 1246 let DecoderMethodName = "decodeOperand_VSrcT16_Lo128_Deferred"; 1247 let EncoderMethod = "getMachineOpValueT16Lo128"; 1248} 1249 1250def VSrcFake16_bf16_Lo128_Deferred 1251 : SrcRegOrImmDeferred9<VS_32_Lo128, "OPW16", "OPERAND_REG_IMM_BF16_DEFERRED", 16, OperandSemantics.BF16>; 1252def VSrcFake16_f16_Lo128_Deferred 1253 : SrcRegOrImmDeferred9<VS_32_Lo128, "OPW16", "OPERAND_REG_IMM_FP16_DEFERRED", 16, OperandSemantics.FP16>; 1254 1255//===----------------------------------------------------------------------===// 1256// VRegSrc_* Operands with a VGPR 1257//===----------------------------------------------------------------------===// 1258 1259// This is for operands with the enum(9), VSrc encoding restriction, 1260// but only allows VGPRs. 1261class SrcReg9<RegisterClass regClass, string width> : RegisterOperand<regClass> { 1262 let DecoderMethod = "decodeSrcReg9<AMDGPUDisassembler::" # width # ">"; 1263} 1264 1265def VRegSrc_32 : SrcReg9<VGPR_32, "OPW32">; 1266def VRegSrc_64 : SrcReg9<VReg_64, "OPW64">; 1267def VRegSrc_96 : SrcReg9<VReg_96, "OPW96">; 1268def VRegSrc_128: SrcReg9<VReg_128, "OPW128">; 1269def VRegSrc_192: SrcReg9<VReg_192, "OPW192">; 1270def VRegSrc_256: SrcReg9<VReg_256, "OPW256">; 1271def VRegSrc_512: SrcReg9<VReg_512, "OPW512">; 1272def VRegSrc_1024: SrcReg9<VReg_1024, "OPW1024">; 1273def VRegOrLdsSrc_32 : SrcReg9<VRegOrLds_32, "OPW32">; 1274 1275// True 16 Operands 1276def VRegSrc_16 : RegisterOperand<VGPR_16> { 1277 let DecoderMethod = "decodeOperand_VGPR_16"; 1278 let EncoderMethod = "getMachineOpValueT16"; 1279} 1280def VRegSrc_fake16: SrcReg9<VGPR_32, "OPW16"> { 1281 let EncoderMethod = "getMachineOpValueT16"; 1282} 1283//===----------------------------------------------------------------------===// 1284// VGPRSrc_* 1285//===----------------------------------------------------------------------===// 1286 1287// An 8-bit RegisterOperand wrapper for a VGPR 1288def VGPRSrc_32 : RegisterOperand<VGPR_32> { 1289 let DecoderMethod = "DecodeVGPR_32RegisterClass"; 1290} 1291def VGPRSrc_32_Lo128 : RegisterOperand<VGPR_32_Lo128> { 1292 let DecoderMethod = "DecodeVGPR_32RegisterClass"; 1293} 1294 1295def VGPRSrc_96 : RegisterOperand<VReg_96> { 1296 let DecoderMethod = "DecodeVReg_96RegisterClass"; 1297} 1298 1299def VGPRSrc_16_Lo128 : RegisterOperand<VGPR_16_Lo128> { 1300 let DecoderMethod = "DecodeVGPR_16_Lo128RegisterClass"; 1301 let EncoderMethod = "getMachineOpValueT16Lo128"; 1302} 1303 1304// True 16 operands. 1305def VGPRSrc_16 : RegisterOperand<VGPR_16> { 1306 let DecoderMethod = "DecodeVGPR_16RegisterClass"; 1307 let EncoderMethod = "getMachineOpValueT16"; 1308} 1309 1310//===----------------------------------------------------------------------===// 1311// ASrc_* Operands with an AccVGPR 1312//===----------------------------------------------------------------------===// 1313 1314class AVOperand<RegisterClass regClass, string decoder, string width> 1315 : RegisterOperand<regClass> { 1316 let DecoderMethod = decoder # "<AMDGPUDisassembler::" # width # ">"; 1317 let EncoderMethod = "getAVOperandEncoding"; 1318} 1319 1320def ARegSrc_32 : AVOperand<AGPR_32, "decodeSrcA9", "OPW32">; 1321 1322//===----------------------------------------------------------------------===// 1323// VCSrc_* Operands with an SGPR, VGPR or an inline constant 1324//===----------------------------------------------------------------------===// 1325 1326def VCSrc_b16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_INLINE_C_INT16", 16, OperandSemantics.INT>; 1327def VCSrc_bf16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_INLINE_C_BF16", 16, OperandSemantics.BF16>; 1328def VCSrc_f16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_INLINE_C_FP16", 16, OperandSemantics.FP16>; 1329def VCSrc_b32 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_INLINE_C_INT32", 32, OperandSemantics.INT>; 1330def VCSrc_f32 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_INLINE_C_FP32", 32, OperandSemantics.FP32>; 1331def VCSrc_v2b16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_INLINE_C_V2INT16", 32, OperandSemantics.INT>; 1332def VCSrc_v2bf16: SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_INLINE_C_V2BF16", 16, OperandSemantics.BF16>; 1333def VCSrc_v2f16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_INLINE_C_V2FP16", 16, OperandSemantics.FP16>; 1334 1335// True 16 Operands 1336def VCSrcT_b16 : SrcRegOrImm9_t16 <"OPERAND_REG_INLINE_C_INT16", OperandSemantics.INT>; 1337def VCSrcT_bf16 : SrcRegOrImm9_t16 <"OPERAND_REG_INLINE_C_BF16", OperandSemantics.BF16>; 1338def VCSrcT_f16 : SrcRegOrImm9_t16 <"OPERAND_REG_INLINE_C_FP16", OperandSemantics.FP16>; 1339//===----------------------------------------------------------------------===// 1340// VISrc_* Operands with a VGPR or an inline constant 1341//===----------------------------------------------------------------------===// 1342 1343def VISrc_64_bf16 : SrcRegOrImm9 <VReg_64, "OPW64", "OPERAND_REG_INLINE_C_BF16", 16, OperandSemantics.BF16>; 1344def VISrc_64_f16 : SrcRegOrImm9 <VReg_64, "OPW64", "OPERAND_REG_INLINE_C_FP16", 16, OperandSemantics.FP16>; 1345def VISrc_64_b32 : SrcRegOrImm9 <VReg_64, "OPW64", "OPERAND_REG_INLINE_C_INT32", 32, OperandSemantics.INT>; 1346def VISrc_64_f64 : SrcRegOrImm9 <VReg_64, "OPW64", "OPERAND_REG_INLINE_C_FP64", 64, OperandSemantics.FP64>; 1347def VISrc_128_bf16 : SrcRegOrImm9 <VReg_128, "OPW128", "OPERAND_REG_INLINE_C_BF16", 16, OperandSemantics.BF16>; 1348def VISrc_128_f16 : SrcRegOrImm9 <VReg_128, "OPW128", "OPERAND_REG_INLINE_C_FP16", 16, OperandSemantics.FP16>; 1349def VISrc_128_b32 : SrcRegOrImm9 <VReg_128, "OPW128", "OPERAND_REG_INLINE_C_INT32", 32, OperandSemantics.INT>; 1350def VISrc_128_f32 : SrcRegOrImm9 <VReg_128, "OPW128", "OPERAND_REG_INLINE_C_FP32", 32, OperandSemantics.FP32>; 1351def VISrc_256_b32 : SrcRegOrImm9 <VReg_256, "OPW256", "OPERAND_REG_INLINE_C_INT32", 32, OperandSemantics.INT>; 1352def VISrc_256_f32 : SrcRegOrImm9 <VReg_256, "OPW256", "OPERAND_REG_INLINE_C_FP32", 32, OperandSemantics.FP32>; 1353def VISrc_256_f64 : SrcRegOrImm9 <VReg_256, "OPW256", "OPERAND_REG_INLINE_C_FP64", 64, OperandSemantics.FP64>; 1354def VISrc_512_b32 : SrcRegOrImm9 <VReg_512, "OPW512", "OPERAND_REG_INLINE_C_INT32", 32, OperandSemantics.INT>; 1355def VISrc_512_f32 : SrcRegOrImm9 <VReg_512, "OPW512", "OPERAND_REG_INLINE_C_FP32", 32, OperandSemantics.FP32>; 1356def VISrc_1024_b32 : SrcRegOrImm9 <VReg_1024, "OPW1024", "OPERAND_REG_INLINE_C_INT32", 32, OperandSemantics.INT>; 1357def VISrc_1024_f32 : SrcRegOrImm9 <VReg_1024, "OPW1024", "OPERAND_REG_INLINE_C_FP32", 32, OperandSemantics.FP32>; 1358 1359//===----------------------------------------------------------------------===// 1360// AVSrc_*, AVDst_*, AVLdSt_* Operands with an AGPR or VGPR 1361//===----------------------------------------------------------------------===// 1362 1363class AVSrcOperand<RegisterClass regClass, string width> 1364 : AVOperand<regClass, "decodeSrcAV10", width>; 1365 1366def AVSrc_32 : AVSrcOperand<AV_32, "OPW32">; 1367def AVSrc_64 : AVSrcOperand<AV_64, "OPW64">; 1368def AVSrc_128 : AVSrcOperand<AV_128, "OPW128">; 1369def AVSrc_192 : AVSrcOperand<AV_192, "OPW192">; 1370def AVSrc_256 : AVSrcOperand<AV_256, "OPW256">; 1371 1372class AVDstOperand<RegisterClass regClass, string width> 1373 : AVOperand<regClass, "decodeAV10", width>; 1374 1375def AVDst_128 : AVDstOperand<AV_128, "OPW128">; 1376def AVDst_256 : AVDstOperand<AV_256, "OPW256">; 1377def AVDst_512 : AVDstOperand<AV_512, "OPW512">; 1378 1379class AVLdStOperand<RegisterClass regClass, string width> 1380 : AVOperand<regClass, "decodeAVLdSt", width>; 1381 1382def AVLdSt_32 : AVLdStOperand<AV_32, "OPW32">; 1383def AVLdSt_64 : AVLdStOperand<AV_64, "OPW64">; 1384def AVLdSt_96 : AVLdStOperand<AV_96, "OPW96">; 1385def AVLdSt_128 : AVLdStOperand<AV_128, "OPW128">; 1386def AVLdSt_160 : AVLdStOperand<AV_160, "OPW160">; 1387def AVLdSt_1024 : AVLdStOperand<AV_1024, "OPW1024">; 1388 1389//===----------------------------------------------------------------------===// 1390// ACSrc_* Operands with an AGPR or an inline constant 1391//===----------------------------------------------------------------------===// 1392 1393class SrcRegOrImmA9<RegisterClass regClass, string opWidth, string operandType, 1394 int immWidth, int OperandSemantics> 1395 : RegOrImmOperand<regClass, operandType> { 1396 let DecoderMethod = "decodeSrcRegOrImmA9<AMDGPUDisassembler::" # opWidth # 1397 ", " # immWidth # ", " # OperandSemantics # ">"; 1398} 1399 1400def AISrc_64_f64 : SrcRegOrImmA9 <AReg_64, "OPW64", "OPERAND_REG_INLINE_AC_FP64", 64, OperandSemantics.FP64>; 1401def AISrc_128_f32 : SrcRegOrImmA9 <AReg_128, "OPW128", "OPERAND_REG_INLINE_AC_FP32", 32, OperandSemantics.FP32>; 1402def AISrc_128_b32 : SrcRegOrImmA9 <AReg_128, "OPW128", "OPERAND_REG_INLINE_AC_INT32", 32, OperandSemantics.INT>; 1403def AISrc_256_f64 : SrcRegOrImmA9 <AReg_256, "OPW256", "OPERAND_REG_INLINE_AC_FP64", 64, OperandSemantics.FP64>; 1404def AISrc_512_f32 : SrcRegOrImmA9 <AReg_512, "OPW512", "OPERAND_REG_INLINE_AC_FP32", 32, OperandSemantics.FP32>; 1405def AISrc_512_b32 : SrcRegOrImmA9 <AReg_512, "OPW512", "OPERAND_REG_INLINE_AC_INT32", 32, OperandSemantics.INT>; 1406def AISrc_1024_f32 : SrcRegOrImmA9 <AReg_1024, "OPW1024", "OPERAND_REG_INLINE_AC_FP32", 32, OperandSemantics.FP32>; 1407def AISrc_1024_b32 : SrcRegOrImmA9 <AReg_1024, "OPW1024", "OPERAND_REG_INLINE_AC_INT32", 32, OperandSemantics.INT>; 1408