1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// SI Instruction format definitions. 10// 11//===----------------------------------------------------------------------===// 12 13class InstSI <dag outs, dag ins, string asm = "", 14 list<dag> pattern = []> : 15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl { 16 // Low bits - basic encoding information. 17 field bit SALU = 0; 18 field bit VALU = 0; 19 20 // SALU instruction formats. 21 field bit SOP1 = 0; 22 field bit SOP2 = 0; 23 field bit SOPC = 0; 24 field bit SOPK = 0; 25 field bit SOPP = 0; 26 27 // VALU instruction formats. 28 field bit VOP1 = 0; 29 field bit VOP2 = 0; 30 field bit VOPC = 0; 31 field bit VOP3 = 0; 32 field bit VOP3P = 0; 33 field bit VINTRP = 0; 34 field bit SDWA = 0; 35 field bit DPP = 0; 36 field bit TRANS = 0; 37 38 // Memory instruction formats. 39 field bit MUBUF = 0; 40 field bit MTBUF = 0; 41 field bit SMRD = 0; 42 field bit MIMG = 0; 43 field bit VIMAGE = 0; 44 field bit VSAMPLE = 0; 45 field bit EXP = 0; 46 field bit FLAT = 0; 47 field bit DS = 0; 48 49 // Combined SGPR/VGPR spill bit 50 field bit Spill = 0; 51 52 // LDSDIR instruction format. 53 field bit LDSDIR = 0; 54 55 // VINTERP instruction format. 56 field bit VINTERP = 0; 57 58 // High bits - other information. 59 field bit VM_CNT = 0; 60 field bit EXP_CNT = 0; 61 field bit LGKM_CNT = 0; 62 63 // Whether WQM _must_ be enabled for this instruction. 64 field bit WQM = 0; 65 66 // Whether WQM _must_ be disabled for this instruction. 67 field bit DisableWQM = 0; 68 69 field bit Gather4 = 0; 70 71 // This is an s_store_dword* instruction that requires a cache flush 72 // on wave termination. It is necessary to distinguish from mayStore 73 // SMEM instructions like the cache flush ones. 74 field bit ScalarStore = 0; 75 76 // Whether the operands can be ignored when computing the 77 // instruction size. 78 field bit FixedSize = 0; 79 80 // This bit indicates that this is a VOP3 opcode which supports op_sel 81 // modifier. 82 field bit VOP3_OPSEL = 0; 83 84 // Is it possible for this instruction to be atomic? 85 field bit maybeAtomic = 1; 86 87 // This bit indicates that this has a floating point result type, so 88 // the clamp modifier has floating point semantics. 89 field bit FPClamp = 0; 90 91 // This bit indicates that instruction may support integer clamping 92 // which depends on GPU features. 93 field bit IntClamp = 0; 94 95 // This field indicates that the clamp applies to the low component 96 // of a packed output register. 97 field bit ClampLo = 0; 98 99 // This field indicates that the clamp applies to the high component 100 // of a packed output register. 101 field bit ClampHi = 0; 102 103 // This bit indicates that this is a packed VOP3P instruction 104 field bit IsPacked = 0; 105 106 // This bit indicates that this is a D16 buffer instruction. 107 field bit D16Buf = 0; 108 109 // This field indicates that FLAT instruction accesses FLAT_GLBL segment. 110 // Must be 0 for non-FLAT instructions. 111 field bit FlatGlobal = 0; 112 113 // Reads the mode register, usually for FP environment. 114 field bit ReadsModeReg = 0; 115 116 // This bit indicates that this uses the floating point double precision 117 // rounding mode flags 118 field bit FPDPRounding = 0; 119 120 // Instruction is FP atomic. 121 field bit FPAtomic = 0; 122 123 // This bit indicates that this is one of MFMA instructions. 124 field bit IsMAI = 0; 125 126 // This bit indicates that this is one of DOT instructions. 127 field bit IsDOT = 0; 128 129 // This field indicates that FLAT instruction accesses FLAT_SCRATCH segment. 130 // Must be 0 for non-FLAT instructions. 131 field bit FlatScratch = 0; 132 133 // Atomic without a return. 134 field bit IsAtomicNoRet = 0; 135 136 // Atomic with return. 137 field bit IsAtomicRet = 0; 138 139 // This bit indicates that this is one of WMMA instructions. 140 field bit IsWMMA = 0; 141 142 // This bit indicates that tied source will not be read. 143 field bit TiedSourceNotRead = 0; 144 145 // This bit indicates that the instruction is never-uniform/divergent 146 field bit IsNeverUniform = 0; 147 148 // ds_gws_* instructions. 149 field bit GWS = 0; 150 151 // This bit indicates that this is one of SWMMAC instructions. 152 field bit IsSWMMAC = 0; 153 154 // These need to be kept in sync with the enum in SIInstrFlags. 155 let TSFlags{0} = SALU; 156 let TSFlags{1} = VALU; 157 158 let TSFlags{2} = SOP1; 159 let TSFlags{3} = SOP2; 160 let TSFlags{4} = SOPC; 161 let TSFlags{5} = SOPK; 162 let TSFlags{6} = SOPP; 163 164 let TSFlags{7} = VOP1; 165 let TSFlags{8} = VOP2; 166 let TSFlags{9} = VOPC; 167 let TSFlags{10} = VOP3; 168 let TSFlags{12} = VOP3P; 169 170 let TSFlags{13} = VINTRP; 171 let TSFlags{14} = SDWA; 172 let TSFlags{15} = DPP; 173 let TSFlags{16} = TRANS; 174 175 let TSFlags{17} = MUBUF; 176 let TSFlags{18} = MTBUF; 177 let TSFlags{19} = SMRD; 178 let TSFlags{20} = MIMG; 179 let TSFlags{21} = VIMAGE; 180 let TSFlags{22} = VSAMPLE; 181 let TSFlags{23} = EXP; 182 let TSFlags{24} = FLAT; 183 let TSFlags{25} = DS; 184 185 let TSFlags{26} = Spill; 186 187 // Reserved, must be 0 188 let TSFlags{27} = 0; 189 190 let TSFlags{28} = LDSDIR; 191 let TSFlags{29} = VINTERP; 192 193 let TSFlags{32} = VM_CNT; 194 let TSFlags{33} = EXP_CNT; 195 let TSFlags{34} = LGKM_CNT; 196 197 let TSFlags{35} = WQM; 198 let TSFlags{36} = DisableWQM; 199 let TSFlags{37} = Gather4; 200 201 // Reserved, must be 0. 202 let TSFlags{38} = 0; 203 204 let TSFlags{39} = ScalarStore; 205 let TSFlags{40} = FixedSize; 206 207 // Reserved, must be 0. 208 let TSFlags{41} = 0; 209 210 let TSFlags{42} = VOP3_OPSEL; 211 212 let TSFlags{43} = maybeAtomic; 213 214 // Reserved, must be 0. 215 let TSFlags{44} = 0; 216 217 let TSFlags{45} = FPClamp; 218 let TSFlags{46} = IntClamp; 219 let TSFlags{47} = ClampLo; 220 let TSFlags{48} = ClampHi; 221 222 let TSFlags{49} = IsPacked; 223 224 let TSFlags{50} = D16Buf; 225 226 let TSFlags{51} = FlatGlobal; 227 228 let TSFlags{52} = FPDPRounding; 229 230 let TSFlags{53} = FPAtomic; 231 232 let TSFlags{54} = IsMAI; 233 234 let TSFlags{55} = IsDOT; 235 236 let TSFlags{56} = FlatScratch; 237 238 let TSFlags{57} = IsAtomicNoRet; 239 240 let TSFlags{58} = IsAtomicRet; 241 242 let TSFlags{59} = IsWMMA; 243 244 let TSFlags{60} = TiedSourceNotRead; 245 246 let TSFlags{61} = IsNeverUniform; 247 248 let TSFlags{62} = GWS; 249 250 let TSFlags{63} = IsSWMMAC; 251 252 let SchedRW = [Write32Bit]; 253 254 let AsmVariantName = AMDGPUAsmVariants.Default; 255 256 // Avoid changing source registers in a way that violates constant bus read limitations. 257 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU); 258} 259 260class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = ""> 261 : InstSI<outs, ins, asm, pattern> { 262 let isPseudo = 1; 263 let isCodeGenOnly = 1; 264} 265 266class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = ""> 267 : PseudoInstSI<outs, ins, pattern, asm> { 268 let SALU = 1; 269} 270 271class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = ""> 272 : PseudoInstSI<outs, ins, pattern, asm> { 273 let VALU = 1; 274 let Uses = [EXEC]; 275} 276 277class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], 278 bit UseExec = 0, bit DefExec = 0> : 279 SPseudoInstSI<outs, ins, pattern> { 280 281 let Uses = !if(UseExec, [EXEC], []); 282 let Defs = !if(DefExec, [EXEC, SCC], [SCC]); 283 let mayLoad = 0; 284 let mayStore = 0; 285 let hasSideEffects = 0; 286} 287 288class Enc32 { 289 field bits<32> Inst; 290 int Size = 4; 291} 292 293class Enc64 { 294 field bits<64> Inst; 295 int Size = 8; 296} 297 298class Enc96 { 299 field bits<96> Inst; 300 int Size = 12; 301} 302 303class Enc128 { 304 field bits<128> Inst; 305 int Size = 16; 306} 307 308def CPolBit { 309 int GLC = 0; 310 int SLC = 1; 311 int DLC = 2; 312 int SCC = 4; 313} 314 315class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">; 316 317def VOPDstOperand_t16 : VOPDstOperand <VGPR_16> { 318 let EncoderMethod = "getMachineOpValueT16"; 319 let DecoderMethod = "DecodeVGPR_16RegisterClass"; 320} 321 322def VOPDstOperand_t16Lo128 : VOPDstOperand <VGPR_16_Lo128> { 323 let EncoderMethod = "getMachineOpValueT16Lo128"; 324 let DecoderMethod = "DecodeVGPR_16_Lo128RegisterClass"; 325} 326 327// Source-encoded destination operand for instructions like v_swap_b16. 328def VOPSrcEncodedDstOperand_t16Lo128 : VOPDstOperand <VGPR_16_Lo128> { 329 let EncoderMethod = VSrcT_b16_Lo128.EncoderMethod; 330 let DecoderMethod = VSrcT_b16_Lo128.DecoderMethod; 331} 332 333class VINTRPe <bits<2> op> : Enc32 { 334 bits<8> vdst; 335 bits<8> vsrc; 336 bits<2> attrchan; 337 bits<6> attr; 338 339 let Inst{7-0} = vsrc; 340 let Inst{9-8} = attrchan; 341 let Inst{15-10} = attr; 342 let Inst{17-16} = op; 343 let Inst{25-18} = vdst; 344 let Inst{31-26} = 0x32; // encoding 345} 346 347class MIMGe_gfxpre11 : Enc64 { 348 bits<10> vdata; 349 bits<4> dmask; 350 bits<1> unorm; 351 bits<5> cpol; 352 bits<1> r128; 353 bits<1> tfe; 354 bits<1> lwe; 355 bit d16; 356 bits<7> srsrc; 357 bits<7> ssamp; 358 359 let Inst{11-8} = dmask; 360 let Inst{12} = unorm; 361 let Inst{13} = cpol{CPolBit.GLC}; 362 let Inst{15} = r128; 363 let Inst{17} = lwe; 364 let Inst{25} = cpol{CPolBit.SLC}; 365 let Inst{31-26} = 0x3c; 366 let Inst{47-40} = vdata{7-0}; 367 let Inst{52-48} = srsrc{6-2}; 368 let Inst{57-53} = ssamp{6-2}; 369 let Inst{63} = d16; 370} 371 372class MIMGe_gfx6789 <bits<8> op> : MIMGe_gfxpre11 { 373 bits<8> vaddr; 374 bits<1> da; 375 376 let Inst{0} = op{7}; 377 let Inst{7} = cpol{CPolBit.SCC}; 378 let Inst{14} = da; 379 let Inst{16} = tfe; 380 let Inst{24-18} = op{6-0}; 381 let Inst{39-32} = vaddr; 382} 383 384class MIMGe_gfx90a <bits<8> op> : MIMGe_gfxpre11 { 385 bits<8> vaddr; 386 bits<1> da; 387 388 let Inst{0} = op{7}; 389 let Inst{7} = cpol{CPolBit.SCC}; 390 let Inst{14} = da; 391 let Inst{16} = vdata{9}; // ACC bit 392 let Inst{24-18} = op{6-0}; 393 let Inst{39-32} = vaddr; 394} 395 396class MIMGe_gfx10 <bits<8> op> : MIMGe_gfxpre11 { 397 bits<8> vaddr0; 398 bits<3> dim; 399 bits<2> nsa; 400 bits<1> a16; 401 402 let Inst{0} = op{7}; 403 let Inst{2-1} = nsa; 404 let Inst{5-3} = dim; 405 let Inst{7} = cpol{CPolBit.DLC}; 406 let Inst{16} = tfe; 407 let Inst{24-18} = op{6-0}; 408 let Inst{39-32} = vaddr0; 409 let Inst{62} = a16; 410} 411 412class MIMGe_gfx11 <bits<8> op> : Enc64 { 413 bits<8> vdata; 414 bits<4> dmask; 415 bits<1> unorm; 416 bits<5> cpol; 417 bits<1> r128; 418 bits<1> tfe; 419 bits<1> lwe; 420 bits<7> srsrc; 421 bits<7> ssamp; 422 bit d16; 423 bits<1> a16; 424 bits<8> vaddr0; 425 bits<3> dim; 426 bits<1> nsa; 427 428 let Inst{0} = nsa; 429 let Inst{4-2} = dim; 430 let Inst{7} = unorm; 431 let Inst{11-8} = dmask; 432 let Inst{12} = cpol{CPolBit.SLC}; 433 let Inst{13} = cpol{CPolBit.DLC}; 434 let Inst{14} = cpol{CPolBit.GLC}; 435 let Inst{15} = r128; 436 let Inst{16} = a16; 437 let Inst{17} = d16; 438 let Inst{25-18} = op; 439 let Inst{31-26} = 0x3c; 440 let Inst{39-32} = vaddr0; 441 let Inst{47-40} = vdata; 442 let Inst{52-48} = srsrc{6-2}; 443 let Inst{53} = tfe; 444 let Inst{54} = lwe; 445 let Inst{62-58} = ssamp{6-2}; 446} 447 448class VIMAGE_VSAMPLE_Common <bits<8> op> : Enc96 { 449 bits<3> dim; 450 bits<1> tfe; 451 bits<1> r128; 452 bit d16; 453 bits<1> a16; 454 bits<4> dmask; 455 bits<8> vdata; 456 bits<9> rsrc; 457 bits<6> cpol; 458 bits<8> vaddr0; 459 bits<8> vaddr1; 460 bits<8> vaddr2; 461 bits<8> vaddr3; 462 463 let Inst{2-0} = dim; 464 let Inst{4} = r128; 465 let Inst{5} = d16; 466 let Inst{6} = a16; 467 let Inst{21-14} = op; 468 let Inst{25-22} = dmask; 469 let Inst{39-32} = vdata; 470 let Inst{49-41} = rsrc; 471 let Inst{51-50} = cpol{4-3}; // scope 472 let Inst{54-52} = cpol{2-0}; // th 473 let Inst{71-64} = vaddr0; 474 let Inst{79-72} = vaddr1; 475 let Inst{87-80} = vaddr2; 476 let Inst{95-88} = vaddr3; 477} 478 479class VSAMPLEe <bits<8> op> : VIMAGE_VSAMPLE_Common<op> { 480 bits<1> unorm; 481 bits<1> lwe; 482 bits<9> samp; 483 484 let Inst{3} = tfe; 485 let Inst{13} = unorm; 486 let Inst{31-26} = 0x39; 487 let Inst{40} = lwe; 488 let Inst{63-55} = samp; 489} 490 491class VIMAGEe <bits<8> op> : VIMAGE_VSAMPLE_Common<op> { 492 bits<8> vaddr4; 493 494 let Inst{31-26} = 0x34; 495 let Inst{55} = tfe; 496 let Inst{63-56} = vaddr4; 497} 498 499class EXPe : Enc64 { 500 bits<4> en; 501 bits<6> tgt; 502 bits<1> done; 503 bits<8> src0; 504 bits<8> src1; 505 bits<8> src2; 506 bits<8> src3; 507 508 let Inst{3-0} = en; 509 let Inst{9-4} = tgt; 510 let Inst{11} = done; 511 let Inst{31-26} = 0x3e; 512 let Inst{39-32} = src0; 513 let Inst{47-40} = src1; 514 let Inst{55-48} = src2; 515 let Inst{63-56} = src3; 516} 517 518// Pre-GFX11 encoding has compr and vm bits. 519class EXPe_ComprVM : EXPe { 520 bits<1> compr; 521 bits<1> vm; 522 523 let Inst{10} = compr; 524 let Inst{12} = vm; 525} 526 527// GFX11+ encoding has row bit. 528class EXPe_Row : EXPe { 529 bits<1> row; 530 531 let Inst{13} = row; 532} 533 534let Uses = [EXEC] in { 535 536class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> : 537 InstSI <outs, ins, asm, pattern> { 538 let VINTRP = 1; 539 // VINTRP instructions read parameter values from LDS, but these parameter 540 // values are stored outside of the LDS memory that is allocated to the 541 // shader for general purpose use. 542 // 543 // While it may be possible for ds_read/ds_write instructions to access 544 // the parameter values in LDS, this would essentially be an out-of-bounds 545 // memory access which we consider to be undefined behavior. 546 // 547 // So even though these instructions read memory, this memory is outside the 548 // addressable memory space for the shader, and we consider these instructions 549 // to be readnone. 550 let mayLoad = 0; 551 let mayStore = 0; 552 let hasSideEffects = 0; 553 let VALU = 1; 554} 555 556} // End Uses = [EXEC] 557