1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// SI DAG Lowering interface definition 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16 17 #include "AMDGPUISelLowering.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 21 namespace llvm { 22 23 class GCNSubtarget; 24 class SIMachineFunctionInfo; 25 class SIRegisterInfo; 26 27 namespace AMDGPU { 28 struct ImageDimIntrinsicInfo; 29 } 30 31 class SITargetLowering final : public AMDGPUTargetLowering { 32 private: 33 const GCNSubtarget *Subtarget; 34 35 public: 36 MVT getRegisterTypeForCallingConv(LLVMContext &Context, 37 CallingConv::ID CC, 38 EVT VT) const override; 39 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 40 CallingConv::ID CC, 41 EVT VT) const override; 42 43 unsigned getVectorTypeBreakdownForCallingConv( 44 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 45 unsigned &NumIntermediates, MVT &RegisterVT) const override; 46 47 private: 48 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL, 49 SDValue Chain, uint64_t Offset) const; 50 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const; 51 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const; 52 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, 53 const SDLoc &SL, SDValue Chain, 54 uint64_t Offset, Align Alignment, 55 bool Signed, 56 const ISD::InputArg *Arg = nullptr) const; 57 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL, 58 Align Alignment, 59 ImplicitParameter Param) const; 60 61 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, 62 const SDLoc &SL, SDValue Chain, 63 const ISD::InputArg &Arg) const; 64 SDValue getPreloadedValue(SelectionDAG &DAG, 65 const SIMachineFunctionInfo &MFI, 66 EVT VT, 67 AMDGPUFunctionArgInfo::PreloadedValue) const; 68 69 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 70 SelectionDAG &DAG) const override; 71 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 72 MVT VT, unsigned Offset) const; 73 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, 74 SelectionDAG &DAG, bool WithChain) const; 75 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset, 76 SDValue CachePolicy, SelectionDAG &DAG) const; 77 78 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 79 unsigned NewOpcode) const; 80 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 81 unsigned NewOpcode) const; 82 83 SDValue lowerWaveID(SelectionDAG &DAG, SDValue Op) const; 84 SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim, 85 const ArgDescriptor &ArgDesc) const; 86 87 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 88 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 89 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 90 91 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset 92 // (the offset that is included in bounds checking and swizzling, to be split 93 // between the instruction's voffset and immoffset fields) and soffset (the 94 // offset that is excluded from bounds checking and swizzling, to go in the 95 // instruction's soffset field). This function takes the first kind of 96 // offset and figures out how to split it between voffset and immoffset. 97 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset, 98 SelectionDAG &DAG) const; 99 100 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const; 101 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 102 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 103 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 104 SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const; 105 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 106 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const; 107 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 108 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 109 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 110 SDValue LowerFFREXP(SDValue Op, SelectionDAG &DAG) const; 111 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 112 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 113 SDValue lowerFSQRTF16(SDValue Op, SelectionDAG &DAG) const; 114 SDValue lowerFSQRTF32(SDValue Op, SelectionDAG &DAG) const; 115 SDValue lowerFSQRTF64(SDValue Op, SelectionDAG &DAG) const; 116 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 117 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 118 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 119 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, 120 SelectionDAG &DAG, ArrayRef<SDValue> Ops, 121 bool IsIntrinsic = false) const; 122 123 SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG, 124 ArrayRef<SDValue> Ops) const; 125 126 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to 127 // dwordx4 if on SI. 128 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, 129 ArrayRef<SDValue> Ops, EVT MemVT, 130 MachineMemOperand *MMO, SelectionDAG &DAG) const; 131 132 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG, 133 bool ImageStore = false) const; 134 135 /// Converts \p Op, which must be of floating point type, to the 136 /// floating point type \p VT, by either extending or truncating it. 137 SDValue getFPExtOrFPRound(SelectionDAG &DAG, 138 SDValue Op, 139 const SDLoc &DL, 140 EVT VT) const; 141 142 SDValue convertArgType( 143 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, 144 bool Signed, const ISD::InputArg *Arg = nullptr) const; 145 146 /// Custom lowering for ISD::FP_ROUND for MVT::f16. 147 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 148 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const; 149 SDValue lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const; 150 SDValue promoteUniformOpToI32(SDValue Op, DAGCombinerInfo &DCI) const; 151 SDValue lowerMUL(SDValue Op, SelectionDAG &DAG) const; 152 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const; 153 SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 154 155 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, 156 SelectionDAG &DAG) const; 157 158 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 159 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 160 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 161 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 162 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 163 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 164 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 165 166 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 167 SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const; 168 SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const; 169 SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const; 170 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const; 171 172 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 173 174 SDValue performUCharToFloatCombine(SDNode *N, 175 DAGCombinerInfo &DCI) const; 176 SDValue performFCopySignCombine(SDNode *N, DAGCombinerInfo &DCI) const; 177 178 SDValue performSHLPtrCombine(SDNode *N, 179 unsigned AS, 180 EVT MemVT, 181 DAGCombinerInfo &DCI) const; 182 183 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const; 184 185 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 186 unsigned Opc, SDValue LHS, 187 const ConstantSDNode *CRHS) const; 188 189 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 190 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 191 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 192 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const; 193 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const; 194 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 195 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT, 196 const APFloat &C) const; 197 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 198 199 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 200 SDValue Op0, SDValue Op1) const; 201 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 202 SDValue Src, SDValue MinVal, SDValue MaxVal, 203 bool Signed) const; 204 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 205 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 206 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; 207 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 208 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 209 SDValue performFPRoundCombine(SDNode *N, DAGCombinerInfo &DCI) const; 210 211 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const; 212 unsigned getFusedOpcode(const SelectionDAG &DAG, 213 const SDNode *N0, const SDNode *N1) const; 214 SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const; 215 SDValue foldAddSub64WithZeroLowBitsTo32(SDNode *N, 216 DAGCombinerInfo &DCI) const; 217 218 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 219 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const; 220 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 221 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 222 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 223 SDValue performFDivCombine(SDNode *N, DAGCombinerInfo &DCI) const; 224 SDValue performFMulCombine(SDNode *N, DAGCombinerInfo &DCI) const; 225 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const; 226 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 227 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; 228 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const; 229 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const; 230 231 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 232 233 unsigned isCFIntrinsic(const SDNode *Intr) const; 234 235 public: 236 /// \returns True if fixup needs to be emitted for given global value \p GV, 237 /// false otherwise. 238 bool shouldEmitFixup(const GlobalValue *GV) const; 239 240 /// \returns True if GOT relocation needs to be emitted for given global value 241 /// \p GV, false otherwise. 242 bool shouldEmitGOTReloc(const GlobalValue *GV) const; 243 244 /// \returns True if PC-relative relocation needs to be emitted for given 245 /// global value \p GV, false otherwise. 246 bool shouldEmitPCReloc(const GlobalValue *GV) const; 247 248 /// \returns true if this should use a literal constant for an LDS address, 249 /// and not emit a relocation for an LDS global. 250 bool shouldUseLDSConstAddress(const GlobalValue *GV) const; 251 252 /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be 253 /// expanded into a set of cmp/select instructions. 254 static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, 255 bool IsDivergentIdx, 256 const GCNSubtarget *Subtarget); 257 258 bool shouldExpandVectorDynExt(SDNode *N) const; 259 260 private: 261 // Analyze a combined offset from an amdgcn_s_buffer_load intrinsic and store 262 // the three offsets (voffset, soffset and instoffset) into the SDValue[3] 263 // array pointed to by Offsets. 264 void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG, 265 SDValue *Offsets, Align Alignment = Align(4)) const; 266 267 // Convert the i128 that an addrspace(8) pointer is natively represented as 268 // into the v4i32 that all the buffer intrinsics expect to receive. We can't 269 // add register classes for i128 on pain of the promotion logic going haywire, 270 // so this slightly ugly hack is what we've got. If passed a non-pointer 271 // argument (as would be seen in older buffer intrinsics), does nothing. 272 SDValue bufferRsrcPtrToVector(SDValue MaybePointer, SelectionDAG &DAG) const; 273 274 // Wrap a 64-bit pointer into a v4i32 (which is how all SelectionDAG code 275 // represents ptr addrspace(8)) using the flags specified in the intrinsic. 276 SDValue lowerPointerAsRsrcIntrin(SDNode *Op, SelectionDAG &DAG) const; 277 278 // Handle 8 bit and 16 bit buffer loads 279 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL, 280 ArrayRef<SDValue> Ops, 281 MachineMemOperand *MMO, 282 bool IsTFE = false) const; 283 284 // Handle 8 bit and 16 bit buffer stores 285 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType, 286 SDLoc DL, SDValue Ops[], 287 MemSDNode *M) const; 288 289 public: 290 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI); 291 292 const GCNSubtarget *getSubtarget() const; 293 294 ArrayRef<MCPhysReg> getRoundingControlRegisters() const override; 295 296 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, 297 EVT SrcVT) const override; 298 299 bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy, 300 LLT SrcTy) const override; 301 302 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override; 303 304 // While address space 7 should never make it to codegen, it still needs to 305 // have a MVT to prevent some analyses that query this function from breaking, 306 // so, to work around the lack of i160, map it to v5i32. 307 MVT getPointerTy(const DataLayout &DL, unsigned AS) const override; 308 MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override; 309 310 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 311 MachineFunction &MF, 312 unsigned IntrinsicID) const override; 313 314 void CollectTargetIntrinsicOperands(const CallInst &I, 315 SmallVectorImpl<SDValue> &Ops, 316 SelectionDAG &DAG) const override; 317 318 bool getAddrModeArguments(const IntrinsicInst *I, 319 SmallVectorImpl<Value *> &Ops, 320 Type *&AccessTy) const override; 321 322 bool isLegalFlatAddressingMode(const AddrMode &AM, unsigned AddrSpace) const; 323 bool isLegalGlobalAddressingMode(const AddrMode &AM) const; 324 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 325 unsigned AS, 326 Instruction *I = nullptr) const override; 327 328 bool canMergeStoresTo(unsigned AS, EVT MemVT, 329 const MachineFunction &MF) const override; 330 331 bool allowsMisalignedMemoryAccessesImpl( 332 unsigned Size, unsigned AddrSpace, Align Alignment, 333 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 334 unsigned *IsFast = nullptr) const; 335 336 bool allowsMisalignedMemoryAccesses( 337 LLT Ty, unsigned AddrSpace, Align Alignment, 338 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 339 unsigned *IsFast = nullptr) const override { 340 if (IsFast) 341 *IsFast = 0; 342 return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace, 343 Alignment, Flags, IsFast); 344 } 345 346 bool allowsMisalignedMemoryAccesses( 347 EVT VT, unsigned AS, Align Alignment, 348 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 349 unsigned *IsFast = nullptr) const override; 350 351 EVT getOptimalMemOpType(const MemOp &Op, 352 const AttributeList &FuncAttributes) const override; 353 354 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 355 356 static bool isNonGlobalAddrSpace(unsigned AS); 357 358 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 359 360 TargetLoweringBase::LegalizeTypeAction 361 getPreferredVectorAction(MVT VT) const override; 362 363 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 364 Type *Ty) const override; 365 366 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 367 unsigned Index) const override; 368 bool isExtractVecEltCheap(EVT VT, unsigned Index) const override; 369 370 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 371 372 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 373 374 unsigned combineRepeatedFPDivisors() const override { 375 // Combine multiple FDIVs with the same divisor into multiple FMULs by the 376 // reciprocal. 377 return 2; 378 } 379 380 bool supportSplitCSR(MachineFunction *MF) const override; 381 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 382 void insertCopiesSplitCSR( 383 MachineBasicBlock *Entry, 384 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 385 386 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 387 bool isVarArg, 388 const SmallVectorImpl<ISD::InputArg> &Ins, 389 const SDLoc &DL, SelectionDAG &DAG, 390 SmallVectorImpl<SDValue> &InVals) const override; 391 392 bool CanLowerReturn(CallingConv::ID CallConv, 393 MachineFunction &MF, bool isVarArg, 394 const SmallVectorImpl<ISD::OutputArg> &Outs, 395 LLVMContext &Context, const Type *RetTy) const override; 396 397 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 398 const SmallVectorImpl<ISD::OutputArg> &Outs, 399 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 400 SelectionDAG &DAG) const override; 401 402 void passSpecialInputs( 403 CallLoweringInfo &CLI, 404 CCState &CCInfo, 405 const SIMachineFunctionInfo &Info, 406 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, 407 SmallVectorImpl<SDValue> &MemOpChains, 408 SDValue Chain) const; 409 410 SDValue LowerCallResult(SDValue Chain, SDValue InGlue, 411 CallingConv::ID CallConv, bool isVarArg, 412 const SmallVectorImpl<ISD::InputArg> &Ins, 413 const SDLoc &DL, SelectionDAG &DAG, 414 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 415 SDValue ThisVal) const; 416 417 bool mayBeEmittedAsTailCall(const CallInst *) const override; 418 419 bool isEligibleForTailCallOptimization( 420 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 421 const SmallVectorImpl<ISD::OutputArg> &Outs, 422 const SmallVectorImpl<SDValue> &OutVals, 423 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 424 425 SDValue LowerCall(CallLoweringInfo &CLI, 426 SmallVectorImpl<SDValue> &InVals) const override; 427 428 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 429 SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; 430 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 431 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 432 433 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; 434 SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 435 SDValue lowerGET_FPENV(SDValue Op, SelectionDAG &DAG) const; 436 SDValue lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const; 437 438 Register getRegisterByName(const char* RegName, LLT VT, 439 const MachineFunction &MF) const override; 440 441 MachineBasicBlock *splitKillBlock(MachineInstr &MI, 442 MachineBasicBlock *BB) const; 443 444 void bundleInstWithWaitcnt(MachineInstr &MI) const; 445 MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI, 446 MachineBasicBlock *BB) const; 447 448 MachineBasicBlock * 449 EmitInstrWithCustomInserter(MachineInstr &MI, 450 MachineBasicBlock *BB) const override; 451 452 bool enableAggressiveFMAFusion(EVT VT) const override; 453 bool enableAggressiveFMAFusion(LLT Ty) const override; 454 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 455 EVT VT) const override; 456 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 457 LLT getPreferredShiftAmountTy(LLT Ty) const override; 458 459 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 460 EVT VT) const override; 461 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 462 const LLT Ty) const override; 463 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override; 464 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override; 465 bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override; 466 467 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 468 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 469 SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 470 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 471 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 472 SelectionDAG &DAG) const override; 473 474 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 475 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 476 void AddMemOpInit(MachineInstr &MI) const; 477 void AdjustInstrPostInstrSelection(MachineInstr &MI, 478 SDNode *Node) const override; 479 480 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 481 482 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 483 SDValue Ptr) const; 484 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 485 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 486 std::pair<unsigned, const TargetRegisterClass *> 487 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 488 StringRef Constraint, MVT VT) const override; 489 ConstraintType getConstraintType(StringRef Constraint) const override; 490 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, 491 std::vector<SDValue> &Ops, 492 SelectionDAG &DAG) const override; 493 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const; 494 bool checkAsmConstraintVal(SDValue Op, StringRef Constraint, 495 uint64_t Val) const; 496 bool checkAsmConstraintValA(SDValue Op, 497 uint64_t Val, 498 unsigned MaxSize = 64) const; 499 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 500 SDValue V) const; 501 502 void finalizeLowering(MachineFunction &MF) const override; 503 504 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 505 const APInt &DemandedElts, 506 const SelectionDAG &DAG, 507 unsigned Depth = 0) const override; 508 void computeKnownBitsForFrameIndex(int FrameIdx, 509 KnownBits &Known, 510 const MachineFunction &MF) const override; 511 void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, 512 KnownBits &Known, 513 const APInt &DemandedElts, 514 const MachineRegisterInfo &MRI, 515 unsigned Depth = 0) const override; 516 517 Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, 518 const MachineRegisterInfo &MRI, 519 unsigned Depth = 0) const override; 520 bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, 521 UniformityInfo *UA) const override; 522 523 bool hasMemSDNodeUser(SDNode *N) const; 524 525 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, 526 SDValue N1) const override; 527 528 bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0, 529 Register N1) const override; 530 531 bool isCanonicalized(SelectionDAG &DAG, SDValue Op, 532 unsigned MaxDepth = 5) const; 533 bool isCanonicalized(Register Reg, const MachineFunction &MF, 534 unsigned MaxDepth = 5) const; 535 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const; 536 bool denormalsEnabledForType(LLT Ty, const MachineFunction &MF) const; 537 538 bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, 539 const TargetRegisterInfo *TRI, 540 const TargetInstrInfo *TII, unsigned &PhysReg, 541 int &Cost) const override; 542 543 bool isProfitableToHoist(Instruction *I) const override; 544 545 bool isKnownNeverNaNForTargetNode(SDValue Op, 546 const SelectionDAG &DAG, 547 bool SNaN = false, 548 unsigned Depth = 0) const override; 549 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override; 550 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 551 AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 552 AtomicExpansionKind 553 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 554 555 void emitExpandAtomicAddrSpacePredicate(Instruction *AI) const; 556 void emitExpandAtomicRMW(AtomicRMWInst *AI) const override; 557 void emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const override; 558 559 LoadInst * 560 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override; 561 562 const TargetRegisterClass *getRegClassFor(MVT VT, 563 bool isDivergent) const override; 564 bool requiresUniformRegister(MachineFunction &MF, 565 const Value *V) const override; 566 Align getPrefLoopAlignment(MachineLoop *ML) const override; 567 568 void allocateHSAUserSGPRs(CCState &CCInfo, 569 MachineFunction &MF, 570 const SIRegisterInfo &TRI, 571 SIMachineFunctionInfo &Info) const; 572 573 void allocatePreloadKernArgSGPRs(CCState &CCInfo, 574 SmallVectorImpl<CCValAssign> &ArgLocs, 575 const SmallVectorImpl<ISD::InputArg> &Ins, 576 MachineFunction &MF, 577 const SIRegisterInfo &TRI, 578 SIMachineFunctionInfo &Info) const; 579 580 void allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF, 581 const SIRegisterInfo &TRI, 582 SIMachineFunctionInfo &Info) const; 583 584 void allocateSystemSGPRs(CCState &CCInfo, 585 MachineFunction &MF, 586 SIMachineFunctionInfo &Info, 587 CallingConv::ID CallConv, 588 bool IsShader) const; 589 590 void allocateSpecialEntryInputVGPRs(CCState &CCInfo, 591 MachineFunction &MF, 592 const SIRegisterInfo &TRI, 593 SIMachineFunctionInfo &Info) const; 594 void allocateSpecialInputSGPRs( 595 CCState &CCInfo, 596 MachineFunction &MF, 597 const SIRegisterInfo &TRI, 598 SIMachineFunctionInfo &Info) const; 599 600 void allocateSpecialInputVGPRs(CCState &CCInfo, 601 MachineFunction &MF, 602 const SIRegisterInfo &TRI, 603 SIMachineFunctionInfo &Info) const; 604 void allocateSpecialInputVGPRsFixed(CCState &CCInfo, 605 MachineFunction &MF, 606 const SIRegisterInfo &TRI, 607 SIMachineFunctionInfo &Info) const; 608 609 MachineMemOperand::Flags 610 getTargetMMOFlags(const Instruction &I) const override; 611 }; 612 613 // Returns true if argument is a boolean value which is not serialized into 614 // memory or argument and does not require v_cndmask_b32 to be deserialized. 615 bool isBoolSGPR(SDValue V); 616 617 } // End namespace llvm 618 619 #endif 620