xref: /llvm-project/llvm/lib/Target/AMDGPU/AMDGPU.h (revision a343b8e595d56bde91800aeaa7826cbed4e0a18d) 
1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12 
13 #include "llvm/CodeGen/MachinePassManager.h"
14 #include "llvm/IR/PassManager.h"
15 #include "llvm/Pass.h"
16 #include "llvm/Support/AMDGPUAddrSpace.h"
17 #include "llvm/Support/CodeGen.h"
18 
19 namespace llvm {
20 
21 class AMDGPUTargetMachine;
22 class GCNTargetMachine;
23 class TargetMachine;
24 
25 // GlobalISel passes
26 void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
27 FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
28 void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
29 FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
30 FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
31 void initializeAMDGPURegBankCombinerPass(PassRegistry &);
32 FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
33 FunctionPass *createAMDGPURegBankSelectPass();
34 FunctionPass *createAMDGPURegBankLegalizePass();
35 
36 // SI Passes
37 FunctionPass *createGCNDPPCombinePass();
38 FunctionPass *createSIAnnotateControlFlowLegacyPass();
39 FunctionPass *createSIFoldOperandsLegacyPass();
40 FunctionPass *createSIPeepholeSDWALegacyPass();
41 FunctionPass *createSILowerI1CopiesLegacyPass();
42 FunctionPass *createSIShrinkInstructionsLegacyPass();
43 FunctionPass *createSILoadStoreOptimizerLegacyPass();
44 FunctionPass *createSIWholeQuadModePass();
45 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
46 FunctionPass *createSIOptimizeExecMaskingPreRAPass();
47 FunctionPass *createSIOptimizeVGPRLiveRangeLegacyPass();
48 FunctionPass *createSIFixSGPRCopiesLegacyPass();
49 FunctionPass *createLowerWWMCopiesPass();
50 FunctionPass *createSIMemoryLegalizerPass();
51 FunctionPass *createSIInsertWaitcntsPass();
52 FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
53 FunctionPass *createSIFormMemoryClausesPass();
54 
55 FunctionPass *createSIPostRABundlerPass();
56 FunctionPass *createAMDGPUImageIntrinsicOptimizerPass(const TargetMachine *);
57 ModulePass *createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *);
58 FunctionPass *createAMDGPUCodeGenPreparePass();
59 FunctionPass *createAMDGPULateCodeGenPrepareLegacyPass();
60 FunctionPass *createAMDGPUReserveWWMRegsPass();
61 FunctionPass *createAMDGPURewriteOutArgumentsPass();
62 ModulePass *
63 createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
64 ModulePass *createAMDGPULowerBufferFatPointersPass();
65 FunctionPass *createSIModeRegisterPass();
66 FunctionPass *createGCNPreRAOptimizationsPass();
67 FunctionPass *createAMDGPUPreloadKernArgPrologLegacyPass();
68 
69 struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
70   AMDGPUSimplifyLibCallsPass() {}
71   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
72 };
73 
74 struct AMDGPUImageIntrinsicOptimizerPass
75     : PassInfoMixin<AMDGPUImageIntrinsicOptimizerPass> {
76   AMDGPUImageIntrinsicOptimizerPass(TargetMachine &TM) : TM(TM) {}
77   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
78 
79 private:
80   TargetMachine &TM;
81 };
82 
83 struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
84   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
85 };
86 
87 class SILowerI1CopiesPass : public PassInfoMixin<SILowerI1CopiesPass> {
88 public:
89   SILowerI1CopiesPass() = default;
90   PreservedAnalyses run(MachineFunction &MF,
91                         MachineFunctionAnalysisManager &MFAM);
92 };
93 
94 void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
95 
96 void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
97 
98 Pass *createAMDGPUAnnotateKernelFeaturesPass();
99 Pass *createAMDGPUAttributorLegacyPass();
100 void initializeAMDGPUAttributorLegacyPass(PassRegistry &);
101 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
102 extern char &AMDGPUAnnotateKernelFeaturesID;
103 
104 // DPP/Iterative option enables the atomic optimizer with given strategy
105 // whereas None disables the atomic optimizer.
106 enum class ScanOptions { DPP, Iterative, None };
107 FunctionPass *createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy);
108 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
109 extern char &AMDGPUAtomicOptimizerID;
110 
111 ModulePass *createAMDGPUCtorDtorLoweringLegacyPass();
112 void initializeAMDGPUCtorDtorLoweringLegacyPass(PassRegistry &);
113 extern char &AMDGPUCtorDtorLoweringLegacyPassID;
114 
115 FunctionPass *createAMDGPULowerKernelArgumentsPass();
116 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
117 extern char &AMDGPULowerKernelArgumentsID;
118 
119 FunctionPass *createAMDGPUPromoteKernelArgumentsPass();
120 void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &);
121 extern char &AMDGPUPromoteKernelArgumentsID;
122 
123 struct AMDGPUPromoteKernelArgumentsPass
124     : PassInfoMixin<AMDGPUPromoteKernelArgumentsPass> {
125   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
126 };
127 
128 ModulePass *createAMDGPULowerKernelAttributesPass();
129 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
130 extern char &AMDGPULowerKernelAttributesID;
131 
132 struct AMDGPULowerKernelAttributesPass
133     : PassInfoMixin<AMDGPULowerKernelAttributesPass> {
134   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
135 };
136 
137 void initializeAMDGPULowerModuleLDSLegacyPass(PassRegistry &);
138 extern char &AMDGPULowerModuleLDSLegacyPassID;
139 
140 struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
141   const AMDGPUTargetMachine &TM;
142   AMDGPULowerModuleLDSPass(const AMDGPUTargetMachine &TM_) : TM(TM_) {}
143 
144   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
145 };
146 
147 void initializeAMDGPULowerBufferFatPointersPass(PassRegistry &);
148 extern char &AMDGPULowerBufferFatPointersID;
149 
150 struct AMDGPULowerBufferFatPointersPass
151     : PassInfoMixin<AMDGPULowerBufferFatPointersPass> {
152   AMDGPULowerBufferFatPointersPass(const TargetMachine &TM) : TM(TM) {}
153   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
154 
155 private:
156   const TargetMachine &TM;
157 };
158 
159 void initializeAMDGPUReserveWWMRegsPass(PassRegistry &);
160 extern char &AMDGPUReserveWWMRegsID;
161 
162 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
163 extern char &AMDGPURewriteOutArgumentsID;
164 
165 void initializeGCNDPPCombineLegacyPass(PassRegistry &);
166 extern char &GCNDPPCombineLegacyID;
167 
168 void initializeSIFoldOperandsLegacyPass(PassRegistry &);
169 extern char &SIFoldOperandsLegacyID;
170 
171 void initializeSIPeepholeSDWALegacyPass(PassRegistry &);
172 extern char &SIPeepholeSDWALegacyID;
173 
174 void initializeSIShrinkInstructionsLegacyPass(PassRegistry &);
175 extern char &SIShrinkInstructionsLegacyID;
176 
177 void initializeSIFixSGPRCopiesLegacyPass(PassRegistry &);
178 extern char &SIFixSGPRCopiesLegacyID;
179 
180 void initializeSIFixVGPRCopiesLegacyPass(PassRegistry &);
181 extern char &SIFixVGPRCopiesID;
182 
183 void initializeSILowerWWMCopiesLegacyPass(PassRegistry &);
184 extern char &SILowerWWMCopiesLegacyID;
185 
186 void initializeSILowerI1CopiesLegacyPass(PassRegistry &);
187 extern char &SILowerI1CopiesLegacyID;
188 
189 void initializeAMDGPUGlobalISelDivergenceLoweringPass(PassRegistry &);
190 extern char &AMDGPUGlobalISelDivergenceLoweringID;
191 
192 void initializeAMDGPURegBankSelectPass(PassRegistry &);
193 extern char &AMDGPURegBankSelectID;
194 
195 void initializeAMDGPURegBankLegalizePass(PassRegistry &);
196 extern char &AMDGPURegBankLegalizeID;
197 
198 void initializeAMDGPUMarkLastScratchLoadPass(PassRegistry &);
199 extern char &AMDGPUMarkLastScratchLoadID;
200 
201 void initializeSILowerSGPRSpillsLegacyPass(PassRegistry &);
202 extern char &SILowerSGPRSpillsLegacyID;
203 
204 void initializeSILoadStoreOptimizerLegacyPass(PassRegistry &);
205 extern char &SILoadStoreOptimizerLegacyID;
206 
207 void initializeSIWholeQuadModePass(PassRegistry &);
208 extern char &SIWholeQuadModeID;
209 
210 void initializeSILowerControlFlowLegacyPass(PassRegistry &);
211 extern char &SILowerControlFlowLegacyID;
212 
213 void initializeSIPreEmitPeepholePass(PassRegistry &);
214 extern char &SIPreEmitPeepholeID;
215 
216 void initializeSILateBranchLoweringPass(PassRegistry &);
217 extern char &SILateBranchLoweringPassID;
218 
219 void initializeSIOptimizeExecMaskingLegacyPass(PassRegistry &);
220 extern char &SIOptimizeExecMaskingLegacyID;
221 
222 void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
223 extern char &SIPreAllocateWWMRegsLegacyID;
224 
225 void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
226 extern char &AMDGPUImageIntrinsicOptimizerID;
227 
228 void initializeAMDGPUPerfHintAnalysisLegacyPass(PassRegistry &);
229 extern char &AMDGPUPerfHintAnalysisLegacyID;
230 
231 void initializeGCNRegPressurePrinterPass(PassRegistry &);
232 extern char &GCNRegPressurePrinterID;
233 
234 void initializeAMDGPUPreloadKernArgPrologLegacyPass(PassRegistry &);
235 extern char &AMDGPUPreloadKernArgPrologLegacyID;
236 
237 // Passes common to R600 and SI
238 FunctionPass *createAMDGPUPromoteAlloca();
239 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
240 extern char &AMDGPUPromoteAllocaID;
241 
242 FunctionPass *createAMDGPUPromoteAllocaToVector();
243 void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry&);
244 extern char &AMDGPUPromoteAllocaToVectorID;
245 
246 struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
247   AMDGPUPromoteAllocaPass(TargetMachine &TM) : TM(TM) {}
248   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
249 
250 private:
251   TargetMachine &TM;
252 };
253 
254 struct AMDGPUPromoteAllocaToVectorPass
255     : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
256   AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM) : TM(TM) {}
257   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
258 
259 private:
260   TargetMachine &TM;
261 };
262 
263 struct AMDGPUAtomicOptimizerPass : PassInfoMixin<AMDGPUAtomicOptimizerPass> {
264   AMDGPUAtomicOptimizerPass(TargetMachine &TM, ScanOptions ScanImpl)
265       : TM(TM), ScanImpl(ScanImpl) {}
266   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
267 
268 private:
269   TargetMachine &TM;
270   ScanOptions ScanImpl;
271 };
272 
273 Pass *createAMDGPUStructurizeCFGPass();
274 FunctionPass *createAMDGPUISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel);
275 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
276 
277 struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
278   AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
279   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
280 
281 private:
282   bool GlobalOpt;
283 };
284 
285 void initializeAMDGPUSwLowerLDSLegacyPass(PassRegistry &);
286 extern char &AMDGPUSwLowerLDSLegacyPassID;
287 ModulePass *
288 createAMDGPUSwLowerLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
289 
290 struct AMDGPUSwLowerLDSPass : PassInfoMixin<AMDGPUSwLowerLDSPass> {
291   const AMDGPUTargetMachine &TM;
292   AMDGPUSwLowerLDSPass(const AMDGPUTargetMachine &TM_) : TM(TM_) {}
293   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
294 };
295 
296 class AMDGPUCodeGenPreparePass
297     : public PassInfoMixin<AMDGPUCodeGenPreparePass> {
298 private:
299   TargetMachine &TM;
300 
301 public:
302   AMDGPUCodeGenPreparePass(TargetMachine &TM) : TM(TM){};
303   PreservedAnalyses run(Function &, FunctionAnalysisManager &);
304 };
305 
306 class AMDGPULateCodeGenPreparePass
307     : public PassInfoMixin<AMDGPULateCodeGenPreparePass> {
308 private:
309   const GCNTargetMachine &TM;
310 
311 public:
312   AMDGPULateCodeGenPreparePass(const GCNTargetMachine &TM) : TM(TM) {};
313   PreservedAnalyses run(Function &, FunctionAnalysisManager &);
314 };
315 
316 class AMDGPULowerKernelArgumentsPass
317     : public PassInfoMixin<AMDGPULowerKernelArgumentsPass> {
318 private:
319   TargetMachine &TM;
320 
321 public:
322   AMDGPULowerKernelArgumentsPass(TargetMachine &TM) : TM(TM){};
323   PreservedAnalyses run(Function &, FunctionAnalysisManager &);
324 };
325 
326 struct AMDGPUAttributorOptions {
327   bool IsClosedWorld = false;
328 };
329 
330 class AMDGPUAttributorPass : public PassInfoMixin<AMDGPUAttributorPass> {
331 private:
332   TargetMachine &TM;
333 
334   AMDGPUAttributorOptions Options;
335 
336 public:
337   AMDGPUAttributorPass(TargetMachine &TM, AMDGPUAttributorOptions Options = {})
338       : TM(TM), Options(Options) {};
339   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
340 };
341 
342 class AMDGPUAnnotateUniformValuesPass
343     : public PassInfoMixin<AMDGPUAnnotateUniformValuesPass> {
344 public:
345   AMDGPUAnnotateUniformValuesPass() {}
346   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
347 };
348 
349 FunctionPass *createAMDGPUAnnotateUniformValuesLegacy();
350 
351 ModulePass *createAMDGPUPrintfRuntimeBinding();
352 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
353 extern char &AMDGPUPrintfRuntimeBindingID;
354 
355 void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &);
356 extern char &AMDGPUResourceUsageAnalysisID;
357 
358 struct AMDGPUPrintfRuntimeBindingPass
359     : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
360   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
361 };
362 
363 ModulePass* createAMDGPUUnifyMetadataPass();
364 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
365 extern char &AMDGPUUnifyMetadataID;
366 
367 struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
368   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
369 };
370 
371 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
372 extern char &SIOptimizeExecMaskingPreRAID;
373 
374 void initializeSIOptimizeVGPRLiveRangeLegacyPass(PassRegistry &);
375 extern char &SIOptimizeVGPRLiveRangeLegacyID;
376 
377 void initializeAMDGPUAnnotateUniformValuesLegacyPass(PassRegistry &);
378 extern char &AMDGPUAnnotateUniformValuesLegacyPassID;
379 
380 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
381 extern char &AMDGPUCodeGenPrepareID;
382 
383 void initializeAMDGPURemoveIncompatibleFunctionsLegacyPass(PassRegistry &);
384 extern char &AMDGPURemoveIncompatibleFunctionsID;
385 
386 void initializeAMDGPULateCodeGenPrepareLegacyPass(PassRegistry &);
387 extern char &AMDGPULateCodeGenPrepareLegacyID;
388 
389 FunctionPass *createAMDGPURewriteUndefForPHILegacyPass();
390 void initializeAMDGPURewriteUndefForPHILegacyPass(PassRegistry &);
391 extern char &AMDGPURewriteUndefForPHILegacyPassID;
392 
393 class AMDGPURewriteUndefForPHIPass
394     : public PassInfoMixin<AMDGPURewriteUndefForPHIPass> {
395 public:
396   AMDGPURewriteUndefForPHIPass() = default;
397   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
398 };
399 
400 class SIAnnotateControlFlowPass
401     : public PassInfoMixin<SIAnnotateControlFlowPass> {
402 private:
403   const AMDGPUTargetMachine &TM;
404 
405 public:
406   SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
407   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
408 };
409 
410 void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &);
411 extern char &SIAnnotateControlFlowLegacyPassID;
412 
413 void initializeSIMemoryLegalizerPass(PassRegistry&);
414 extern char &SIMemoryLegalizerID;
415 
416 void initializeSIModeRegisterPass(PassRegistry&);
417 extern char &SIModeRegisterID;
418 
419 void initializeAMDGPUInsertDelayAluPass(PassRegistry &);
420 extern char &AMDGPUInsertDelayAluID;
421 
422 void initializeSIInsertHardClausesPass(PassRegistry &);
423 extern char &SIInsertHardClausesID;
424 
425 void initializeSIInsertWaitcntsPass(PassRegistry&);
426 extern char &SIInsertWaitcntsID;
427 
428 void initializeSIFormMemoryClausesPass(PassRegistry&);
429 extern char &SIFormMemoryClausesID;
430 
431 void initializeSIPostRABundlerPass(PassRegistry&);
432 extern char &SIPostRABundlerID;
433 
434 void initializeGCNCreateVOPDPass(PassRegistry &);
435 extern char &GCNCreateVOPDID;
436 
437 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
438 extern char &AMDGPUUnifyDivergentExitNodesID;
439 
440 ImmutablePass *createAMDGPUAAWrapperPass();
441 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
442 ImmutablePass *createAMDGPUExternalAAWrapperPass();
443 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
444 
445 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
446 
447 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringLegacyPass();
448 void initializeAMDGPUOpenCLEnqueuedBlockLoweringLegacyPass(PassRegistry &);
449 extern char &AMDGPUOpenCLEnqueuedBlockLoweringLegacyID;
450 
451 void initializeGCNNSAReassignPass(PassRegistry &);
452 extern char &GCNNSAReassignID;
453 
454 void initializeGCNPreRALongBranchRegPass(PassRegistry &);
455 extern char &GCNPreRALongBranchRegID;
456 
457 void initializeGCNPreRAOptimizationsPass(PassRegistry &);
458 extern char &GCNPreRAOptimizationsID;
459 
460 FunctionPass *createAMDGPUSetWavePriorityPass();
461 void initializeAMDGPUSetWavePriorityPass(PassRegistry &);
462 
463 void initializeGCNRewritePartialRegUsesPass(llvm::PassRegistry &);
464 extern char &GCNRewritePartialRegUsesID;
465 
466 namespace AMDGPU {
467 enum TargetIndex {
468   TI_CONSTDATA_START,
469   TI_SCRATCH_RSRC_DWORD0,
470   TI_SCRATCH_RSRC_DWORD1,
471   TI_SCRATCH_RSRC_DWORD2,
472   TI_SCRATCH_RSRC_DWORD3
473 };
474 
475 static inline bool addrspacesMayAlias(unsigned AS1, unsigned AS2) {
476   static_assert(AMDGPUAS::MAX_AMDGPU_ADDRESS <= 9, "Addr space out of range");
477 
478   if (AS1 > AMDGPUAS::MAX_AMDGPU_ADDRESS || AS2 > AMDGPUAS::MAX_AMDGPU_ADDRESS)
479     return true;
480 
481   // This array is indexed by address space value enum elements 0 ... to 9
482   // clang-format off
483   static const bool ASAliasRules[10][10] = {
484     /*                       Flat   Global Region  Group Constant Private Const32 BufFatPtr BufRsrc BufStrdPtr */
485     /* Flat     */            {true,  true,  false, true,  true,  true,  true,  true,  true,  true},
486     /* Global   */            {true,  true,  false, false, true,  false, true,  true,  true,  true},
487     /* Region   */            {false, false, true,  false, false, false, false, false, false, false},
488     /* Group    */            {true,  false, false, true,  false, false, false, false, false, false},
489     /* Constant */            {true,  true,  false, false, false, false, true,  true,  true,  true},
490     /* Private  */            {true,  false, false, false, false, true,  false, false, false, false},
491     /* Constant 32-bit */     {true,  true,  false, false, true,  false, false, true,  true,  true},
492     /* Buffer Fat Ptr  */     {true,  true,  false, false, true,  false, true,  true,  true,  true},
493     /* Buffer Resource */     {true,  true,  false, false, true,  false, true,  true,  true,  true},
494     /* Buffer Strided Ptr  */ {true,  true,  false, false, true,  false, true,  true,  true,  true},
495   };
496   // clang-format on
497 
498   return ASAliasRules[AS1][AS2];
499 }
500 
501 }
502 
503 } // End namespace llvm
504 
505 #endif
506